* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Kalama adds support for uidle fill level scaling to allow
fal10 mode for 90 and above fps use cases.
Pre-Kalama, the fill levels are clamped at 4-bit values supported
by the threshold registers. But to achieve the targeted 50us idle
time on fal10 modes with higher FPS use cases, we need fill levels
higher than 15 (max for 4 bit). The hardware change in Kalama
achieves by using a 5 bit scale factor in combination with the
programmed threshold values.
Change-Id: I638705355c03910a83e7d922b6fe48ab11c120a8
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
This change updates copyright description with correct
license marking as per the guidelines.
Change-Id: Ia74b721e78afcc7f8e88bcbccfcf15430111ec37
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
This change adds Detail Enhancer LPF blend support from MDSS 9.0.
Support is added for qseed block in both SSPP and Destination Scaler.
Change-Id: Ic8e3732059498a156f51fb93c5fd6638bd731c57
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Parametrize RC minimum region width restriction as it
differs starting from Kailua.
Change-Id: I41e7cd6812ed2fadb5719ee51f4db0723be632fe
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
The HW support for RGB pipes were removed from MDSS 3.x and cursor pipes
from MDSS 4.x. Remove the support from s/w as well with this change.
Change-Id: Ib5b363234e200ee5c421684cf1904a38a5d90b58
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Update the cwb block offset and stride values for kalama
target in sde hw catalog. As part of the change, allow the
ctl wb-flush bit for cwb to be set based on the wb idx used.
Change-Id: Ibf7ccda88cbb47bddacf53b5af9841d381a4766c
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
From kalama, add support for QoS fill level calculations based on
line-based QoS calculations.
Change-Id: I524ca29c6e9d1912b44a328a2a88d08341cccefc
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add support to parse and configure QoS values for offline writeback.
Expose a writeback connector property to allow user-mode to set
the usage type of the writeback block - WFD, CWB, offline-WB.
Change-Id: I864f79c4896ec757ac2d8b0f57a6a5775d164f21
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Update the sde HW catalog parsing to get separate values for rp_remap
and lvl_remap for each qos level. Previously, only rp_remap were provided
and the same was applied for lvl_remap. As part of the change, add cnoc
remap level which is added as part of MDSS 9.x.
Change-Id: I112a715f8b33cd4b028886d8074e35fef75b8aab
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Update the DT parsing logic to get danger/safe LUT values for
both portrait & landscape for all the usage types.
As part of the change, fix the correct CDP write setting for
CWB usecase.
Change-Id: I4fb6d17537de5df31c9b7f52983c0c3890265174
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Currently, CDM usage is restricted to WB2 and INTF3. Expand the usage
to all writeback blocks. However, CDM is a single HW block and can be
used by only one interface at any point of time, which is controlled by
the sde_rm reservation.
Change-Id: I9fc892046e5df6c1d4d74ca410bf48053136a1ca
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
With full DSC size of 20k, RT performance issues are seen due to the
stress created during larger prefill needed to fill up the 20k DSC buffer.
Limiting DSC size to 10k helps to mitigate these RT performace issues.
This change adds support for this based on new flag has_reduced_ob_max
in sde_mdss_cfg data structure. Flag has_reduced_ob_max has be set
true only on targets where its recommended.
Change-Id: I649d213bcd378025bd0548fb982b55c98c99224f
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
MDSS.9.0 adds support for mdp vsync based HW timestamps
on top the existing support for panel vsync based timestamps.
This allows us to enable vsync timestamp calculations for all the
use cases including a few corner cases (e.g. programmable fetch)
which we couldn't support with the existing HW.
This change adds the new HW register support and modifies the
timestamp read logic to use mdp vsync on supporting targets.
Change-Id: I2cb1b56ca9154174331c4fc1d8f82319b6989247
Signed-off-by: Michael Ru <mru@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
Dedicated registers are introduced for DSC 4HS merge block
programming from MDSS.9.0. This change adds support in the
driver to identify the change using a DSC feature flag
and separates out 4HS merge block programming to use appropriate
registers based on the DSC HW feature.
Change-Id: Ia64a1ed4bc5f5f301ab422144916cdce2a1dadac
Signed-off-by: Michael Ru <mru@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
From Kalama, the HW scheduler abstracts the low level
PP_DONE/WB_DONE interrupts and generates a common
CTL_DONE interrupt per hw ctl. This saves the software
the irq latency delays to process the frame complete
operations when multiple encoders are involved.
If supported, this change enables and waits for the
CTL_DONE interrupt instead of PP_DONE and WB_DONE.
This change adds support to wait for CTL_DONE irq in
only command mode panels as we don't drive two WB blocks
with single CTL.
Change-Id: I084d6bfb6a9fb0b48f912fe5787401c460ec5b56
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
Add sde catalog entries for the downscale blur supported filters
and the corresponding downscale ratios. The PCMN supports ratio
from 1 to 128 and gaussian filter supports specific ratios in the
range between 8 to 64.
Change-Id: Ifdf1a8fc7cfc5f5bd1297f10c7946c2bf9b63dcd
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add device tree parsing code for downscale blur block and sub blocks.
Add restrictions to allow downscale blur block to be used only by the
writeback. Set allowed interfaces for the block while parsing from
device-tree to restrict usage.
Change-Id: Ifa4c89ec52863d245a40bd4715a4e31f542b8117
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add support to enable writeback block to use system cache for writing
the output buffer. This is useful in cases where output is routed to
primary source pipes with 2-pass composition. The implementation is
modelled based on existing pipe based cache configuration.
Change-Id: I2b9a96c5b42eb5727d11ca0f337aeeb4e69362c9
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
From MDSS 9.x, the pp-done wait requirement as part of autorefresh
sequence is not required. Add a catalog flag to avoid the wait for
mdss 9.x+ and to support backward compatibility.
Change-Id: Ieca008d3d6ef0f7326b65433ef42ed9f49a94f87
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
From MDSS 9.0, writeback supports a programmable lineptr support, which
generates an interrupt when the configured writeback output height is
reached. Add software support to configure the prog_line and to process
the interrupt.
Change-Id: I3293ad2984c51417e4691c5b11e9c9a010067e1c
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Remove the hw feature flags that are set by default for writeback as
it does not add any value. As part of the change, remove the unused
wb register offsets.
Change-Id: I04376242e764d8d0a1edb763c9f799d7ae5447ac
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add kalama mdss revision and enable features based
on the hardware capability.
Change-Id: I27dff07b00ba16d313c5c8dc2661a10e522daea5
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Align the HW catalog to use common naming amongst the "revision"
and "version" structure members.
Change-Id: Ib6c81aee6cb49208b0699db4a75b4eb9dc79e800
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
Move all the individual boolean flags from HW catalog into a
"features" bitmap. These flags are used to specify support of
various target specific features.
Change-Id: I2334b3b873f3737f91bbae4ef576408247710156
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
Include of_common header file explicitly to use
of_fdt_get_ddrtype().
Change-Id: Idd814d6188d585b2d0ecd6935f3260a79d15401b
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
With this change, the IB vote will be based on the following:
IB = AB_aggregated / number of DDR Channels / DRAM efficiency factor
Number of DDR Channels and DRAM efficiency factor are now device tree
properties which can be modified and parsed at boot up.
Change-Id: I298043807150faec1cbc0d74eefcdd1a534b460a
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Unmult feature is currently using offsets from previous targets.
This leads to unexpected alpha transparency errors on screen.
This change updates the new offsets based on hw version and
retains the original offsets for backward compatibility.
Change-Id: Icdba050371a583f1a20b91a451be3324de12c2cf
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
TUI clients are the display sub-drivers that participate
during the TUI transition. They register with the display
TUI notification framework with a list of callbacks functions
that will be invoked during pre/post transitions and for quering
I/O memory that need to be access controlled. This change
adds RSC to the TUI client list.
In Trusted VM, all the sub-drivers are not enabled to avoid
any re-configuration of respective module registers. But the
TUI framework need to know the sub-driver I/O memory ranges
in order to accept the I/O memory list lent by the HLOS VM.
So, SDE provides them ranges by reading from a custom
devicetree property.
Change-Id: I2c4b254d539d04771339ae4a7bf4d296b7a7f91a
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
This change sets a flag to true if a mixer is a virtual mixer.
Virtual mixers will skip setting up mixer ops and debug register
dumps as their range is not valid. Since mixer ops are no longer
guaranteed to be set, add null checks before using these ops.
Change-Id: Idfe7e1e2b893dadbbe6756d69d0c4ca4fa6ae4ce
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Add support to send a data packet of info, written to
predefined buffers, providing information about each submitted frame.
Add required UAPI definitions for frame data buffers and event
notification.
Add support to read ubwc statistics from hw, based on defined rois.
Change-Id: I51f279de98ae4e2a02b0df6943d334764011d5db
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Add AVR step support so SW can trigger a late frame and instead
of immediately triggering, HW will perform the update at the
start of the next step interval. This allows for a fixed SW
vsync timeline to be maintained in userland, eliminating the
usual drift from the actual HW vsync caused by a late frame.
This change adds AVR_STEP support via a DRM property.
Change-Id: I4cf8a296989805f134c2165a3bed0b050bb09c96
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
