* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
When cwb is enabled enable software override for fal10 veto to
block fal10 entry as MDSS can keep asserting uidle if there
are no fetch clients like dim layer only usecase.
Change-Id: Ief51499d370c20fcbdda79576aee0179578650fd
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
From Kalama, the HW scheduler abstracts the low level
PP_DONE/WB_DONE interrupts and generates a common
CTL_DONE interrupt per hw ctl. This saves the software
the irq latency delays to process the frame complete
operations when multiple encoders are involved.
If supported, this change enables and waits for the
CTL_DONE interrupt instead of PP_DONE and WB_DONE.
This change adds support to wait for CTL_DONE irq in
only command mode panels as we don't drive two WB blocks
with single CTL.
Change-Id: I084d6bfb6a9fb0b48f912fe5787401c460ec5b56
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
If an external display, such as DP, requests for the available
resources, resource manager (RM) will provide a count of all unused
mixers. If the primary/secondary display(s) are not active, the RM
will report the associated preferred mixers as free resources.
However, RM will not allow preferred mixers to be allocated to other
displays. DP driver could look at these available resources and assume
a high resolution mode is possible and fail during resource allocation.
This change updates the available resources info API to account for
primary/secondary preferences while exposing available resources.
Change-Id: I134a1047f24ac9f1fcee695aa14a1d3e43c1571f
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
MDSS INTF HW block does not generate vsync if controller
turns off the link clock prematurely. This leads to
frame trigger timeout and SDE driver triggers the retire
fence after 84ms to recover gracefully. A client may switch
source pipe from one CTL path to another CTL path based
on delayed retire fence. It can lead to other ctl path
hang. This can be resolved by resetting the lm blend
stages for each missing vsync frame trigger.
Change-Id: I5a6ed03afbdad83d8fd6decc593d39e04bef62e4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Current timeout values in sde driver for vblank, kickoff and
frame complete timeouts are fixed and can be much lower than
a vsync incase of low refresh rate display. Compute timeouts
based on refresh rate for low refresh rate displays.
Change-Id: I9dda41feb15446de7451824e185321de421ad575
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
VA minidumps supports to add any allocated variable or data to
minidumps. Add panic notifier and wrapper function to add
sde data to minidump va. Add event log, register log, register dumps,
debug bus and different sde variables and states info to minidump.
Change-Id: If54da0b7067df17877e4da645d82f1705baa3f6d
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
Delayed work items may touch HW registers. If these work items
run while HW is not owned by this VM it will lead to invalid
access. This happens in video mode as HAL does not disable idle
power-collapse in this mode. It can also happen with ESD status
if lastclose or TUI transition failure occurs.
Although there is a contract with user mode to turn off certain
features, kernel cannot rely on it to always do the right thing.
Prevent potential crashes from certain corner cases by
cancelling all delayed work items when the HW ownership is
transferred.
Change-Id: I08da17f2ce72bf2fddf71924c3e8edd2e2715be8
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Add changes to modify the phys_enc->in_clone_mode variable
post wb_reset_state since this is a shared variable used
during atomic_check and atomic_commit. In current issue case,
wb_atomic_check has set in_clone_mode to true in commit N,
and in commit N-1 CWB is being disabled and re-sets the
in_clone_mode variable to false causing pp_done timeouts in
primary in commit N.
Change-Id: I8159bbdb5622a351d76bdc4dba75d48df20f4365
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Topology in sde_encoder is no longer used, so remove this
variable from sde_encoder.
Change-Id: Iba02ae690d81d39252d0df83882a72e35f2916ec
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
This change adds logic to determine dsc switch based on
the connector property "CONNECTOR_PROP_DSC_MODE" and
performs seamless DSC switch if there is any change in
DSC configuration. The connector property is populated
in msm_sub_mode based on which suitable mode is selected.
Change-Id: Ifc4931f16dfb814781bc1d72b103e09103e6bfee
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
SDE RSCC solver state and autorefresh enable concurrency
is not supported. This change moves the rscc solver state
to disable to avoid concurrency. It also resets the autorefresh
software structure state when encoder is disabled. This allows
autorefresh reconfiguration with next encoder enable.
Change-Id: Idb8c722c823d9f46d3cd03e1b046da69c8d88fc4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Report the AVR_STATUS which indicates if there's a pending
trigger when Adaptive Variable Refresh feature is enabled.
This allows SW to detect whether the old frame is repeated
or if the new frame was taken when the trigger is very
close to Vsync.
Change-Id: I6b04482e5c4c3bb92bad426c529c1fd3612d41c3
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Calculate line_time once during modeset and allow
each plane to use it instead of calculating for each frame.
It also simplifies the line_time calculation for
command mode display.
Change-Id: I94ce29eec94bfdbee9016fbf93378661ebf79c03
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Retire fence for frames are signaled based on vsync. Use the HW
vsync timestamp counter to calculate the precise vsync timestamp
and update the retire fence signal timestamp. This will offset
all IRQ and SW delays and sends the precise timestamp. Avoid
calculating the timestamp on error or panel dead events and
set the current ktime for those cases.
Change-Id: Ic762f7cd6daead9c8fdcb0f8aad6386cf980407d
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add precise vblank timestamp support through the DRM framework.
Implement the vblank related hooks to get the vblank count and
timestamp. Use MDSS 8.x, hardware feature that supports logging
of the vsync timestamp counter which can be used to derive the
accurate kernel timestamp. The current ktime would be returned
for older targets to support backward compatibility.
Change-Id: I2d35ed4a643a519e602278b6d16e67ccee16a60b
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
From MDSS 8.x, vsync timestamp counter register is added in all the
interfaces. Add interface to get the vsync counter and use the global
qtmr reference counter to get the counter delta. This can be used
with reference to the curret ktime to deduce the accurate vsync
timestamp. This utility is intended to be used for setting the vblank
and retire fence timestamps which would be notified to user-mode.
Change-Id: I608a284c035cda50053eedbb311f1f54b3d3d557
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Move away from the private and private_flags fields from drm_mode,
as it is being deprecated in latest kernel version. Instead, Add
msm_display_mode as a wrapper to be used in downstream to store these
parameters. Also, store msm_mode in connector_state to be accessed
in commit path.
Change-Id: Ia5bdebe75f00aa15fb7db4dc3a0d50c30894a95c
Signed-off-by: Orion Brody <obrody@codeaurora.org>
Commit a25b988ff83f ("drm/bridge: Extend bridge API to
disable connector creation") and commit ee68c743f8d0 ("drm: Stop
including drm_bridge.h from drm_crtc.h) add additional input flags.
This change adds fixes to the drm bridge attach API and includes
relevant drm_bridge header files.
Change-Id: I85e84eaff7df2995243896108a217fae81716b63
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
The current SDE driver logic during MDP hang cases is to send a capture
event to user-mode if recovery custom event is registered. Otherwise, it
will enforce a device panic for debugging purpose. This might have a race
condition during the display tear-down sequence as user-mode unregisters
the recovery event when the last frame is in progress. If the last frame
causes any MDP hang, it will result in a device reset. Support only the
event registration to avoid this case, since HW recovery is not expected
to be changed dynamically.
Change-Id: I8a11e1060b239ac6827f1d078e3e396cff4c1325
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
This change adds support for delaying kickoff in case of ESD error.
This delay is required to handle a race condition between esd
workqueue and display thread.
When ESD workqueue detects the esd and while handling the failure
notification if the new updates arrive on display thread, there
is a possibility that ESD workqueue will keep on waiting on pp_done.
This could happen if display thread keeps on incrementing the kickoff_cnt
before workqueue can check the condition. With this change the kickoff is
delayed, allowing the workqueue to get scheduled and avoiding the race
condition.
Change-Id: I8e6fff5ea5494ae801d1e60ae85b7ad19cc12961
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Commit Ifa100424733 ("disp: msm: sde: delay
encoder disable for clone mode") delays the CWB
encoder disable but it is also skipping the CWB
disable flush. That can cause the underrun on dp
display if it uses the same 3d_merge HW block. This
change reverts the portion of original code and
only delays the last cwb frame done wait. It still
keep the last CWB frame done wait as it is if crtc
is also moving to inactive state.
Change-Id: I3461188a35197f2925899ceea7ef705adf00a398
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
It is not applicable for all DFPS cases to update UIDLE state
according to current frame rate. If DFPS changes frame rate
through vertical front porch values, the SDE clocks and transfer
time will not get changed accordingly, and it always get fixed
at max frame rate configuration of DFPS.
Add this change to check max FPS of DFPS instead of current
frame rate for UIDLE update, if DFPS is enabled with VFP.
Change-Id: I7634bce6a9eb1af212ba19a267735be08b20ae1f
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
This change fixes the vblank wait after system cache read mode
update. Without this change the wait does not happen since there is
no pending kickoff. This change uses encoder api to flush the
configuration and explicitly waits for vblank.
Change-Id: I8942f9b638e784c8fd9b5df33a9ccc7087a5eaef
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Display input touch event is replaced with IOCTL in performance HAL
to early wake up DSI clock.
Add a property to enable/disable display input touch event for backward
compatibility.
Change-Id: Ib6b9123d726e79a2927b05d1ef77c343f01d0c5e
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
In current SDE driver when misr is enabled, for each commit in
encoder kickoff stage misr is configured for both lm and interface
misr blks. This can clear misr data before client could collect misr.
This change avoids misr data clear and configures misr based on
user input.
Change-Id: I85fc19c78afc6d01346219250c82f2ada824eb0d
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Display clocks and IRQs are disabled during idle state
on command mode for power saving, and will be enabled
when a new frame commits to display driver. But enable
display clocks and IRQs will cause some latency.
So add a new SDE custom IOCTL for user-space to early wake
up display before first frame commits to kernel.
Change-Id: I6ca0188d321c4964f29c46e588b64d06b9634c59
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
Expose an API in encoder to control display irq's
when the VM enters and exits TUI use case.
Change-Id: Ic2386dcebfd8a9dd2ce06f068c6daf066a3e885f
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Add support for all 4LM topologies in new DCE encoder framework.
This change also aligns with the new way of checking topology
information.
Change-Id: I5358d60634070bdb26059056db884ad4161c073e
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Vsync event timer wakeup was designed to reduced the
interrupt latency and trigger retire fence without delay.
This is fixed by avoiding CPU power collapse where MDSS
interrupt is scheduled. This change avoids extra CPU
wakeup.
Change-Id: Iadaf0e2b84fb079bbc64d9201230df54f8dbe8c1
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Add support for all 4LM topologies in new DCE encoder framework.
This change also aligns with the new way of checking topology
information.
Change-Id: I20785c96569fd07cbd8016d244a7e4c929bfa071
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
From Lahaina onwards, widebus is enabled for compressed DSI stream.
This change adjusts interface timing parameters to account for widebus.
Change-Id: Ie6b739ed2cdb515064e3a94404b3e0fe07755d7e
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
This change adds helper to retrieve the kms from
the drm_enc structure and provides additional error
checking which can be avoided in the callers.
Change-Id: Id8ba07a2d48a605dd4ce846e5d61f302e5861b4d
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Submit a cwb frame event signal to notify the crtc that cwb
is completed. Currently cwb also uses the same frame done
event as primary. When a single cwb commit is completed, because
cwb is on a slower path there is a race condition in which the
subsequent frame done event for primary clears the refcount.
This fix isolates the events and removes this situation.
Change-Id: Ic3e18302eb8a497cbd7a00f271de2ab320576c83
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Reset MDP ctl path and DSI ctl on autorefresh
disable failure. This will enable the hardware
to recover from the hang.
Change-Id: Ia9acc8573c22e0713179ef4f6ef604caacabfadb
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add support to configure the DPU pipeline to support VDC-m
topologies.
Change-Id: Ib8ce9a0eaeaa838759fb09cb2ee164d4765e4989
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Certain DSC hw blocks only support 444 mode, while others
support both 444 and 422 modes. This change adds support in
resource manager to check the hw resource requirement with
the capability of the block and then reserve the correct
hw resource.
Change-Id: If85beb2f2f25e9eb7f8a8321c94b57878d048369
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This change moves the DSC implementation into a separate file.
This is required to add support for new compression algorithms.
This cleanup change also, moves struct sde_encoder_virt
declaration to the encoder header file.
Change-Id: Idc3b96e65fcce2a7ee6e17af604cec0cb574f6f7
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
In dual display cases when secondary display is resumed first,
primary CTL and LM is selected for secondary path which leads to
invalid configuration. Changes are made to correct the reservation
to select primary CTL and LM for primary connector and secondary
LM to secondary connector.
Change-Id: I6b2a8bedaf46f18bdb28b45ac765f32b26207304
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
During SUI validations and transitions, the encoders
are iterated to find the panel-mode. If concurrent
writeback is enabled, it is assumed as video mode.
Add check to consider only the built-in display
panel mode during sui to avoid wrong interpretation.
Change-Id: I2901eb29a0799571a95f6ab6f9f3f2c6154424c5
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Primary and secondary displays should have first priority
when reserving lms. Static reservation can potentially block
higher resolutions for the required displays. This patch gets
the layer mixer requirement for primary or secondary display
if available. It reserves those layer mixers dynamically
for the respective display when connector is registered.
Change-Id: Id69dac4c72d6b20008049f4aeb71c0f97d0a426b
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
