Add apis to map generic registers to shadow region. Existing
logic includes mapping only srng based regs to the shadow
region.
Add support to map REO control regs and WBM2SW2 rel
ring HP reg address to the shadow region in case the direct
reg writes in IPA enable/disable autonomy fail due to UMAC
block being in a power collapsed state.
Shadow reg mapping for these regs is provided to FW during
init. Add stat shadow_reg_write_fail to track shadow reg
write failure and shadow_reg_write_succ to track successful
shadow writes.
Change-Id: I04790765a3de80047689657e2cad0b73123440b9
CRs-Fixed: 2790321
If reo_dst_ctrl register writing failed, this is a fatal error for
IPA pipe going to down case as RX frames will still be routed to
IPA rings then hit NOC error. retry register writing to see any
chance to write successfully, if fail always, trigger SSR or panic.
Change-Id: I3c03faa28e6cc93f396944579a360d5405c8138e
CRs-Fixed: 2774789
The logging macros implicitly takes care of embedding function name
in the log, hence there is no need to include __func__ again.
Getting rid of redundant __func__ reduces driver memory footprint.
Change-Id: I6b5beea990e78486e1e5aab5a8df5fc2f1e5ab51
CRs-Fixed: 2774457
Configure low threshold for monitor ring only when monitor
vap is created. This is needed to avoid spurious low threshold
interrupts on monitor ring since the low threshold condition always
evaluates to true.
Change-Id: I452c0ada84e0a4f18e410c865d8a6a7f50329aef
In ipq5018 CE registers(0x08400000) kept outside WCSS(0x0C000000) block.
As both regions are more than 60MB apart, not feasible to allocate
single resource which include both.
So, using a separate I/O region to access CE registers.
Change-Id: I67bb6d5ac82a1c0ed1d3e13f7776f9d69ee19956
make sure both PCIe and device are force woken for the register
writes for hsp, or write may fail.
Earlier WAR is not required as we have root caused it.
Change-Id: I350b810a6cef8eec46428e57f5b779f888552c1b
CRs-Fixed: 2677342
Currently as part of runtime PM, only the active
tasklets are being drained. For chips eg. QCA6390,
QCA6490 etc, there are grp_tasklets and delayed reg
write work which has to be drained before entering
runtime PM.
Add the logic to drain all the possible tasks
before entering runtime PM.
Change-Id: Ieb486f00fffd7346dcdc1faea6fed5850ef6daf7
CRs-Fixed: 2676000
Add prefetch_timer configuration for CE rings.
Set prefetch_timer=1 configuration for qca6490 destination CEs,
prefetch_timer=0 configuration for other targets CEs.
Basically setting to 1us asking CE hw to update ring tail pointer to
update within 1us. FW side CE SW sets all rings to 1us already.
Idea behind this change is, we have seen pre-silicon issue where SRC
ring TP read by SW was not seen updated value when prefetch was set
to 8us. Changing prefetch timer value to 1us helps to resolve
pre-silicon issue.
So host side rings need to update the prefetch timer to 1us.
Change-Id: I0830c73517c29cf39e6b2974bf3faa44e5673741
CRs-Fixed: 2669762
The delayed register write enqueue fills a queue element
with the required data which can be dequeued in a workqueue
running on a different CPU. Since these operations are not
lock protected, there can be stale value access when memory
write has not been flushed to the actual address.
Using write memory barrier before setting the valid flag for
a queue element will make sure that the dequeuing worker
thread will always see the updated values if the element valid
flag is set and thereby avoid any race condition.
Change-Id: I81b0735f0fb39599095ad309157020c691e25a0b
CRs-Fixed: 2665576
The delayed register write for srngs will have
the value of the HP/TP at the time of enqueue,
but the final value which is written to the
hp_addr/tp_addr will be determined based on
HP/TP value at the time of dequeue of the
entry for a particular srng.
Hence to know what was the exact value which
was written to the HP/TP address, add one more
element in the delayed register write entry.
This element will contain the value of the
HP/TP which was actually written to the address.
Change-Id: I73e592611fa50b106da1deda06b839cf4fbe2126
CRs-Fixed: 2658331
As a part of enabling IPA pipes, the WBM2SW2 head
pointer register is written with the number of
buffers which have been allocated initially. This
register write is a critical one and failure in
writing this register can be fatal.
Confirm the written value, when initializing
the HP register for WBM2SW2 (for IPA).
Change-Id: Ib2da3a7aa6096375cf64857721619f47c50658de
CRs-Fixed: 2620750
Initial changes for ipq5018 compilation.
Added device ID and target type checks for ipq5018 traget.
Change-Id: Ib86a371fbe66749fcb6d114e7a4a9931b684e03d
Build failure happen when use the incorrect print format for
pointer. The timer type should not be used for time difference.
Use %pK for pointer format, and change the variable type to
uint64_t for delta_us.
Change-Id: I7da553ee2a770e4498a23f16d5187dec74357635
CRs-Fixed: 2639868
In case the bus is in low power mode, the register writes (followed by a
memory barrier) may take a long time (~4ms). This can cause the caller
to block till the PCIe write is completed. Thus, even though PCI
writes are posted, it can still block the caller.
Hence, in case the bus is in low power mode (not in M0), or not in high
throughput scenarios, queue the register write in a workqueue. The
register write will happen in the delayed work context. In other cases,
i.e ,when the bus is not in low power mode or in high thoughput
scenarios, do the register writes in caller context.
Change-Id: Idf218e4581545bc6ac67b91d0f70d495387ca90e
CRs-Fixed: 2602029
Handle minidump logging using dynamic
configurablity options. Data structures
to be logged in minidump can be configured
using internal INI file.
Change-Id: I99f12b3f98c4a9c0e15c3e5d611019e6b8d0909a
Maintain a history of the register writes which
have failed. The failure of register write is
determined by reading back the register after
writing a value to that register. If the read
value does not match the value which was written
then it is termed as a failed register write.
Change-Id: Ic3423c2cbd74bf498c0d3dd8ee7ce4231054541a
CRs-Fixed: 2624475
Use static window for accessing UMAC and CE register in qca6750. For
UMAC and CE register access, separate static window is mapped. Host
accesses these registers using relative offset to window address.
Change-Id: I7940336579553f05a11f1379f635689d08508c56
CRs-Fixed: 2617684
When SAP do connection with first Ref-STA or dis-connection with
last Ref_STA, wlan host need to re-configure REO Dst ring control
register. one of the register offset is 0xA38004, host need to write
remap window register (offset 0x310C) with value 0x14 first, but
sometimes this remap window writing not work, so just use the remap
window value 0x3F left by last writing, final Dst register offset will
be 0x1FB8004 which is out of valid range.
Find that if we read back the remap window after writing is done,
remap window writing failure issue is gone. as a WAR, check register
writing result for this specific register REO_R0_DST_RING_CTRL_IX_0
always before root caused.
Change-Id: I8d385a0f974ff37bdd867d2ec946f2f46f6eff32
CRs-Fixed: 2570728
Write into hal register using three floating windows instead of one.
This change is done to avoid frequent window changes for writing into
DP and CE registers. Instead 3 windows are used. One window is statically
mapped to CE block and another window is mapped statically to DP block.
Due to this design there is no need to change the window register to
write into these blocks and write can be done on corresponding window
with single iowrite32. Similar loginc is used for ioread32.
Also modified the hp_addr and tp_addr in initialisation stage so that
hal_write will not have multiple if checks.
Change-Id: Ibb99ec4da7f63323082e46a28afbe90e1f555545
CRs-fixed: 2507441
1. Add hif_force_wake_request API to wake the
mhi and umac before reading/writing the memory region
greater than BAR+4K.
2. Add hif_force_wake_release API to release the
PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG so the
umac can power collapse again at a later point of time.
3. Add pci stats to dump the force wake status.
Change-Id: Ic6d5463ea0cdb28d9144be61da55e43033b53298
CRs-Fixed: 2478052
a. Add new macro HAL_REG_WRITE_CONFIRM to check register writing result,
enable register writing result check when do REO DST ring remap for
IPA.
b. only enable register writing result check when macro
HAL_REGISTER_WRITE_DEBUG is configured.
Change-Id: Ib52e6b0d689ccf714876b3978fa8e356f652d25e
CRs-Fixed: 2557252
Add debugging infrastructure to record every event posted to reo
command ring. The infrastructure maintains the record of the last
64 events posted to the ring.
Change-Id: Id56fc352050eb664a64b0abb767f3b4a6b4c3aa3
CRs-Fixed: 2552822
Add the following support for QCA6490:
1. Initialize the qca6490_hal_hw_txrx_ops
2. Initialize the hw_srng_table
3. Attach hal_qca6490_attach
Change-Id: Ic53c520ef804eb4fbe1434c704e9040c83011d3d
CRs-Fixed: 2522133
Currently after runtime resume all SW2TCL data and reo cmd
srng rings hp and tp value are flushed. In case of IPA
offload case SW2TCL3 righ hp value will be updated by IPA
and not by host. In case of runtime pm enable host is
setting the value to zero as part of runtime resume which
results in incorrect hp value of SW2TCL3. As part of this
change set flush event for rings which are accessed by host
during link down state and after runtime resume flush the
rings for which flush event is set.
Change-Id: I5c9afa708277cf3a6e6d5ef99447bc21f88cfdcf
CRs-Fixed: 2514621
Add device ID change and target type checks for pine.
Also remove memory war added for Hk emulation.
Change-Id: Idf531a48a03202d4fb241a92a1d671ee2b94cfbd
CRs-fixed: 2453899
Add code to replace usage of void pointers from
HAL layer and instead use appropriate opaque pointers
Change-Id: Id950bd9130a99014305738937aed736cf0144aca
CRs-Fixed: 2487250
Add code to remove void pointer usage for hal_srng
and use opaque pointer dp_hal_ring_t instead.
Change-Id: I6907f7376d7fe3c9180b8795bd96f49fead2ec64
CRs-Fixed: 2484404
Add code to remove void pointer usage for hal_soc
and introduce opaque pointer to be used intead of void
from dp layer into hal layer
Change-Id: Ia38571174c6ed79558d0f0c9cd1a0f4afaa66483
CRs-Fixed: 2480857
qca6018 and qca8072v2 uses the same WCSS block and the source
files of qca8074v2 shall be used for qca6018 as well
This will also ensure all fixes for qca8074v2 gets auto
propagated to qca6018 as well.
Change-Id: I2ead316c7ed16b6ee315bda05ce82d268ba04bbb
Observed that when IPA offload is enabled, RX packets
are not routed correctly to IPA ring. Currently only
IX0 of REO_DESTINATION_CTRL_IX registers are remapped,
which only covers 3-bit reo_destination_indication of
range 0 to 7.
Fix is to remap REO_DESTINATION_CTRL_IX2|3 registers
so that reo_destination_indication of range 16 to
31 can also be routed REO2IPA ring when IPA offload
is enabled. Upon IPA offload is disabled, save values
of IX2 and IX3 are reset back to HW.
Change-Id: I3428b450ab10076d27c7628a3729e8cec088bd94
CRs-Fixed: 2434331
Some of the print messages in HAL module come very excessively.
Use hal_verbose_debug() API to print them.
CRs-fixed: 2405028
Change-Id: I4b4754af65c00edb571de898527026b6183ef15f
Currently hal shadow pointers after memory allocation
are not memset to zero. In case of SMMU S1 enable when
host starts to access hal srng the random value of shadow
memory is copied to host cached values which leads to accessing
the rings even when HW has not updated to it. So zero out
the memory of hal shadow ring pointers after memory allocation.
Change-Id: I10ac6bfff957e953ee9caa15056ce3fa9d57b70e
CRs-Fixed: 2368491
Functions hal_update_srng_hp_tp_address and hal_set_one_shadow_config
are dumping a lot of information, which is not needed.
Reduce INFO log levels to DEBUG.
Change-Id: I210cd5493d758685312b7851eb37e05ce93b6071
CRs-Fixed: 2342960
- Support to pass IPA enabled(disabled) flag from ini to DP layer
- Use ioremap call to translate tx_comp_doorbell_paddr obtained from
calling ipa_setup api to tx_comp_doorbell_vaddr. This is needed to
write the initial value of HP at the doorbell address.
- Change REO_DST_RING_SIZE and WLAN_CFG_TX_RING_SIZE to 1023
for napier/hastings if IPA is enabled. This is needed because,
ipa_setup API can handle only 16-bit values for the size param(bytes)
of the ring.
- Disable hash based flow steering for SAP peers in case IPA is enabled
and set default reo_dest_ring_4 as default RX ring. Since IPA will be
reaping RX packets from reo_dest_ring_4 only, flow steering is not
needed for SAP peers.
- Unmap pre-allocated TX buffers for IPA in the TX completion ring.
- Donot execute IPA functionality if IPA is disabled from ini.
Change-Id: I6855bfe293a457ccc0abd1ad5567f5c95232a9d2
CRs-Fixed: 2183519
- Change the SR mapping address for QCA6390
- Use ring direction field from HAL ring config instead of HAL ring
directly as ring is not yet initialized here.
Change-Id: I900b2329367cc02ae2f9d7f164e5f867d8253d90
CRs-Fixed: 2299919
CE service file includes APIs for both legacy and lithium
architecture.
These are getting compiled for both targets today. Separate the CE
services into legacy and srng and selectively compile based on
targets present in the SoC.
Note: Generic APIs implemented for both legacy and SRNG services
are separated out through this change. Fast path implementation
will be de-coupled from common service and moved to legacy source
in a follow-up change.
CRs-Fixed: 2258640
Change-Id: If86c21c0bf560a360474c9efcdbcd4841a09828d
Some of the macro names defined in qca8074v1, are defined with
a slightly different name in qca8074v2, and few macros have the
same name in both headers but are defined with different values.
Fixed the same.
Change-Id: I5e948baf5326d1d8fdfa2bd7ee8aa072c710d17c
Clean up datapath component prints by correcting trace levels for
regularly occurring prints and removing newlines from converged
print APIs since qdf_trace_msh appends them by default.
Change-Id: Ie8fe319fcb737720f7400a165e134b6a18bd15b5
CRs-Fixed: 2243843
1. Allocate and Initialize host and target copy engine configuration
for QCA6390 based products.
2. Setup Copy engine service map for QCA6390.
3. Add conditional compilation flag QCA_WIFI_QCA6390 to support
QCA6390 based products.
Change-Id: Ia4dd4d436b8ecae0e9f91faa0c1fe7dbd14f001f
CRs-Fixed: 2259312
Removed qdf exports on functions defined in target specific
header files and defined those functions as static. Revert
changes on hal_rx_msdu_end_sa_idx_get and make
hal_rx_msdu_end_da_idx_get target specific
Change-Id: I2858b1d77118f0a26b54bf983bd342c7a4fe757d
hal_hw_srng table and register offsets array, some target specific
functions are defined separately for each new target.
define the same for qca6290.
Change-Id: I08c1243bc50460fac776e28186acfa192fb1ff66
Create separate individual hal_srng_table and hal register
offset in target specific source files. Create separate
functions for qca6290 and qca8074 for few hal rx tx
functions as the macro value differs between the chipsets.
Assign target specific hal tx, rx ops as part of hal_attach
and call respective hal tx, rx ops through callbacks.
Change-Id: Ibbf490c678c39fdd9d54191aad7aaec786db30ec
