Grafik Komit

18 Melakukan

Penulis SHA1 Pesan Tanggal
Nilaan Gunabalachandran
868fb9cb24 disp: msm: sde: fix frame event signal for cwb
Submit a cwb frame event signal to notify the crtc that cwb
is completed. Currently cwb also uses the same frame done
event as primary. When a single cwb commit is completed, because
cwb is on a slower path there is a race condition in which the
subsequent frame done event for primary clears the refcount.
This fix isolates the events and removes this situation.

Change-Id: Ic3e18302eb8a497cbd7a00f271de2ab320576c83
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-03-29 16:52:27 -07:00
Krishna Manikandan
4442431141 disp: msm: sde: cleanup writeback phys_enc structures during wb disable
Hardware structures for writeback ctl and cdm are set
to null during wb disable, to prevent crtc mode change
on primary during subsequent wfd and cwb sessions.

Change-Id: I7536203761c615c37c8633d1621951475895400a
Signed-off-by: Prashant Singh <prasin@codeaurora.org>
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2020-03-29 16:49:12 -07:00
Veera Sundaram Sankaran
20a7886cc5 disp: msm: sde: avoid vblank notification for cwb
The vsync callback for concurrent writeback is
not necessary. This would conflict with vblank
notification of primary as both belongs to the
same crtc.

Change-Id: Idb67915de086f94feb231d61b6f7e4e068a1ac35
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-03-29 09:55:00 -07:00
qctecmdr
1fc486ad3e Merge "disp: msm: sde: ctl hw flush ops clean up" 2020-03-21 13:08:07 -07:00
Dhaval Patel
2843f86793 disp: msm: sde: support fps based qos setting
Support different safe, danger and creq qos lut
configuration based on display fps. It also removes
the fill level calculations from sspp and wb block
because mdss hw supports simple configuration.

Change-Id: I203e4300c9eab27d3632c890bedd6383cca0e5a8
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2020-03-02 09:52:47 -08:00
Nilaan Gunabalachandran
f51424f8a7 disp: msm: sde: ctl hw flush ops clean up
Using individual flush functions for each active hw blk
is not scable-able for future use. Clean up the ops to merge
all flush functions into one and manage HW block id
with same API.

Change-Id: I62afbc51fa7d345b3a1f5721e5e09661a4215f7a
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-02-25 14:18:59 -05:00
Abhijit Kulkarni
616c59b000 disp: msm: sde: add support for 3d_mux DSC topology
This change adds support for dsc using the 3d mux hw block.
The 3d_mux hw block merges the input from layer mixer before passing to
dsc block for compression.

Change-Id: I21544c33fff2c1e604c0ae712a036a127d25afcf
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 13:58:06 -08:00
Abhijit Kulkarni
af5306875f disp: msm: sde: add ctl api to enable/disable sub-blocks
Certain sub-blocks need to be enabled disabled dynamically on a
seemless mode switch (for ex. partial update) CWB is another example
where control path interface configuration needs to be dynamically
changed on enable/disable of concurrent writeback. Similarly
3d mux needs to be enabled/disabled for partial update use cases.
This change modfies the current api update_cwb_cfg and makes it
more generic and adds support to enable/disable only the 3d mux.

Change-Id: I5e5a6e78b0599f689cb2f83d0d626a5f392eff6e
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 13:58:06 -08:00
Narendra Muppalla
a0b168f7b3 Config: enable techpack display driver compilation for lahaina
This change enables display drivers code compilation
for lahaina target and current location of header files
is replacing the header files in usr/include/drm directory
before installing display specific header files. This change
ensures both the drm and msm_drv header files are exported
to user mode clients.

Change-Id: If6fc347598b902e670b7206dbcb82fe0740b3984
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2020-01-14 14:10:45 -08:00
Narendra Muppalla
d1d9ae8b19 Disp: Snapshot change for lahaina display driver
This snapshot change adds downstream support
for drm 5.x+(msm_lahaina branch) linux kernel.

Change-Id: Ia691c95da155a00e449c91a2f1a5b20a8e71aed4
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2019-11-24 12:30:51 -08:00
Dhaval Patel
6f06e5cd6f disp: msm: sde: wait for specific pp_done instead of zero
2 Frames transfer pending is possible with posted start.
One ongoing frame and another triggered frame. Current SW
waits for pp_done interrupt if pending frame count is greater
than 1. It is possible that interrupt may be missed for ongoing
frame. In that case, SW should run pp_done wait for one by one
frame instead of two frames together. It allows encoder to
check the ctl scheduler status and trigger the frame done
event on time.

Change-Id: I4817842292d96747890ee70da8a5bdf9b56816ed
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2019-08-20 21:12:52 -07:00
qctecmdr
3588284310 Merge "disp: msm: sde: fix cwb, dp and wb tear down sequence" 2019-07-22 11:52:53 -07:00
Dhaval Patel
bcd97aa368 disp: msm: sde: fix cwb, dp and wb tear down sequence
CWB, DP and WB displays tear down sequence must reset
3d_merge, ctl, pingpong_binding, etc. MDP HW
blocks. This change fixes the tear down
sequence register programming. It also moves flush
sw reset before encoder_disable call. That allows
CWB tear down to update the flush configuration
on primary ctl path.

Change-Id: I21c521b39456af4144cf836c65d46a25c985f51d
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2019-07-18 14:13:33 -07:00
Lakshmi Narayana Kalavala
d28cec1b1a disp: msm: sde: fix the race condition with wb output buffers
In the case of concurrent writeback, display thread
does not wait for writeback done and the fences are released
immediately if the pending frame count is one or zero.
Also during this skip wait process, the output frame buffers are also
cleaned up. If there are couple of bad writeback frames, there could
be a race condition between frame buffer cleanup in the display driver
and DRM_IOCTL_MODE_RMFB ioctl from userspace. Hence add appropriate
ref count logic with output frame buffers while the driver is using them.

Change-Id: I1cf919b93424011c75c39bcddd296a03a9d5c4ee
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
2019-07-08 13:18:01 -07:00
Dhaval Patel
df2fbca4b8 disp: msm: sde: avoid wb done wait for cwb in wait_for_commit
Existing cwb implementation waits for WB done interrupt in
wait_for_commit_done API call. This serializes the cwb commit
and causes frame trigger delay on primary display. MDSS hw allows
to trigger the cwb frame when previous frame is in-progress. This
change updates driver to allow parallel frame trigger for cwb
enabled display. It releases frame N cwb output buffer in frame
N+1 wait_for_commit done call.

Change-Id: Id4f2a0cc78a3f24a1b5ce96dc907780246768dbf
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
2019-06-03 10:04:19 -07:00
Samantha Tran
3be27eafcc disp: msm: snapshot of msm and sde driver
This snapshot ports changes from 4.14 to 4.19 into
the msm and sde layer. Snapshot was taken as of
commit 0f8fb25421ff ("cnss2: Add device version to
SOC info structure").

Change-Id: I59b799a78319c2db6930a2a10bc38976f8c09898
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2019-05-22 13:08:31 -07:00
Lakshmi Narayana Kalavala
78560ee888 disp: msm: sde: update ds atomic check for pu and cwb
This change fixes the destination scaler atomic check
to support PU with CWB disable without an additional
frame in between. It also fixes the destination height
calculation.

Change-Id: I93ae8471d2db0b4e2574d18a873d4d4e180cbcbb
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
2019-04-24 15:22:26 -07:00
Narendra Muppalla
3709853456 Display drivers kernel project initial snapshot
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.

Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2019-04-14 22:20:59 -07:00