During cwb disable, encoder reset should be invoked to clean up
and release hw resources. This encoder reset should happen even
if cwb encoder TX_DONE is not successful to avoid rm rsvp leak.
Change-Id: I81353f19b69cb68d71f7d5b6477e37b6dab3ae00
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
This change adds hardware programming that will update the
txq wr_ptr upon output fence firing.
Change-Id: I79ff0ea5fb2b7f73a48bd70e3c8e71ea69fead95
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
For a proxy-scheduled VCPU like the TUI VM, assignment to a
physical core is a runtime decision made by the HLOS scheduler,
and it may change frequently. pm_qos vote added by PVM for
specific CPUs won't be sufficient for addressing irq latency.
This change updates votes for all possible CPUs during TVM
entry and also removes the vote during exit.
Change-Id: Iab5cb5f57e2389ee57689ba2ab69394376f59788
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Both trusted-vm and secure-camera preview buffers uses the same
VMID_TVM. In primary-vm, the check is used to determine the camera
preview usecase and attach it to the correct device. This is not
necessary for trusted-vm as it can default to nested trusted-vm
context bank. Avoid the check while its in trusted-vm.
Change-Id: I4391a4a1da9dca5d1f4b1719733b8d4edc1900a8
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
During VM transition there should be no pending crtc event
thread operations in progress to avoid any resource access
after vm release. Flush the event thread worker in prerelease
to ensure it.
Change-Id: I51d6c78a702235ee926c9ff6415c8d69f74b5929
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Add capability to read avr step for each timing mode. This will
be in addition to the existing avr-step-list which is defined
when dfps is enabled. Expose the avr-step as part of each
mode in connector caps to user-mode.
Additionally, change the avr_step connector property to enum
to give usermode just the capability to enable/disable avr-step
and not alter the step value as its fixed from the device tree.
Change-Id: I6d7f8e9fcf03f98abef7640fc741e5e1be8597a1
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Force vbif axi halt on all the power-collapse with/without RSC.
This will keep the logic simple for all targets.
Change-Id: I5a4956cbc1f5875d923d5cf818016fba7ed2c8f7
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add DCS command to read the panel scan line value and associated
time stamp in nano-seconds.
Change-Id: I06a76d3a6c5ad7a2e7681413c741e5b97b34d73f
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
This change adds support for bypassing hw access in DSI PHY/PLL
drivers which enables the DSI driver to run on emulation
platforms that might be missing those modules.
Change-Id: I3e83155a79d60f2357606746214d776cefabd651
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Signed-off-by: Alex Danila <quic_eadanila@quicinc.com>
Update the LUT DMA register range registration to target
specific ranges of valid registers instead of the full
memory region of the LUT DMA module. This ensures that
unused LUT DMA register regions are not dumped.
Change-Id: I3739692ae7fcfd5777bb8774dd34c16ab87c3ae1
Signed-off-by: Christopher Braga <quic_cbraga@quicinc.com>
This change adds a device-tree configurable property to define
the ipcc client id of the dpu used for registers access and
configuration. Starting pineapple, this is the ipcc client physical
id, distinct from the ipcc client virtual id.
Change-Id: Icb59111c85c7132c0efd7b207eaa5417cca013eb
Signed-off-by: Grace An <quic_gracan@quicinc.com>
The memblock_free API has been updated to return void. This
change removes the check on return and passes the pointer
address in correctly.
Change-Id: I8b60c8d3c5e3e8c2f94e33015c2c03686a556807
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Fix the max crtc count based on the number of real layer mixers
available. Usermode can use the crtc count to derive the number
of layer mixers. This will be used in usermode to check if a new
DP/IWE/WB session can be supported by the HW, based on the existing
displays at that point. This will avoid atomic_check validation
failures in driver.
Change-Id: I63b033604ac549fc01bccef2a9320e0befab5926
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add changes to get drm object reference for connector and
remove out fb in dual display recovery case.
Change-Id: I1fd0c4818575b3f532d51ad41285031e8320c5fe
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
This change skips msm_lastclose, when splash enabled builtin-displays
equals number of actual displays and are stuck in continuous splash.
It fixes the issue seen with change commit 548b17185e95
("disp: msm: send power_on event in dual display composer kill scenario").
Change-Id: I1f5417d8945db621dc20ab0a9cc0146eabae5e22
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
This patch cancels all the delayed_off_works if scheduled and flushes
the display threads for completion during msm_lastclose. The commit
from msm_lastclose client modeset to disable any crtcs if enabled is
always scheduled on primary crtc_commit thread. In the current issue,
delayed_off_work is scheduled on secondary display crtc_commit thread
and primary crtc_commit thread is scheduled to turn off active crtcs
from msm_lastclose leading to null dereference access of sde_enc's
cur_master. This race is avoided by serializing the operations in
msm_lastclose.
Change-Id: I30cc95b925c8134f0064816ebe2cfdb86a49fb36
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
With speculative retire fence, the first commit from HAL depends
on crtc power_on event instead of retire fence signal to unblock
the wait completion. Hence avoid triggering PM suspend/resume if
any of the displays have continuous splash enabled. This will avoid
any state changes in drm_atomic_state and will be inline with
HAL expectation.
Change-Id: I97360e3815651eefdd7e2c1494fa6e882df883b5
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
When VSYNC interrupts are delayed due to irq latencies, there is a
possibility that the timeout handler checking the irq status and the
irq handler clearing the status bit happening at the same time on
different CPU cores. This is reported as an error, though there is
not actual issue. Handle this case, by adding an additional ctl-flush
register check in the vsync timeout handler. As part of the change
add error/eventlogs in commit-done wait failures.
Change-Id: Ie7e30dc4ef1e50651cee9015cd3f2caeacf47e5f
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
On composer kill event, drm lastclose occurs during which suspend
commit gets triggered on primary. If secondary display is stuck in
continuous splash, then we do a early return without triggering
this suspend commit. On composer start, userspace waits for power on
event, but the drm_driver has never entered suspend state, so power
on event is never sent to userspace. This causes HWC deadlock side
effect and the current change triggers null_commit on secondary
display and then issues a suspend commit on both the displays to
avoid this deadlock issue.
Change-Id: I126f43ba3dd2c3bfa83346e8fd4678f35527893d
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change adds one-to-one memory mapping for the hwfence
ipcc register memory needed for hw fence feature.
Change-Id: I0e264183e02d0ed5f2254b409cc5e776d670f0dc
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Starting mdss 9.0, dpu supports triggering
the frame fetch through hw-fencing. This change
adds support for this hw-fence feature.
Change-Id: Icc7d0b69fc2a51103d14612f5ac89b44a47ed826
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Toggle LLCC SCID for each consecutive LLCC write
operations and force read allocate when NSE bit
set.
Change-Id: Ice473cb126b627056b7346f142bc84c120e05f0b
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
This change adds a connector OP, that will be used to update frame
transfer time dynamically at the request from user space.
It also adds parsing for new device tree entries that set the minimum
and maximum trasnfer times on a mode basis. These min and max transfer
times are also published to userspace through the connector mode info
capabilities blob.
Change-Id: I12aedf96a51ff7feb2c5b3b1353d3c4ec8dcb068
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
SID registers and offsets are changed in display
MDSS 9.0.0. Changes are made to program these new registers.
Also, added new revision check for backward
compatibility.
Change-Id: I4e1ea374f38c95a4d1019c2596418bb6bb7c5347
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Add check to avoid more than 1 CWB active per commit as
hardware doesn't support multiple CWB even if they are
on different OP.
Change-Id: I13416cc2af881de0d8bdd6544a4fdc180fb7a050
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
The sde power event function needs to get actual sde kms irq
number to handle irq update call, but it is not able to know
the irq number before irq installation, so move sde power event
call into kms post init to avoid unbalanced irq issues.
Change-Id: Id262b86f98299fbb9a51c9ccb8e68c7bde7f57ed
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
The splash memory initialized by the bootloader needs
to be released after the first frame update. Add
memblock_free() call to release this memory that was
reserved during the kernel boot.
Change-Id: I463139a3f930dd9284d3ba9516714ead0c77cc02
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Drop refcount on pm_suspend commit state if atomic
commit is skipped due to failure. It will avoid frame
trigger during pm_resume call.
Change-Id: Ib650ff348ef53122cccad9cb5d200ae295fd2b30
Signed-off-by: Dhaval Patel <quic_pdhaval@quicinc.com>
Use #if IS_ENABLED() instead of #ifdef for configurations as vendor module
guidelines.
Use #if IS_ENABLED(CONFIG_XXX) instead of #ifdef CONFIG_XXX to ensure that
the code inside the #if block continues to compile if the config changes
to a tristate config in the future.
The differences are as follows:
1.#if IS_ENABLED(CONFIG_XXX) evaluates to true when CONFIG_XXX is set to
module (=m) or built-in (=y).
2.#ifdef CONFIG_XXX evaluates to true when CONFIG_XXX is set to
built-in(=y) , but doesn't when CONFIG_XXX is set to module(=m).
Use this only when you're certain you want to do the same thing
when the config is set to module or is disabled.
Change-Id: Ia806b9b01ad8414d0e4de027a382cb68e7fb4a6a
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
The HW support for RGB pipes were removed from MDSS 3.x and cursor pipes
from MDSS 4.x. Remove the support from s/w as well with this change.
Change-Id: Ib5b363234e200ee5c421684cf1904a38a5d90b58
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
pm_runtime_get_sync increases the usage_count refcount immaterial of
success/failure of the call, leading to invalid refcount on failures.
Use pm_runtime_resume_and_get instead, which takes care of reducing the
refcount on failure cases before returning from the function.
Change-Id: Ib96050d5d7ecbd717e58b8a0dde2d03312444e15
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change acquires the vm lock before pre-releasing the
dependent drivers. This avoids any race condition on any
parallel async commands transfers scheduled on connector
drivers. Additionally the main irq line is only disabled
after the pre-release to allow any ongoing transfers
to complete.
Change-Id: Ic0bffc93ebb1b69fbd8d1f096b320a86ad84c857
Signed-off-by: Abhijit Kulkarni <quic_kabhijit@quicinc.com>
If vm has already transitioned from primary to trusted,
triggering a wb/secondary display commit will result in
crash since hw is not owned by the vm. This change adds
necessary changes to fail atomic check in such usecases.
Change-Id: Ic9886d479726c27d1072d12304a87f3bf5deeb76
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
This change adds support in mdp and dsi driver to support
multiple SIS.
Change-Id: I432068cea17e1784d7570a472fbadaa86695df07
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Currently, cwb disable path issues a cleanup flush & waits for the
commit-done. Wait for the tx-done to ensure the transfer is complete.
Change-Id: I509711c157f1d6646646ad96ed140d6bc76d2dba
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
This change sends a notification to user mode after msm_drm
driver releases the mmio and irq resources on trusted vm transition
request. This is required as user mode has no other way to know
when the resources where actually released. User mode driver earlier
relied on retire fence signaling but retire fences are send before
releasing the hw.
Change-Id: Ia218cfcbf398b2de1ad9578fb9baedf348b067df
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This change moves TVM related code under SDE VM config.
Change-Id: I8357d6a984fd97f18f24eee33464299e8ea66b12
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
Align the HW catalog to use common naming amongst the "revision"
and "version" structure members.
Change-Id: Ib6c81aee6cb49208b0699db4a75b4eb9dc79e800
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
Move all the individual boolean flags from HW catalog into a
"features" bitmap. These flags are used to specify support of
various target specific features.
Change-Id: I2334b3b873f3737f91bbae4ef576408247710156
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
