The DP debugfs node for CRC read currently does not check
if the panel is enabled before attempting the read. This
could cause unclocked access of DP registers. This change
adds the necessary protection and bails out if the clocks
are not turned on.
Change-Id: Ia555e2473fc9f0f7434ee3665eb4fb7cfb4f97cf
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Some rate limited logs in dp aux and dp ctrl are using
pr_err_ratelimited function to print the logs instead of
the standard DP log macros. So this change adds a new
ratelimited DP log macro and make the logging consistent.
Change-Id: I75d7306d94c7c360783f39259c509c32fe59cdf5
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
When calculating the Rate Governor parameters for MST, if the
stream is compressed, the calculator expects the input bpp to be
the compressed bpp, but currently the driver is passing uncompressed
bpp. This change updates the driver to pass compressed bpp to the
calculator.
Change-Id: Iac51d75843bd0072bbe07142ac4533d841f795f5
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Convert clock operation to byte2 ops to meet DISPCC requirement.
Clock unit is changed from KHZ to HZ. Added link clock parent as
freq table is no longer supported in byte2 ops.
Change-Id: Icf5a595708040e8afefecebe7f371bb832d6673e
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
This change adds a debug node named 'crc' to drm_dp to read
the frame CRC values for DP controller and DP Sink. In order
to facilitate the immediate read of the CRC values when
accessed, it enables the CRC calculation on the controller
and sink automatically when the stream is enabled. In addition
to the frame CRC values it also reads the MISR values from
controller and PHY to validate the data flow from controller
to PHY.
Change-Id: I1acee2dba931e4635caf4a400e336a72c86e88bf
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
DSC enable status is updated in DP panel struct as per the DPCD reg
read which is done at the start of the HPD ISR. However, there is a
chance that DSC is actually disabled later during mode query due to
shortage of DSC blocks. This status is stored as part of compression
info structure. This change checks for the latter struct to determine
the actual DSC status.
Change-Id: Id7cd4e65060f2ec939f945e9ac4f4e66260605d3
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change updates copyright description with correct
license marking as per the guidelines.
Change-Id: Ia74b721e78afcc7f8e88bcbccfcf15430111ec37
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
During link training, after the swing/preemphasis is updated, the driver
is supposed to poll the link status on the sink and quit once the
LINK_STATUS_UPDATED bit is set and also latch the next set of
swing/preemphasis requested by the sink. But currently, the driver is
exiting the loop only when the LINK_STATUS_UPDATED bit is cleared. So,
it also latches the swing/emphasis request from the second read.
Typically, the SW read is slow enough that the bit is set on the first
read. The driver then reads the second time and exits the loop, since
the bit would be cleared then. In most cases, this doesn't affect
the training sequence, since the swing/preemphasis request for next
attempt is retained on the second read. But, atleast in one
specific case, it was observed that the swing/emphasis request
gets reset along with LINK_STATUS_UPDATED and so the driver ends
up missing the actual request and latches incorrect values instead.
This causes link training to fail as it keep retrying with the
same values that it starts with.
This change fixes the exit condition check so the driver quits the loop
as soon as the LINK_STATUS_UPDATED bit is set.
Change-Id: I7f5d9c6b30d48e113aef628d2ab2c1bd972fe743
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
In an effort to reset the DP controller states on a disconnect, the
driver is issuing a SW reset to the controller. But SW reset on
the controller doesn't necessarily restore the controller to its
full reset state. It only resets part of the logic. So if for some
reason the MST streams were not disabled properly, ie. the slot
allocations were not reset properly in the controller, then a SW
reset would result in the DP controller raising state interrupts.
Since this SW reset is issued in the tail end of the disconnect
processing, the driver turns off all the clocks and also
removes the irq handler. This results in an interrupt storm at
the MDSS top level.
This change removes the SW reset on the disconnect path and
relies on the SW reset that already exists in the connect path
to restore controller state.
Change-Id: Ie7115e17d3c50c46c83c6f0e333da5cb534b8227
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
During link training, after the swing/preemphasis is updated, the driver
is supposed to poll the link status on the sink and quit once the
LINK_STATUS_UPDATED bit is set and also latch the next set of
swing/preemphasis requested by the sink. But currently, the driver is
exiting the loop only when the LINK_STATUS_UPDATED bit is cleared. So,
it also latches the swing/emphasis request from the second read.
Typically, the SW read is slow enough that the bit is set on the first
read. The driver then reads the second time and exits the loop, since
the bit would be cleared then. In most cases, this doesn't affect
the training sequence, since the swing/preemphasis request for next
attempt is retained on the second read. But, atleast in one
specific case, it was observed that the swing/emphasis request
gets reset along with LINK_STATUS_UPDATED and so the driver ends
up missing the actual request and latches incorrect values instead.
This causes link training to fail as it keep retrying with the
same values that it starts with.
This change fixes the exit condition check so the driver quits the loop
as soon as the LINK_STATUS_UPDATED bit is set.
Change-Id: I7f5d9c6b30d48e113aef628d2ab2c1bd972fe743
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
In an effort to reset the DP controller states on a disconnect, the
driver is issuing a SW reset to the controller. But SW reset on
the controller doesn't necessarily restore the controller to its
full reset state. It only resets part of the logic. So if for some
reason the MST streams were not disabled properly, ie. the slot
allocations were not reset properly in the controller, then a SW
reset would result in the DP controller raising state interrupts.
Since this SW reset is issued in the tail end of the disconnect
processing, the driver turns off all the clocks and also
removes the irq handler. This results in an interrupt storm at
the MDSS top level.
This change removes the SW reset on the disconnect path and
relies on the SW reset that already exists in the connect path
to restore controller state.
Change-Id: Ie7115e17d3c50c46c83c6f0e333da5cb534b8227
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Commit 1ef7ff2 ("disp: msm: dp: pass drm_dp_aux to drm_dp_link_train* APIs")
passes additional parameter drm_dp_aux to drm_dp_link_train APIs in order
to use drm_dbg_* within those functions.
This change put a macro in the drm_dp_link_train* APIs caller to handle API
changes for both kernel version 5.10 and version 5.15.
Change-Id: I9fd22e0effbe87b6cfecf72b38a10d74a2c0c5ea
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
If MST is enabled, the controller needs MST ACT to be
completed to successfully transition to 'Ready for Video'
state. The driver is sending ACT during the normal flow
when transitioning from link training to stream enable.
But it is not sending ACT, if a link maintenance is
triggered after stream enable. This change adds the ACT
update to the link maintenance call flow.
Change-Id: I7aea53a1e54202f1d9059a8eb59f01fa97fe9eb9
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
Pass additional parameter drm_dp_aux to drm_dp_link_train APIs
in order to use drm_dbg_* within those functions.
Change-Id: Icc111ecce78fbbac77eb044ce4200377d3616fc9
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Add safety checks to check for dp link and core clocks before accessing
the main control registers during dp teardown or dp setup.
Change-Id: Ic80050b7c1cec59d7fc27a1c5f12fa1b244f86fb
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Currently the DP driver always uses a compression ratio of 3, if
DSC is enabled. So if the sink supports 30bpp, the compressed
output is set to 10bpp. But since the hardware supports
compressing this to 8bpp, it would require less link bandwidth
than 10bpp compressed output. For compliance testing, the
test equipment limits the link bandwidth based on the most
efficient compression ratio and for some resolutions there
is not enough link bandwidth for 3:1 compression.
This change always sets the compression output to 8bpp to
minimize the link bandwidth utilization.
Change-Id: Ifa6129444c2bab4e9c357ddfe49f76efa5b04be0
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
FEC is a link specific configuration and should be configured before
the MST streams are enabled. Currently, the driver is configuring FEC
for each stream and in a case where the first stream is compressed and
the second stream is uncompressed, it enables FEC before the first
stream is enabled but ends up disabling FEC when the second stream is
enabled.
This change splits FEC/DSC configuration into separate functions and
skips FEC configuration for the second stream.
Change-Id: Ic1bab321dc77da7ec5c0253c93bb69735a217fd6
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
Currently, the max voltage swing supported is level 2. This change
adds support for voltage swing level 3 in the dp driver.
Change-Id: Idf1dbb4e74edff924067130a5edea869f392bf38
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
This change adds the support to request the dp link clk rate
through the mmrm driver. In the case the system can not
support the rate, user space is notified of the failure and
dp is diconnected.
Change-Id: I4a074054ce42425ca940d4aec505723724736b44
Signed-off-by: Christina Oliveira <coliveir@codeaurora.org>
The current pll driver models the entire DP clock
hierarchy using the clock framework. This creates
unnecessary dependency between the dp driver and
the clock driver and also limits the flexibility
to dp driver when configuring the DP clocks.
This change models these clocks as single nodes
and provide full control to the dp driver and
also minimizes the dependency on the clock driver.
Change-Id: Id5221441ea33b576e7c543396a12cbeb7b44d319
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
On the latest kernel, several drm_dp_link functions were removed.
This change moves the functions needed downstream.
Change-Id: I0a76c52edff450d8bd33edffb9da41c1933b9681
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Remove all debug logs and replace them with event logs in the isr
path. This change will reduce the likelihood of an interrupt storm
causing a watchdog bark if display threads are being prevented
from completing execution due to debug logs holding the console
lock.
CRs-Fixed: 2810115
Change-Id: I906f19fb73a7501114fd0a62e9ae66c83dde4d5d
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Prior to Makena, hardware requires SW to retry FEC EN sequence when first
attempts fails. This is needed because hardware doesn't prevent FEC EN
logic to be inserted while BS symbols are sent. Which can lead to some
sink device to not being able to detect FEC EN sequence.
This change implements HPG guidelines, by monitoring FEC_STATUS and
retrying 3 times before failing the enable call.
Change-Id: I350eabe31d39f619e536ef87648874b4d58a7292
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
The lane_count used for validating the display mode
to be set is wrongly taken from the initial panel
capability. So, when lane count is reduced during
link training, the reduced lane count will not be
considered for validating supported modes. Hence
reporting incorrect display modes.
This change will use the correct lane count which
is obtained after the link training sequence.
Change-Id: Iab6239280c29961f7bc6f945ff3ecee9954b0b73
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
Reinitialize video_comp completion variable before using it again
to wait for interrupt.
Change-Id: Ifc105eaa758d85ef604a440b3be7adfdafe7fc0f
Signed-off-by: Rajat Gupta <rajatgu@codeaurora.org>
Skip link training when in simulation mode considering that we
are not yet implementing tests specific to link training. This
change will reduce the time it takes to power on the panel in
simulation mode, and also reduce the likelihood of failures
caused by unresponsive host machines.
Change-Id: Ie215cafd545bb25b4a033ceae1f275c690e7433d
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
This change adds more debug logs and event logs to MST callflows
to help with MST stability issues.
Change-Id: I9053eab5932487fccce522cc17ed2e9fb8d887ab
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
While running DP simulation script for stability and the rare
occasions when link clock fails to enable, the ctrl power_on
flag is wrongly set indicating the link is powered on. This
flag is used in the ctrl sub-module to check that the link
clock is on before accessing the registers powered by the
link clock. When this flag is wrongly set, the link registers
are accessed while processing the cable disconnect to cause a
NOC error.
The change will ensure the power_on flag is set when the link
clock is on so that the access to registers in the link clock
domain can be correctly filtered by the power_on flag.
Change-Id: I40af054a5738172f5ea86079a9258518f8fdd44e
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Exit stream enable on cable disconnect considering that the
controller and display modules would have transitioned to aborted
state. It is possible that the disconnect might have prevented
the link clock from being enabled, so we have to skip any register
programming in the link clock domain. We remove the unprepare
call from the DRM wrapper error handling since that path can lead
to unclocked register access when the link clock is not enabled.
Change-Id: I92595c0824193df63c2746bc8cd644f59c33604a
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
During resume, DP uses AUX to perform various functionalities
like DPCD/EDID read or link training etc. This involves other
hardware modules as well like USB and Charger. In a situation
like continuous suspend/resume, while DP is processing resume,
suspend can trigger resulting in dependent hardware modules
to go to sleep. As AUX communication is hardware interrupt
based, this can result in unstable system.
Abort all functionalities before going to suspend to
avoid unnecessary AUX and other functionality failures.
Change-Id: Id52d408270232adf7258a7eb064ee969eba4be71
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
As overall display driver is moving away from hard-coded compression
ratios, prepare the DP driver for the same by removing the usage of
the compression ratio enum.
Change-Id: I298db7d20baed8afec9f96dff8c7e950702bfec9
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
This change enforces dp, dsi and the sde drivers to use the
drm framework defined dsc_config data structure. As a part of this,
it introduces the sde_dsc_helper API to configure the dsc params
and creating a PPS command. Earlier each driver implemented it's
private versions leading to duplication of code. Additionaly the
helper api supports DSC spec 1.2 422 and 420 mode.
Change-Id: I25933fab08cdabbc6787079926885d1a78945e97
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
When doing multiple immediate plug-unplug, the DP display
driver is waiting for a link training to exhaust the retry
count before processing the disconnect request while flushing
the connect_work. The driver should stop link training and
exit if the link is disconnected. This change will use the
ctrl_aborted flag to early return from link training and
perform the host init/deinit and host ready/unready in pairs
while handling connect/disconnect to reset the abort flags
for the next connect.
Change-Id: If321136ecf12ab2f67d13ef841f1590142aad406
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
Ensure that the driver is handling DSC and FEC
enablement properly. FEC can now be independently
enabled without DSC. FEC configuration is also
now performed after link training in order to
avoid link training failures as per the DP spec.
Consequently, DSC can now be left on during
compliance testing. For DSC use-cases, ensure
that the minimum supported bpp is set to 24, as
required by the DSC spec.
CRs-Fixed: 2517994
Change-Id: I40339585da5b4e51251a3be7119b6959954954d7
Signed-off-by: Fuad Hossain <fhossain@codeaurora.org>
Use one level lower test pattern in case the current
test pattern fails to train link. This helps with few
monitors which sometimes fail with a selected test
pattern. Instead of failing the link, try with a lower
test pattern.
CRs-Fixed: 2507729
Change-Id: I394253398f49b03084dc547dacaededa49a9c527
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
DP specification mandate test pattern #4 for CTS 1.4a. Add
support for the same in link training #2 as per specification.
CRs-Fixed: 2490128
Change-Id: I2f72fec340b56270e7fd1c2940adafe1068bab43
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Adding prefixes for error, debug and info
messages in dp files. To enable debug logs
run "echo 0x100 > /sys/module/drm/parameters/debug"
CRs-Fixed: 2493739
Change-Id: Ibf509e837f527be6bff6b7a1c34b0cde2921b388
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Break the host initialization and de-initialization to
create late initialization and early de-initialization.
Call host init/deinit on physical connect/disconnect only
As attention messages from sink doesn't change the physical
cable configurations, call only late init/early deinit in
this case to avoid unnecessary hardware resources
re-initialization.
CRs-Fixed: 2490128
Change-Id: Ib930d250724ab3ea811a7388c7ad0aeae1164e21
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Update the PLL and PHY power on and clock set sequence as per
the hardware recommendations. Move the post link clock phy enable
part to the catalog so that it can be programmed after enabling
link clock.
Change-Id: I9b3b49e5a9ac93bebcb1cb7da63b715a8d5ed85c
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Add support for new requirements in 1.4a CTS which need
to try link training 1 on different lane counts and link
rates.
CRs-Fixed: 2458753
Change-Id: I2039822f420a73232df7293afcddd7bee263c7b4
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Update the link training process along with the AUX
communications during link training as per hardware
recommendations.
Update the pre-emphasis and swing values for active
lanes only instead of all lanes.
During link training, update pre-emphasis and swing
values in hardware first and then update sink.
CRs-Fixed: 2458753
Change-Id: Ie05c9d6508b0c564b194032ae4ebb1bc5550e7b8
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
