HAL generic APIs which use HW definitons that
do not have same value across all lithium chipset
are moved to header files. So that these will be
compiled with appropriate header files
Change-Id: I6c167afa4212c5e884f5e18ff1ccb3bbbba8f5f5
Currently the hardware srng register offset is statically
assigned to the handle. This can lead to incorrect index access
when targets (eg: wcn7850) is added which require additional
register offsets to be stored in the hw srng register offset table.
Move to the index based assignment of the srng register offset.
Change-Id: I8e38bdd0c28068029a0267fce706edf4378b9df8
CRs-Fixed: 2965081
Assign th HAL TX/RX ops in a function instead of assining a structure
directly. This can be later extended to have default ops for a family of
chips and then override that with chip specific ops.
This also helps the case where a new hal_soc->ops needs to be added.
The new 'op' will need to be added to only a default ops initializer
(with assumption that it applies to all chips).
Change-Id: Iefa23d14110fa5252444fad89737a3b2b2fbab6f
CRs-Fixed: 2891049
Currently the FW configures the mac with appropriate
offsets for rx pkt tlvs using the structure defined in
te FW and the host does not send the ring selction config
HTT message. This can create a problem when FW stops subscribing
to tlvs or changes its rx pkt tlvs offset.
Fix this by configuring the rx pkt tlv offsets via HTT
ring selection config message.
Change-Id: I1a2865f91b34dd7bda1af8651d7831097dac0bee
CRs-Fixed: 2860504
Change hal_hw_txrx_ops struct to designated initializer syntax for
structs for 6750.
Change-Id: I6a6728eb9d5f7f9c3256a087726abd9a627fd14d
CRs-Fixed: 2837917
Add hal_rx_msdu_get_reo_destination_indication API for QCA6750
target. Add NULL check to avoid possible null pointer dereference
for targets API is not supported.
Change-Id: I2c78e16a6796b0b09834cb91749244357f3de753
CRs-Fixed: 2793284
If frames from the same FISA flow goes into different REO2SW rings, it
will result in an unexpected FISA behavior. This can happen if the
frames have been reinjected from FW offload module since FW will select
REO2SW1 ring. If the same flow frames hash to other REO2SW rings, then
the same flow UDP frames will do to different rings.
Reo_destination_indication of 6 indicates if the frame has been
reinjected from FW. If so, then continue to deliver the packet without
FISA.
Change-Id: I14a17a10d04909adfb30557d58beb1610e59bf70
CRs-Fixed: 2790292
Adding write/read APIs for accessing the CMEM.
Currently in QCA6750, UMAC and CE windows are statically mapped,
a new static window for CMEM is added for CMEM transactions.
Change-Id: Ie10b33a6f468c6e4db314ea85856414962ef29e3
CRs-Fixed: 2771193
Rxdma decrypt errors are observed when the association
is in progress as AP sends encrypted data packets to
DUT-STA. As part of the rxdma error handling, excessive
prints are logged to console resulting in an assert.
Fix is to rate limit rxdma decrypt error related log
Change-Id: I2ef28c635d77e3acafd067b921cdb13c277756c7
CRs-Fixed: 2725335
Due to changes in datapath init/deinit path, mon_lock spinlock was not
getting created. Create mon_lock spinlock during
dp_rx_pdev_mon_cmn_desc_pool_init.
Add null check to validate rx_tlv_header before calling
hal_rx_mpdu_start_tlv_tag_valid.
Change-Id: I41c781de29f2c8c05ec1bfa90f9c8f742f2539bf
CRs-Fixed: 2693687
Size of the TLVs have changed across generation of chipsets
Offset values need to be configured into DMA register for preheader DMA
Added APIs to get offsets of each TLV based on chip type
Change-Id: Ic011332cbf3a1017f324f246e47c9e2c91441c70
Support RX 2K jump/OOR frame handling from REO2TCL ring.
(a) configure REO error destination ring register to route 2K jump
/OOR frame to REO2TCL ring.
(b) for 2K jump RX frame, only accept ARP frame and drop others,
meanwhile, send delba action frame to remote peer once receive first
2K jump data.
(c) for OOR RX frame, accept ARP/EAPOL/DHCP/IPV6_DHCP frame, otherwise
drop it.
Change-Id: I7cb33279a8ba543686da4eba547e40f86813e057
CRs-Fixed: 2631949
In QCN9000, wbm release ring has msdu continuation bit
support for invld peer MPDUs. Host needs to form SG
buffer for packets with msdu continuation bit set
Change-Id: Ica03c78068d32d2c8dc609b9a50298b91dd48c0a
For qca6750, update the SHADOW REGISTER OFFSET value and
fix the compilation issue.
Change-Id: Ic4b44c1c40e62ddcc50c0a66d37c0663a70b5c54
CRs-Fixed: 2633044
Use static window for accessing UMAC and CE register in qca6750. For
UMAC and CE register access, separate static window is mapped. Host
accesses these registers using relative offset to window address.
Change-Id: I7940336579553f05a11f1379f635689d08508c56
CRs-Fixed: 2617684
Update CE registers offset during hal srng configuration
and configure CE IRQ for qcac6750.
Change-Id: I4fd3d37783361f0029c7ef80e32425f8790d1250
CRs-Fixed: 2617699
Move HAL_RX_MSDU_END_DA_IDX_GET macros to chip specific header file.
Fixing compilation failure for 6490 and 6750.
hal_rx_msdu_packet_metadata_get_generic need not be chip specific,
macros defining the function are already chip specific.
Change-Id: I940a289662bdeddfbf99fae2a80d7796334832e7
CRs-Fixed: 2595314
Rather than extracting msdu end pkt tlv information per field basis
during fast data path, extract msdu end pkt tlv information at once
and store in local structure.
Change-Id: I0877ba4f824d480cc0851c72090f010852d0d203
