The height and width of ROI alignment must be integral multiple of
DSC slice height and width.
Add a check in partial update DT parsing function and disable
patrial update when panel ROI alignment can't match DSC slice
settings.
Change-Id: Ib80ca1cde5041936f9525e19757e95ff5898137f
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
Add capability to read avr step for each timing mode. This will
be in addition to the existing avr-step-list which is defined
when dfps is enabled. Expose the avr-step as part of each
mode in connector caps to user-mode.
Additionally, change the avr_step connector property to enum
to give usermode just the capability to enable/disable avr-step
and not alter the step value as its fixed from the device tree.
Change-Id: I6d7f8e9fcf03f98abef7640fc741e5e1be8597a1
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
devm_of_pwm_get is deprecated and need to change
to devm_pwm_get.
Change-Id: Ibeee90261ff40dc50b6a5e40e583bee11a5b177c
Signed-off-by: Maria Yu <quic_aiquny@quicinc.com>
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
For calculating bit rate in cphy, we multiply bit rate by a factor of
7/16 where 7 is the number of symbols and 16 is the bits per symbol.
But we are currently not considering the 7/16 factor while calculating
minimum bit clk value for command mode which is resulting in a smaller
bit rate value than the minimum bit clk.
Bit rate should always be greater than the minimum bit clk which otherwise
can lead to discrepancies. Correct minimum bit clk calculation for command
mode, by multiplying a factor of 7/16 if cphy.
Change-Id: I39b202dcafe60e2047549f84ff9388b46ae490a5
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
This change fixes printk arguments in display driver which is
found with additional compilation flags and adds the compile
flags too.
Change-Id: Ic653591db49b49b9ce1ce04e7df89216772d0e71
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Sim panels are not working well with video mode, parse panel ack
disabled property to fix sim video mode identification issue.
Change-Id: Ife3b533d5a6db97618459dacf1f7ce8d3fc896bf
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
Add line insertion support for sspp, this is used to support
display with external splitter. Line insertion logic checks
the difference between screen logical height and physical
height. If any difference is observed adds dummy and active
lines on screen.
Change-Id: Ieec322273df000a53fb39e05174c2d67c3c2da81
Signed-off-by: Rajesh kv <quic_kvrajesh@quicinc.com>
In transfer-time calculation remove fixed prefill lines assumption
and consider max of default prefill lines, prefill lines
specified from the panel timing info and Vtotal. For panels with
higher porches exceeding default prefill lines, alternate framedrops
can occur if transfer-time exceeds RSC static waketup time
as actual prefill lines are considered in RSC static wakeup timer
calculation. This change ensures transfer-time is within
RSC static wakeup time.
Change-Id: Ic489d69cf99cfb6750e871c7fc8197243f61acf3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change adds a connector OP, that will be used to update frame
transfer time dynamically at the request from user space.
It also adds parsing for new device tree entries that set the minimum
and maximum trasnfer times on a mode basis. These min and max transfer
times are also published to userspace through the connector mode info
capabilities blob.
Change-Id: I12aedf96a51ff7feb2c5b3b1353d3c4ec8dcb068
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Fix the Watchdog timer load value calculation with jitter feature.
Change the long term jitter value check to have jitter < 10.
Change-Id: If834e16d3b8fad5009642e479f529fa5b7cf2d17
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This reverts commit 6547137f7b.
This change can cause negative mdp_transfer_time_us for the panels with
VFP as big as panel active height.
Change-Id: Ibebfcacd9c4eddf80749fa55509821b332fba4cf
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
In transfer-time calculation remove fixed prefill lines assumption
and consider max of default prefill lines and prefill lines specified
from the panel timing info.
For panels with higher porches exceeding default prefill lines
alternate framedrops can occur if transfer-time exceeds RSC static
waketup time as actual prefill lines are considered in RSC static
wakeup timer calculation. This change ensures transfer-time is with
in RSC static wakeup time.
Change-Id: I3663f9c9179efb7225a748f456f2a2cf167d241e
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
In certain usecase where qsync is enabled without qsync
min fps list, incorrect list length might cause issues
while populating modes. This change sets qsync_min_fps
length to zero if its empty which resolves such issues.
Change-Id: I23083d8fd9610665dad63188f5d2db7eb6b23ee1
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
API got deprecated in kernel 5.15. Remove the usage.
Change-Id: I10c4fdee1074fcf50ae4fe28124692dae7a31c7c
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Add new properties to support dynamically turning on and off digital
dimming and setting new minimum backlight.
Change-Id: I3b94190877d556768ba2c92ec59432dec44de0de
Signed-off-by: Ping Li <pingli@codeaurora.org>
The controller flags need to be reset for each command. On resetting
it only for a batch of commands, it may carry stale values and cause
unexpected behavior.
Change-Id: I8473be0c4361965a58c33a3d45420c533d48646b
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Update dsc configuration and pps programming for 422 and
420 encoding as per the DSC hardware spec.
Change-Id: I4251614cdcd550ed724b1d0dba4846cada4b5392
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
This change adds support for qsync min refresh rate per
timing mode and populates qsync min refresh rate based
on the current fps when qsync is enabled.
Change-Id: I191d1d72e95dd065c8c0b56a6100104c00c6d8f6
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Currently when RFI is used on a video mode panel the horizontal or
vertical front porch values can be adjusted to maintain a constant FPS.
When this feature is enabled, driver is not propagating the new
htotal or vtotal values to usermode for accurate BW and MDP clock
calculation, which may lead to underrun in some usecase.
This change publishes beforehand all the RFI related timing
such as compensation type, hfp or vfp and clock values for
each mode for accurate BW and clock calculation.
Change-Id: Ib89c5e318fe978b0ae2215dedc430e057a9a81b9
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Some panels may require that the DSI link returns to the low-power
stop state (LP11) after transmission of every line. If a panel
requires that the DSI link returns to LP11, apply the LP11
insertion between lines feature.
This change adds support to
- Disable the command mdp burst mode
- Enable mdp idle ctrl
- Program the No. of dsi pclk cycles of idle time to
insert between command mode mdp packets. The idle time
must be long enough to cover the time link takes to
switch between HS to LP11 mode.
Change-Id: Ie718d334f05ce6c1ecd1a05b379bbbe18dec6330
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
The CASET and PASET commands can be batched together and sent using the
MIPI_DSI_MSG_BATCH_COMMAND flag. This was during pre kickoff there is
no unnecessary wait between the ROI commands.
Change-Id: I96ce30367f66024dc56f67bc1f113cac36353a9b
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Use tlmm api to retrieve and populate address mappings of
the panel gpio pins participating in the VM swtich
on Trusted UI.
Change-Id: Ibf2d13eac3fe907b729f4c2b54c63a3808022583
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
DSI driver stubs out GPIO parsing in trusted vm. Add support
for ESD trigger in trusted vm by explicitly parsing the
reset gpio and setting the value.
Change-Id: I8c04e4b27b234eb236ec51df633c06738f2a5c96
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
At present, the sim panels and physical panels booting up as sim
panels have a call flow issue causing reset gpio to be set in the
panel reset sequence even without valid reset gpio. This causes
GPIO warnings as it tries to set value for invalid reset GPIO.
The following change fixes these GPIO warnings, by checking
valid reset GPIO before setting value.
Change-Id: Id8f54a563c61dd3d244d31b10081042e376287d4
Signed-off-by: Santosh Kumar Aenugu <santoshkumar@codeaurora.org>
DSI or panel configurations might be changed dynamically, so clear
ctrl_flags of private DCS command to regenerate it according
to current display configurations.
Change-Id: Iddfcbe7f14de65ed0edf408a75b0a50bdb0a2d29
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
If RSCC solver is disabled, the transfer time calculation can be
skip using TE jitter. This case threshold time becomes prefill
time + DCS command transfer threshold. The threshold for DCS
command transfer is configured to 40us.
Change-Id: I1260df33e9d928aacd8961bdedfcd136563a806b
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change adds allowed_dsc_reservation_switch to determine if
dsc seamless switch is supported for DP. Also, based on the
flag, it determines and populates the required number of
available resources for DP.
Change-Id: I9cd7219a50d352369c5bc8386ce7dc25c30b80b6
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Mode information apart from the fields in
drm_mode_modeinfo that can trigger a modeset like
dsc-nondsc, video-cmd are defined in sub mode.
For each mode in connector->modes there can be
multiple submodes.
Change-Id: Ib8697d3fa4ea5261d9ac4943b1a4149e22c4da2f
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
For higher refresh, to provide higher transfer time we need to disable
RSC solver in MDP. This can be configured through the panel timing node
devicetree property. This change adds the parsing of the devicetree
property.
Change-Id: I9e708325da35086d2f955cbcc80bb164ccb116cd
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
For simulation panels, GPIOS are not needed for panel bootup.
This change handles GPIO parsing, toggle sequences in
simulation panels.
Change-Id: I0a3f03d1958ffe9079a7d9fef3f412e2445b0b9b
Signed-off-by: Santosh Kumar Aenugu <santoshkumar@codeaurora.org>
Some panels require a fixed step rate for a particular mode.
This change allows DSI panels to specify a single supported
step rate for each nominal fps rate which SDE will enforce
during atomic check of AVR parameters.
Change-Id: I049415449bc88ccd396fced16d4534251eac3a06
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
In CPHY, packet header and checksum is sent twice and SYNC is
sent in between two headers. So, increase packet overhead used
in clock calculation to 15 bytes. Packet Header: 8 bytes,
CRC: 4 bytes, SYNC: 2 bytes and dcs command: 1 byte.
Change-Id: I7a1160cbb57ba4f1faeb4b36a16c322e6069d58f
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
In trusted-vm, there are no power cfg entries in device-tree as
there is no support. Add stub function to avoid parsing errors
related to power cfg in trusted-vm.
Change-Id: Id28ad9a4d5608d561e22b318a08c6bc1ccc5f2ee
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
The order of the panel timing nodes specified in the device tree is
not guaranteed to be the same while being parsed in the driver. This
results in unintended modes being set as preferred timing mode. The change
introduces cell-index property, so that the timing modes can be
accurately indexed and parsed.
Change-Id: I8ccd4d5a15643bfe72bc8be084f5e91fac26feb4
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Change adds support for enabling splitlink sublinks video data swap.
Change-Id: I731b85a5e8fe8638005433819957dd0658f72963
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Panel GPIO's pins can be provided through DT or firmware data.
Use dsi parser util in consistent with other node parsings to
read their values.
Change-Id: I6dc687516aa0ce51fc56e54f4b5cbadc17f0dc1d
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
