The clk_ctrl_cb and post_cmd_tx_workq callbacks are assigned
to individual ctrl during display bind. In case of dual display
with shared DSI, where primary display has ctrl0 & ctrl1 and
secondary display has ctrl1, the callbacks of ctrl1 of the
primary display gets overwritten with the callbacks of ctrl1
of the secondary display.
In the shared DSI design, only one display will be active at
a time. So, move the callback assignment of clk_ctrl_cb and
post_cmd_tx_workq to display prepare to fix this.
Change-Id: Ic02fa2f00c430fd5759400e06d82d004d4f7cba4
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
Add capability to read avr step for each timing mode. This will
be in addition to the existing avr-step-list which is defined
when dfps is enabled. Expose the avr-step as part of each
mode in connector caps to user-mode.
Additionally, change the avr_step connector property to enum
to give usermode just the capability to enable/disable avr-step
and not alter the step value as its fixed from the device tree.
Change-Id: I6d7f8e9fcf03f98abef7640fc741e5e1be8597a1
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add DCS command to read the panel scan line value and associated
time stamp in nano-seconds.
Change-Id: I06a76d3a6c5ad7a2e7681413c741e5b97b34d73f
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
This change adds support for bypassing hw access in DSI PHY/PLL
drivers which enables the DSI driver to run on emulation
platforms that might be missing those modules.
Change-Id: I3e83155a79d60f2357606746214d776cefabd651
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Signed-off-by: Alex Danila <quic_eadanila@quicinc.com>
Allow TPG patterns to be displayed on command mode and
video mode panels.
Change-Id: Ie9ba9b404ceb965f8a06d1f19e932dd2e051983b
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
This change moves warning log to info log if secondary default panel
is not available.
Change-Id: Iad420a05c6440afdf0fcc5f7d33197eaf5c158c4
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
When display is left on from the bootloader, disp_cc driver will put a
proxy vote on clocks to maintain the hardware configuration of bootloader.
Once all the consumers have been probed, the dispcc driver will synchronize
the hardware state of the device to match the aggregated software state
requested by all the consumers using sync_state call.
If there is an idle power collapse or a suspend before sync state call,
branch clocks and in turn RCG will not get turned off during clocks
disable sequence because of the proxy vote of disp_cc driver. This can be
the case even if there is a vote from any other disp_cc consumers.
During a subsequent call to enable the clocks from DSI driver, we are
currently switching RCG parent to PLL and then turning on the PLL.
If the sync state call doesn't happen before we enable the clocks back,
we'll be setting PLL which is off as a parent to RCG that is on.
But ideally when RCG is on, both the old and new sources should be on
while switching the RCG parent.
Avoid this by turning on the PLL before switching RCG parent during clock
enable sequence.
Change-Id: I1597cf2c8095957cd2b2a20a72bf7199e0d61809
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Pass the DRM_BRIDGE_ATTACH_NO_CONNECTOR flag when attaching the
bridge so that the bridge driver would not create another
drm connector.
Change-Id: I838bd87c40d0eea3df36187befeb7195fb87d5b3
Signed-off-by: Rahul Sharma <quic_rahsha@quicinc.com>
Sim panels are not working well with video mode, parse panel ack
disabled property to fix sim video mode identification issue.
Change-Id: Ife3b533d5a6db97618459dacf1f7ce8d3fc896bf
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
This change adds a connector OP, that will be used to update frame
transfer time dynamically at the request from user space.
It also adds parsing for new device tree entries that set the minimum
and maximum trasnfer times on a mode basis. These min and max transfer
times are also published to userspace through the connector mode info
capabilities blob.
Change-Id: I12aedf96a51ff7feb2c5b3b1353d3c4ec8dcb068
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Refactor the function 'dsi_display_get_modes' to
reduce its complexity.
Change-Id: I1a8ecaa780e5070bac7fa40404677c0a8a5d7cd8
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change updates copyright description with correct
license marking as per the guidelines.
Change-Id: Ia74b721e78afcc7f8e88bcbccfcf15430111ec37
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Use #if IS_ENABLED() instead of #ifdef for configurations as vendor module
guidelines.
Use #if IS_ENABLED(CONFIG_XXX) instead of #ifdef CONFIG_XXX to ensure that
the code inside the #if block continues to compile if the config changes
to a tristate config in the future.
The differences are as follows:
1.#if IS_ENABLED(CONFIG_XXX) evaluates to true when CONFIG_XXX is set to
module (=m) or built-in (=y).
2.#ifdef CONFIG_XXX evaluates to true when CONFIG_XXX is set to
built-in(=y) , but doesn't when CONFIG_XXX is set to module(=m).
Use this only when you're certain you want to do the same thing
when the config is set to module or is disabled.
Change-Id: Ia806b9b01ad8414d0e4de027a382cb68e7fb4a6a
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
As per the HW requirements it is highly recommended to use DMA start window
to trigger broadcast commands. If not used then it can result in a hardware
hang with the DSI controllers going out of sync. This behavior is even more
prominent in cases of higher refresh rates.
Currently, reset_trigger_controls is called as part of next command.
Due to this, when unicast command is sent after broadcast command,
reset_trigger_controls does not get called for slave controller,
leading to issues.
As part of this change, DMA start window scheduling is enabled as default
for broadcast commands and reset_trigger_controls is done as part of
post_cmd_transfer operations.
Change-Id: I2402214ed79b376d102b88d4f7e6a06fcb5712d3
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
pm_runtime_get_sync increases the usage_count refcount immaterial of
success/failure of the call, leading to invalid refcount on failures.
Use pm_runtime_resume_and_get instead, which takes care of reducing the
refcount on failure cases before returning from the function.
Change-Id: Ib96050d5d7ecbd717e58b8a0dde2d03312444e15
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
During a force update of DSI clocks, the state of the byte and pclks are
toggled irrespective of the ref-count. This in addition with ASYNC
command wait can result in interrupt storm, if and when the clocks are
being toggled a previous command that was triggered using the ASYNC
wait flag fires an ISR. The interrupt status doesn't get cleared if
the ISR is being serviced with the clocks are off.
The change adds a check for pending queued commands before any force
update of DSI clocks.
Change-Id: I4ca60d0ad43767791255f00c9af8e99e74786097
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Commit bf0d220 ("disp: msm: dsi: add _NO_ to MIPI_DSI_* flags
disabling features") update names of DSI flags to follow upstream
convention. Purpose of the name change is to more clearly indicate
what is not supported when the flag is set.
This change puts macros around MIPI_DSI_* flags to adapt the name change
of flags for kernel version 5.10 and version 5.15..
Change-Id: I1c9a8da3819a6b641ca9b6d81191bc944913b49e
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Currently, in dsi_display_get_modes, priv_info, rates,
front_porches and pixel_clks_khz memory is allocated for each
timing node and the same memory is copied for each supported fps.
The values of front porches calculated to maintain constant fps for
each bit clk rate gets overwritten with the values for last fps in
the dfps list. But the values of front porches should be different
in case where DFPS and dynamic clock are both supported either by
vfp approach or hfp approach. To fix this, allocate memory
separately for each fps.
Change-Id: Ibf753aa8cca8d77b02b20785b5435f1aba05106e
Signed-off-by: Kashish Jain <kashjain@codeaurora.org>
This change adds additional logs in dsi driver for
easy debugging of issues related to command transfer.
Change-Id: Ica784bed6c360b2760d6606d625837e23a22410c
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
After an ESD failure, the PHY lanes and controller can be stuck in
an unknown state. This can result in interrupt storms and watchdog
failures, if these error states are not handled correctly. The following
change implements the below mechanism to avoid failures.
1) Disable error interrupts during an ESD reg read, which are re-enabled once
ESD check is successful.
2) On ESD failure, before turning off LP clocks, reset the PHY lanes and DSI
controller.
3) After the HS clocks are turned off, issue a PHY hard reset.
4) Before enabling/disabling error interrupts, clear the error status registers
as they are not cleared as part of controller reset.
Change-Id: If10e4edf095a334a9416d109ec4b1401d1a84505
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Update names of DSI flags to follow upstream convention. Purpose of
the name change is to more clearly indicate what is not supported
when the flag is set.
Change-Id: Ifd62610c4dfebcbbccb0fb2046a7c453e39c9107
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Currently the bit clk rate is overridden by cached clock rate
even in dynamic clock disabled usecase where it is not configured.
Avoid this override by retaining calculated bit clock rate for respective
mode in such usecase.
Change-Id: Ib159219fd50ab977edb8332c83bc8b34aee2dc0f
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
Alter allocation method from kzalloc to kvzalloc since virtually
contiguous allocation should suffice requirement. This will avoid
unnecessary invocation of OOO handlers.
Change-Id: I8291ddae08f6427478cdd9b88d6148e02d7ab002
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
When validating panel resource, no need to check reset gpio if using
ext bridge mode.
Change-Id: Id0df84b9e0d8b10f4dd6851d5b3ab31b220f8622
Signed-off-by: Yu Wu <zwy@codeaurora.org>
Wait for asynchronous DSI DCS command transfers to complete
before disabling DSI interrupts during pre-release. This is
required to resolve a race condition where dsi worker threads
can trigger HW access while a VM lend/release is occurring on
the CRTC commit thread.
Change-Id: Ia1f153a2cd008c617dba274473e7678b01a38d29
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
The ROI commands are sent with an asynchronous command transfer wait.
If the queued CMD DMA wait for done gets scheduled before the DSI
controller timing engine programming, the later will be blocked waiting
on the ctrl_lock, which was acquired by the queued DMA wait for done work.
This effectively negates any advantage of having the async wait flag for
ROI commands blocking the main commit thread.
The change swaps this order to ensure that such a scenario never happens.
Change-Id: I8a971c0c7733eea3d435b637ca41b34fa60adfc1
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Add new properties to support dynamically turning on and off digital
dimming and setting new minimum backlight.
Change-Id: I3b94190877d556768ba2c92ec59432dec44de0de
Signed-off-by: Ping Li <pingli@codeaurora.org>
In the current code for finding the qsync min fps for a
mode, entire mode list is iterated which involves acquiring
dsi display_lock. During conn tx debugfs commands, if
qsync min fps is required, we try to acquire dsi
display_lock twice which results in hang state. This change
adds qsync min fps value in dsi_display_mode_priv_info
struct in order to get the qsync fps from the
msm_display_mode present in connector state instead of
looping through all the modes to find the mode qsync fps.
Change-Id: Ifded40d1f12462bb50fc7bdafb746ae5b8d9512a
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Current display driver can't support kernel dts property
qcom,mdss-dsi-bl-min-level to adjust backlight min level,
so adding this change to make it work well if user wants to
increase the backlight min level of display panel.
Change-Id: Iac74ee44aafac88548ceba6b221d13251dc3d5ef
Signed-off-by: Yahui Wang <yahuiw@codeaurora.org>
Issuing a DSI command transfer while in continuous splash can
disable the CMD engine since no enable call has taken place.
Ignore updating the engine during display enable/disable paths
only for trusted VM and allow it for continuous splash.
Change-Id: I250df6a78af5558ad1e03a3931d11fd8d13e4555
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This reverts commit 65f3cc37a4.
This change breaks TUI use-cases by allowing CMD engine to be
disabled on trusted VM without primary VM having knowledge of
this HW update.
Change-Id: Ieb67dc841299a149e9f1028fd8f98bd857f1f711
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This reverts commit 61518d4f5f.
This change corrupts the DSI engine state machine which expects
all the state tracking updates from the calls that are now being
skipped.
Change-Id: I506ecbd98cc771950b17212a2702e7dde81fe539
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Secondary VM will do a disable commit when transferring HW
ownership back to primary. This will end up disabling the CMD
engine before releasing HW back to primary VM. Primary is
unaware that the engine has been disabled and ends up in a
bad state until it gets re-enabled.
This issue was introduced by: commit 65f3cc3 (disp: msm: dsi:
allow cmd-engine enable/disable HW op at all times).
Fix the issue by ensuring CMD engine does not get turned off
in the display disable path for trusted VM.
Change-Id: I1638a181d136e18a836c3ba08daee1c5fcaa9de3
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
To ensure that no other command transfer is in progress, during DSI
TX operation through debugfs, panel lock needs to be acquired.
Change-Id: I8d3871e32277840867d9494720e77df3566e30d3
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change adds support for qsync min refresh rate per
timing mode and populates qsync min refresh rate based
on the current fps when qsync is enabled.
Change-Id: I191d1d72e95dd065c8c0b56a6100104c00c6d8f6
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
