Current HAL delayed reg write is tied to SRNG notions, hence
implement delayed reg write logic in HIF since WCN6450 does
not use SRNG interface.
New feature flag FEATURE_HIF_DELAYED_REG_WRITE is introduced
to disable/enable this support.
Change-Id: Id7087ad53cd5879cf49ee0e84dd727de61137541
CRs-Fixed: 3519702
Add the following hif/ce changes to add support for wcn6450,
* New host/target wlan ce config for wcn6450
* New service to pipe map for wcn6450
* New host/ce/target table attach for wcn6450
Change-Id: I20fa1410f5e4e7a0146bc2d0b48a18269ca4a8c9
CRs-Fixed: 3381111
Current code has incorrect BAR remap register offset defined.
Fix this by adding peach specific BAR remap register offset.
Change-Id: I8bbd6270f502da87fa1ccbcf667662bcf916dc03
CRs-Fixed: 3388309
The kernel-doc script identified a large number of kernel-doc issues
in the hif/src folder, so fix them.
Change-Id: Ia944c6c9f1bcb6a8f5f0ff07ca0afa7bf3a40ad0
CRs-Fixed: 3375493
Currently window register accessing with PLD lock is not enabled for
HIF path of KIWI, enable it so there is no race condition with HAL
register accessing path.
Change-Id: Iceeba36ca6febdeca0e7f7bc0dcb7d4adc17bc51
CRs-Fixed: 3110425
Select window failed sometimes, then following register writing by offset
leaded to NOC error.
PCIe local register space is mapped to BAR0 lower address, don't need
select window when write wake up umac register.
Add read back to confirm select window register writing passed through.
Change-Id: Iaa5359722e9b7a3434efd1a819a951ce6c8d3f4f
CRs-Fixed: 2952127
Enable force wake recipe feature DEVICE_FORCE_WAKE_ENABLE
and disable the generic shadow register write feature
GENERIC_SHADOW_REGISTER_ACCESS_ENABLE.
Force wake recipe will be used to write to the REO remap
control registers by waking up the UMAC instead of using
shadow register writes.
Assert soc wake reg and poll on the scratch reg to check
if UMAC is awake.
Enable HIF_REG_WINDOW_SUPPORT to enable windowed reg
read/write in HIF layer.
Change-Id: Ib696e27e19a07c0084c097b95b7780b56e643c8b
CRs-Fixed: 2850590
Before accessing any register on chip 6750, check if target is
ready or not.
Do not allow register access if target is not ready.
Change-Id: I41a604d04e861c97bdd676998222ccecbf12fd5a
CRs-Fixed: 2688920
Update CE registers offset during hal srng configuration
and configure CE IRQ for qcac6750.
Change-Id: I4fd3d37783361f0029c7ef80e32425f8790d1250
CRs-Fixed: 2617699
1. Add hif_force_wake_request API to wake the
mhi and umac before reading/writing the memory region
greater than BAR+4K.
2. Add hif_force_wake_release API to release the
PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG so the
umac can power collapse again at a later point of time.
3. Add pci stats to dump the force wake status.
Change-Id: Ic6d5463ea0cdb28d9144be61da55e43033b53298
CRs-Fixed: 2478052
Currently, Shadow registers is not implemented for all registers.
This can lead to unclocked access and followed by NOC errors.
In Rx path Interrupt Status and src/dst read index are directly
accessed without shadow block. Target may execute
reset sequence due to PDR/SSR while rx path is active.
Avoid direct access to below registers if target is crashed due
to PDR/SSR.
HOST_IE_ADDRESS
HOST_IS_ADDRESS
CURRENT_DRRI_ADDRESS
CURRENT_SRRI_ADDRESS
Return from ISR without scheduling the bottom half if target is
crashed due to PDR/SSR.
Change-Id: Ifa993e978579b4d061d21281338494292e19700a
CRs-Fixed: 2123967
hif_exec_context extends hif_ext_groups to support napi and tasklet models.
Some of the rename and enahancements have been done to support merging of
the execution context management code between the CE and DP contexts, as
well as supporting irq affinity for both napi & tasklet contexts.
Change-Id: I82c8abf2e906f027ec80faf7353a7685536bb79b
CRs-Fixed: 2051902
Pointerizing these apis is easier than removing external
references or unifying them. Support multibus by
pointerizing them.
Change-Id: Iab86adf2076a082b75d9ba393123798e16f5b82e
CRs-Fixed: 986480
Sleep state adjust has been added the the bus_ops table and the
macros using it can be unified.
Change-Id: Ib788800c83457919ae7eee01f6687cbb57c84a4b
CRs-Fixed: 986480
Sleep state adjust has been added the the bus_ops table and the
macros using it can be unified.
Change-Id: Id08f5d95c295ab8419c0ae60519aae064c318856
CRs-Fixed: 986480
Use new HIF_SNOC instead of assuming snoc when pci is not defined.
Exposes duplicate function defs with HIF_SNOC and HIF_PCI both defined.
Remove some trivial HIF_PCI conditional compilation.
Change-Id: I958740f49b3298c165e662b89b586bda2b3d2ee8
CRs-Fixed: 986480
Initial host-common file folder cleanup and moves
on top of baseline reference of MCL WLAN driver
SU#5.0.0.160.
Move dp, ht comm, hif, wmi and qdf folders one level up
Change-Id: I2120898024b1eafd5d651c48768dbf48bf05995d
