qcacmn: Add hif register windowing support

Add hif register windowing support for
Genoa.

Change-Id: I216382aed4dba25ccdcc1126f73f0096f398a5b3
CRs-Fixed: 2265915

hif/src/ce/ce_diag.c

@@ -46,7 +46,7 @@ hif_ce_dump_target_memory(struct hif_softc *scn, void *ramdump_base,
 		return;
 
 	while (j < size) {
-		val = hif_read32_mb(scn->mem + loc + j);
+		val = hif_read32_mb(scn, scn->mem + loc + j);
 		qdf_mem_copy(temp, &val, 4);
 		j += 4;
 		temp += 4;
@@ -63,21 +63,21 @@ hif_ce_dump_target_memory(struct hif_softc *scn, void *ramdump_base,
  * but that's not guaranteed.
  */
 #ifdef QCA_WIFI_3_0
-#define TARG_CPU_SPACE_TO_CE_SPACE(pci_addr, addr) \
+#define TARG_CPU_SPACE_TO_CE_SPACE(sc, pci_addr, addr) \
 	(scn->mem_pa + addr)
 #else
-#define TARG_CPU_SPACE_TO_CE_SPACE(pci_addr, addr) \
-	(((hif_read32_mb((pci_addr) + \
+#define TARG_CPU_SPACE_TO_CE_SPACE(sc, pci_addr, addr) \
+	(((hif_read32_mb(sc, (pci_addr) + \
 	(SOC_CORE_BASE_ADDRESS|CORE_CTRL_ADDRESS)) & 0x7ff) << 21) \
 	 | 0x100000 | ((addr) & 0xfffff))
 #endif
 
-#define TARG_CPU_SPACE_TO_CE_SPACE_IPQ4019(pci_addr, addr) \
-	(hif_read32_mb((pci_addr)+(WIFICMN_PCIE_BAR_REG_ADDRESS)) \
+#define TARG_CPU_SPACE_TO_CE_SPACE_IPQ4019(scn, pci_addr, addr) \
+	(hif_read32_mb(scn, (pci_addr) + (WIFICMN_PCIE_BAR_REG_ADDRESS)) \
 	| ((addr) & 0xfffff))
 
-#define TARG_CPU_SPACE_TO_CE_SPACE_AR900B(pci_addr, addr) \
-	(hif_read32_mb((pci_addr)+(WIFICMN_PCIE_BAR_REG_ADDRESS)) \
+#define TARG_CPU_SPACE_TO_CE_SPACE_AR900B(scn, pci_addr, addr) \
+	(hif_read32_mb(scn, (pci_addr) + (WIFICMN_PCIE_BAR_REG_ADDRESS)) \
 	| 0x100000 | ((addr) & 0xfffff))
 
 #define SRAM_BASE_ADDRESS 0xc0000
@@ -113,17 +113,17 @@ static qdf_dma_addr_t get_ce_phy_addr(struct hif_softc *sc, uint32_t  address,
 	}
 
 	if ((target_type == TARGET_TYPE_IPQ4019) && sramregion == 1) {
-		ce_phy_addr =
-			TARG_CPU_SPACE_TO_CE_SPACE_IPQ4019(sc->mem, address);
+		ce_phy_addr = TARG_CPU_SPACE_TO_CE_SPACE_IPQ4019(sc, sc->mem,
+								 address);
 	} else if ((target_type == TARGET_TYPE_AR900B) ||
 	    (target_type == TARGET_TYPE_QCA9984) ||
 	    (target_type == TARGET_TYPE_IPQ4019) ||
 	    (target_type == TARGET_TYPE_QCA9888)) {
 		ce_phy_addr =
-		    TARG_CPU_SPACE_TO_CE_SPACE_AR900B(sc->mem, address);
+		    TARG_CPU_SPACE_TO_CE_SPACE_AR900B(sc, sc->mem, address);
 	} else {
 		ce_phy_addr =
-		    TARG_CPU_SPACE_TO_CE_SPACE(sc->mem, address);
+		    TARG_CPU_SPACE_TO_CE_SPACE(sc, sc->mem, address);
 	}
 
 	return ce_phy_addr;

hif/src/ce/ce_main.c

@@ -2848,7 +2848,7 @@ static void hif_post_static_buf_to_target(struct hif_softc *scn)
 		HIF_TRACE("Memory allocation failed could not post target buf");
 		return;
 	}
-	hif_write32_mb(scn->mem + BYPASS_QMI_TEMP_REGISTER, target_pa);
+	hif_write32_mb(scn, scn->mem + BYPASS_QMI_TEMP_REGISTER, target_pa);
 	HIF_TRACE("target va %pK target pa %pa", target_va, &target_pa);
 }
 #else

hif/src/ce/ce_service.c

@@ -349,25 +349,26 @@ void war_ce_src_ring_write_idx_set(struct hif_softc *scn,
 
 		if (!war1_allow_sleep
 		    && ctrl_addr == CE_BASE_ADDRESS(CDC_WAR_DATA_CE)) {
-			hif_write32_mb(indicator_addr,
-				      (CDC_WAR_MAGIC_STR | write_index));
+			hif_write32_mb(scn, indicator_addr,
+				       (CDC_WAR_MAGIC_STR | write_index));
 		} else {
 			unsigned long irq_flags;
 
 			local_irq_save(irq_flags);
-			hif_write32_mb(indicator_addr, 1);
+			hif_write32_mb(scn, indicator_addr, 1);
 
 			/*
 			 * PCIE write waits for ACK in IPQ8K, there is no
 			 * need to read back value.
 			 */
-			(void)hif_read32_mb(indicator_addr);
-			(void)hif_read32_mb(indicator_addr); /* conservative */
+			(void)hif_read32_mb(scn, indicator_addr);
+			/* conservative */
+			(void)hif_read32_mb(scn, indicator_addr);
 
 			CE_SRC_RING_WRITE_IDX_SET(scn,
 						  ctrl_addr, write_index);
 
-			hif_write32_mb(indicator_addr, 0);
+			hif_write32_mb(scn, indicator_addr, 0);
 			local_irq_restore(irq_flags);
 		}
 	} else {

hif/src/hif_io32.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -23,10 +23,30 @@
 #include "hif.h"
 #include "hif_main.h"
 
-#define hif_read32_mb(addr)         ioread32((void __iomem *)addr)
-#define hif_write32_mb(addr, value) \
+#if defined(HIF_REG_WINDOW_SUPPORT) && defined(HIF_PCI)
+
+static inline
+void hif_write32_mb_reg_window(void *sc,
+			       void __iomem *addr, uint32_t value);
+
+static inline uint32_t hif_read32_mb_reg_window(void *sc,
+						void __iomem *addr);
+
+#define hif_read32_mb(scn, addr) \
+	hif_read32_mb_reg_window((void *)scn, \
+				 (void __iomem *)addr)
+#define hif_write32_mb(scn, addr, value) \
+	hif_write32_mb_reg_window((void *)scn, \
+				  (void __iomem *)addr, value)
+
+#else
+
+#define hif_read32_mb(scn, addr)         ioread32((void __iomem *)addr)
+#define hif_write32_mb(scn, addr, value) \
 	iowrite32((u32)(value), (void __iomem *)(addr))
 
+#endif
+
 #define Q_TARGET_ACCESS_BEGIN(scn) \
 	hif_target_sleep_state_adjust(scn, false, true)
 #define Q_TARGET_ACCESS_END(scn) \
@@ -78,6 +98,84 @@
 #include "hif_io32_snoc.h"
 #endif /* HIF_PCI */
 
+#if defined(HIF_REG_WINDOW_SUPPORT) && defined(HIF_PCI)
+#include "qdf_lock.h"
+#include "qdf_util.h"
+
+/* Device memory is 32MB but bar size is only 1MB.
+ * Register remapping logic is used to access 32MB device memory.
+ * 0-512KB : Fixed address, 512KB-1MB : remapped address.
+ * Use PCIE_REMAP_1M_BAR_CTRL register to set window.
+ * Offset: 0x310C
+ * Bits  : Field Name
+ * 31      FUNCTION_ENABLE_V
+ * 5:0     ADDR_24_19_V
+ */
+
+#define MAX_UNWINDOWED_ADDRESS 0x80000 /* 512KB */
+#define WINDOW_ENABLE_BIT 0x80000000 /* 31st bit to enable window */
+#define WINDOW_REG_ADDRESS 0x310C /* PCIE_REMAP_1M_BAR_CTRL Reg offset */
+#define WINDOW_SHIFT 19
+#define WINDOW_VALUE_MASK 0x3F
+#define WINDOW_START MAX_UNWINDOWED_ADDRESS
+#define WINDOW_RANGE_MASK 0x7FFFF
+
+static inline void hif_select_window(struct hif_pci_softc *sc, uint32_t offset)
+{
+	uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
+
+	if (window != sc->register_window) {
+		qdf_iowrite32(sc->mem + WINDOW_REG_ADDRESS,
+			      WINDOW_ENABLE_BIT | window);
+		sc->register_window = window;
+	}
+}
+
+/**
+ * note1: WINDOW_RANGE_MASK = (1 << WINDOW_SHIFT) -1
+ * note2: 1 << WINDOW_SHIFT = MAX_UNWINDOWED_ADDRESS
+ * note3: WINDOW_VALUE_MASK = big enough that trying to write past that window
+ *				would be a bug
+ */
+static inline void hif_write32_mb_reg_window(void *scn,
+					     void __iomem *addr, uint32_t value)
+{
+	struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn);
+	uint32_t offset = addr - sc->mem;
+
+	if (!sc->use_register_windowing ||
+	    offset < MAX_UNWINDOWED_ADDRESS) {
+		qdf_iowrite32(addr, value);
+	} else {
+		qdf_spin_lock_irqsave(&sc->register_access_lock);
+		hif_select_window(sc, offset);
+		qdf_iowrite32(sc->mem + WINDOW_START +
+			  (offset & WINDOW_RANGE_MASK), value);
+		qdf_spin_unlock_irqrestore(&sc->register_access_lock);
+	}
+}
+
+static inline uint32_t hif_read32_mb_reg_window(void *scn, void __iomem *addr)
+{
+	struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn);
+	uint32_t ret;
+	uint32_t offset = addr - sc->mem;
+
+	if (!sc->use_register_windowing ||
+	    offset < MAX_UNWINDOWED_ADDRESS) {
+		return qdf_ioread32(addr);
+	}
+
+	qdf_spin_lock_irqsave(&sc->register_access_lock);
+	hif_select_window(sc, offset);
+	ret = qdf_ioread32(sc->mem + WINDOW_START +
+		       (offset & WINDOW_RANGE_MASK));
+	qdf_spin_unlock_irqrestore(&sc->register_access_lock);
+
+	return ret;
+}
+#endif
+
 #ifdef CONFIG_IO_MEM_ACCESS_DEBUG
 uint32_t hif_target_read_checked(struct hif_softc *scn,
 					uint32_t offset);
@@ -90,9 +188,9 @@ void hif_target_write_checked(struct hif_softc *scn, uint32_t offset,
 	hif_target_write_checked(scn, (offset), (value))
 #else                           /* CONFIG_ATH_PCIE_ACCESS_DEBUG */
 #define A_TARGET_READ(scn, offset) \
-	hif_read32_mb(scn->mem + (offset))
+	hif_read32_mb(scn, scn->mem + (offset))
 #define A_TARGET_WRITE(scn, offset, value) \
-	hif_write32_mb((scn->mem) + (offset), value)
+	hif_write32_mb(scn, (scn->mem) + (offset), value)
 #endif
 
 void hif_irq_enable(struct hif_softc *scn, int irq_id);

hif/src/hif_main.c

@@ -1205,7 +1205,7 @@ void hif_reg_write(struct hif_opaque_softc *hif_ctx, uint32_t offset,
 {
 	struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx);
 
-	hif_write32_mb(scn->mem + offset, value);
+	hif_write32_mb(scn, scn->mem + offset, value);
 
 }
 qdf_export_symbol(hif_reg_write);
@@ -1223,7 +1223,7 @@ uint32_t hif_reg_read(struct hif_opaque_softc *hif_ctx, uint32_t offset)
 
 	struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx);
 
-	return hif_read32_mb(scn->mem + offset);
+	return hif_read32_mb(scn, scn->mem + offset);
 }
 qdf_export_symbol(hif_reg_read);
 

hif/src/mp_dev.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, 2016-2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2014, 2016-2018 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -69,10 +69,11 @@ struct priv_ctrl_ctx {
 
 static struct priv_ctrl_ctx g_priv_dump_ctx;
 
-static inline void set_target_reg_bits(void __iomem *mem, uint32_t reg,
+static inline void set_target_reg_bits(struct hif_softc *scn,
+				       void __iomem *mem, uint32_t reg,
 				       uint32_t bitmask, uint32_t val)
 {
-	uint32_t value = hif_read32_mb(mem + (reg));
+	uint32_t value = hif_read32_mb(scn, mem + (reg));
 	uint32_t shift = 0;
 
 	value &= ~(bitmask);
@@ -80,13 +81,14 @@ static inline void set_target_reg_bits(void __iomem *mem, uint32_t reg,
 		shift++;
 
 	value |= (((val) << shift) & (bitmask));
-	hif_write32_mb(mem + (reg), value);
+	hif_write32_mb(scn, mem + (reg), value);
 }
 
-static inline uint32_t get_target_reg_bits(void __iomem *mem,
+static inline uint32_t get_target_reg_bits(struct hif_softc *scn,
+					   void __iomem *mem,
 					   uint32_t reg, uint32_t bitmask)
 {
-	uint32_t value = hif_read32_mb(mem + (reg));
+	uint32_t value = hif_read32_mb(scn, mem + (reg));
 	uint32_t shift = 0;
 
 	while (!((bitmask >> shift) & 0x01))
@@ -97,22 +99,22 @@ static inline uint32_t get_target_reg_bits(void __iomem *mem,
 
 void priv_start_cap_chaninfo(struct hif_softc *scn)
 {
-	set_target_reg_bits(scn->mem, BB_chaninfo_ctrl,
+	set_target_reg_bits(scn, scn->mem, BB_chaninfo_ctrl,
 			    CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK, 1);
 }
 
 void priv_start_agc(struct hif_softc *scn)
 {
 	g_priv_dump_ctx.gain_min_offsets_orig =
-		hif_read32_mb(scn->mem + BB_gains_min_offsets);
-	set_target_reg_bits(scn->mem, BB_gains_min_offsets,
+		hif_read32_mb(scn, scn->mem + BB_gains_min_offsets);
+	set_target_reg_bits(scn, scn->mem, BB_gains_min_offsets,
 			    AGC_HISTORY_DUMP_MASK,
 			    0x0f);
 }
 
 static void priv_stop_agc(struct hif_softc *scn)
 {
-	set_target_reg_bits(scn->mem, BB_gains_min_offsets,
+	set_target_reg_bits(scn, scn->mem, BB_gains_min_offsets,
 			    AGC_HISTORY_DUMP_MASK,
 			    0);
 }
@@ -125,13 +127,13 @@ void priv_dump_chaninfo(struct hif_softc *scn)
 	uint32_t chain0, chain1;
 
 	chain_mask =
-		get_target_reg_bits(scn->mem, BB_multichain_enable,
+		get_target_reg_bits(scn, scn->mem, BB_multichain_enable,
 				    MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK);
 	chain0 = chain_mask & 1;
 	chain1 = chain_mask & 2;
 
 	HIF_TRACE("%s: E", __func__);
-	bw = get_target_reg_bits(scn->mem, BB_chaninfo_ctrl,
+	bw = get_target_reg_bits(scn, scn->mem, BB_chaninfo_ctrl,
 				 CHANINFO_CTRL_CHANINFOMEM_BW_MASK);
 
 	if (bw == 0)
@@ -152,24 +154,23 @@ void priv_dump_chaninfo(struct hif_softc *scn)
 	 */
 
 	if (chain0) {
-		hif_write32_mb(scn->mem + BB_chn_tables_intf_addr,
-			      0x80003200);
+		hif_write32_mb(scn, scn->mem + BB_chn_tables_intf_addr,
+			       0x80003200);
 	}
 	if (chain1) {
-		hif_write32_mb(scn->mem + BB_chn1_tables_intf_addr,
-			      0x80003200);
+		hif_write32_mb(scn, scn->mem + BB_chn1_tables_intf_addr,
+			       0x80003200);
 	}
 
-	set_target_reg_bits(scn->mem, BB_chaninfo_ctrl,
-			CHANINFOMEM_S2_READ_MASK, 0);
+	set_target_reg_bits(scn, scn->mem, BB_chaninfo_ctrl,
+			    CHANINFOMEM_S2_READ_MASK, 0);
 
 	if (chain0) {
 		if (bw < 2) {
 			len = (bw == 0) ? 53 : 57;
 			for (i = 0; i < len; i++) {
-				val =
-					hif_read32_mb(scn->mem +
-						     BB_chn_tables_intf_data) &
+				val = hif_read32_mb(scn, scn->mem +
+						    BB_chn_tables_intf_data) &
 					0x0000ffff;
 				qdf_debug("0x%x\t", val);
 				if (i % 4 == 0)
@@ -178,9 +179,8 @@ void priv_dump_chaninfo(struct hif_softc *scn)
 		} else {
 			len = (bw == 2) ? 59 : 60;
 			for (i = 0; i < len; i++) {
-				tmp =
-					hif_read32_mb(scn->mem +
-						     BB_chn_tables_intf_data);
+				tmp = hif_read32_mb(scn, scn->mem +
+						    BB_chn_tables_intf_data);
 				qdf_debug("0x%x\t", ((tmp >> 16) & 0x0000ffff));
 				qdf_debug("0x%x\t", (tmp & 0x0000ffff));
 				if (i % 2 == 0)
@@ -188,14 +188,13 @@ void priv_dump_chaninfo(struct hif_softc *scn)
 			}
 			if (bw > 2) {
 				/* bw == 3 for vht80 */
-				hif_write32_mb(scn->mem +
+				hif_write32_mb(scn, scn->mem +
 					      BB_chn_tables_intf_addr,
 					      0x80003300);
 				len = 61;
 				for (i = 0; i < len; i++) {
-					tmp =
-						hif_read32_mb(scn->mem +
-						     BB_chn_tables_intf_data);
+					tmp = hif_read32_mb(scn, scn->mem +
+						BB_chn_tables_intf_data);
 					qdf_debug("0x%x\t",
 					       ((tmp >> 16) & 0x0000ffff));
 					qdf_debug("0x%x\t", (tmp & 0x0000ffff));
@@ -210,7 +209,7 @@ void priv_dump_chaninfo(struct hif_softc *scn)
 			len = (bw == 0) ? 53 : 57;
 			for (i = 0; i < len; i++) {
 				val =
-					hif_read32_mb(scn->mem +
+					hif_read32_mb(scn, scn->mem +
 						BB_chn1_tables_intf_data) &
 					0x0000ffff;
 				qdf_debug("0x%x\t", val);
@@ -221,7 +220,7 @@ void priv_dump_chaninfo(struct hif_softc *scn)
 			len = (bw == 2) ? 59 : 60;
 			for (i = 0; i < len; i++) {
 				tmp =
-					hif_read32_mb(scn->mem +
+					hif_read32_mb(scn, scn->mem +
 						     BB_chn1_tables_intf_data);
 				qdf_debug("0x%x\n", (tmp >> 16) & 0x0000ffff);
 				qdf_debug("0x%x\n", tmp & 0x0000ffff);
@@ -230,13 +229,13 @@ void priv_dump_chaninfo(struct hif_softc *scn)
 			}
 			if (bw > 2) {
 				/* bw == 3 for vht80 */
-				hif_write32_mb(scn->mem +
+				hif_write32_mb(scn, scn->mem +
 					      BB_chn1_tables_intf_addr,
 					      0x80003300);
 				len = 61;
 				for (i = 0; i < len; i++) {
 					tmp =
-						hif_read32_mb(scn->mem +
+						hif_read32_mb(scn, scn->mem +
 						     BB_chn1_tables_intf_data);
 					qdf_debug("0x%x\t",
 					       ((tmp >> 16) & 0x0000ffff));
@@ -259,7 +258,7 @@ void priv_dump_agc(struct hif_softc *scn)
 		return;
 
 	chain_mask =
-		get_target_reg_bits(scn->mem, BB_multichain_enable,
+		get_target_reg_bits(scn, scn->mem, BB_multichain_enable,
 				    MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK);
 	chain0 = chain_mask & 1;
 	chain1 = chain_mask & 2;
@@ -267,16 +266,16 @@ void priv_dump_agc(struct hif_softc *scn)
 	len = len << 1;         /* each agc item is 64bit, total*2 */
 	priv_stop_agc(scn);
 
-	set_target_reg_bits(scn->mem, BB_chaninfo_ctrl,
-			CHANINFOMEM_S2_READ_MASK, 0);
+	set_target_reg_bits(scn, scn->mem, BB_chaninfo_ctrl,
+			    CHANINFOMEM_S2_READ_MASK, 0);
 
 	HIF_TRACE("%s: AGC history buffer dump: E", __func__);
 	if (chain0) {
 		for (i = 0; i < len; i++) {
-			hif_write32_mb(scn->mem +
+			hif_write32_mb(scn, scn->mem +
 				PHY_BB_CHN_TABLES_INTF_ADDR,
 				BB_chaninfo_tab_b0 + i * 4);
-			val = hif_read32_mb(scn->mem +
+			val = hif_read32_mb(scn, scn->mem +
 				PHY_BB_CHN_TABLES_INTF_DATA);
 			qdf_debug("0x%x\t", val);
 			if (i % 4 == 0)
@@ -285,10 +284,10 @@ void priv_dump_agc(struct hif_softc *scn)
 	}
 	if (chain1) {
 		for (i = 0; i < len; i++) {
-			hif_write32_mb(scn->mem +
+			hif_write32_mb(scn, scn->mem +
 				PHY_BB_CHN1_TABLES_INTF_ADDR,
 				BB_chaninfo_tab_b0 + i * 4);
-			val = hif_read32_mb(scn->mem +
+			val = hif_read32_mb(scn, scn->mem +
 				PHY_BB_CHN1_TABLES_INTF_DATA);
 			qdf_debug("0x%x\t", val);
 			if (i % 4 == 0)
@@ -297,8 +296,8 @@ void priv_dump_agc(struct hif_softc *scn)
 	}
 	HIF_TRACE("%s: AGC history buffer dump X", __func__);
 	/* restore original value */
-	hif_write32_mb(scn->mem + BB_gains_min_offsets,
-		      g_priv_dump_ctx.gain_min_offsets_orig);
+	hif_write32_mb(scn, scn->mem + BB_gains_min_offsets,
+		       g_priv_dump_ctx.gain_min_offsets_orig);
 
 	Q_TARGET_ACCESS_END(scn);
 
@@ -309,13 +308,13 @@ void priv_dump_bbwatchdog(struct hif_softc *scn)
 	uint32_t val;
 
 	HIF_TRACE("%s: BB watchdog dump E", __func__);
-	val = hif_read32_mb(scn->mem + BB_watchdog_status);
+	val = hif_read32_mb(scn, scn->mem + BB_watchdog_status);
 	qdf_debug("0x%x\t", val);
-	val = hif_read32_mb(scn->mem + BB_watchdog_ctrl_1);
+	val = hif_read32_mb(scn, scn->mem + BB_watchdog_ctrl_1);
 	qdf_debug("0x%x\t", val);
-	val = hif_read32_mb(scn->mem + BB_watchdog_ctrl_2);
+	val = hif_read32_mb(scn, scn->mem + BB_watchdog_ctrl_2);
 	qdf_debug("0x%x\t", val);
-	val = hif_read32_mb(scn->mem + BB_watchdog_status_B);
+	val = hif_read32_mb(scn, scn->mem + BB_watchdog_status_B);
 	qdf_debug("0x%x", val);
 	HIF_TRACE("%s: BB watchdog dump X", __func__);
 }

hif/src/pcie/if_pci.c

@@ -87,15 +87,15 @@ static void hif_pci_route_adrastea_interrupt(struct hif_pci_softc *sc)
 	unsigned int target_enable0, target_enable1;
 	unsigned int target_cause0, target_cause1;
 
-	target_enable0 = hif_read32_mb(sc->mem + Q6_ENABLE_REGISTER_0);
-	target_enable1 = hif_read32_mb(sc->mem + Q6_ENABLE_REGISTER_1);
-	target_cause0 = hif_read32_mb(sc->mem + Q6_CAUSE_REGISTER_0);
-	target_cause1 = hif_read32_mb(sc->mem + Q6_CAUSE_REGISTER_1);
+	target_enable0 = hif_read32_mb(sc, sc->mem + Q6_ENABLE_REGISTER_0);
+	target_enable1 = hif_read32_mb(sc, sc->mem + Q6_ENABLE_REGISTER_1);
+	target_cause0 = hif_read32_mb(sc, sc->mem + Q6_CAUSE_REGISTER_0);
+	target_cause1 = hif_read32_mb(sc, sc->mem + Q6_CAUSE_REGISTER_1);
 
 	if ((target_enable0 & target_cause0) ||
 	    (target_enable1 & target_cause1)) {
-		hif_write32_mb(sc->mem + Q6_ENABLE_REGISTER_0, 0);
-		hif_write32_mb(sc->mem + Q6_ENABLE_REGISTER_1, 0);
+		hif_write32_mb(sc, sc->mem + Q6_ENABLE_REGISTER_0, 0);
+		hif_write32_mb(sc, sc->mem + Q6_ENABLE_REGISTER_1, 0);
 
 		if (scn->notice_send)
 			pld_intr_notify_q6(sc->dev);
@@ -128,12 +128,12 @@ static void pci_dispatch_interrupt(struct hif_softc *scn)
 		if ((scn->target_status != TARGET_STATUS_RESET) &&
 			(!qdf_atomic_read(&scn->link_suspended))) {
 
-			hif_write32_mb(scn->mem +
+			hif_write32_mb(scn, scn->mem +
 				(SOC_CORE_BASE_ADDRESS |
 				PCIE_INTR_ENABLE_ADDRESS),
 				HOST_GROUP0_MASK);
 
-			hif_read32_mb(scn->mem +
+			hif_read32_mb(scn, scn->mem +
 					(SOC_CORE_BASE_ADDRESS |
 					PCIE_INTR_ENABLE_ADDRESS));
 		}
@@ -169,9 +169,9 @@ irqreturn_t hif_pci_legacy_ce_interrupt_handler(int irq, void *arg)
 			return IRQ_HANDLED;
 
 		if (ADRASTEA_BU) {
-			host_enable = hif_read32_mb(sc->mem +
+			host_enable = hif_read32_mb(sc, sc->mem +
 						    PCIE_INTR_ENABLE_ADDRESS);
-			host_cause = hif_read32_mb(sc->mem +
+			host_cause = hif_read32_mb(sc, sc->mem +
 						   PCIE_INTR_CAUSE_ADDRESS);
 			if (!(host_enable & host_cause)) {
 				hif_pci_route_adrastea_interrupt(sc);
@@ -184,25 +184,26 @@ irqreturn_t hif_pci_legacy_ce_interrupt_handler(int irq, void *arg)
 		 * after INTR_ENABLE is set to 0,
 		 * otherwise interrupt can not be really cleared
 		 */
-		hif_write32_mb(sc->mem +
+		hif_write32_mb(sc, sc->mem +
 			      (SOC_CORE_BASE_ADDRESS |
 			       PCIE_INTR_ENABLE_ADDRESS), 0);
 
-		hif_write32_mb(sc->mem +
+		hif_write32_mb(sc, sc->mem +
 			      (SOC_CORE_BASE_ADDRESS | PCIE_INTR_CLR_ADDRESS),
 			       ADRASTEA_BU ?
 			       (host_enable & host_cause) :
 			      HOST_GROUP0_MASK);
 
 		if (ADRASTEA_BU)
-			hif_write32_mb(sc->mem + 0x2f100c, (host_cause >> 1));
+			hif_write32_mb(sc, sc->mem + 0x2f100c,
+				       (host_cause >> 1));
 
 		/* IMPORTANT: this extra read transaction is required to
 		 * flush the posted write buffer
 		 */
 		if (!ADRASTEA_BU) {
 		tmp =
-			hif_read32_mb(sc->mem +
+			hif_read32_mb(sc, sc->mem +
 				     (SOC_CORE_BASE_ADDRESS |
 				      PCIE_INTR_ENABLE_ADDRESS));
 
@@ -233,26 +234,26 @@ irqreturn_t hif_pci_legacy_ce_interrupt_handler(int irq, void *arg)
 
 			HIF_ERROR("%s: RTC_STATE_ADDRESS = 0x%08x",
 				  __func__,
-				  hif_read32_mb(sc->mem +
+				  hif_read32_mb(sc, sc->mem +
 						PCIE_LOCAL_BASE_ADDRESS
 						+ RTC_STATE_ADDRESS));
 			HIF_ERROR("%s: PCIE_SOC_WAKE_ADDRESS = 0x%08x",
 				  __func__,
-				  hif_read32_mb(sc->mem +
+				  hif_read32_mb(sc, sc->mem +
 						PCIE_LOCAL_BASE_ADDRESS
 						+ PCIE_SOC_WAKE_ADDRESS));
 			HIF_ERROR("%s: 0x80008 = 0x%08x, 0x8000c = 0x%08x",
 				  __func__,
-				  hif_read32_mb(sc->mem + 0x80008),
-				  hif_read32_mb(sc->mem + 0x8000c));
+				  hif_read32_mb(sc, sc->mem + 0x80008),
+				  hif_read32_mb(sc, sc->mem + 0x8000c));
 			HIF_ERROR("%s: 0x80010 = 0x%08x, 0x80014 = 0x%08x",
 				  __func__,
-				  hif_read32_mb(sc->mem + 0x80010),
-				  hif_read32_mb(sc->mem + 0x80014));
+				  hif_read32_mb(sc, sc->mem + 0x80010),
+				  hif_read32_mb(sc, sc->mem + 0x80014));
 			HIF_ERROR("%s: 0x80018 = 0x%08x, 0x8001c = 0x%08x",
 				  __func__,
-				  hif_read32_mb(sc->mem + 0x80018),
-				  hif_read32_mb(sc->mem + 0x8001c));
+				  hif_read32_mb(sc, sc->mem + 0x80018),
+				  hif_read32_mb(sc, sc->mem + 0x8001c));
 			QDF_BUG(0);
 		}
 
@@ -346,7 +347,7 @@ void hif_pci_cancel_deferred_target_sleep(struct hif_softc *scn)
 	if (hif_state->fake_sleep == true) {
 		qdf_timer_stop(&hif_state->sleep_timer);
 		if (hif_state->verified_awake == false) {
-			hif_write32_mb(pci_addr + PCIE_LOCAL_BASE_ADDRESS +
+			hif_write32_mb(scn, pci_addr + PCIE_LOCAL_BASE_ADDRESS +
 				      PCIE_SOC_WAKE_ADDRESS,
 				      PCIE_SOC_WAKE_RESET);
 		}
@@ -360,12 +361,12 @@ inline void hif_pci_cancel_deferred_target_sleep(struct hif_softc *scn)
 }
 #endif
 
-#define A_PCIE_LOCAL_REG_READ(mem, addr) \
-	hif_read32_mb((char *)(mem) + \
+#define A_PCIE_LOCAL_REG_READ(sc, mem, addr) \
+	hif_read32_mb(sc, (char *)(mem) + \
 	PCIE_LOCAL_BASE_ADDRESS + (uint32_t)(addr))
 
-#define A_PCIE_LOCAL_REG_WRITE(mem, addr, val) \
-	hif_write32_mb(((char *)(mem) + \
+#define A_PCIE_LOCAL_REG_WRITE(sc, mem, addr, val) \
+	hif_write32_mb(sc, ((char *)(mem) + \
 	PCIE_LOCAL_BASE_ADDRESS + (uint32_t)(addr)), (val))
 
 #ifdef QCA_WIFI_3_0
@@ -394,7 +395,7 @@ static bool hif_targ_is_awake(struct hif_softc *scn, void *__iomem *mem)
 
 	if (scn->recovery)
 		return false;
-	val = hif_read32_mb(mem + PCIE_LOCAL_BASE_ADDRESS
+	val = hif_read32_mb(scn, mem + PCIE_LOCAL_BASE_ADDRESS
 		+ RTC_STATE_ADDRESS);
 	return (RTC_STATE_V_GET(val) & RTC_STATE_V_ON) == RTC_STATE_V_ON;
 }
@@ -427,7 +428,7 @@ static void hif_pci_device_reset(struct hif_pci_softc *sc)
 	 * NB: If we try to write SOC_GLOBAL_RESET_ADDRESS without first
 	 * writing WAKE_V, the Target may scribble over Host memory!
 	 */
-	A_PCIE_LOCAL_REG_WRITE(mem, PCIE_SOC_WAKE_ADDRESS,
+	A_PCIE_LOCAL_REG_WRITE(sc, mem, PCIE_SOC_WAKE_ADDRESS,
 			       PCIE_SOC_WAKE_V_MASK);
 	for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
 		if (hif_targ_is_awake(scn, mem))
@@ -437,11 +438,11 @@ static void hif_pci_device_reset(struct hif_pci_softc *sc)
 	}
 
 	/* Put Target, including PCIe, into RESET. */
-	val = A_PCIE_LOCAL_REG_READ(mem, SOC_GLOBAL_RESET_ADDRESS);
+	val = A_PCIE_LOCAL_REG_READ(sc, mem, SOC_GLOBAL_RESET_ADDRESS);
 	val |= 1;
-	A_PCIE_LOCAL_REG_WRITE(mem, SOC_GLOBAL_RESET_ADDRESS, val);
+	A_PCIE_LOCAL_REG_WRITE(sc, mem, SOC_GLOBAL_RESET_ADDRESS, val);
 	for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
-		if (A_PCIE_LOCAL_REG_READ(mem, RTC_STATE_ADDRESS) &
+		if (A_PCIE_LOCAL_REG_READ(sc, mem, RTC_STATE_ADDRESS) &
 		    RTC_STATE_COLD_RESET_MASK)
 			break;
 
@@ -450,17 +451,18 @@ static void hif_pci_device_reset(struct hif_pci_softc *sc)
 
 	/* Pull Target, including PCIe, out of RESET. */
 	val &= ~1;
-	A_PCIE_LOCAL_REG_WRITE(mem, SOC_GLOBAL_RESET_ADDRESS, val);
+	A_PCIE_LOCAL_REG_WRITE(sc, mem, SOC_GLOBAL_RESET_ADDRESS, val);
 	for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
 		if (!
-		    (A_PCIE_LOCAL_REG_READ(mem, RTC_STATE_ADDRESS) &
+		    (A_PCIE_LOCAL_REG_READ(sc, mem, RTC_STATE_ADDRESS) &
 		     RTC_STATE_COLD_RESET_MASK))
 			break;
 
 		qdf_mdelay(1);
 	}
 
-	A_PCIE_LOCAL_REG_WRITE(mem, PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET);
+	A_PCIE_LOCAL_REG_WRITE(sc, mem, PCIE_SOC_WAKE_ADDRESS,
+			       PCIE_SOC_WAKE_RESET);
 }
 
 /* CPU warm reset function
@@ -493,7 +495,7 @@ static void hif_pci_device_warm_reset(struct hif_pci_softc *sc)
 	 * NB: If we try to write SOC_GLOBAL_RESET_ADDRESS without first
 	 * writing WAKE_V, the Target may scribble over Host memory!
 	 */
-	A_PCIE_LOCAL_REG_WRITE(mem, PCIE_SOC_WAKE_ADDRESS,
+	A_PCIE_LOCAL_REG_WRITE(sc, mem, PCIE_SOC_WAKE_ADDRESS,
 			       PCIE_SOC_WAKE_V_MASK);
 	for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
 		if (hif_targ_is_awake(scn, mem))
@@ -505,84 +507,87 @@ static void hif_pci_device_warm_reset(struct hif_pci_softc *sc)
 	 * Disable Pending interrupts
 	 */
 	val =
-		hif_read32_mb(mem +
+		hif_read32_mb(sc, mem +
 			     (SOC_CORE_BASE_ADDRESS |
 			      PCIE_INTR_CAUSE_ADDRESS));
 	HIF_INFO_MED("%s: Host Intr Cause reg 0x%x : value : 0x%x", __func__,
 		    (SOC_CORE_BASE_ADDRESS | PCIE_INTR_CAUSE_ADDRESS), val);
 	/* Target CPU Intr Cause */
-	val = hif_read32_mb(mem + (SOC_CORE_BASE_ADDRESS | CPU_INTR_ADDRESS));
+	val = hif_read32_mb(sc, mem +
+			    (SOC_CORE_BASE_ADDRESS | CPU_INTR_ADDRESS));
 	HIF_INFO_MED("%s: Target CPU Intr Cause 0x%x", __func__, val);
 
 	val =
-		hif_read32_mb(mem +
+		hif_read32_mb(sc, mem +
 			     (SOC_CORE_BASE_ADDRESS |
 			      PCIE_INTR_ENABLE_ADDRESS));
-	hif_write32_mb((mem +
+	hif_write32_mb(sc, (mem +
 		       (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS)), 0);
-	hif_write32_mb((mem + (SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS)),
-		      HOST_GROUP0_MASK);
+	hif_write32_mb(sc, (mem +
+		       (SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS)),
+		       HOST_GROUP0_MASK);
 
 	qdf_mdelay(100);
 
 	/* Clear FW_INDICATOR_ADDRESS */
 	if (HAS_FW_INDICATOR) {
-		fw_indicator = hif_read32_mb(mem + FW_INDICATOR_ADDRESS);
-		hif_write32_mb(mem + FW_INDICATOR_ADDRESS, 0);
+		fw_indicator = hif_read32_mb(sc, mem + FW_INDICATOR_ADDRESS);
+		hif_write32_mb(sc, mem + FW_INDICATOR_ADDRESS, 0);
 	}
 
 	/* Clear Target LF Timer interrupts */
 	val =
-		hif_read32_mb(mem +
+		hif_read32_mb(sc, mem +
 			     (RTC_SOC_BASE_ADDRESS +
 			      SOC_LF_TIMER_CONTROL0_ADDRESS));
 	HIF_INFO_MED("%s: addr 0x%x :  0x%x", __func__,
 	       (RTC_SOC_BASE_ADDRESS + SOC_LF_TIMER_CONTROL0_ADDRESS), val);
 	val &= ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK;
-	hif_write32_mb(mem +
+	hif_write32_mb(sc, mem +
 		      (RTC_SOC_BASE_ADDRESS + SOC_LF_TIMER_CONTROL0_ADDRESS),
 		      val);
 
 	/* Reset CE */
 	val =
-		hif_read32_mb(mem +
+		hif_read32_mb(sc, mem +
 			     (RTC_SOC_BASE_ADDRESS |
 			      SOC_RESET_CONTROL_ADDRESS));
 	val |= SOC_RESET_CONTROL_CE_RST_MASK;
-	hif_write32_mb((mem +
+	hif_write32_mb(sc, (mem +
 		       (RTC_SOC_BASE_ADDRESS | SOC_RESET_CONTROL_ADDRESS)),
 		      val);
 	val =
-		hif_read32_mb(mem +
+		hif_read32_mb(sc, mem +
 			     (RTC_SOC_BASE_ADDRESS |
 			      SOC_RESET_CONTROL_ADDRESS));
 	qdf_mdelay(10);
 
 	/* CE unreset */
 	val &= ~SOC_RESET_CONTROL_CE_RST_MASK;
-	hif_write32_mb(mem + (RTC_SOC_BASE_ADDRESS | SOC_RESET_CONTROL_ADDRESS),
-		      val);
+	hif_write32_mb(sc, mem + (RTC_SOC_BASE_ADDRESS |
+		       SOC_RESET_CONTROL_ADDRESS), val);
 	val =
-		hif_read32_mb(mem +
+		hif_read32_mb(sc, mem +
 			     (RTC_SOC_BASE_ADDRESS |
 			      SOC_RESET_CONTROL_ADDRESS));
 	qdf_mdelay(10);
 
 	/* Read Target CPU Intr Cause */
-	val = hif_read32_mb(mem + (SOC_CORE_BASE_ADDRESS | CPU_INTR_ADDRESS));
+	val = hif_read32_mb(sc, mem +
+			    (SOC_CORE_BASE_ADDRESS | CPU_INTR_ADDRESS));
 	HIF_INFO_MED("%s: Target CPU Intr Cause after CE reset 0x%x",
 		    __func__, val);
 
 	/* CPU warm RESET */
 	val =
-		hif_read32_mb(mem +
+		hif_read32_mb(sc, mem +
 			     (RTC_SOC_BASE_ADDRESS |
 			      SOC_RESET_CONTROL_ADDRESS));
 	val |= SOC_RESET_CONTROL_CPU_WARM_RST_MASK;
-	hif_write32_mb(mem + (RTC_SOC_BASE_ADDRESS | SOC_RESET_CONTROL_ADDRESS),
-		      val);
+	hif_write32_mb(sc, mem + (RTC_SOC_BASE_ADDRESS |
+		       SOC_RESET_CONTROL_ADDRESS), val);
 	val =
-		hif_read32_mb(mem +
+		hif_read32_mb(sc, mem +
 			     (RTC_SOC_BASE_ADDRESS |
 			      SOC_RESET_CONTROL_ADDRESS));
 	HIF_INFO_MED("%s: RESET_CONTROL after cpu warm reset 0x%x",
@@ -604,7 +609,7 @@ int hif_check_fw_reg(struct hif_opaque_softc *hif_ctx)
 
 	if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
 		return ATH_ISR_NOSCHED;
-	val = hif_read32_mb(mem + FW_INDICATOR_ADDRESS);
+	val = hif_read32_mb(sc, mem + FW_INDICATOR_ADDRESS);
 	if (Q_TARGET_ACCESS_END(scn) < 0)
 		return ATH_ISR_SCHED;
 
@@ -634,15 +639,15 @@ int hif_check_soc_status(struct hif_opaque_softc *hif_ctx)
 	}
 
 	/* Check PCIe local register for bar/memory access */
-	val = hif_read32_mb(sc->mem + PCIE_LOCAL_BASE_ADDRESS +
+	val = hif_read32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS +
 			   RTC_STATE_ADDRESS);
 	HIF_INFO_MED("%s: RTC_STATE_ADDRESS is %08x", __func__, val);
 
 	/* Try to wake up taget if it sleeps */
-	hif_write32_mb(sc->mem + PCIE_LOCAL_BASE_ADDRESS +
+	hif_write32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS +
 		PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_V_MASK);
 	HIF_INFO_MED("%s: PCIE_SOC_WAKE_ADDRESS is %08x", __func__,
-		hif_read32_mb(sc->mem + PCIE_LOCAL_BASE_ADDRESS +
+		hif_read32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS +
 		PCIE_SOC_WAKE_ADDRESS));
 
 	/* Check if taget can be woken up */
@@ -650,16 +655,16 @@ int hif_check_soc_status(struct hif_opaque_softc *hif_ctx)
 		if (timeout_count >= PCIE_WAKE_TIMEOUT) {
 			HIF_ERROR("%s: wake up timeout, %08x, %08x",
 				__func__,
-				hif_read32_mb(sc->mem +
+				hif_read32_mb(sc, sc->mem +
 					     PCIE_LOCAL_BASE_ADDRESS +
 					     RTC_STATE_ADDRESS),
-				hif_read32_mb(sc->mem +
+				hif_read32_mb(sc, sc->mem +
 					     PCIE_LOCAL_BASE_ADDRESS +
 					PCIE_SOC_WAKE_ADDRESS));
 			return -EACCES;
 		}
 
-		hif_write32_mb(sc->mem + PCIE_LOCAL_BASE_ADDRESS +
+		hif_write32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS +
 			      PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_V_MASK);
 
 		qdf_mdelay(100);
@@ -668,7 +673,7 @@ int hif_check_soc_status(struct hif_opaque_softc *hif_ctx)
 
 	/* Check Power register for SoC internal bus issues */
 	val =
-		hif_read32_mb(sc->mem + RTC_SOC_BASE_ADDRESS +
+		hif_read32_mb(sc, sc->mem + RTC_SOC_BASE_ADDRESS +
 			     SOC_POWER_REG_OFFSET);
 	HIF_INFO_MED("%s: Power register is %08x", __func__, val);
 
@@ -697,49 +702,51 @@ static void __hif_pci_dump_registers(struct hif_softc *scn)
 
 	/* DEBUG_INPUT_SEL_SRC = 0x6 */
 	val =
-		hif_read32_mb(mem + GPIO_BASE_ADDRESS +
+		hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS +
 			     WLAN_DEBUG_INPUT_SEL_OFFSET);
 	val &= ~WLAN_DEBUG_INPUT_SEL_SRC_MASK;
 	val |= WLAN_DEBUG_INPUT_SEL_SRC_SET(0x6);
-	hif_write32_mb(mem + GPIO_BASE_ADDRESS + WLAN_DEBUG_INPUT_SEL_OFFSET,
-		      val);
+	hif_write32_mb(sc, mem + GPIO_BASE_ADDRESS +
+		       WLAN_DEBUG_INPUT_SEL_OFFSET, val);
 
 	/* DEBUG_CONTROL_ENABLE = 0x1 */
-	val = hif_read32_mb(mem + GPIO_BASE_ADDRESS +
+	val = hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS +
 			   WLAN_DEBUG_CONTROL_OFFSET);
 	val &= ~WLAN_DEBUG_CONTROL_ENABLE_MASK;
 	val |= WLAN_DEBUG_CONTROL_ENABLE_SET(0x1);
-	hif_write32_mb(mem + GPIO_BASE_ADDRESS +
+	hif_write32_mb(sc, mem + GPIO_BASE_ADDRESS +
 		      WLAN_DEBUG_CONTROL_OFFSET, val);
 
 	HIF_INFO_MED("%s: Debug: inputsel: %x dbgctrl: %x", __func__,
-	       hif_read32_mb(mem + GPIO_BASE_ADDRESS +
+	       hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS +
 			    WLAN_DEBUG_INPUT_SEL_OFFSET),
-	       hif_read32_mb(mem + GPIO_BASE_ADDRESS +
+	       hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS +
 			    WLAN_DEBUG_CONTROL_OFFSET));
 
 	HIF_INFO_MED("%s: Debug CE", __func__);
 	/* Loop CE debug output */
 	/* AMBA_DEBUG_BUS_SEL = 0xc */
-	val = hif_read32_mb(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET);
+	val = hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS +
+			    AMBA_DEBUG_BUS_OFFSET);
 	val &= ~AMBA_DEBUG_BUS_SEL_MASK;
 	val |= AMBA_DEBUG_BUS_SEL_SET(0xc);
-	hif_write32_mb(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET, val);
+	hif_write32_mb(sc, mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET,
+		       val);
 
 	for (i = 0; i < sizeof(wrapper_idx) / sizeof(uint32_t); i++) {
 		/* For (i=1,2,3,4,8,9) write CE_WRAPPER_DEBUG_SEL = i */
-		val = hif_read32_mb(mem + CE_WRAPPER_BASE_ADDRESS +
+		val = hif_read32_mb(sc, mem + CE_WRAPPER_BASE_ADDRESS +
 				   CE_WRAPPER_DEBUG_OFFSET);
 		val &= ~CE_WRAPPER_DEBUG_SEL_MASK;
 		val |= CE_WRAPPER_DEBUG_SEL_SET(wrapper_idx[i]);
-		hif_write32_mb(mem + CE_WRAPPER_BASE_ADDRESS +
+		hif_write32_mb(sc, mem + CE_WRAPPER_BASE_ADDRESS +
 			      CE_WRAPPER_DEBUG_OFFSET, val);
 
 		HIF_INFO_MED("%s: ce wrapper: %d amdbg: %x cewdbg: %x",
 			    __func__, wrapper_idx[i],
-			    hif_read32_mb(mem + GPIO_BASE_ADDRESS +
+			    hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS +
 				AMBA_DEBUG_BUS_OFFSET),
-			    hif_read32_mb(mem + CE_WRAPPER_BASE_ADDRESS +
+			    hif_read32_mb(sc, mem + CE_WRAPPER_BASE_ADDRESS +
 				CE_WRAPPER_DEBUG_OFFSET));
 
 		if (wrapper_idx[i] <= 7) {
@@ -747,29 +754,29 @@ static void __hif_pci_dump_registers(struct hif_softc *scn)
 				ce_base = CE_BASE_ADDRESS(wrapper_idx[i]);
 				/* For (j=0~5) write CE_DEBUG_SEL = j */
 				val =
-					hif_read32_mb(mem + ce_base +
+					hif_read32_mb(sc, mem + ce_base +
 						     CE_DEBUG_OFFSET);
 				val &= ~CE_DEBUG_SEL_MASK;
 				val |= CE_DEBUG_SEL_SET(j);
-				hif_write32_mb(mem + ce_base + CE_DEBUG_OFFSET,
-					      val);
+				hif_write32_mb(sc, mem + ce_base +
+					       CE_DEBUG_OFFSET, val);
 
 				/* read (@gpio_athr_wlan_reg)
 				 * WLAN_DEBUG_OUT_DATA
 				 */
-				val = hif_read32_mb(mem + GPIO_BASE_ADDRESS +
-						   WLAN_DEBUG_OUT_OFFSET);
+				val = hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS
+						    + WLAN_DEBUG_OUT_OFFSET);
 				val = WLAN_DEBUG_OUT_DATA_GET(val);
 
 				HIF_INFO_MED("%s: module%d: cedbg: %x out: %x",
 					    __func__, j,
-					    hif_read32_mb(mem + ce_base +
+					    hif_read32_mb(sc, mem + ce_base +
 						    CE_DEBUG_OFFSET), val);
 			}
 		} else {
 			/* read (@gpio_athr_wlan_reg) WLAN_DEBUG_OUT_DATA */
 			val =
-				hif_read32_mb(mem + GPIO_BASE_ADDRESS +
+				hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS +
 					     WLAN_DEBUG_OUT_OFFSET);
 			val = WLAN_DEBUG_OUT_DATA_GET(val);
 
@@ -780,31 +787,33 @@ static void __hif_pci_dump_registers(struct hif_softc *scn)
 	HIF_INFO_MED("%s: Debug PCIe:", __func__);
 	/* Loop PCIe debug output */
 	/* Write AMBA_DEBUG_BUS_SEL = 0x1c */
-	val = hif_read32_mb(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET);
+	val = hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS +
+			    AMBA_DEBUG_BUS_OFFSET);
 	val &= ~AMBA_DEBUG_BUS_SEL_MASK;
 	val |= AMBA_DEBUG_BUS_SEL_SET(0x1c);
-	hif_write32_mb(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET, val);
+	hif_write32_mb(sc, mem + GPIO_BASE_ADDRESS +
+		       AMBA_DEBUG_BUS_OFFSET, val);
 
 	for (i = 0; i <= 8; i++) {
 		/* For (i=1~8) write AMBA_DEBUG_BUS_PCIE_DEBUG_SEL = i */
 		val =
-			hif_read32_mb(mem + GPIO_BASE_ADDRESS +
+			hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS +
 				     AMBA_DEBUG_BUS_OFFSET);
 		val &= ~AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK;
 		val |= AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(i);
-		hif_write32_mb(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET,
-			      val);
+		hif_write32_mb(sc, mem + GPIO_BASE_ADDRESS +
+			       AMBA_DEBUG_BUS_OFFSET, val);
 
 		/* read (@gpio_athr_wlan_reg) WLAN_DEBUG_OUT_DATA */
 		val =
-			hif_read32_mb(mem + GPIO_BASE_ADDRESS +
+			hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS +
 				     WLAN_DEBUG_OUT_OFFSET);
 		val = WLAN_DEBUG_OUT_DATA_GET(val);
 
 		HIF_INFO_MED("%s: amdbg: %x out: %x %x", __func__,
-		       hif_read32_mb(mem + GPIO_BASE_ADDRESS +
+		       hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS +
 				    WLAN_DEBUG_OUT_OFFSET), val,
-		       hif_read32_mb(mem + GPIO_BASE_ADDRESS +
+		       hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS +
 				    WLAN_DEBUG_OUT_OFFSET));
 	}
 
@@ -1467,7 +1476,7 @@ static void hif_wake_target_cpu(struct hif_softc *scn)
  */
 static void soc_wake_reset(struct hif_softc *scn)
 {
-	hif_write32_mb(scn->mem +
+	hif_write32_mb(scn, scn->mem +
 		PCIE_LOCAL_BASE_ADDRESS +
 		PCIE_SOC_WAKE_ADDRESS,
 		PCIE_SOC_WAKE_RESET);
@@ -1536,7 +1545,7 @@ static void hif_set_hia_extnd(struct hif_softc *scn)
 		 * in RTC space
 		 */
 		tgt_info->target_revision
-			= CHIP_ID_REVISION_GET(hif_read32_mb(scn->mem
+			= CHIP_ID_REVISION_GET(hif_read32_mb(scn, scn->mem
 					+ CHIP_ID_ADDRESS));
 		qdf_print(KERN_INFO"chip_id 0x%x chip_revision 0x%x\n",
 			target_type, tgt_info->target_revision);
@@ -1718,7 +1727,7 @@ static int hif_set_hia(struct hif_softc *scn)
 #ifdef QCA_WIFI_3_0
 	i = 0;
 	while (i < HIF_HIA_MAX_POLL_LOOP) {
-		host_interest_area = hif_read32_mb(scn->mem +
+		host_interest_area = hif_read32_mb(scn, scn->mem +
 						A_SOC_CORE_SCRATCH_0_ADDRESS);
 		if ((host_interest_area & 0x01) == 0) {
 			qdf_mdelay(HIF_HIA_POLLING_DELAY_MS);
@@ -1728,7 +1737,7 @@ static int hif_set_hia(struct hif_softc *scn)
 				HIF_ERROR("%s: poll timeout(%d)", __func__, i);
 		} else {
 			host_interest_area &= (~0x01);
-			hif_write32_mb(scn->mem + 0x113014, 0);
+			hif_write32_mb(scn, scn->mem + 0x113014, 0);
 			break;
 		}
 	}
@@ -2243,7 +2252,7 @@ static int hif_pci_probe_tgt_wakeup(struct hif_pci_softc *sc)
 	 * We try to catch that here in order to reset the Target and
 	 * retry the probe.
 	 */
-	hif_write32_mb(sc->mem + PCIE_LOCAL_BASE_ADDRESS +
+	hif_write32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS +
 				  PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_V_MASK);
 	while (!hif_targ_is_awake(scn, sc->mem)) {
 		if (0 == targ_awake_limit) {
@@ -2260,7 +2269,7 @@ static int hif_pci_probe_tgt_wakeup(struct hif_pci_softc *sc)
 		int wait_limit = 200;
 		/* Synchronization point: wait the BAR0 is configured */
 		while (wait_limit-- &&
-			   !(hif_read32_mb(sc->mem +
+			   !(hif_read32_mb(sc, c->mem +
 					  PCIE_LOCAL_BASE_ADDRESS +
 					  PCIE_SOC_RDY_STATUS_ADDRESS)
 					  & PCIE_SOC_RDY_STATUS_BAR_MASK)) {
@@ -2277,8 +2286,8 @@ static int hif_pci_probe_tgt_wakeup(struct hif_pci_softc *sc)
 #endif
 
 #ifndef QCA_WIFI_3_0
-	fw_indicator = hif_read32_mb(sc->mem + FW_INDICATOR_ADDRESS);
-	hif_write32_mb(sc->mem + PCIE_LOCAL_BASE_ADDRESS +
+	fw_indicator = hif_read32_mb(sc, sc->mem + FW_INDICATOR_ADDRESS);
+	hif_write32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS +
 				  PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET);
 
 	if (fw_indicator & FW_IND_INITIALIZED) {
@@ -2429,10 +2438,10 @@ static int hif_configure_msi(struct hif_pci_softc *sc)
 	}
 
 	if (ret == 0) {
-		hif_write32_mb(sc->mem+(SOC_CORE_BASE_ADDRESS |
+		hif_write32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS |
 			  PCIE_INTR_ENABLE_ADDRESS),
 			  HOST_GROUP0_MASK);
-		hif_write32_mb(sc->mem +
+		hif_write32_mb(sc, sc->mem +
 			  PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS,
 			  PCIE_SOC_WAKE_RESET);
 	}
@@ -2469,12 +2478,12 @@ static int hif_pci_configure_legacy_irq(struct hif_pci_softc *sc)
 	 */
 	sc->irq = sc->pdev->irq;
 	/* Use Legacy PCI Interrupts */
-	hif_write32_mb(sc->mem+(SOC_CORE_BASE_ADDRESS |
+	hif_write32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS |
 		  PCIE_INTR_ENABLE_ADDRESS),
 		  HOST_GROUP0_MASK);
-	hif_read32_mb(sc->mem+(SOC_CORE_BASE_ADDRESS |
+	hif_read32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS |
 			       PCIE_INTR_ENABLE_ADDRESS));
-	hif_write32_mb(sc->mem + PCIE_LOCAL_BASE_ADDRESS +
+	hif_write32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS +
 		      PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET);
 
 	if ((target_type == TARGET_TYPE_IPQ4019) ||
@@ -2485,7 +2494,7 @@ static int hif_pci_configure_legacy_irq(struct hif_pci_softc *sc)
 			(target_type == TARGET_TYPE_AR6320V1) ||
 			(target_type == TARGET_TYPE_AR6320V2) ||
 			(target_type == TARGET_TYPE_AR6320V3)) {
-		hif_write32_mb(scn->mem + PCIE_LOCAL_BASE_ADDRESS +
+		hif_write32_mb(scn, scn->mem + PCIE_LOCAL_BASE_ADDRESS +
 				PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_V_MASK);
 	}
 end:
@@ -2619,8 +2628,8 @@ void hif_pci_disable_bus(struct hif_softc *scn)
 	if (ADRASTEA_BU) {
 		hif_vote_link_down(GET_HIF_OPAQUE_HDL(scn));
 
-		hif_write32_mb(sc->mem + PCIE_INTR_ENABLE_ADDRESS, 0);
-		hif_write32_mb(sc->mem + PCIE_INTR_CLR_ADDRESS,
+		hif_write32_mb(sc, sc->mem + PCIE_INTR_ENABLE_ADDRESS, 0);
+		hif_write32_mb(sc, sc->mem + PCIE_INTR_CLR_ADDRESS,
 			       HOST_GROUP0_MASK);
 	}
 
@@ -3228,11 +3237,11 @@ static int hif_log_soc_wakeup_timeout(struct hif_pci_softc *sc)
 	HIF_ERROR("%s: PCI BAR 0 = 0x%08x", __func__, bar);
 
 	HIF_ERROR("%s: SOC_WAKE_ADDR 0%08x", __func__,
-			hif_read32_mb(pci_addr + PCIE_LOCAL_BASE_ADDRESS +
+			hif_read32_mb(scn, pci_addr + PCIE_LOCAL_BASE_ADDRESS +
 						PCIE_SOC_WAKE_ADDRESS));
 
 	HIF_ERROR("%s: RTC_STATE_ADDR 0x%08x", __func__,
-			hif_read32_mb(pci_addr + PCIE_LOCAL_BASE_ADDRESS +
+			hif_read32_mb(scn, pci_addr + PCIE_LOCAL_BASE_ADDRESS +
 							RTC_STATE_ADDRESS));
 
 	HIF_ERROR("%s:error, wakeup target", __func__);
@@ -3337,7 +3346,7 @@ int hif_pci_target_sleep_state_adjust(struct hif_softc *scn,
 		} else {
 			if (hif_state->keep_awake_count == 0) {
 				/* Force AWAKE */
-				hif_write32_mb(pci_addr +
+				hif_write32_mb(sc, pci_addr +
 					      PCIE_LOCAL_BASE_ADDRESS +
 					      PCIE_SOC_WAKE_ADDRESS,
 					      PCIE_SOC_WAKE_V_MASK);
@@ -3382,15 +3391,15 @@ int hif_pci_target_sleep_state_adjust(struct hif_softc *scn,
 		debug = 0;
 		HIF_ERROR("%s: INTR_ENABLE_REG = 0x%08x, INTR_CAUSE_REG = 0x%08x, CPU_INTR_REG = 0x%08x, INTR_CLR_REG = 0x%08x, CE_INTERRUPT_SUMMARY_REG = 0x%08x",
 			__func__,
-			hif_read32_mb(sc->mem + SOC_CORE_BASE_ADDRESS +
+			hif_read32_mb(sc, sc->mem + SOC_CORE_BASE_ADDRESS +
 				PCIE_INTR_ENABLE_ADDRESS),
-			hif_read32_mb(sc->mem + SOC_CORE_BASE_ADDRESS +
+			hif_read32_mb(sc, sc->mem + SOC_CORE_BASE_ADDRESS +
 				PCIE_INTR_CAUSE_ADDRESS),
-			hif_read32_mb(sc->mem + SOC_CORE_BASE_ADDRESS +
+			hif_read32_mb(sc, sc->mem + SOC_CORE_BASE_ADDRESS +
 				CPU_INTR_ADDRESS),
-			hif_read32_mb(sc->mem + SOC_CORE_BASE_ADDRESS +
+			hif_read32_mb(sc, sc->mem + SOC_CORE_BASE_ADDRESS +
 				PCIE_INTR_CLR_ADDRESS),
-			hif_read32_mb(sc->mem + CE_WRAPPER_BASE_ADDRESS +
+			hif_read32_mb(sc, sc->mem + CE_WRAPPER_BASE_ADDRESS +
 				CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS));
 	}
 
@@ -3404,7 +3413,7 @@ uint32_t hif_target_read_checked(struct hif_softc *scn, uint32_t offset)
 	void *addr;
 
 	addr = scn->mem + offset;
-	value = hif_read32_mb(addr);
+	value = hif_read32_mb(scn, addr);
 
 	{
 		unsigned long irq_flags;
@@ -3428,7 +3437,7 @@ hif_target_write_checked(struct hif_softc *scn, uint32_t offset, uint32_t value)
 	void *addr;
 
 	addr = scn->mem + (offset);
-	hif_write32_mb(addr, value);
+	hif_write32_mb(scn, addr, value);
 
 	{
 		unsigned long irq_flags;
@@ -3732,11 +3741,11 @@ end:
  */
 static void hif_target_sync(struct hif_softc *scn)
 {
-	hif_write32_mb(scn->mem+(SOC_CORE_BASE_ADDRESS |
+	hif_write32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS |
 				PCIE_INTR_ENABLE_ADDRESS),
 				PCIE_INTR_FIRMWARE_MASK);
 
-	hif_write32_mb(scn->mem + PCIE_LOCAL_BASE_ADDRESS +
+	hif_write32_mb(scn, scn->mem + PCIE_LOCAL_BASE_ADDRESS +
 			PCIE_SOC_WAKE_ADDRESS,
 			PCIE_SOC_WAKE_V_MASK);
 	while (!hif_targ_is_awake(scn, scn->mem))
@@ -3748,13 +3757,13 @@ static void hif_target_sync(struct hif_softc *scn)
 
 		HIF_TRACE("%s: Loop checking FW signal", __func__);
 		while (1) {
-			fw_ind = hif_read32_mb(scn->mem +
+			fw_ind = hif_read32_mb(scn, scn->mem +
 					FW_INDICATOR_ADDRESS);
 			if (fw_ind & FW_IND_INITIALIZED)
 				break;
 			if (wait_limit-- < 0)
 				break;
-			hif_write32_mb(scn->mem+(SOC_CORE_BASE_ADDRESS |
+			hif_write32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS |
 				PCIE_INTR_ENABLE_ADDRESS),
 				PCIE_INTR_FIRMWARE_MASK);
 
@@ -3767,7 +3776,7 @@ static void hif_target_sync(struct hif_softc *scn)
 			HIF_TRACE("%s: Got FW signal, retries = %x",
 					__func__, 500-wait_limit);
 	}
-	hif_write32_mb(scn->mem + PCIE_LOCAL_BASE_ADDRESS +
+	hif_write32_mb(scn, scn->mem + PCIE_LOCAL_BASE_ADDRESS +
 			PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET);
 }
 
@@ -3786,6 +3795,28 @@ static void hif_pci_get_soc_info(struct hif_pci_softc *sc, struct device *dev)
 {}
 #endif
 
+#ifdef HIF_REG_WINDOW_SUPPORT
+static void hif_pci_init_reg_windowing_support(struct hif_pci_softc *sc,
+					       u32 target_type)
+{
+	switch (target_type) {
+	case TARGET_TYPE_QCN7605:
+		sc->use_register_windowing = true;
+		qdf_spinlock_create(&sc->register_access_lock);
+		sc->register_window = 0;
+		break;
+	default:
+		sc->use_register_windowing = false;
+	}
+}
+#else
+static void hif_pci_init_reg_windowing_support(struct hif_pci_softc *sc,
+					       u32 target_type)
+{
+	sc->use_register_windowing = false;
+}
+#endif
+
 /**
  * hif_enable_bus(): enable bus
  *
@@ -3856,6 +3887,8 @@ again:
 	hif_register_tbl_attach(ol_sc, hif_type);
 	hif_target_register_tbl_attach(ol_sc, target_type);
 
+	hif_pci_init_reg_windowing_support(sc, target_type);
+
 	tgt_info->target_type = target_type;
 
 	if (ce_srng_based(ol_sc)) {
@@ -3926,12 +3959,12 @@ void hif_pci_irq_enable(struct hif_softc *scn, int ce_id)
 			(scn->target_status != TARGET_STATUS_RESET) &&
 			(!qdf_atomic_read(&scn->link_suspended))) {
 
-			hif_write32_mb(scn->mem +
+			hif_write32_mb(scn, scn->mem +
 				(SOC_CORE_BASE_ADDRESS |
 				PCIE_INTR_ENABLE_ADDRESS),
 				HOST_GROUP0_MASK);
 
-			hif_read32_mb(scn->mem +
+			hif_read32_mb(scn, scn->mem +
 					(SOC_CORE_BASE_ADDRESS |
 					PCIE_INTR_ENABLE_ADDRESS));
 		}

hif/src/pcie/if_pci.h

@@ -116,6 +116,9 @@ struct hif_pci_softc {
 	u16 devid;
 	struct hif_tasklet_entry tasklet_entries[HIF_MAX_TASKLET_NUM];
 	bool pci_enabled;
+	bool use_register_windowing;
+	uint32_t register_window;
+	qdf_spinlock_t register_access_lock;
 	qdf_spinlock_t irq_lock;
 	qdf_work_t reschedule_tasklet_work;
 	uint32_t lcr_val;

hif/src/pcie/if_pci_internal.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2016, 2018 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -34,12 +34,12 @@
 #define PCI_CLR_CAUSE0_REGISTER(sc) \
 { \
 	uint32_t tmp_cause0; \
-	tmp_cause0 = hif_read32_mb(sc->mem + PCIE_INTR_CAUSE_ADDRESS); \
-	hif_write32_mb(sc->mem + PCIE_INTR_CLR_ADDRESS, \
+	tmp_cause0 = hif_read32_mb(sc, sc->mem + PCIE_INTR_CAUSE_ADDRESS); \
+	hif_write32_mb(sc, sc->mem + PCIE_INTR_CLR_ADDRESS, \
 		      PCIE_INTR_FIRMWARE_MASK | tmp_cause0); \
-	hif_read32_mb(sc->mem + PCIE_INTR_CLR_ADDRESS); \
-	hif_write32_mb(sc->mem + PCIE_INTR_CLR_ADDRESS, 0); \
-	hif_read32_mb(sc->mem + PCIE_INTR_CLR_ADDRESS); \
+	hif_read32_mb(sc, sc->mem + PCIE_INTR_CLR_ADDRESS); \
+	hif_write32_mb(sc, sc->mem + PCIE_INTR_CLR_ADDRESS, 0); \
+	hif_read32_mb(sc, sc->mem + PCIE_INTR_CLR_ADDRESS); \
 }
 #else
 #define PCI_CLR_CAUSE0_REGISTER(sc)

hif/src/snoc/hif_io32_snoc.h

@@ -42,7 +42,7 @@ static inline void ce_enable_irq_in_individual_register(struct hif_softc *scn,
 		hif_err_rl("%s: target access is not allowed", __func__);
 		return;
 	}
-	hif_write32_mb(scn->mem + offset, 1);
+	hif_write32_mb(scn, scn->mem + offset, 1);
 }
 
 static inline void ce_disable_irq_in_individual_register(struct hif_softc *scn,
@@ -55,12 +55,12 @@ static inline void ce_disable_irq_in_individual_register(struct hif_softc *scn,
 		hif_err_rl("%s: target access is not allowed", __func__);
 		return;
 	}
-	hif_write32_mb(scn->mem + offset, 0);
+	hif_write32_mb(scn, scn->mem + offset, 0);
 
 	if (!TARGET_REGISTER_ACCESS_ALLOWED(scn)) {
 		hif_err_rl("%s: target access is not allowed", __func__);
 		return;
 	}
-	hif_read32_mb(scn->mem + offset);
+	hif_read32_mb(scn, scn->mem + offset);
 }
 #endif

hif/src/snoc/if_ahb.c

@@ -234,13 +234,12 @@ int hif_ahb_configure_legacy_irq(struct hif_pci_softc *sc)
 	sc->irq = irq;
 
 	/* Use Legacy PCI Interrupts */
-	hif_write32_mb(sc->mem+(SOC_CORE_BASE_ADDRESS |
+	hif_write32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS |
 				PCIE_INTR_ENABLE_ADDRESS),
 			PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
 	/* read once to flush */
-	hif_read32_mb(sc->mem+(SOC_CORE_BASE_ADDRESS |
-				PCIE_INTR_ENABLE_ADDRESS)
-		     );
+	hif_read32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS |
+				PCIE_INTR_ENABLE_ADDRESS));
 
 end:
 	return ret;
@@ -367,32 +366,32 @@ int hif_target_sync_ahb(struct hif_softc *scn)
 	int limit = 0;
 
 	while (limit < 50) {
-		hif_write32_mb(scn->mem +
+		hif_write32_mb(scn, scn->mem +
 			(SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS),
 			PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
 		qdf_mdelay(10);
-		val = hif_read32_mb(scn->mem +
+		val = hif_read32_mb(scn, scn->mem +
 			(SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS));
 		if (val == 0)
 			break;
 		limit++;
 	}
-	hif_write32_mb(scn->mem +
+	hif_write32_mb(scn, scn->mem +
 		(SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS),
 		PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
-	hif_write32_mb(scn->mem + FW_INDICATOR_ADDRESS, FW_IND_HOST_READY);
+	hif_write32_mb(scn, scn->mem + FW_INDICATOR_ADDRESS, FW_IND_HOST_READY);
 	if (HAS_FW_INDICATOR) {
 		int wait_limit = 500;
 		int fw_ind = 0;
 
 		while (1) {
-			fw_ind = hif_read32_mb(scn->mem +
+			fw_ind = hif_read32_mb(scn, scn->mem +
 					FW_INDICATOR_ADDRESS);
 			if (fw_ind & FW_IND_INITIALIZED)
 				break;
 			if (wait_limit-- < 0)
 				break;
-			hif_write32_mb(scn->mem+(SOC_CORE_BASE_ADDRESS |
+			hif_write32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS |
 				PCIE_INTR_ENABLE_ADDRESS),
 				PCIE_INTR_FIRMWARE_MASK);
 			qdf_mdelay(10);
@@ -649,25 +648,26 @@ void hif_ahb_irq_enable(struct hif_softc *scn, int ce_id)
 		if (target_ce_conf->pipedir & PIPEDIR_OUT) {
 			reg_offset = HOST_IE_ADDRESS;
 			qdf_spin_lock_irqsave(&hif_state->irq_reg_lock);
-			regval = hif_read32_mb(scn->mem + reg_offset);
+			regval = hif_read32_mb(scn, scn->mem + reg_offset);
 			regval |= HOST_IE_REG1_CE_BIT(ce_id);
-			hif_write32_mb(scn->mem + reg_offset, regval);
+			hif_write32_mb(scn, scn->mem + reg_offset, regval);
 			qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock);
 		}
 		if (target_ce_conf->pipedir & PIPEDIR_IN) {
 			reg_offset = HOST_IE_ADDRESS_2;
 			qdf_spin_lock_irqsave(&hif_state->irq_reg_lock);
-			regval = hif_read32_mb(scn->mem + reg_offset);
+			regval = hif_read32_mb(scn, scn->mem + reg_offset);
 			regval |= HOST_IE_REG2_CE_BIT(ce_id);
-			hif_write32_mb(scn->mem + reg_offset, regval);
+			hif_write32_mb(scn, scn->mem + reg_offset, regval);
 			if (tgt_info->target_type == TARGET_TYPE_QCA8074) {
 				/* Enable destination ring interrupts for 8074
 				 * TODO: To be removed in 2.0 HW */
-				regval = hif_read32_mb(scn->mem +
+				regval = hif_read32_mb(scn, scn->mem +
 					HOST_IE_ADDRESS_3);
 				regval |= HOST_IE_REG3_CE_BIT(ce_id);
 			}
-			hif_write32_mb(scn->mem + HOST_IE_ADDRESS_3, regval);
+			hif_write32_mb(scn, scn->mem + HOST_IE_ADDRESS_3,
+				       regval);
 			qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock);
 		}
 	} else {
@@ -694,25 +694,26 @@ void hif_ahb_irq_disable(struct hif_softc *scn, int ce_id)
 		if (target_ce_conf->pipedir & PIPEDIR_OUT) {
 			reg_offset = HOST_IE_ADDRESS;
 			qdf_spin_lock_irqsave(&hif_state->irq_reg_lock);
-			regval = hif_read32_mb(scn->mem + reg_offset);
+			regval = hif_read32_mb(scn, scn->mem + reg_offset);
 			regval &= ~HOST_IE_REG1_CE_BIT(ce_id);
-			hif_write32_mb(scn->mem + reg_offset, regval);
+			hif_write32_mb(scn, scn->mem + reg_offset, regval);
 			qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock);
 		}
 		if (target_ce_conf->pipedir & PIPEDIR_IN) {
 			reg_offset = HOST_IE_ADDRESS_2;
 			qdf_spin_lock_irqsave(&hif_state->irq_reg_lock);
-			regval = hif_read32_mb(scn->mem + reg_offset);
+			regval = hif_read32_mb(scn, scn->mem + reg_offset);
 			regval &= ~HOST_IE_REG2_CE_BIT(ce_id);
-			hif_write32_mb(scn->mem + reg_offset, regval);
+			hif_write32_mb(scn, scn->mem + reg_offset, regval);
 			if (tgt_info->target_type == TARGET_TYPE_QCA8074) {
 				/* Disable destination ring interrupts for 8074
 				 * TODO: To be removed in 2.0 HW */
-				regval = hif_read32_mb(scn->mem +
+				regval = hif_read32_mb(scn, scn->mem +
 					HOST_IE_ADDRESS_3);
 				regval &= ~HOST_IE_REG3_CE_BIT(ce_id);
 			}
-			hif_write32_mb(scn->mem + HOST_IE_ADDRESS_3, regval);
+			hif_write32_mb(scn, scn->mem + HOST_IE_ADDRESS_3,
+				       regval);
 			qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock);
 		}
 	}

hif/src/snoc/if_ahb_reset.c

@@ -151,8 +151,8 @@ int hif_ahb_enable_radio(struct hif_pci_softc *sc,
 
 	/* Program the above values into Wifi scratch regists */
 	if (msienable) {
-		hif_write32_mb(sc->mem + FW_AXI_MSI_ADDR, msi_addr);
-		hif_write32_mb(sc->mem + FW_AXI_MSI_DATA, msi_base);
+		hif_write32_mb(sc, sc->mem + FW_AXI_MSI_ADDR, msi_addr);
+		hif_write32_mb(sc, sc->mem + FW_AXI_MSI_DATA, msi_base);
 	}
 
 	/* TBD: Temporary changes. Frequency should be
@@ -181,7 +181,8 @@ int hif_ahb_enable_radio(struct hif_pci_softc *sc,
 			HIF_INFO("%s: GCC ioremap failed\n", __func__);
 			return PTR_ERR(mem_gcc);
 		}
-		gcc_fepll_pll_div = hif_read32_mb(mem_gcc + GCC_FEPLL_PLL_DIV);
+		gcc_fepll_pll_div = hif_read32_mb(sc, mem_gcc +
+						  GCC_FEPLL_PLL_DIV);
 		clk_sel = (wifi_core_id == 0) ? ((gcc_fepll_pll_div &
 				GCC_FEPLL_PLL_CLK_WIFI_0_SEL_MASK) >>
 					GCC_FEPLL_PLL_CLK_WIFI_0_SEL_SHIFT) :
@@ -191,7 +192,8 @@ int hif_ahb_enable_radio(struct hif_pci_softc *sc,
 
 		HIF_INFO("Wifi%d CPU frequency %u\n", wifi_core_id,
 							current_freq);
-		hif_write32_mb(sc->mem + FW_CPU_PLL_CONFIG, gcc_fepll_pll_div);
+		hif_write32_mb(sc, sc->mem + FW_CPU_PLL_CONFIG,
+			       gcc_fepll_pll_div);
 		iounmap(mem_gcc);
 	}
 
@@ -282,7 +284,8 @@ void hif_ahb_device_reset(struct hif_softc *scn)
 	int wait_limit = ATH_AHB_RESET_WAIT_MAX;
 
 
-	wifi_core_id = hif_read32_mb(sc->mem + WLAN_SUBSYSTEM_CORE_ID_ADDRESS);
+	wifi_core_id = hif_read32_mb(sc, sc->mem +
+				     WLAN_SUBSYSTEM_CORE_ID_ADDRESS);
 	glb_cfg_offset = (wifi_core_id == 0) ? TCSR_WIFI0_GLB_CFG :
 							TCSR_WIFI1_GLB_CFG;
 	haltreq_offset = (wifi_core_id == 0) ? TCSR_WCSS0_HALTREQ :
@@ -295,20 +298,20 @@ void hif_ahb_device_reset(struct hif_softc *scn)
 		HIF_INFO("%s: TCSR ioremap failed\n", __func__);
 		return;
 	}
-	reg_value = hif_read32_mb(mem_tcsr + haltreq_offset);
-	hif_write32_mb(mem_tcsr + haltreq_offset, reg_value | 0x1);
+	reg_value = hif_read32_mb(sc, mem_tcsr + haltreq_offset);
+	hif_write32_mb(sc, mem_tcsr + haltreq_offset, reg_value | 0x1);
 	/* Wait for halt ack before asserting reset */
 	while (wait_limit) {
 
-		if (hif_read32_mb(mem_tcsr + haltack_offset) & 0x1)
+		if (hif_read32_mb(sc, mem_tcsr + haltack_offset) & 0x1)
 			break;
 
 		qdf_mdelay(1);
 		wait_limit--;
 	}
 
-	reg_value = hif_read32_mb(mem_tcsr + glb_cfg_offset);
-	hif_write32_mb(mem_tcsr + glb_cfg_offset, reg_value | (1 << 25));
+	reg_value = hif_read32_mb(sc, mem_tcsr + glb_cfg_offset);
+	hif_write32_mb(sc, mem_tcsr + glb_cfg_offset, reg_value | (1 << 25));
 
 	core_resetctl = reset_control_get(&pdev->dev, AHB_RESET_TYPE);
 	if (IS_ERR(core_resetctl)) {
@@ -368,10 +371,10 @@ void hif_ahb_device_reset(struct hif_softc *scn)
 	reset_control_put(resetctl);
 
 	/* Clear gbl_cfg and haltreq before clearing Wifi core reset */
-	reg_value = hif_read32_mb(mem_tcsr + haltreq_offset);
-	hif_write32_mb(mem_tcsr + haltreq_offset, reg_value & ~0x1);
-	reg_value = hif_read32_mb(mem_tcsr + glb_cfg_offset);
-	hif_write32_mb(mem_tcsr + glb_cfg_offset, reg_value & ~(1 << 25));
+	reg_value = hif_read32_mb(sc, mem_tcsr + haltreq_offset);
+	hif_write32_mb(sc, mem_tcsr + haltreq_offset, reg_value & ~0x1);
+	reg_value = hif_read32_mb(sc, mem_tcsr + glb_cfg_offset);
+	hif_write32_mb(sc, mem_tcsr + glb_cfg_offset, reg_value & ~(1 << 25));
 
 	/* de-assert wifi core reset */
 	reset_control_deassert(core_resetctl);