In the case of DMS the dsi phy timings get updated in
dsi_display_set_mode() and the clock in pre_kickoff().
This brings a mismatch between phy timing and the clock between the
above two operations. For example, during dsi_display_enable(),
the HW is programmed with the new phy timings but the clock is still
running at the older rate. This mismatch can lead to screen flicker
or error.
Update the phy timings and clocks together during pre_kickoff().
Change-Id: I30198e91aba5879b1773103c088d94175639790c
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Set topology override to cmdline topology before parsing timings so that
correct topology is set in mode.
Change-Id: I7ba371370c71516b436dbe5ec07064f7b54975bb
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
In legacy POMS feature, there were separate timing nodes for
video and command mode. So, while calculating the total number
of modes, 1 extra mode is added for command mode if POMS feature
is enabled in video mode panel.
But as per the new design, this is clubbed into one timing node.
So, there is no separate mode for command mode. This change removes
the check to add 1 extra mode count otherwise it leads to null
pointer dereference while getting lm for this extra mode. Also
avoid overriding mode capability when POMS is enabled.
Change-Id: I73f3b89b22f566e40c88178f2af392214b1ada8d
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
In case of underflow/overflow IRQ storm, send panel dead event from
scheduled underflow and overflow workqueue handler.
Change-Id: Ic6cd6cbae097ea970a392fa99e30b3b620633d40
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
Suppose there's a mode change in Nth commit and N+1th commit mode
change request for dynamic clock came even before the Nth commit
mode is set in DSI. Now, restoring the bit clock and porches during
mode set of Nth commit will update the clock and porches according
to the new dynamic clock request which should have actually been
handled in N+1th commit mode set and this can lead to DSI underflow
/overflow.
Avoid restoring bit clock during bridge enable as it is already
taken care during bridge mode fixup.
Change-Id: Ieecb0020a77f5e082a8b9da0ecf461acdbe89e0c
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
To set frequencies for link clks, the clk manager index of
ctrl is require. Use ctrl cell index to get clk manager index.
Change-Id: I175d0721e672fb4d368349584c8b448ba63f4224
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
Acquire mngr clk_mutex before updating link clock frequencies.
Failing this may lead to race around condition while setting the
link clock frequency rates.
Make sure byteclk and pclk rates of PLL are configured according
to clock manager and not the controller.
Change-Id: I2cd26e659ce166d5bc55eb6c060672eeee192bea
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
In the case of DSI underflow or overflow, skip enabling back the DSI error
interrupts and instead send panel_dead. The error interrupt will be enabled
later by HAL as part of handling panel_dead event. Not enabling back the
DSI error interrupts immediately can prevent IRQ storm from occurring.
Change-Id: I769872bb5ac9ef8826c3e4caaab7723901dfc7d8
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
During qsync frequency step down, it is possible for the changing
frame window to lead to frame buffers being transferred when it
is unsafe to update. Pineapple r2 hardware supports using the
panel's TE level, instead of the start window, to trigger the
frame transfer.
This change enables using TE level during QSYNC or AVR, if the
hardware supports it.
Change-Id: Ie675edaaeb80921c639905395b709f4c67134fc7
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Support 8bit and 10bit bpp switch for display.
Change-Id: Ia5fcb330df95618596377773d0598be2b5609de1
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
In case of DATABUS_WIDEN, follow the HPG to calculate bitclk,
byteclk and pclk. Configure the DST_FORMAT and the clock
dividers in DSI PHY and DISP_CC w.r.t. the bpp before
compression.
Change-Id: I526eab5bc88b8d667b8b1a0d257b2f147998286a
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Currently we are always doing command transfer cleanup which includes
disabling command engine, clocks, gdsc and unmasking overflow interrupt
as part of post command transfer function only after CMD DMA wait is
done. Cleanup should also be done if an ESD failure happens before
kickoff of a batch command. Organize code so that command transfer
cleanup can be done irrespective of whether command kickoff is done
or not.
Change-Id: Ieb92daa7f5da62c16c71f1b23ceff20adfbf3621
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Qsync ON/OFF commands have to be sent to the panel before connector
kickoff and sending them in the commit thread blocks it for few
millliseconds, and can lead to frame drops. Avoid this by sending
them asyncronously.
Change-Id: Ia7bc694871faf02b7c1a068b3d0ee7056c272506
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Replaced lane swap register for lane swap in DSI controller.
Added check for where to perform lane swap based on DSI controller
version. Replaced function to parse device tree data for lane swap,
as previous function did not work.
Change-Id: I5e50a761b6ac0d2658ba73a5648e2f80f3470b96
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
The clk_ctrl_cb and post_cmd_tx_workq callbacks are assigned
to individual ctrl during display bind. In case of dual display
with shared DSI, where primary display has ctrl0 & ctrl1 and
secondary display has ctrl1, the callbacks of ctrl1 of the
primary display gets overwritten with the callbacks of ctrl1
of the secondary display.
In the shared DSI design, only one display will be active at
a time. So, move the callback assignment of clk_ctrl_cb and
post_cmd_tx_workq to display prepare to fix this.
Change-Id: Ic02fa2f00c430fd5759400e06d82d004d4f7cba4
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
Add capability to read avr step for each timing mode. This will
be in addition to the existing avr-step-list which is defined
when dfps is enabled. Expose the avr-step as part of each
mode in connector caps to user-mode.
Additionally, change the avr_step connector property to enum
to give usermode just the capability to enable/disable avr-step
and not alter the step value as its fixed from the device tree.
Change-Id: I6d7f8e9fcf03f98abef7640fc741e5e1be8597a1
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add DCS command to read the panel scan line value and associated
time stamp in nano-seconds.
Change-Id: I06a76d3a6c5ad7a2e7681413c741e5b97b34d73f
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
This change adds support for bypassing hw access in DSI PHY/PLL
drivers which enables the DSI driver to run on emulation
platforms that might be missing those modules.
Change-Id: I3e83155a79d60f2357606746214d776cefabd651
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Signed-off-by: Alex Danila <quic_eadanila@quicinc.com>
Allow TPG patterns to be displayed on command mode and
video mode panels.
Change-Id: Ie9ba9b404ceb965f8a06d1f19e932dd2e051983b
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
This change moves warning log to info log if secondary default panel
is not available.
Change-Id: Iad420a05c6440afdf0fcc5f7d33197eaf5c158c4
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
When display is left on from the bootloader, disp_cc driver will put a
proxy vote on clocks to maintain the hardware configuration of bootloader.
Once all the consumers have been probed, the dispcc driver will synchronize
the hardware state of the device to match the aggregated software state
requested by all the consumers using sync_state call.
If there is an idle power collapse or a suspend before sync state call,
branch clocks and in turn RCG will not get turned off during clocks
disable sequence because of the proxy vote of disp_cc driver. This can be
the case even if there is a vote from any other disp_cc consumers.
During a subsequent call to enable the clocks from DSI driver, we are
currently switching RCG parent to PLL and then turning on the PLL.
If the sync state call doesn't happen before we enable the clocks back,
we'll be setting PLL which is off as a parent to RCG that is on.
But ideally when RCG is on, both the old and new sources should be on
while switching the RCG parent.
Avoid this by turning on the PLL before switching RCG parent during clock
enable sequence.
Change-Id: I1597cf2c8095957cd2b2a20a72bf7199e0d61809
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Pass the DRM_BRIDGE_ATTACH_NO_CONNECTOR flag when attaching the
bridge so that the bridge driver would not create another
drm connector.
Change-Id: I838bd87c40d0eea3df36187befeb7195fb87d5b3
Signed-off-by: Rahul Sharma <quic_rahsha@quicinc.com>
Sim panels are not working well with video mode, parse panel ack
disabled property to fix sim video mode identification issue.
Change-Id: Ife3b533d5a6db97618459dacf1f7ce8d3fc896bf
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
This change adds a connector OP, that will be used to update frame
transfer time dynamically at the request from user space.
It also adds parsing for new device tree entries that set the minimum
and maximum trasnfer times on a mode basis. These min and max transfer
times are also published to userspace through the connector mode info
capabilities blob.
Change-Id: I12aedf96a51ff7feb2c5b3b1353d3c4ec8dcb068
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Refactor the function 'dsi_display_get_modes' to
reduce its complexity.
Change-Id: I1a8ecaa780e5070bac7fa40404677c0a8a5d7cd8
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change updates copyright description with correct
license marking as per the guidelines.
Change-Id: Ia74b721e78afcc7f8e88bcbccfcf15430111ec37
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Use #if IS_ENABLED() instead of #ifdef for configurations as vendor module
guidelines.
Use #if IS_ENABLED(CONFIG_XXX) instead of #ifdef CONFIG_XXX to ensure that
the code inside the #if block continues to compile if the config changes
to a tristate config in the future.
The differences are as follows:
1.#if IS_ENABLED(CONFIG_XXX) evaluates to true when CONFIG_XXX is set to
module (=m) or built-in (=y).
2.#ifdef CONFIG_XXX evaluates to true when CONFIG_XXX is set to
built-in(=y) , but doesn't when CONFIG_XXX is set to module(=m).
Use this only when you're certain you want to do the same thing
when the config is set to module or is disabled.
Change-Id: Ia806b9b01ad8414d0e4de027a382cb68e7fb4a6a
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
As per the HW requirements it is highly recommended to use DMA start window
to trigger broadcast commands. If not used then it can result in a hardware
hang with the DSI controllers going out of sync. This behavior is even more
prominent in cases of higher refresh rates.
Currently, reset_trigger_controls is called as part of next command.
Due to this, when unicast command is sent after broadcast command,
reset_trigger_controls does not get called for slave controller,
leading to issues.
As part of this change, DMA start window scheduling is enabled as default
for broadcast commands and reset_trigger_controls is done as part of
post_cmd_transfer operations.
Change-Id: I2402214ed79b376d102b88d4f7e6a06fcb5712d3
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
pm_runtime_get_sync increases the usage_count refcount immaterial of
success/failure of the call, leading to invalid refcount on failures.
Use pm_runtime_resume_and_get instead, which takes care of reducing the
refcount on failure cases before returning from the function.
Change-Id: Ib96050d5d7ecbd717e58b8a0dde2d03312444e15
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
During a force update of DSI clocks, the state of the byte and pclks are
toggled irrespective of the ref-count. This in addition with ASYNC
command wait can result in interrupt storm, if and when the clocks are
being toggled a previous command that was triggered using the ASYNC
wait flag fires an ISR. The interrupt status doesn't get cleared if
the ISR is being serviced with the clocks are off.
The change adds a check for pending queued commands before any force
update of DSI clocks.
Change-Id: I4ca60d0ad43767791255f00c9af8e99e74786097
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Commit bf0d220 ("disp: msm: dsi: add _NO_ to MIPI_DSI_* flags
disabling features") update names of DSI flags to follow upstream
convention. Purpose of the name change is to more clearly indicate
what is not supported when the flag is set.
This change puts macros around MIPI_DSI_* flags to adapt the name change
of flags for kernel version 5.10 and version 5.15..
Change-Id: I1c9a8da3819a6b641ca9b6d81191bc944913b49e
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Currently, in dsi_display_get_modes, priv_info, rates,
front_porches and pixel_clks_khz memory is allocated for each
timing node and the same memory is copied for each supported fps.
The values of front porches calculated to maintain constant fps for
each bit clk rate gets overwritten with the values for last fps in
the dfps list. But the values of front porches should be different
in case where DFPS and dynamic clock are both supported either by
vfp approach or hfp approach. To fix this, allocate memory
separately for each fps.
Change-Id: Ibf753aa8cca8d77b02b20785b5435f1aba05106e
Signed-off-by: Kashish Jain <kashjain@codeaurora.org>
This change adds additional logs in dsi driver for
easy debugging of issues related to command transfer.
Change-Id: Ica784bed6c360b2760d6606d625837e23a22410c
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
After an ESD failure, the PHY lanes and controller can be stuck in
an unknown state. This can result in interrupt storms and watchdog
failures, if these error states are not handled correctly. The following
change implements the below mechanism to avoid failures.
1) Disable error interrupts during an ESD reg read, which are re-enabled once
ESD check is successful.
2) On ESD failure, before turning off LP clocks, reset the PHY lanes and DSI
controller.
3) After the HS clocks are turned off, issue a PHY hard reset.
4) Before enabling/disabling error interrupts, clear the error status registers
as they are not cleared as part of controller reset.
Change-Id: If10e4edf095a334a9416d109ec4b1401d1a84505
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Update names of DSI flags to follow upstream convention. Purpose of
the name change is to more clearly indicate what is not supported
when the flag is set.
Change-Id: Ifd62610c4dfebcbbccb0fb2046a7c453e39c9107
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Currently the bit clk rate is overridden by cached clock rate
even in dynamic clock disabled usecase where it is not configured.
Avoid this override by retaining calculated bit clock rate for respective
mode in such usecase.
Change-Id: Ib159219fd50ab977edb8332c83bc8b34aee2dc0f
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
Alter allocation method from kzalloc to kvzalloc since virtually
contiguous allocation should suffice requirement. This will avoid
unnecessary invocation of OOO handlers.
Change-Id: I8291ddae08f6427478cdd9b88d6148e02d7ab002
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
