The kernel-doc script identified a number of kernel-doc issues in the
hal/wifi3.0 folder, so fix them.
Note that there are a number of instances where public functions have
their implementation documented in addition to having their interface
documented, so remove the duplicate documentation since only the
interfaces should be documented.
Change-Id: Ic238c0f53658e8754882c83204ffae5ad713ec6b
CRs-Fixed: 3410624
Retain ds ring indices across wifi restart to avoid
edma hang. Fetch the indices from ds module and set
the corresponding ds ring indices.
Change-Id: Ia299a7006166aef096c7d2c1f65f6bef65415a37
CRs-Fixed: 3332152
The MSI address and data information for Direct Link
copy engines will be available once the WiFi driver
on LPASS is initialized. Add support to configure the
IPCC address and data values into Direct Link copy
engines at runtime.
Change-Id: I5e7dff90c2f1ff764462c235deb5795ed019a16b
CRs-Fixed: 3316679
get the HP of the RXDMA ring without incrementing
This will ensure in case of nbuf failures the ring
HP remains unchanged
Change-Id: I69ec9207a44a4c50484933797326e962ad2d4a5c
CRs-Fixed: 3309394
Hal layer changes to handle Umac post reset
and post reset complete events from firmware.
Change-Id: Ib25427930aab25650731c87b38e2ef7e47ae98d9
CRs-Fixed: 3267222
Add HW, SW and nbuf prefetch support in Berryllium, this will
ensure we have prefetched the HW desc, SW desc and nbuf by
the time we are in the 3rd iteration of the dp_rx_be_process
first loop.
CRs-Fixed: 3218647
Change-Id: I27d371c5d1c9a37d61e4fc00d5eb03609fad589c
Add support to track the high watermark for the number
of entries which are used at any given instant. This helps
in identifying if the ring size is sufficient or is being
full for certain use-cases.
Change-Id: Id3ffa52c653696699fbcfbb556a815d5f7908863
CRs-Fixed: 3235115
With restructuring in HIF runtime PM module, modules are
required to register with the HIF runtime PM module. Also,
changes are done in functions of allowing and preventing
runtime PM suspend as part of restructuring.
This change registers DP, HTC and HAL internal modules
with runtime PM module and update HIF runtime PM function
calls with the restructured code of HIF runtime PM module.
Change-Id: I8899a1d3b92a90a05c5eaf4df7609f4008f739f8
CRs-Fixed: 3169372
The original BA window size given from CP might > max DP supported,
add sanity check based on HAL target allowed.
Change-Id: Ibadaddeffe65165a89d580d8a5cbf5f7c724c809
CRs-Fixed: 3193852
For reo_cmd ring, in current implementation, we call hal_srng_access_end
in case a descriptor is not available before baling out. This may cause
a write to the shadow register for the reo_cmd ring. In case we are in
the middle of WOW, this can be problematic.
Modify existing implementation to use hal_srng_access_end_reap, which
will not schedule a write to the register and simply return.
Change-Id: Ifb83d904e39b3d749522cd246a5ab3fe51a3104e
CRs-Fixed: 3194289
Shadow config v2 can support max of 36 shadow
registers only. For KIWI target, there are 40
shadow registers supported.
Hence add support to send shadow config v3
for KIWI.
Change-Id: If57e6597397da3e239f25a6c0cc24f8fd37dcdf1
CRs-Fixed: 3167758
In ring WRAP around case invalidate the descriptors which
are being reaped
Also use no_dsb invalidate API for invalidate descriptors
Change-Id: Iafa844c81a8364af31520ce5fa3e030073e7c706
CRs-Fixed: 3198373
Currently in some case we are receiving non error packets on REO2TCL
ring, which is causing issue.
Fix is to set DEST_RING_MAPPING_0 to SW1 for REO dest ctrl
register, So that non error packets with reo_destination_indication
with 0x0 in the reo entrance ring will be routed to SW1 ring.
Change-Id: I67f78f35e7dba899943307902d99d0325a60498f
CRs-Fixed: 3150186
Currently window register accessing with PLD lock is not enabled for
HIF path of KIWI, enable it so there is no race condition with HAL
register accessing path.
Change-Id: Iceeba36ca6febdeca0e7f7bc0dcb7d4adc17bc51
CRs-Fixed: 3110425
Prefetch RX HW desc, SW desc and SKB in pipeline
fasion in the first loop of RX processing.
This has improved TPUT by 200Mbps and provided a
10% gain in CPU (single core)
PINE with other optimizations: 3960Mbps @ 100% core-3
PINE + pipeline prefetch: 4130Mbps @ 90% core-3
Change-Id: I47f351601b264eb3a2b50e4154229d55da738724
Added an API to do a batch invalidation of REO descs
saw an improvement of 40 to 45 Mbps.
Note: this change is applicable only for cached
descriptors
PINE with Default driver: 3189 @ 100% core-3
PINE with skb prefetch: 3469 @ 100% core-3
PINE with skb pre + batch inv: 3506 @ 100% core-3
Change-Id: Ic2cf294972acfe5765448a18bed7e903562836c3
This FEATURE_HAL_DELAYED_REG_WRITE_V2 was added to fix the
Audio jank issue, but it could not resolve it completely,
so that was later fixed by existing delayed reg write
support with the help of SMP2P messages to communicate
with FW regarding PCIe link status. This code is not being
used, so removing it and cleaning up the redundant code.
Change-Id: Iada088e72a76b4c071c8a80ee945f36ac959670e
CRs-Fixed: 3056475
Initialize the last_desc_cleared pointer to -1 not 0, and
also fix the check it should always behind tp.
Change-Id: I281e066d45a99ac99d4f3c4e0bcc3f65f14bb589
CRs-Fixed: 2987029
Currently the EAPOL/ARP/DHCP frames arriving as 2K-jump
or out-of-order frmaes are being delivered to the network
stack, without checking for the packet-number sequence.
WCN7850 has hardware support to provide the packet number
of the previous successful re-ordered packet from hardware.
Use this feature to check if the packet-number are in proper
sequence for these EAPOL/ARP/DHCP packets arriving as 2k-jump
or out-of-order packets before submitting it to the network
stack.
Change-Id: I1078452afce4bc00b2509436295e5bd80000feb4
CRs-Fixed: 2965086
WCN7850 has support for near full indication for
the consumer srngs. This interrupt is used to take
preventive actions to avoid ring full watchdog irq
trigger.
Register for the near full irq and add the necessary
ext groups for these near-full irqs.
Change-Id: Ic16381fceabc54e6c52b34dd13abea74cad4d38c
CRs-Fixed: 2965081
Return LMAC start id also as part of hal_get_meminfo API.
This field is added to hal_mem_info struct.
Change-Id: I013d357cf4337702c06a91ed15e8337469865270
While Rx buffers are getting umapped from net rx context if IPA
pipes are enabled at same time from MC thread context this is
leading to race condition and IPA map/unmap is going out of sync.
To fix this introducing IPA mapping lock and IPA mapping need to
be handled with lock held.
Change-Id: I9fa71bdb6d4e4aa93fc795cc5dd472a181325991
CRs-Fixed: 2945063
hal_get_entrysize_from_srng returns the entry size
in dwords but the caller expects in bytes. This results
in insufficient data to be recorded for CE event.
Fix is to left shift the entry size by two bits in
hal_get_entrysize_from_srng so that the entry size
value returned is in bytes.
Change-Id: If532da7abe5ce9c293969f0052455085f18b1926
CRs-Fixed: 2935196
Add iwpriv option 34 to dump the reo rx h/w descs
in DDR for debugging. This cmd will first send cache
flush cmd to REO for all rx tids and invalidate the h/w
cache. Henceforth ensuring that the reo status tlvs and
the DDR values are in sync.
iwpriv wlan0 txrx_stats 34 0
Add fix to ensure bar frame with 2k jump err code is
processed correctly using the REO error code instead of the
REO push reason.
Change-Id: Ia05be668343f3a5d4b3262b8d6a367a50875add5
CRs-Fixed: 2895965
Add wbm head/tail pointer stats to dp_txrx_stats and ring
usage percentage for all SRC and DST rings.
Stats added to the following cmd: iwpriv wlan0 txrx_stats 26 0
CRs-Fixed: 2865996
Change-Id: I7d144d87c5f3485ec9ba85f50b036b69a64e53c6
Enable force wake recipe feature DEVICE_FORCE_WAKE_ENABLE
and disable the generic shadow register write feature
GENERIC_SHADOW_REGISTER_ACCESS_ENABLE.
Force wake recipe will be used to write to the REO remap
control registers by waking up the UMAC instead of using
shadow register writes.
Assert soc wake reg and poll on the scratch reg to check
if UMAC is awake.
Enable HIF_REG_WINDOW_SUPPORT to enable windowed reg
read/write in HIF layer.
Change-Id: Ib696e27e19a07c0084c097b95b7780b56e643c8b
CRs-Fixed: 2850590
Add delayed SRNG register writes support for Tx Ring, also add
dedicated workqueue to do the delayed Tx SRNG register writes.
Change-Id: I8dd157d341f3035e988804eab50d1ca681ab789b
CRs-Fixed: 2868989
WLAN HW can still access the IPA tx doorbell address post
disable pipes if there are any pending tx completions which
could result in a NOC error.
Fix is to reset the WBM2SW ring HP addr to shadow addr in
DDR before pipes are disabled.
Change-Id: I52900eb34530388487923a887354ef8839d8c728
CRs-Fixed: 2846421
Current implementation of hal_srng_access_start() reads the ring pointer
in the same byte-order as it is written by the target. This results in
byte-order mismatch on a big-endian Host because the WLAN target is
little-endian based. For most of the srngs, the target already takes of
this by converting the ring pointer to the host-order before writing to the
DDR. But for other srngs, the Host needs to handle the endianness
conversions. Add HAL APIs to do the same.
CRs-Fixed: 2844519
Change-Id: Ieb47391ac0acc3724e854f433915dd5b1219bebe
Use cache invalidate api instead of cache_sync since
cache_sync api is not available in MIPS platform.
Change-Id: I4b8e2fc3cb9055d1c392c2f6dbe7d6be7c66031b
Excessive logging is detected when force wake request
command fails.
Rate limit the logs in hif_force_wake_request and
hal_write32_mb.
Change-Id: I9b1166074dfdb2d58d811571c802a75a6dbc03c5
CRs-Fixed: 2823961
Add reo ring descrptor swap in case of big endian platform.
Convert msi_data into little endian format before writing into
MSI_DATA register. Also change into little endian format while accessing
the shared LMAC registers.
Change-Id: I07f4ae4e6df4608201b63d325c2cbc37436d1592
REO remap register direct writes as part of SAP stop could
result in a NOC error if the UMAC is in low power state.
Fix is to use shadow register writes for REO remap and
WBM HP registers.
Change-Id: Ie515c3d28f4ccdd99a3757808f1ab6c5cf373e3d
CRs-Fixed: 2813105
Due to recent FW changes not filtering out BAR frames, redirect these
frames to REO exception ring and handle as normal data packets.
Change-Id: I4540929fddab14de57a23f6364fc916a70057cbe
CRs-Fixed: 2795499
Delayed register write work needs to be flushed before bus suspend to
make sure there are on pending writes after driver's bus suspend routine
exits. In case delayed work context is not able to finish before the bus
(PCI) is suspended (DRV), it may lead to a NOC error.
Change-Id: I40cbcec5d23ddd75ec87aed69ac45d95510fa880
CRs-Fixed: 2813733
Add apis to map generic registers to shadow region. Existing
logic includes mapping only srng based regs to the shadow
region.
Add support to map REO control regs and WBM2SW2 rel
ring HP reg address to the shadow region in case the direct
reg writes in IPA enable/disable autonomy fail due to UMAC
block being in a power collapsed state.
Shadow reg mapping for these regs is provided to FW during
init. Add stat shadow_reg_write_fail to track shadow reg
write failure and shadow_reg_write_succ to track successful
shadow writes.
Change-Id: I04790765a3de80047689657e2cad0b73123440b9
CRs-Fixed: 2790321
