Allocate memory based on what is configured to FW. Avoid
hardcoded allocations, thereby reducing the memory
footprint. The change also updates size check for a SMMU
mapping, if the size of the buffer is beyond the assigned
va range fail the mapping.
CRs-Fixed: 3477543
Change-Id: I3c2e262f57cdfdbd51255679b2405d855d7d5353
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Reduce size of the buffer to drain the dbg_q. Add a mutex for
dbg_q, and in HFI read validate the input buffer size prior
to copying the queue contents into the input buffer.
CRs-Fixed: 3477543
Change-Id: I2043f3db6189ebfc8b8ead8db0266a83bc94b6a2
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Allocate memory based on what is configured to FW. Avoid
hardcoded allocations, thereby reducing the memory
footprint. The change also updates size check for a SMMU
mapping, if the size of the buffer is beyond the assigned
va range fail the mapping.
CRs-Fixed: 3477543
Change-Id: Idfdce7febfe6624db33ff466b978207e96d4a902
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Reduce size of the buffer to drain the dbg_q. Add a mutex for
dbg_q, and in HFI read validate the input buffer size prior
to copying the queue contents into the input buffer.
CRs-Fixed: 3477543
Change-Id: If7246f7d1d521ed683a6fe785aa4c8d0457b5f0f
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
To avoid using GP registers to send different memory region
info, use GP registers to configure only the consolidated region.
The specifics for different regions within the consolidated region
are later sent to FW as a new HFI cmd.
CRs-Fixed: 3469619
Change-Id: I2eb9511a4df5c8eb4ca09b60acd1fcffb3ac4dff
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Fill out ICP v2 query cap request from UMD based on v2 query
cap structure. With the query cap info, UMD can know which HW
devices (IPE/BPS/OFE/...) supported by the ICP v4l2 device.
CRs-Fixed: 3364226
Change-Id: I775f6248a4971b47eb7f832e2e6b6b3d3ab9952e
Signed-off-by: Petar Ivanov <quic_pivanov@quicinc.com>
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
Modifying the info/error/dbg logs in hw mgr, context and hfi
layers to spit out relevant info to determine which ICP device
is running the execution.
Change type defination of hw_dev_type to enum in local instances in
functions and the field of hw ctx struct.
CRs-Fixed: 3361905
Change-Id: Ib50208eaf243c50678d07845461c750b36d19bf9
Signed-off-by: Petar Ivanov <quic_pivanov@quicinc.com>
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
During probe, each hw mgr register as a client to HFI layer and share
the handle to icp core layer to book keep. HFI register routine searches
for a free hfi slot to dynamically allocated hfi info struct and returns
a client handle to the caller. During open sequence, HW mgr is required to
initialize the hfi using the handle obtained from the registering in boot
up. Upon unregistering, the hfi slot and the hfi info memory is freed.
Hw mgr layer can invoke the existing hfi interfaces by passing hfi handle
to fetch the right hfi info. With this change, each hw mgr can
independently run on one HFI to interact with FW.
Add support in enabling OFE PC and config OFE UBWC in hfi layer, and parse
OFE UBWC config values from DT.
CRs-Fixed: 3338951
Change-Id: Iec2358fef124e9c169d06df79ce31b65a9b80d40
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
Add OFE device allocation and initialization. Verify number
of DT listed devices with cpas capability. Create common
sets of command types for IPE/BPS/OFE. Refactor the current usage
of IPE/BPS device interfaces to scale to n number of devices
including OFE. Add support for OFE functionality: acquire/
release, init/deinit, PC/Resume, get gdsc, clock update,
OFE HFI commands and message handlers.
CRs-Fixed: 3337784
Change-Id: I94c9bd21cf21dead6733c7cd6b86e343e86169de
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
Add support to map global sync and hw mutex memory for ICP.
Share the region information with FW over GP registers.
CRs-Fixed: 3351015
Change-Id: Ie7a6af40ffd922ae89d64205787e3c656a007c49
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Increase cmdq/msgq size to 8K. Update HFI read API to
reflect the bump in size.
CRs-Fixed: 3190507
Change-Id: I70f5ded8e6155534cf2fa0fe94d3fdd1a378b5f7
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
ICP driver change the clk based on input request.
ICP fw needs this clock frequency to measure
processing time.
Send freq info to ICP firmware.
CRs-Fixed: 3037964
Change-Id: Iceed0bd43105da4316a023f345d46477e760b202
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Use fw_uncached region instead of secondary heap region. Pass
this region information to FW through CSR registers.
Allocate Qtlb, cmd_q, msg_q, dbg_q from fw_uncached region
instead of shared mem region. Allocate Sec heap also from
fw uncached region instead of its own dedicated region.
CRs-Fixed: 2722486
Change-Id: Ib88b2202ca1b610946c712fcca936b72d4eecd15
Signed-off-by: Pavan Kumar Chilamkurthi <pchilamk@codeaurora.org>
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
The HFI interface registers will have a different base address
on the LX7 processor. We can utilize the newly added HFI ops to
abstract the calculation of the address by kicking that info out
to the device interface. The HFI register definitions have been
tweaked to support offsets based on the calculated addresses.
CRs-Fixed: 2722486
Change-Id: I93b9b2827ec0820eaac6ee2e6a611363b96a3223
Signed-off-by: Fernando Pacheco <fpacheco@codeaurora.org>
The steps to enable and send interrupts will differ between processors.
Pull this logic out of the HFI and out to the devices, so that we can
adapt to the specific irq management of any processor.
CRs-Fixed: 2722486
Change-Id: I2a889b91ec13295aa14bb2b16252332482a1225a
Signed-off-by: Fernando Pacheco <fpacheco@codeaurora.org>
The LX7 processor will require a new mechanism to resume/collapse.
Make the current mechanism transparent to the ICP HW manager in
preparation for the new proc. By going through the hw_ops we let
the device interface decide which mechanism to use.
CRs-Fixed: 2722486
Change-Id: I719314b3f505270a33892cb247082e43dad2e92d
Signed-off-by: Fernando Pacheco <fpacheco@codeaurora.org>
msm: camera: tfe: Fix variable initialization issues
msm: camera: isp: Dual tfe event check with proper hw idx
msm: camera: smmu: Add support for non-contiguous mermory region
msm: camera: smmu: Use iommu best match algo for camera
msm: camera: ope: Optimize allocation of IO configuration
msm: camera: ope: Fix for KW Issues
msm: camera: ope: Add support for stripe level height configuration
msm: camera: tfe: Enable the delay line clc
msm: camera: ope: Fix false alarm for OPE HW timeout
msm: camera: tfe: Support register dump per request
msm: camera: ope: Increase max number of stripes
msm: camera: ope: Change packer and unpacker format in case NV12
msm: camera: tfe: Add packet code get command for tfe
msm: camera: ope: Trigger recovery in case of violation on write bus
msm: camera: ope: Protect ope hw reset with mutex
msm: camera: ope: Add a check for valid request in cdm callback
msm: camera: ope: Remove the BW & clock vote in release context
msm: camera: ope: Reduce OPE BUS memory
msm: camera: ope: Fix return value for ope acquire
msm: camera: ope: Fix false alarm for OPE request timeout
msm: camera: ope: Avoid deadlock during recovery after HW hang
msm: camera: tfe: tfe debug enhancement
msm: camera: cdm: Fix irq_data value in case of inline irq
msm: camera: flash: Switch off flash on provider crash
msm: camera: ope: Initialize ope hw mutex structure
msm: camera: cdm: Flush all available FIFOs during reset
msm: camera: cpas: Add mandatory bw option for axi ports clocks
msm: camera: ope: Use vzalloc to allocate the write bus ctx structure
msm: camera: ope: Fix handling of init hw failure
msm: camera: tfe: Enable per frame register dump for rdi only context
msm: camera: cdm: Protect cdm core status bits with mutex
msm: camera: cdm: correct the error check in cmd submit irq
msm: camera: ope: Fix unclock access during HW reset
msm: camera: ope: Program frame level settings after idle event
msm: camera: ope: Delay releasing of resources for last context
msm: camera: isp: Increase default SOF freeze timeout
msm: camera: smmu: Add map and unmap monitor
msm: camera: isp: Add trace events across ISP
msm: camera: smmu: Profile time taken for map, unmap
msm: camera: ope: Start context timer on receiving new request
msm: camera: tfe: Reduce stack size during set axi bw
msm: camera: cdm: Check for HW state before dumping registers
msm: camera: ope: Reduce stack footprint during acquire
msm: camera: tfe: Disable clock if tfe2 is not supported
msm: camera: cdm: Avoid cdm pause incase of BL submit
msm: camera: tfe: Optimize CSID IRQ logging
msm: camera: ope: Move request id validity check outside of lock
msm: camera: tfe: Correct the tfe hw manager dump logic
msm: camera: ope: Synchronize flush and submit BLs
msm: camera: cdm: Protect cdm reset status
msm: camera: cdm: Handle cdm deinit sequence properly
msm: camera: tfe: Reduce reset timeout to 100ms
msm: camera: ope: Fix hang detection
msm: camera: ope: Make non-fatal logs as debug and info logs
msm: camera: tfe: set overflow pending bit to zero after HW reset
msm: camera: ope: Do not disable CDM during error handling
msm: camera: ope: Add support for OPE Replay
msm: camera: ope: Stop OPE in case of init failure
msm: camera: ope: Synchronize process cmd and flush request
msm: camera: cdm: Fix CDM IRQ handling
msm: camera: tfe: LDAR dump for TFE
msm: camera: ope: Fix the length check for debug buffer
msm: camera: cdm: Fix CDM reset logic
msm: camera: ope: Dump debug registers in case of HW hang
msm: camera: tfe: Support the RDI bus port for line based mode
msm: camera: cdm: Handle out of order reset done events
msm: camera: ope: Consider other contexts during timeout
msm: camera: ope: Put GenIRQ in last stripe BL
msm: camera: tfe: Process the rdi interrupts for rdi only resource
msm: camera: jpeg: Check the HW state before accessing register
msm: camera: csiphy: Update csiphy power-up sequence for lito v2
msm: camera: cdm: Secure freeing of request lists using locks
msm: camera: cpas: Add support for Scuba camnoc
msm: camera: csiphy: Clear secure phy flags on release
msm: camera: tfe: validate the tfe bw num paths
msm: camera: ope: Reorder the reset order in ope acquire
msm: camera: ope: Dump debug registers in case of reset failure
msm: camera: ope: Add logic to detect hang in CDM
msm: camera: isp: Increase max count of cfg to support more init packets
msm: camera: core: Fix cpas axi clk rate overflow.
CRs-Fixed: 2668666
Change-Id: I882ca4bd117bebc7d1c62bc82299d69d7b5c9388
Signed-off-by: Trishansh Bhardwaj <tbhardwa@codeaurora.org>
Add support to discard a memory region inside the full dma map
virtual address space region.
CRs-Fixed: 2580128
Change-Id: I76cc778f2437a01a4efabec836ce92c47d983d61
Signed-off-by: Pavan Kumar Chilamkurthi <pchilamk@codeaurora.org>
Bring over camera driver changes as of msm-4.19
commit 5a5551a7 (Merge "msm: camera: reqmgr: Fix CRM
shift one req issue").
Change-Id: Ic0c2b2d74d1b3470c1c51d98228e312fb13c501a
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
