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3192 Incheckningar

Upphovsman SHA1 Meddelande Datum
Christina Oliveira
d3104b1f9f disp: msm: sde: add fence ready in event log
This change adds the value of hw-fence ready to
event logs for video and command modes.

Change-Id: I40a2e886a3b95e8853efcbdddf7fd9f6ce48eb9b
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
2022-05-16 12:44:59 -07:00
Christina Oliveira
0e20e27cc1 disp: msm: sde: adds mem mapping for hwfence ipcc reg
This change adds one-to-one memory mapping for the hwfence
ipcc register memory needed for hw fence feature.

Change-Id: I0e264183e02d0ed5f2254b409cc5e776d670f0dc
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
2022-05-16 12:44:45 -07:00
Ingrid Gallardo
62ad586d91 disp: config: add hw fence configuration files for Kalama
Add configuration files to compile hw-fence driver
for Kalama display.

Change-Id: Icd45b7688988b54d6b31bd07998b811116506b30
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
2022-05-16 12:43:35 -07:00
Christina Oliveira
640c8111d3 disp: msm: sde: add support for hw-fence feature
Starting mdss 9.0, dpu supports triggering
the frame fetch through hw-fencing. This change
adds support for this hw-fence feature.

Change-Id: Icc7d0b69fc2a51103d14612f5ac89b44a47ed826
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
2022-05-16 12:41:28 -07:00
qctecmdr
487e4ebec2 Merge "disp: msm: sde: add reg dma support for vig DE lpf" 2022-05-16 08:37:45 -07:00
Rahul Sharma
840b5d7003 disp: enable the msm_drm packing for auto builds
remove the TARGET_BOARD_AUTO flag check to enable
the display driver msm_drm.ko packing for automotive builds.

Change-Id: I3eda4b3ecb497be71cbe156acb62a0731f12ccde
Signed-off-by: Rahul Sharma <quic_rahsha@quicinc.com>
2022-05-14 23:06:15 +05:30
qctecmdr
705ad08735 Merge "disp: msm: dp: add ability to select pattern for tpg" 2022-05-13 09:58:57 -07:00
Vara Reddy
194baedbee disp: msm: remove parsing deep color modes in sde parser
Change removes downstream parsing of deep color modes function
_sde_edid_update_dc_modes, which is presently parsed in upstream
function drm_parse_ycbcr420_deep_color_info in drm_edid file.

Change-Id: I4426e190cdc1e5f139a0c0439cc45f3cc7884c3d
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
2022-05-12 20:06:42 -07:00
qctecmdr
7f6a4cdee7 Merge "disp: msm: sde: add custom event to notify OPR, MISR value change" 2022-05-10 21:25:05 -07:00
qctecmdr
98d739db59 Merge "disp: msm: sde: toggle LLCC SCID for consecutive LLCC write" 2022-05-10 08:38:47 -07:00
Akshay Ashtunkar
9423445a34 disp: msm: sde: add custom event to notify OPR, MISR value change
This change collects the OPR, MISR values. If the values are
different than the previous then notify to client with custom event.

Change-Id: I2546439be1f665d90e6505d65283d28096bf7cdd
Signed-off-by: Akshay Ashtunkar <quic_akshayaa@quicinc.com>
2022-05-10 09:51:16 +05:30
Amine Najahi
d03f18c6b9 disp: msm: sde: toggle LLCC SCID for consecutive LLCC write
Toggle LLCC SCID for each consecutive LLCC write
operations and force read allocate when NSE bit
set.

Change-Id: Ice473cb126b627056b7346f142bc84c120e05f0b
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-05-09 17:07:58 -04:00
Renchao Liu
b56c45e4be disp: msm: sde: add reg dma support for vig DE lpf
This change adds reg dma support for vig DE lpf.

Change-Id: I9108046bb2afb987eec49224df4a45c37f9c27cd
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
2022-05-07 16:34:11 +08:00
qctecmdr
0384633caf Merge "disp: msm: sde: update vsync soure as part of post modeset" 2022-05-06 06:09:04 -07:00
qctecmdr
63a9b89055 Merge "disp: msm: sde: fix precise vsync feature check" 2022-05-06 01:23:21 -07:00
Narendra Muppalla
f014267f93 disp: msm: sde: update vsync soure as part of post modeset
This change updates vsync source as part of rc post modeset. For some
use cases like idlepc with DFPS, vsync could be configured for
previous fps and can cause timeouts during next frame.

Change-Id: I110fd958d2970eaca50ace0e72c4faea3fc64ce8
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
2022-05-03 15:02:54 -07:00
qctecmdr
be3eb851cf Merge "disp: msm: dsi: Don't clear status interrupts while error interrupts toggle" 2022-04-30 22:49:59 -07:00
qctecmdr
25dd16eeb0 Merge "disp: msm: Address static analysis issues" 2022-04-30 18:45:41 -07:00
Nisarg Bhavsar
75aedb1c53 disp: msm: Address static analysis issues
Avoid various possible nullptr dereferences.
Addresses various issues highlighted by static analysis.

Change-Id: I36d34d610b37bf2799a7e34cd1de8b909b5c0ae4
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2022-04-28 11:53:38 -04:00
Rahul Sharma
d28f68dede disp: msm: add augen3 configuration
Add augen3 configuration for SA8155/SA8195/SA6155 family.

Change-Id: I206f0a636ef9f33b4c46cb0159ae2659a3dced59
Signed-off-by: Rahul Sharma <quic_rahsha@quicinc.com>
2022-04-28 07:42:28 -07:00
Srihitha Tangudu
4799920fc7 disp: msm: dsi: Don't clear status interrupts while error interrupts toggle
To toggle error interrupts, we currently read the DSI_INT_CTRL register,
toggle the DSI_ERROR_MASK bit and write back to the register. While doing
so we are also writing back 1 to any status bits set by HW, thus clearing
the status interrupts. Clearing the status bits should always be done as
part of interrupt handling, which otherwise can lead to command transfer
failures.

Avoid clearing status interrupts while error interrupts are toggled.

Change-Id: Iaae10c279f2341269ed49074448167e68ab7e13c
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
2022-04-27 11:28:05 +05:30
Rajkumar Subbiah
609f084c8a disp: msm: dp: improve accuracy of mvid/nvid calculation
The software mvid/nvid values represent the ratio of mode clock
to link clock. Currently we are converting the link clock to vco
clock, get the ratio of vco clock to mode clock and then adjust
the resulting values to get the ratio of link clock to mode clock.
This change simplifies this logic by directly using the link
clock to get the ratio and uses fixed point arithmetic to scale
the resulting mvid, nvid values to meet requirements.

Change-Id: Ifdfa27edb73d2db6381e592db219e75806d6bdc7
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2022-04-26 18:58:47 -07:00
Veera Sundaram Sankaran
2d889b43ea disp: msm: sde: fix precise vsync feature check
Check the precise vsync feature bit in sde hw catalog features
bitmap for checking the precise vsync feature and remove the
obsolete has_precise_vsync_ts variable.

Change-Id: I1f0cfabe5dcf387358548e8ff5ea0d65d4d7cecf
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-04-26 15:46:33 -07:00
qctecmdr
b0aa8dbb0f Merge "disp: msm: sde: add support for LLCC_DISP_1 SCID" 2022-04-26 13:11:31 -07:00
Amine Najahi
bffdc0271d disp: msm: sde: add support for LLCC_DISP_1 SCID
Currently only LLCC_DISP SCID is used to read and write to
system cache during static display use case.

This changes adds SCID LLCC_DISP_1 to allow each SCID to
have a dedicated function (read/write).

Change-Id: I5604ec1183d99a8492b005ec06ac94e5db60b5f7
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-04-26 10:29:29 -04:00
qctecmdr
2ed5675910 Merge "disp: msm: sde: convert system cache boolean to feature bit" 2022-04-26 06:38:24 -07:00
Amine Najahi
50092909c0 disp: msm: sde: convert system cache boolean to feature bit
Currently a boolean variable is used to track if the system
cache feature is enable for a particular SCID.

This change converts it to use a feature bit instead.

Change-Id: I8461fd9fb837b871c4ac5c67a9ab7613aadea7bb
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-04-25 16:33:00 -04:00
Amine Najahi
edd8be4319 disp: msm: sde: log SCID during LLCC activation
Add SCID to event log and debug print during LLCC activation.

Change-Id: Ib4c0a68506e9620ca42aba03db35c9ee21eda6dd
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-04-25 16:32:53 -04:00
Bruce Hoo
02e97873a2 disp: msm: merge flag of register and dbgbus
Merge reg_dump and dbgbus dump flag into dump_mode, and bring
back debugfs node "evtlog_dump" to keep flexible controlling
of evtlog.
Set in_mem option as default dump mode, since in_coredump
option will be enabled once HW recovery feature is enabled.

Change-Id: I75de1a69b01594b652479bf79201591ac0bf62e5
Signed-off-by: Bruce Hoo <quic_bingchua@quicinc.com>
2022-04-25 08:07:46 -07:00
qctecmdr
13d8ca3148 Merge "disp: msm: sde: change ubwc revision" 2022-04-22 23:08:47 -07:00
Amine Najahi
3cfd52c905 disp: msm: sde: enable vsync irq during sys cache read work
Currently, when doze mode is enabled the encoder off work
worker is started 1 ms after idle power collapse because of
aggressive idle-pc feature. This causes the system cache
worker to start after the clocks and vsync interrupt are disabled.

This change independently enables clocks and interrupts during
system cache work thread to decouple it from the encoder
off work sequence.

Change-Id: I8ed172b0e7c5c8e4e270e768434301d972e90eb9
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-04-20 13:23:06 -04:00
Shamika Joshi
b2f0c90aca disp: msm: sde: change ubwc revision
UBWC revision is in the expanded form, no need to process it again.

Change-Id: Ie4aafeea5459a76f325a07e58af1de5665fe45ba
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
2022-04-19 09:32:11 -07:00
qctecmdr
6015c178db Merge "disp: msm: dp: update pll params with latest HPG values" 2022-04-15 22:15:56 -07:00
qctecmdr
7f0ec61940 Merge "disp: msm: dp: set drm device pointer in dp aux object" 2022-04-15 22:15:56 -07:00
qctecmdr
35ebbbfd59 Merge "disp: config: enable HDCP config for kalama" 2022-04-15 22:15:56 -07:00
Rajkumar Subbiah
bbd8a4b5ab disp: msm: dp: add ability to select pattern for tpg
Currently the tpg_ctrl node takes a boolean flag to enable or disable
test pattern output on DP controller. It always sets the pattern type
to a default pattern. This change updates this interface to accept an
integer value so the user can select different patterns supported by
the controller.

Change-Id: I399091a57f353b2fb8d29a48a8390898ca9afb55
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2022-04-14 18:08:34 -04:00
Vara Reddy
657ac66343 disp: config: enable HDCP config for kalama
Enable HPCP module for Kalama.

Change-Id: I40daa8525b46533818990908404197ed0921c729
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
2022-04-13 14:05:21 -07:00
Vara Reddy
8c413f511e disp: msm: link HDCP sec-module as a dependency
HDCP sec_module is linked as an additional dependency for display drivers.
This change links hdcp_qseecom symbols needed for display drivers.

Change-Id: I227382dbf31b8488479b983b730d10b17c3b3af2
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
2022-04-13 11:46:57 -07:00
Vara Reddy
4c42ab82d4 Revert "disp: msm: dp: avoid duplicate read of link status"
This reverts commit 80efc128db.

Change-Id: Iea9e8a7ca7b7ea85ffef6c45f732b0a214c93e19
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
2022-04-12 16:10:58 -07:00
qctecmdr
99e41b7489 Merge "disp: msm: sde: reset plane cache state on plane disable" 2022-04-11 16:47:35 -07:00
Sandeep Gangadharaiah
e8ccba4d59 disp: msm: dp: set drm device pointer in dp aux object
drm device pointer is not set in dp aux object which
is leading to a warning message during device bootup.
This change will set that pointer before registering
aux object.

Change-Id: Ib79ece56d7d5efd098e06104eb020648d1d075f7
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-04-11 09:42:50 -07:00
qctecmdr
93a2cea771 Merge "disp: msm: avoid rotator code compilation" 2022-04-11 07:26:59 -07:00
qctecmdr
97c6db4693 Merge "disp: msm: sde: use LLCC_DISP for static display usecase with cwb" 2022-04-10 07:19:01 -07:00
qctecmdr
efb465749b Merge "disp: msm: sde: handle SSPP system cache for multi-plane scenario" 2022-04-10 03:21:03 -07:00
qctecmdr
3a8e850ac9 Merge "disp: msm: sde: fix GEM object inactive list locking" 2022-04-10 03:21:01 -07:00
qctecmdr
cb6ce492b5 Merge "disp: msm: sde: update HFC layer checks" 2022-04-09 16:51:07 -07:00
qctecmdr
95eb4d982c Merge "disp: msm: sde: add the DE lpf flag setting" 2022-04-09 13:24:42 -07:00
qctecmdr
6e5db7e5eb Merge "drm: msm: add spr by pass support" 2022-04-09 13:24:42 -07:00
qctecmdr
9607366aa9 Merge "disp: msm: dsi: parse panel ack disabled property for sim panels" 2022-04-09 06:33:20 -07:00
qctecmdr
652628e747 Merge "disp: msm: hdcp: set default topology as DOWN_REQUEST_TOPOLOGY" 2022-04-09 06:33:20 -07:00