msm: camera: cpas: Modify Client CPAS reg read/write

Remove all instances of cpas camnoc reg read/write by clients.
Move cpas reg base enums to internal cpas file that is only visible
to CPAS usages, and create cpastop reg base macro in CPAS API file.
So, clients can now read and write to cpastop reg only.

CRs-Fixed: 3405131
Change-Id: I1793377a8b6f010bb2c79ac9020cfa3d21e31812
Signed-off-by: Sokchetra Eung <[email protected]>

drivers/cam_cpas/cam_cpas_hw_intf.h

@@ -31,6 +31,20 @@ enum cam_cpas_hw_type {
 	CAM_HW_CAMSSTOP,
 };
 
+/**
+ * enum cam_cpas_reg_base - Enum for register base identifier. These
+ *                          are the identifiers used in generic register
+ *                          write/read APIs provided by cpas driver.
+ */
+enum cam_cpas_reg_base {
+	CAM_CPAS_REG_CPASTOP,
+	CAM_CPAS_REG_CAMNOC,
+	CAM_CPAS_REG_CAMSS,
+	CAM_CPAS_REG_RPMH,
+	CAM_CPAS_REG_CESTA,
+	CAM_CPAS_REG_MAX
+};
+
 /**
  * enum cam_cpas_hw_cmd_process - Enum for CPAS HW process command type
  */

drivers/cam_cpas/cam_cpas_intf.c

@@ -444,9 +444,19 @@ int cam_cpas_get_hw_info(uint32_t *camera_family,
 }
 EXPORT_SYMBOL(cam_cpas_get_hw_info);
 
-int cam_cpas_reg_write(uint32_t client_handle,
-	enum cam_cpas_reg_base reg_base, uint32_t offset, bool mb,
-	uint32_t value)
+static inline enum cam_cpas_reg_base __cam_cpas_get_internal_reg_base(
+	enum cam_cpas_regbase_types reg_base)
+{
+	switch (reg_base) {
+	case CAM_CPAS_REGBASE_CPASTOP:
+		return CAM_CPAS_REG_CPASTOP;
+	default:
+		return CAM_CPAS_REG_MAX;
+	}
+}
+
+int cam_cpas_reg_write(uint32_t client_handle, enum cam_cpas_regbase_types reg_base,
+	uint32_t offset, bool mb, uint32_t value)
 {
 	int rc;
 
@@ -457,9 +467,17 @@ int cam_cpas_reg_write(uint32_t client_handle,
 
 	if (g_cpas_intf->hw_intf->hw_ops.process_cmd) {
 		struct cam_cpas_hw_cmd_reg_read_write cmd_reg_write;
+		enum cam_cpas_reg_base internal_reg_base;
+
+		internal_reg_base = __cam_cpas_get_internal_reg_base(reg_base);
+		if (internal_reg_base >= CAM_CPAS_REG_MAX) {
+			CAM_ERR(CAM_CPAS, "Invalid reg base: %d for write ops client: %u",
+				reg_base, client_handle);
+			return -EINVAL;
+		}
 
 		cmd_reg_write.client_handle = client_handle;
-		cmd_reg_write.reg_base = reg_base;
+		cmd_reg_write.reg_base = internal_reg_base;
 		cmd_reg_write.offset = offset;
 		cmd_reg_write.value = value;
 		cmd_reg_write.mb = mb;
@@ -479,9 +497,8 @@ int cam_cpas_reg_write(uint32_t client_handle,
 }
 EXPORT_SYMBOL(cam_cpas_reg_write);
 
-int cam_cpas_reg_read(uint32_t client_handle,
-	enum cam_cpas_reg_base reg_base, uint32_t offset, bool mb,
-	uint32_t *value)
+int cam_cpas_reg_read(uint32_t client_handle, enum cam_cpas_regbase_types reg_base,
+	uint32_t offset, bool mb, uint32_t *value)
 {
 	int rc;
 
@@ -497,9 +514,17 @@ int cam_cpas_reg_read(uint32_t client_handle,
 
 	if (g_cpas_intf->hw_intf->hw_ops.process_cmd) {
 		struct cam_cpas_hw_cmd_reg_read_write cmd_reg_read;
+		enum cam_cpas_reg_base internal_reg_base;
+
+		internal_reg_base = __cam_cpas_get_internal_reg_base(reg_base);
+		if (internal_reg_base >= CAM_CPAS_REG_MAX) {
+			CAM_ERR(CAM_CPAS, "Invalid reg base: %d for read ops client: %u",
+				reg_base, client_handle);
+			return -EINVAL;
+		}
 
 		cmd_reg_read.client_handle = client_handle;
-		cmd_reg_read.reg_base = reg_base;
+		cmd_reg_read.reg_base = internal_reg_base;
 		cmd_reg_read.offset = offset;
 		cmd_reg_read.mb = mb;
 		cmd_reg_read.value = 0;

drivers/cam_cpas/include/cam_cpas_api.h

@@ -31,6 +31,14 @@
 #define CAM_CPAS_QOS_DEFAULT_SETTINGS_MASK 0x1
 #define CAM_CPAS_QOS_CUSTOM_SETTINGS_MASK  0x2
 
+/**
+ * enum cam_cpas_regbase_types - Enum for cpas regbase available for clients
+ *                             to read/write
+ */
+enum cam_cpas_regbase_types {
+	CAM_CPAS_REGBASE_CPASTOP,
+	CAM_CPAS_REGBASE_MAX
+};
 
 /**
  * enum cam_cpas_vote_type - Enum for cpas vote type
@@ -41,20 +49,6 @@ enum cam_cpas_vote_type {
 	CAM_CPAS_VOTE_TYPE_MAX,
 };
 
-/**
- * enum cam_cpas_reg_base - Enum for register base identifier. These
- *                          are the identifiers used in generic register
- *                          write/read APIs provided by cpas driver.
- */
-enum cam_cpas_reg_base {
-	CAM_CPAS_REG_CPASTOP,
-	CAM_CPAS_REG_CAMNOC,
-	CAM_CPAS_REG_CAMSS,
-	CAM_CPAS_REG_RPMH,
-	CAM_CPAS_REG_CESTA,
-	CAM_CPAS_REG_MAX
-};
-
 /**
  * enum cam_cpas_hw_index  - Enum for identify HW index
  */
@@ -685,7 +679,7 @@ int cam_cpas_update_axi_vote(
  */
 int cam_cpas_reg_write(
 	uint32_t                  client_handle,
-	enum cam_cpas_reg_base    reg_base,
+	enum cam_cpas_regbase_types reg_base,
 	uint32_t                  offset,
 	bool                      mb,
 	uint32_t                  value);
@@ -706,7 +700,7 @@ int cam_cpas_reg_write(
  */
 int cam_cpas_reg_read(
 	uint32_t                  client_handle,
-	enum cam_cpas_reg_base    reg_base,
+	enum cam_cpas_regbase_types reg_base,
 	uint32_t                  offset,
 	bool                      mb,
 	uint32_t                 *value);

drivers/cam_icp/icp_hw/bps_hw/bps_core.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/of.h>
@@ -161,7 +161,7 @@ static int cam_bps_handle_pc(struct cam_hw_info *bps_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
+			CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_ctrl,
 			true, &pwr_ctrl);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
@@ -170,7 +170,7 @@ static int cam_bps_handle_pc(struct cam_hw_info *bps_dev)
 
 	if (!(pwr_ctrl & BPS_COLLAPSE_MASK)) {
 		rc = cam_cpas_reg_read(core_info->cpas_handle,
-				CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
+				CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_status,
 				true, &pwr_status);
 		if (rc) {
 			CAM_ERR(CAM_ICP, "power status read failed rc=%d", rc);
@@ -178,7 +178,7 @@ static int cam_bps_handle_pc(struct cam_hw_info *bps_dev)
 		}
 
 		cam_cpas_reg_write(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP,
+			CAM_CPAS_REGBASE_CPASTOP,
 			hw_info->pwr_ctrl, true, 0x1);
 
 		if ((pwr_status >> BPS_PWR_ON_MASK))
@@ -193,7 +193,7 @@ static int cam_bps_handle_pc(struct cam_hw_info *bps_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
+			CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_ctrl,
 			true, &pwr_ctrl);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
@@ -201,7 +201,7 @@ static int cam_bps_handle_pc(struct cam_hw_info *bps_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
+			CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_status,
 			true, &pwr_status);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power status read failed rc=%d", rc);
@@ -232,7 +232,7 @@ static int cam_bps_handle_resume(struct cam_hw_info *bps_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
+			CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_ctrl,
 			true, &pwr_ctrl);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
@@ -242,7 +242,7 @@ static int cam_bps_handle_resume(struct cam_hw_info *bps_dev)
 	if (pwr_ctrl & BPS_COLLAPSE_MASK) {
 		CAM_DBG(CAM_PERF, "BPS: pwr_ctrl set(%x)", pwr_ctrl);
 		cam_cpas_reg_write(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP,
+			CAM_CPAS_REGBASE_CPASTOP,
 			hw_info->pwr_ctrl, true, 0);
 	}
 
@@ -253,7 +253,7 @@ static int cam_bps_handle_resume(struct cam_hw_info *bps_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
+			CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_ctrl,
 			true, &pwr_ctrl);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
@@ -261,7 +261,7 @@ static int cam_bps_handle_resume(struct cam_hw_info *bps_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
+			CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_status,
 			true, &pwr_status);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power status read failed rc=%d", rc);
@@ -340,10 +340,10 @@ static int cam_bps_cmd_reset(struct cam_hw_soc_info *soc_info,
 	}
 
 	cam_cpas_reg_read(core_info->cpas_handle,
-		CAM_CPAS_REG_CPASTOP, core_info->bps_hw_info->pwr_ctrl,
+		CAM_CPAS_REGBASE_CPASTOP, core_info->bps_hw_info->pwr_ctrl,
 		true, &pwr_ctrl);
 	cam_cpas_reg_read(core_info->cpas_handle,
-		CAM_CPAS_REG_CPASTOP, core_info->bps_hw_info->pwr_status,
+		CAM_CPAS_REGBASE_CPASTOP, core_info->bps_hw_info->pwr_status,
 		true, &pwr_status);
 	CAM_DBG(CAM_ICP, "(After) pwr_ctrl = %x pwr_status = %x",
 		pwr_ctrl, pwr_status);
@@ -433,7 +433,7 @@ int cam_bps_process_cmd(void *device_priv, uint32_t cmd_type,
 			if (clk_upd_cmd->dev_pc_enable) {
 				cam_bps_handle_pc(bps_dev);
 				cam_cpas_reg_write(core_info->cpas_handle,
-					CAM_CPAS_REG_CPASTOP,
+					CAM_CPAS_REGBASE_CPASTOP,
 					hw_info->pwr_ctrl, true, 0x0);
 			}
 			rc = cam_bps_toggle_clk(soc_info, true);

drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/of.h>
@@ -159,7 +159,7 @@ static int cam_ipe_handle_pc(struct cam_hw_info *ipe_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
+			CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_ctrl,
 			true, &pwr_ctrl);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
@@ -168,7 +168,7 @@ static int cam_ipe_handle_pc(struct cam_hw_info *ipe_dev)
 
 	if (!(pwr_ctrl & IPE_COLLAPSE_MASK)) {
 		rc = cam_cpas_reg_read(core_info->cpas_handle,
-				CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
+				CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_status,
 				true, &pwr_status);
 		if (rc) {
 			CAM_ERR(CAM_ICP, "power status read failed rc=%d", rc);
@@ -176,7 +176,7 @@ static int cam_ipe_handle_pc(struct cam_hw_info *ipe_dev)
 		}
 
 		cam_cpas_reg_write(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP,
+			CAM_CPAS_REGBASE_CPASTOP,
 			hw_info->pwr_ctrl, true, 0x1);
 
 		if (pwr_status >> IPE_PWR_ON_MASK)
@@ -192,7 +192,7 @@ static int cam_ipe_handle_pc(struct cam_hw_info *ipe_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
+			CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_ctrl,
 			true, &pwr_ctrl);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
@@ -200,7 +200,7 @@ static int cam_ipe_handle_pc(struct cam_hw_info *ipe_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
+			CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_status,
 			true, &pwr_status);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power status read failed rc=%d", rc);
@@ -231,7 +231,7 @@ static int cam_ipe_handle_resume(struct cam_hw_info *ipe_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
+			CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_ctrl,
 			true, &pwr_ctrl);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
@@ -241,7 +241,7 @@ static int cam_ipe_handle_resume(struct cam_hw_info *ipe_dev)
 	if (pwr_ctrl & IPE_COLLAPSE_MASK) {
 		CAM_DBG(CAM_PERF, "IPE pwr_ctrl set(%x)", pwr_ctrl);
 		cam_cpas_reg_write(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP,
+			CAM_CPAS_REGBASE_CPASTOP,
 			hw_info->pwr_ctrl, true, 0);
 	}
 
@@ -252,7 +252,7 @@ static int cam_ipe_handle_resume(struct cam_hw_info *ipe_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
+			CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_ctrl,
 			true, &pwr_ctrl);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
@@ -260,7 +260,7 @@ static int cam_ipe_handle_resume(struct cam_hw_info *ipe_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
+			CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_status,
 			true, &pwr_status);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power status read failed rc=%d", rc);
@@ -336,10 +336,10 @@ static int cam_ipe_cmd_reset(struct cam_hw_soc_info *soc_info,
 	}
 
 	cam_cpas_reg_read(core_info->cpas_handle,
-		CAM_CPAS_REG_CPASTOP, core_info->ipe_hw_info->pwr_ctrl,
+		CAM_CPAS_REGBASE_CPASTOP, core_info->ipe_hw_info->pwr_ctrl,
 		true, &pwr_ctrl);
 	cam_cpas_reg_read(core_info->cpas_handle,
-		CAM_CPAS_REG_CPASTOP, core_info->ipe_hw_info->pwr_status,
+		CAM_CPAS_REGBASE_CPASTOP, core_info->ipe_hw_info->pwr_status,
 		true, &pwr_status);
 	CAM_DBG(CAM_ICP, "(After)pwr_ctrl = %x pwr_status = %x",
 		pwr_ctrl, pwr_status);
@@ -423,7 +423,7 @@ int cam_ipe_process_cmd(void *device_priv, uint32_t cmd_type,
 			if (clk_upd_cmd->dev_pc_enable) {
 				cam_ipe_handle_pc(ipe_dev);
 				cam_cpas_reg_write(core_info->cpas_handle,
-					CAM_CPAS_REG_CPASTOP,
+					CAM_CPAS_REGBASE_CPASTOP,
 					hw_info->pwr_ctrl, true, 0x0);
 			}
 			rc = cam_ipe_toggle_clk(soc_info, true);

drivers/cam_icp/icp_hw/ofe_hw/ofe_core.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/of.h>
@@ -160,7 +160,7 @@ static int cam_ofe_handle_pc(struct cam_hw_info *ofe_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-		CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
+		CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_ctrl,
 		true, &pwr_ctrl);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
@@ -169,7 +169,7 @@ static int cam_ofe_handle_pc(struct cam_hw_info *ofe_dev)
 
 	if (!(pwr_ctrl & OFE_COLLAPSE_MASK)) {
 		rc = cam_cpas_reg_read(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
+			CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_status,
 			true, &pwr_status);
 		if (rc) {
 			CAM_ERR(CAM_ICP, "power status read failed rc=%d", rc);
@@ -177,7 +177,7 @@ static int cam_ofe_handle_pc(struct cam_hw_info *ofe_dev)
 		}
 
 		cam_cpas_reg_write(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP,
+			CAM_CPAS_REGBASE_CPASTOP,
 			hw_info->pwr_ctrl, true, 0x1);
 
 		if ((pwr_status >> OFE_PWR_ON_MASK))
@@ -192,7 +192,7 @@ static int cam_ofe_handle_pc(struct cam_hw_info *ofe_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-		CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
+		CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_ctrl,
 		true, &pwr_ctrl);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
@@ -200,7 +200,7 @@ static int cam_ofe_handle_pc(struct cam_hw_info *ofe_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-		CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
+		CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_status,
 		true, &pwr_status);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power status read failed rc=%d", rc);
@@ -229,7 +229,7 @@ static int cam_ofe_handle_resume(struct cam_hw_info *ofe_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-		CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
+		CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_ctrl,
 		true, &pwr_ctrl);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
@@ -239,7 +239,7 @@ static int cam_ofe_handle_resume(struct cam_hw_info *ofe_dev)
 	if (pwr_ctrl & OFE_COLLAPSE_MASK) {
 		CAM_DBG(CAM_PERF, "OFE: pwr_ctrl set(%x)", pwr_ctrl);
 		cam_cpas_reg_write(core_info->cpas_handle,
-			CAM_CPAS_REG_CPASTOP,
+			CAM_CPAS_REGBASE_CPASTOP,
 			hw_info->pwr_ctrl, true, 0);
 	}
 
@@ -250,7 +250,7 @@ static int cam_ofe_handle_resume(struct cam_hw_info *ofe_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-		CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
+		CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_ctrl,
 		true, &pwr_ctrl);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
@@ -258,7 +258,7 @@ static int cam_ofe_handle_resume(struct cam_hw_info *ofe_dev)
 	}
 
 	rc = cam_cpas_reg_read(core_info->cpas_handle,
-		CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
+		CAM_CPAS_REGBASE_CPASTOP, hw_info->pwr_status,
 		true, &pwr_status);
 	if (rc) {
 		CAM_ERR(CAM_ICP, "power status read failed rc=%d", rc);
@@ -335,10 +335,10 @@ static int cam_ofe_cmd_reset(struct cam_hw_soc_info *soc_info,
 	}
 
 	cam_cpas_reg_read(core_info->cpas_handle,
-		CAM_CPAS_REG_CPASTOP, core_info->ofe_hw_info->pwr_ctrl,
+		CAM_CPAS_REGBASE_CPASTOP, core_info->ofe_hw_info->pwr_ctrl,
 		true, &pwr_ctrl);
 	cam_cpas_reg_read(core_info->cpas_handle,
-		CAM_CPAS_REG_CPASTOP, core_info->ofe_hw_info->pwr_status,
+		CAM_CPAS_REGBASE_CPASTOP, core_info->ofe_hw_info->pwr_status,
 		true, &pwr_status);
 	CAM_DBG(CAM_ICP, "(After) pwr_ctrl = %x pwr_status = %x",
 		pwr_ctrl, pwr_status);
@@ -428,7 +428,7 @@ int cam_ofe_process_cmd(void *device_priv, uint32_t cmd_type,
 			if (clk_upd_cmd->dev_pc_enable) {
 				cam_ofe_handle_pc(ofe_dev);
 				cam_cpas_reg_write(core_info->cpas_handle,
-					CAM_CPAS_REG_CPASTOP,
+					CAM_CPAS_REGBASE_CPASTOP,
 					hw_info->pwr_ctrl, true, 0x0);
 			}
 			rc = cam_ofe_toggle_clk(soc_info, true);

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.c

@@ -244,7 +244,7 @@ int cam_ife_csid_enable_ife_force_clock_on(struct cam_hw_soc_info  *soc_info,
 	soc_private = soc_info->soc_private;
 	cpass_ife_force_clk_offset =
 		cpas_ife_base_offset + (0x4 * soc_info->index);
-	rc = cam_cpas_reg_write(soc_private->cpas_handle, CAM_CPAS_REG_CPASTOP,
+	rc = cam_cpas_reg_write(soc_private->cpas_handle, CAM_CPAS_REGBASE_CPASTOP,
 		cpass_ife_force_clk_offset, 1, 1);
 
 	if (rc)
@@ -272,7 +272,7 @@ int cam_ife_csid_disable_ife_force_clock_on(struct cam_hw_soc_info *soc_info,
 	soc_private = soc_info->soc_private;
 	cpass_ife_force_clk_offset =
 		cpas_ife_base_offset + (0x4 * soc_info->index);
-	rc = cam_cpas_reg_write(soc_private->cpas_handle, CAM_CPAS_REG_CPASTOP,
+	rc = cam_cpas_reg_write(soc_private->cpas_handle, CAM_CPAS_REGBASE_CPASTOP,
 		cpass_ife_force_clk_offset,  1, 0);
 
 	if (rc)

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.c

@@ -170,7 +170,7 @@ int cam_tfe_csid_enable_tfe_force_clock_on(struct cam_hw_soc_info  *soc_info,
 	soc_private = soc_info->soc_private;
 	cpass_tfe_force_clk_offset =
 		cpas_tfe_base_offset + (0x4 * soc_info->index);
-	rc = cam_cpas_reg_write(soc_private->cpas_handle, CAM_CPAS_REG_CPASTOP,
+	rc = cam_cpas_reg_write(soc_private->cpas_handle, CAM_CPAS_REGBASE_CPASTOP,
 		cpass_tfe_force_clk_offset, 1, 1);
 
 	if (rc)
@@ -198,7 +198,7 @@ int cam_tfe_csid_disable_tfe_force_clock_on(struct cam_hw_soc_info *soc_info,
 	soc_private = soc_info->soc_private;
 	cpass_tfe_force_clk_offset =
 		cpas_tfe_base_offset + (0x4 * soc_info->index);
-	rc = cam_cpas_reg_write(soc_private->cpas_handle, CAM_CPAS_REG_CPASTOP,
+	rc = cam_cpas_reg_write(soc_private->cpas_handle, CAM_CPAS_REGBASE_CPASTOP,
 		cpass_tfe_force_clk_offset,  1, 0);
 
 	if (rc)

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/delay.h>
@@ -352,10 +352,8 @@ static void cam_tfe_log_error_irq_status(
 		CAM_INFO(CAM_ISP, "Top debug [i]:0x%x", i, val_0);
 	}
 
-	cam_cpas_reg_read(soc_private->cpas_handle,
-		CAM_CPAS_REG_CAMNOC, 0x20, true, &val_0);
-	CAM_INFO(CAM_ISP, "tfe_niu_MaxWr_Low offset 0x20 val 0x%x",
-		val_0);
+	cam_cpas_dump_camnoc_buff_fill_info(soc_private->cpas_handle);
+
 	for (i = 0; i < top_priv->common_data.common_reg->num_perf_cfg; i++) {
 		val_0 = cam_io_r(mem_base  +
 			top_priv->common_data.common_reg->perf_cfg[i].perf_pixel_count);
@@ -1519,10 +1517,7 @@ static int cam_tfe_top_get_reg_dump(
 		wm_offset += reg_dump_data->bus_client_offset;
 	}
 
-	cam_cpas_reg_read(soc_private->cpas_handle,
-		CAM_CPAS_REG_CAMNOC, 0x20, true, &val_0);
-	CAM_INFO(CAM_ISP, "tfe_niu_MaxWr_Low offset 0x20 val 0x%x",
-		val_0);
+	cam_cpas_dump_camnoc_buff_fill_info(soc_private->cpas_handle);
 
 	/* dump the clock votings */
 	CAM_INFO(CAM_ISP, "TFE:%d clk=%ld",
@@ -1748,9 +1743,7 @@ dump_bw:
 		sizeof(struct cam_isp_hw_dump_header));
 	start = addr;
 	hdr->word_size = sizeof(uint32_t);
-	cam_cpas_reg_read(soc_private->cpas_handle,
-		CAM_CPAS_REG_CAMNOC, 0x20, true, &val);
-	*addr++ = val;
+
 	hdr->size = hdr->word_size * (addr - start);
 	dump_args->offset +=  hdr->size +
 		sizeof(struct cam_isp_hw_dump_header);

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/slab.h>
@@ -417,73 +417,6 @@ static int cam_vfe_camif_lite_handle_irq_top_half(uint32_t evt_id,
 	return rc;
 }
 
-static int cam_vfe_camif_lite_cpas_fifo_levels_reg_dump(
-	struct cam_vfe_mux_camif_lite_data *camif_lite_priv)
-{
-	int rc = 0;
-	struct cam_vfe_soc_private *soc_private =
-		camif_lite_priv->soc_info->soc_private;
-	uint32_t  val;
-
-	if (soc_private->cpas_version == CAM_CPAS_TITAN_175_V120 ||
-		soc_private->cpas_version == CAM_CPAS_TITAN_175_V130 ||
-		soc_private->cpas_version == CAM_CPAS_TITAN_165_V100) {
-		rc = cam_cpas_reg_read(soc_private->cpas_handle,
-				CAM_CPAS_REG_CAMNOC, 0x3A20, true, &val);
-		if (rc) {
-			CAM_ERR(CAM_ISP,
-				"IFE0_nRDI_MAXWR_LOW read failed rc=%d",
-				rc);
-			return rc;
-		}
-		CAM_INFO(CAM_ISP, "IFE0_nRDI_MAXWR_LOW offset 0x3A20 val 0x%x",
-			val);
-
-		rc = cam_cpas_reg_read(soc_private->cpas_handle,
-				CAM_CPAS_REG_CAMNOC, 0x5420, true, &val);
-		if (rc) {
-			CAM_ERR(CAM_ISP,
-				"IFE1_nRDI_MAXWR_LOW read failed rc=%d",
-				rc);
-			return rc;
-		}
-		CAM_INFO(CAM_ISP, "IFE1_nRDI_MAXWR_LOW offset 0x5420 val 0x%x",
-			val);
-
-		rc = cam_cpas_reg_read(soc_private->cpas_handle,
-				CAM_CPAS_REG_CAMNOC, 0x3620, true, &val);
-		if (rc) {
-			CAM_ERR(CAM_ISP,
-				"IFE0123_RDI_WR_MAXWR_LOW read failed rc=%d",
-				rc);
-			return rc;
-		}
-		CAM_INFO(CAM_ISP,
-			"IFE0123_RDI_WR_MAXWR_LOW offset 0x3620 val 0x%x", val);
-
-	} else if (soc_private->cpas_version < CAM_CPAS_TITAN_175_V120) {
-		rc = cam_cpas_reg_read(soc_private->cpas_handle,
-				CAM_CPAS_REG_CAMNOC, 0x420, true, &val);
-		if (rc) {
-			CAM_ERR(CAM_ISP, "IFE02_MAXWR_LOW read failed rc=%d",
-				rc);
-			return rc;
-		}
-		CAM_INFO(CAM_ISP, "IFE02_MAXWR_LOW offset 0x420 val 0x%x", val);
-
-		rc = cam_cpas_reg_read(soc_private->cpas_handle,
-				CAM_CPAS_REG_CAMNOC, 0x820, true, &val);
-		if (rc) {
-			CAM_ERR(CAM_ISP, "IFE13_MAXWR_LOW read failed rc=%d",
-				rc);
-			return rc;
-		}
-		CAM_INFO(CAM_ISP, "IFE13_MAXWR_LOW offset 0x820 val 0x%x", val);
-	}
-
-	return 0;
-}
-
 static int cam_vfe_camif_lite_handle_irq_bottom_half(
 	void                                 *handler_priv,
 	void                                 *evt_payload_priv)
@@ -553,7 +486,8 @@ static int cam_vfe_camif_lite_handle_irq_bottom_half(
 
 		err_evt_info.err_type = CAM_VFE_IRQ_STATUS_OVERFLOW;
 		evt_info.event_data = (void *)&err_evt_info;
-		cam_vfe_camif_lite_cpas_fifo_levels_reg_dump(camif_lite_priv);
+
+		cam_cpas_dump_camnoc_buff_fill_info(soc_private->cpas_handle);
 
 		ktime_get_boottime_ts64(&ts);
 		CAM_INFO(CAM_ISP,

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c

@@ -554,33 +554,7 @@ static int cam_vfe_camif_reg_dump(
 	}
 
 	soc_private = camif_priv->soc_info->soc_private;
-	if (soc_private->cpas_version == CAM_CPAS_TITAN_175_V120 ||
-		soc_private->cpas_version == CAM_CPAS_TITAN_175_V130 ||
-		soc_private->cpas_version == CAM_CPAS_TITAN_165_V100) {
-		cam_cpas_reg_read(soc_private->cpas_handle,
-			CAM_CPAS_REG_CAMNOC, 0x3A20, true, &val);
-		CAM_INFO(CAM_ISP, "IFE0_nRDI_MAXWR_LOW offset 0x3A20 val 0x%x",
-			val);
-
-		cam_cpas_reg_read(soc_private->cpas_handle,
-			CAM_CPAS_REG_CAMNOC, 0x5420, true, &val);
-		CAM_INFO(CAM_ISP, "IFE1_nRDI_MAXWR_LOW offset 0x5420 val 0x%x",
-			val);
-
-		cam_cpas_reg_read(soc_private->cpas_handle,
-			CAM_CPAS_REG_CAMNOC, 0x3620, true, &val);
-		CAM_INFO(CAM_ISP,
-			"IFE0123_RDI_WR_MAXWR_LOW offset 0x3620 val 0x%x", val);
-
-	} else if (soc_private->cpas_version < CAM_CPAS_TITAN_175_V120) {
-		cam_cpas_reg_read(soc_private->cpas_handle,
-			CAM_CPAS_REG_CAMNOC, 0x420, true, &val);
-		CAM_INFO(CAM_ISP, "IFE02_MAXWR_LOW offset 0x420 val 0x%x", val);
-
-		cam_cpas_reg_read(soc_private->cpas_handle,
-			CAM_CPAS_REG_CAMNOC, 0x820, true, &val);
-		CAM_INFO(CAM_ISP, "IFE13_MAXWR_LOW offset 0x820 val 0x%x", val);
-	}
+	cam_cpas_dump_camnoc_buff_fill_info(soc_private->cpas_handle);
 
 	return 0;
 }

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_fe_ver1.c

@@ -391,13 +391,7 @@ static int cam_vfe_fe_reg_dump(
 		CAM_INFO(CAM_ISP, "offset 0x%x val 0x%x", i, val);
 	}
 
-	cam_cpas_reg_read(soc_private->cpas_handle,
-		CAM_CPAS_REG_CAMNOC, 0x420, true, &val);
-	CAM_INFO(CAM_ISP, "IFE02_MAXWR_LOW offset 0x420 val 0x%x", val);
-
-	cam_cpas_reg_read(soc_private->cpas_handle,
-		CAM_CPAS_REG_CAMNOC, 0x820, true, &val);
-	CAM_INFO(CAM_ISP, "IFE13_MAXWR_LOW offset 0x820 val 0x%x", val);
+	cam_cpas_dump_camnoc_buff_fill_info(soc_private->cpas_handle);
 
 	return rc;
 }

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/slab.h>
@@ -86,73 +86,6 @@ static int cam_vfe_rdi_put_evt_payload(
 	return 0;
 }
 
-static int cam_vfe_rdi_cpas_reg_dump(
-struct cam_vfe_mux_rdi_data *rdi_priv)
-{
-	int rc = 0;
-	struct cam_vfe_soc_private *soc_private =
-		rdi_priv->soc_info->soc_private;
-	uint32_t  val;
-
-	if (soc_private->cpas_version == CAM_CPAS_TITAN_175_V120 ||
-		soc_private->cpas_version == CAM_CPAS_TITAN_175_V130 ||
-		soc_private->cpas_version == CAM_CPAS_TITAN_165_V100) {
-		rc = cam_cpas_reg_read(soc_private->cpas_handle,
-				CAM_CPAS_REG_CAMNOC, 0x3A20, true, &val);
-		if (rc) {
-			CAM_ERR(CAM_ISP,
-				"IFE0_nRDI_MAXWR_LOW read failed rc=%d",
-				rc);
-			return rc;
-		}
-		CAM_INFO(CAM_ISP, "IFE0_nRDI_MAXWR_LOW offset 0x3A20 val 0x%x",
-			val);
-
-		rc = cam_cpas_reg_read(soc_private->cpas_handle,
-				CAM_CPAS_REG_CAMNOC, 0x5420, true, &val);
-		if (rc) {
-			CAM_ERR(CAM_ISP,
-				"IFE1_nRDI_MAXWR_LOW read failed rc=%d",
-				rc);
-			return rc;
-		}
-		CAM_INFO(CAM_ISP, "IFE1_nRDI_MAXWR_LOW offset 0x5420 val 0x%x",
-			val);
-
-		rc = cam_cpas_reg_read(soc_private->cpas_handle,
-				CAM_CPAS_REG_CAMNOC, 0x3620, true, &val);
-		if (rc) {
-			CAM_ERR(CAM_ISP,
-				"IFE0123_RDI_WR_MAXWR_LOW read failed rc=%d",
-				rc);
-			return rc;
-		}
-		CAM_INFO(CAM_ISP,
-			"IFE0123_RDI_WR_MAXWR_LOW offset 0x3620 val 0x%x", val);
-
-	} else if (soc_private->cpas_version < CAM_CPAS_TITAN_175_V120) {
-		rc = cam_cpas_reg_read(soc_private->cpas_handle,
-				CAM_CPAS_REG_CAMNOC, 0x420, true, &val);
-		if (rc) {
-			CAM_ERR(CAM_ISP, "IFE02_MAXWR_LOW read failed rc=%d",
-				rc);
-			return rc;
-		}
-		CAM_INFO(CAM_ISP, "IFE02_MAXWR_LOW offset 0x420 val 0x%x", val);
-
-		rc = cam_cpas_reg_read(soc_private->cpas_handle,
-				CAM_CPAS_REG_CAMNOC, 0x820, true, &val);
-		if (rc) {
-			CAM_ERR(CAM_ISP, "IFE13_MAXWR_LOW read failed rc=%d",
-				rc);
-			return rc;
-		}
-		CAM_INFO(CAM_ISP, "IFE13_MAXWR_LOW offset 0x820 val 0x%x", val);
-	}
-
-	return 0;
-}
-
 static int cam_vfe_rdi_err_irq_top_half(
 	uint32_t                               evt_id,
 	struct cam_irq_th_payload             *th_payload)
@@ -539,7 +472,7 @@ static int cam_vfe_rdi_handle_irq_bottom_half(void *handler_priv,
 			"current monotonic timestamp:[%lld.%09lld]",
 			ts.tv_sec, ts.tv_nsec);
 
-		cam_vfe_rdi_cpas_reg_dump(rdi_priv);
+		cam_cpas_dump_camnoc_buff_fill_info(soc_private->cpas_handle);
 
 		CAM_INFO(CAM_ISP, "ife_clk_src:%lld",
 			soc_private->ife_clk_src);

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

@@ -1611,7 +1611,7 @@ static int __csiphy_cpas_configure_for_main_or_aon(
 		return rc;
 	}
 
-	cam_cpas_reg_read(cpas_handle, CAM_CPAS_REG_CPASTOP,
+	cam_cpas_reg_read(cpas_handle, CAM_CPAS_REGBASE_CPASTOP,
 		aon_sel_params->aon_cam_sel_offset[g_phy_data[phy_idx].aon_cam_id],
 		true, &aon_config);
 
@@ -1630,7 +1630,7 @@ static int __csiphy_cpas_configure_for_main_or_aon(
 	}
 
 	CAM_DBG(CAM_CSIPHY, "value of aon_config = %u", aon_config);
-	rc = cam_cpas_reg_write(cpas_handle, CAM_CPAS_REG_CPASTOP,
+	rc = cam_cpas_reg_write(cpas_handle, CAM_CPAS_REGBASE_CPASTOP,
 		aon_sel_params->aon_cam_sel_offset[g_phy_data[phy_idx].aon_cam_id],
 		true, aon_config);
 	if (rc)