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@@ -54,8 +54,9 @@
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* @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter.
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* Return: void
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*/
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-static inline void hal_rx_wbm_err_info_get_generic_li(void *wbm_desc,
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- void *wbm_er_info1)
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+static inline
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+void hal_rx_wbm_err_info_get_generic_li(void *wbm_desc,
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+ void *wbm_er_info1)
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{
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struct hal_wbm_err_desc_info *wbm_er_info =
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(struct hal_wbm_err_desc_info *)wbm_er_info1;
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@@ -1990,4 +1991,345 @@ static uint32_t hal_rx_pkt_tlv_offset_get_generic(void)
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}
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#endif
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+#if defined(QDF_BIG_ENDIAN_MACHINE)
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+/**
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+ * hal_setup_reo_swap() - Set the swap flag for big endian machines
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+ * @soc: HAL soc handle
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+ *
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+ * Return: None
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+ */
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+static inline void hal_setup_reo_swap(struct hal_soc *soc)
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+{
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+ uint32_t reg_val;
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+
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+ reg_val = HAL_REG_READ(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(
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+ SEQ_WCSS_UMAC_REO_REG_OFFSET));
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+
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+ reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, WRITE_STRUCT_SWAP, 1);
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+ reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, READ_STRUCT_SWAP, 1);
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+
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+ HAL_REG_WRITE(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(
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+ SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val);
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+}
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+#else
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+static inline void hal_setup_reo_swap(struct hal_soc *soc)
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+{
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+}
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+#endif
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+
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+/**
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+ * hal_reo_setup_generic_li - Initialize HW REO block
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+ *
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+ * @hal_soc: Opaque HAL SOC handle
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+ * @reo_params: parameters needed by HAL for REO config
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+ */
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+static
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+void hal_reo_setup_generic_li(struct hal_soc *soc, void *reoparams)
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+{
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+ uint32_t reg_val;
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+ struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams;
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+
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+ reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
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+ SEQ_WCSS_UMAC_REO_REG_OFFSET));
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+
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+ hal_reo_config(soc, reg_val, reo_params);
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+ /* Other ring enable bits and REO_ENABLE will be set by FW */
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+
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+ /* TODO: Setup destination ring mapping if enabled */
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+
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+ /* TODO: Error destination ring setting is left to default.
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+ * Default setting is to send all errors to release ring.
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+ */
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+
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+ /* Set the reo descriptor swap bits in case of BIG endian platform */
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+ hal_setup_reo_swap(soc);
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+
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+ HAL_REG_WRITE(soc,
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+ HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
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+ SEQ_WCSS_UMAC_REO_REG_OFFSET),
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+ HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000);
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+
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+ HAL_REG_WRITE(soc,
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+ HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
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+ SEQ_WCSS_UMAC_REO_REG_OFFSET),
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+ (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
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+
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+ HAL_REG_WRITE(soc,
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+ HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
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+ SEQ_WCSS_UMAC_REO_REG_OFFSET),
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+ (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
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+
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+ HAL_REG_WRITE(soc,
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+ HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
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+ SEQ_WCSS_UMAC_REO_REG_OFFSET),
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+ (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000));
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+
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+ /*
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+ * When hash based routing is enabled, routing of the rx packet
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+ * is done based on the following value: 1 _ _ _ _ The last 4
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+ * bits are based on hash[3:0]. This means the possible values
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+ * are 0x10 to 0x1f. This value is used to look-up the
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+ * ring ID configured in Destination_Ring_Ctrl_IX_* register.
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+ * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3
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+ * registers need to be configured to set-up the 16 entries to
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+ * map the hash values to a ring number. There are 3 bits per
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+ * hash entry which are mapped as follows:
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+ * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI),
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+ * 7: NOT_USED.
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+ */
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+ if (reo_params->rx_hash_enabled) {
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+ HAL_REG_WRITE(soc,
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+ HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
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+ SEQ_WCSS_UMAC_REO_REG_OFFSET),
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+ reo_params->remap1);
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+
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+ hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
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+ HAL_REG_READ(soc,
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+ HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
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+ SEQ_WCSS_UMAC_REO_REG_OFFSET)));
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+
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+ HAL_REG_WRITE(soc,
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+ HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
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+ SEQ_WCSS_UMAC_REO_REG_OFFSET),
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+ reo_params->remap2);
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+
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+ hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x",
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+ HAL_REG_READ(soc,
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+ HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
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+ SEQ_WCSS_UMAC_REO_REG_OFFSET)));
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+ }
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+
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+ /* TODO: Check if the following registers shoould be setup by host:
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+ * AGING_CONTROL
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+ * HIGH_MEMORY_THRESHOLD
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+ * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2]
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+ * GLOBAL_LINK_DESC_COUNT_CTRL
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+ */
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+}
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+
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+/**
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+ * hal_setup_link_idle_list_generic_li - Setup scattered idle list using the
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+ * buffer list provided
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+ *
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+ * @hal_soc: Opaque HAL SOC handle
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+ * @scatter_bufs_base_paddr: Array of physical base addresses
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+ * @scatter_bufs_base_vaddr: Array of virtual base addresses
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+ * @num_scatter_bufs: Number of scatter buffers in the above lists
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+ * @scatter_buf_size: Size of each scatter buffer
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+ * @last_buf_end_offset: Offset to the last entry
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+ * @num_entries: Total entries of all scatter bufs
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+ *
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+ * Return: None
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+ */
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+static void
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+hal_setup_link_idle_list_generic_li(struct hal_soc *soc,
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+ qdf_dma_addr_t scatter_bufs_base_paddr[],
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+ void *scatter_bufs_base_vaddr[],
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+ uint32_t num_scatter_bufs,
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+ uint32_t scatter_buf_size,
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+ uint32_t last_buf_end_offset,
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+ uint32_t num_entries)
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+{
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+ int i;
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+ uint32_t *prev_buf_link_ptr = NULL;
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+ uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size;
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+ uint32_t val;
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+
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+ /* Link the scatter buffers */
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+ for (i = 0; i < num_scatter_bufs; i++) {
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+ if (i > 0) {
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+ prev_buf_link_ptr[0] =
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+ scatter_bufs_base_paddr[i] & 0xffffffff;
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+ prev_buf_link_ptr[1] = HAL_SM(
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+ HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
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+ BASE_ADDRESS_39_32,
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+ ((uint64_t)(scatter_bufs_base_paddr[i])
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+ >> 32)) | HAL_SM(
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+ HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
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+ ADDRESS_MATCH_TAG,
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+ ADDRESS_MATCH_TAG_VAL);
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+ }
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+ prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] +
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+ scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE);
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+ }
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+
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+ /* TBD: Register programming partly based on MLD & the rest based on
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+ * inputs from HW team. Not complete yet.
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+ */
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+
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+ reg_scatter_buf_size = (scatter_buf_size -
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+ WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64;
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+ reg_tot_scatter_buf_size = ((scatter_buf_size -
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+ WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64;
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+
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+ HAL_REG_WRITE(soc,
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+ HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR
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+ (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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+ HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL,
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+ SCATTER_BUFFER_SIZE,
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+ reg_scatter_buf_size) |
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+ HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL,
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+ LINK_DESC_IDLE_LIST_MODE, 0x1));
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+
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+ HAL_REG_WRITE(soc,
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+ HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR
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+ (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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+ HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE,
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+ SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST,
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+ reg_tot_scatter_buf_size));
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+
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+ HAL_REG_WRITE(soc,
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+ HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR
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+ (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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+ scatter_bufs_base_paddr[0] & 0xffffffff);
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+
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+ HAL_REG_WRITE(soc,
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+ HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR
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+ (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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+ ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) &
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+ HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK);
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+
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+ HAL_REG_WRITE(soc,
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+ HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR
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+ (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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+ HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
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+ BASE_ADDRESS_39_32,
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+ ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) |
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+ HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
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+ ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL));
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+
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+ /* ADDRESS_MATCH_TAG field in the above register is expected to match
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+ * with the upper bits of link pointer. The above write sets this field
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+ * to zero and we are also setting the upper bits of link pointers to
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+ * zero while setting up the link list of scatter buffers above
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+ */
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+
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+ /* Setup head and tail pointers for the idle list */
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+ HAL_REG_WRITE(soc,
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+ HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR
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+ (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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+ scatter_bufs_base_paddr[num_scatter_bufs - 1] &
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+ 0xffffffff);
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+ HAL_REG_WRITE(soc,
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+ HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR
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+ (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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+ HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
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+ BUFFER_ADDRESS_39_32,
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+ ((uint64_t)(scatter_bufs_base_paddr
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+ [num_scatter_bufs - 1]) >> 32)) |
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+ HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
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+ HEAD_POINTER_OFFSET, last_buf_end_offset >> 2));
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+
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+ HAL_REG_WRITE(soc,
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+ HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR
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+ (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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+ scatter_bufs_base_paddr[0] & 0xffffffff);
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+
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+ HAL_REG_WRITE(soc,
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+ HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR
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+ (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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+ scatter_bufs_base_paddr[0] & 0xffffffff);
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+ HAL_REG_WRITE(soc,
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+ HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR
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+ (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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+ HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
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+ BUFFER_ADDRESS_39_32,
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+ ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) |
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+ HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
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+ TAIL_POINTER_OFFSET, 0));
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+
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+ HAL_REG_WRITE(soc,
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+ HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR
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+ (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2 * num_entries);
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+
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+ /* Set RING_ID_DISABLE */
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+ val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1);
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+
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+ /*
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+ * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence
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+ * check the presence of the bit before toggling it.
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+ */
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+#ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK
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+ val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1);
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+#endif
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+ HAL_REG_WRITE(soc,
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+ HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR
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+ (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
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+ val);
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+}
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+
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+#ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET
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+/**
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+ * hal_tx_desc_set_search_type_generic_li - Set the search type value
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+ * @desc: Handle to Tx Descriptor
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+ * @search_type: search type
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+ * 0 – Normal search
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+ * 1 – Index based address search
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+ * 2 – Index based flow search
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+ *
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+ * Return: void
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+ */
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+static inline
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+void hal_tx_desc_set_search_type_generic_li(void *desc, uint8_t search_type)
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+{
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+ HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |=
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+ HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type);
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+}
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+#else
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+static inline
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+void hal_tx_desc_set_search_type_generic_li(void *desc, uint8_t search_type)
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+{
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+}
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+
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+#endif
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+
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+#ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET
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+/**
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+ * hal_tx_desc_set_search_index_generic_li - Set the search index value
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+ * @desc: Handle to Tx Descriptor
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+ * @search_index: The index that will be used for index based address or
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+ * flow search. The field is valid when 'search_type' is
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+ * 1 0r 2
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+ *
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+ * Return: void
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+ */
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+static inline
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+void hal_tx_desc_set_search_index_generic_li(void *desc, uint32_t search_index)
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+{
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+ HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |=
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+ HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index);
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+}
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+#else
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+static inline
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+void hal_tx_desc_set_search_index_generic_li(void *desc, uint32_t search_index)
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+{
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+}
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+#endif
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+
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+#ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET
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+/**
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+ * hal_tx_desc_set_cache_set_num_generic_li - Set the cache-set-num value
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+ * @desc: Handle to Tx Descriptor
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+ * @cache_num: Cache set number that should be used to cache the index
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+ * based search results, for address and flow search.
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+ * This value should be equal to LSB four bits of the hash value
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+ * of match data, in case of search index points to an entry
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+ * which may be used in content based search also. The value can
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+ * be anything when the entry pointed by search index will not be
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+ * used for content based search.
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+ *
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+ * Return: void
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+ */
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+static inline
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+void hal_tx_desc_set_cache_set_num_generic_li(void *desc, uint8_t cache_num)
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+{
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+ HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |=
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+ HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num);
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+}
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+#else
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+static inline
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+void hal_tx_desc_set_cache_set_num_generic_li(void *desc, uint8_t cache_num)
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+{
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+}
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+#endif
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#endif /* _HAL_LI_GENERIC_API_H_ */
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Chaithanya Garrepalli