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qcacmn: Remove support for QCA6180

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This is deprecated emulation hardware.

Change-Id: Ibafc2e55a26bcac28e88a325689a419e058997b5
CRs-Fixed: 1003804
This commit is contained in:
Houston Hoffman
2016-04-12 15:39:04 -07:00
committed by Gerrit - the friendly Code Review server
parent 247f09b86a
commit f789c661a8
9 changed files with 27 additions and 1101 deletions
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3
hif/inc/hif.h
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@@ -54,7 +54,6 @@ typedef void __iomem *A_target_id_t;
#define HIF_TYPE_AR6320V2 8 #define HIF_TYPE_AR6320V2 8
/* For attaching Peregrine 2.0 board host_reg_tbl only */ /* For attaching Peregrine 2.0 board host_reg_tbl only */
#define HIF_TYPE_AR9888V2 8 #define HIF_TYPE_AR9888V2 8
#define HIF_TYPE_QCA6180 9
#define HIF_TYPE_ADRASTEA 10 #define HIF_TYPE_ADRASTEA 10
#define TARGET_TYPE_UNKNOWN 0 #define TARGET_TYPE_UNKNOWN 0
@@ -76,8 +75,6 @@ typedef void __iomem *A_target_id_t;
#define TARGET_TYPE_AR6320V3 13 #define TARGET_TYPE_AR6320V3 13
/* For Tufello1.0 target_reg_tbl ID*/ /* For Tufello1.0 target_reg_tbl ID*/
#define TARGET_TYPE_QCA9377V1 14 #define TARGET_TYPE_QCA9377V1 14
/* For QCA6180 target */
#define TARGET_TYPE_QCA6180 15
/* For Adrastea target */ /* For Adrastea target */
#define TARGET_TYPE_ADRASTEA 16 #define TARGET_TYPE_ADRASTEA 16

40
hif/src/adrastea_reg_def.h
View File

@@ -1261,28 +1261,28 @@
#define ADRASTEA_TARG_DRAM_START 0x00400000 #define ADRASTEA_TARG_DRAM_START 0x00400000
#define ADRASTEA_SOC_SYSTEM_SLEEP_OFFSET 0x000000c0 #define ADRASTEA_SOC_SYSTEM_SLEEP_OFFSET 0x000000c0
#define ADRASTEA_SOC_RESET_CONTROL_OFFSET \ #define ADRASTEA_SOC_RESET_CONTROL_OFFSET \
(0x00000000 + _RTC_SOC_REG_BASE_ADDRESS) (0x00000000 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS)
#define ADRASTEA_SOC_CLOCK_CONTROL_OFFSET \ #define ADRASTEA_SOC_CLOCK_CONTROL_OFFSET \
(0x00000028 + _RTC_SOC_REG_BASE_ADDRESS) (0x00000028 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS)
#define ADRASTEA_SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 #define ADRASTEA_SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
#define ADRASTEA_SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001 #define ADRASTEA_SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001
#define ADRASTEA_WLAN_GPIO_PIN0_ADDRESS \ #define ADRASTEA_WLAN_GPIO_PIN0_ADDRESS \
(0x50 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS) (0x50 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
#define ADRASTEA_WLAN_GPIO_PIN1_ADDRESS \ #define ADRASTEA_WLAN_GPIO_PIN1_ADDRESS \
(0x54 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS) (0x54 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
#define ADRASTEA_WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 #define ADRASTEA_WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
#define ADRASTEA_WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 #define ADRASTEA_WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
#define ADRASTEA_SOC_CPU_CLOCK_OFFSET 0x00000020 #define ADRASTEA_SOC_CPU_CLOCK_OFFSET 0x00000020
#define ADRASTEA_SOC_LPO_CAL_OFFSET \ #define ADRASTEA_SOC_LPO_CAL_OFFSET \
(0xe0 + _RTC_SOC_REG_BASE_ADDRESS) (0xe0 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS)
#define ADRASTEA_WLAN_GPIO_PIN10_ADDRESS \ #define ADRASTEA_WLAN_GPIO_PIN10_ADDRESS \
(0x78 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS) (0x78 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
#define ADRASTEA_WLAN_GPIO_PIN11_ADDRESS \ #define ADRASTEA_WLAN_GPIO_PIN11_ADDRESS \
(0x7c + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS) (0x7c + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
#define ADRASTEA_WLAN_GPIO_PIN12_ADDRESS \ #define ADRASTEA_WLAN_GPIO_PIN12_ADDRESS \
(0x80 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS) (0x80 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
#define ADRASTEA_WLAN_GPIO_PIN13_ADDRESS \ #define ADRASTEA_WLAN_GPIO_PIN13_ADDRESS \
(0x84 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS) (0x84 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
#define ADRASTEA_SOC_CPU_CLOCK_STANDARD_LSB 0 #define ADRASTEA_SOC_CPU_CLOCK_STANDARD_LSB 0
#define ADRASTEA_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 #define ADRASTEA_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
#define ADRASTEA_SOC_LPO_CAL_ENABLE_LSB 20 #define ADRASTEA_SOC_LPO_CAL_ENABLE_LSB 20
@@ -1304,12 +1304,12 @@
#define ADRASTEA_SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 #define ADRASTEA_SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
#define ADRASTEA_SI_CONFIG_DIVIDER_LSB 0 #define ADRASTEA_SI_CONFIG_DIVIDER_LSB 0
#define ADRASTEA_SI_CONFIG_DIVIDER_MASK 0x0000000f #define ADRASTEA_SI_CONFIG_DIVIDER_MASK 0x0000000f
#define ADRASTEA_SI_CONFIG_OFFSET (0x00000000 + _SI_REG_BASE_ADDRESS) #define ADRASTEA_SI_CONFIG_OFFSET (0x00000000 + ADRASTEA_SI_REG_BASE_ADDRESS)
#define ADRASTEA_SI_TX_DATA0_OFFSET (0x00000008 + _SI_REG_BASE_ADDRESS) #define ADRASTEA_SI_TX_DATA0_OFFSET (0x00000008 + ADRASTEA_SI_REG_BASE_ADDRESS)
#define ADRASTEA_SI_TX_DATA1_OFFSET (0x0000000c + _SI_REG_BASE_ADDRESS) #define ADRASTEA_SI_TX_DATA1_OFFSET (0x0000000c + ADRASTEA_SI_REG_BASE_ADDRESS)
#define ADRASTEA_SI_RX_DATA0_OFFSET (0x00000010 + _SI_REG_BASE_ADDRESS) #define ADRASTEA_SI_RX_DATA0_OFFSET (0x00000010 + ADRASTEA_SI_REG_BASE_ADDRESS)
#define ADRASTEA_SI_RX_DATA1_OFFSET (0x00000014 + _SI_REG_BASE_ADDRESS) #define ADRASTEA_SI_RX_DATA1_OFFSET (0x00000014 + ADRASTEA_SI_REG_BASE_ADDRESS)
#define ADRASTEA_SI_CS_OFFSET (0x00000004 + _SI_REG_BASE_ADDRESS) #define ADRASTEA_SI_CS_OFFSET (0x00000004 + ADRASTEA_SI_REG_BASE_ADDRESS)
#define ADRASTEA_SI_CS_DONE_ERR_MASK 0x00000400 #define ADRASTEA_SI_CS_DONE_ERR_MASK 0x00000400
#define ADRASTEA_SI_CS_DONE_INT_MASK 0x00000200 #define ADRASTEA_SI_CS_DONE_INT_MASK 0x00000200
#define ADRASTEA_SI_CS_START_LSB 8 #define ADRASTEA_SI_CS_START_LSB 8
@@ -1521,10 +1521,10 @@
#define ADRASTEA_SOC_LF_TIMER_CONTROL0_ADDRESS 0xffffffff #define ADRASTEA_SOC_LF_TIMER_CONTROL0_ADDRESS 0xffffffff
#define ADRASTEA_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0xffffffff #define ADRASTEA_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0xffffffff
#define ADRASTEA_SOC_RESET_CONTROL_ADDRESS \ #define ADRASTEA_SOC_RESET_CONTROL_ADDRESS \
(0x00000000 + _RTC_SOC_REG_BASE_ADDRESS) (0x00000000 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS)
#define ADRASTEA_SOC_RESET_CONTROL_CE_RST_MASK 0x0100 #define ADRASTEA_SOC_RESET_CONTROL_CE_RST_MASK 0x0100
#define ADRASTEA_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 #define ADRASTEA_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
#define ADRASTEA_CORE_CTRL_ADDRESS (0x0000 + _SOC_CORE_REG_BASE_ADDRESS) #define ADRASTEA_CORE_CTRL_ADDRESS (0x0000 + ADRASTEA_SOC_CORE_REG_BASE_ADDRESS)
#define ADRASTEA_CORE_CTRL_CPU_INTR_MASK 0x00002000 #define ADRASTEA_CORE_CTRL_CPU_INTR_MASK 0x00002000
#define ADRASTEA_LOCAL_SCRATCH_OFFSET 0x00000018 #define ADRASTEA_LOCAL_SCRATCH_OFFSET 0x00000018
#define ADRASTEA_CLOCK_GPIO_OFFSET 0xffffffff #define ADRASTEA_CLOCK_GPIO_OFFSET 0xffffffff
@@ -1629,8 +1629,8 @@
#define ADRASTEA_FW_INDICATOR_ADDRESS \ #define ADRASTEA_FW_INDICATOR_ADDRESS \
(ADRASTEA_WIFICMN_BASE_ADDRESS + ADRASTEA_SCRATCH_3_ADDRESS) (ADRASTEA_WIFICMN_BASE_ADDRESS + ADRASTEA_SCRATCH_3_ADDRESS)
#define ADRASTEA_SYSTEM_SLEEP_OFFSET ADRASTEA_SOC_SYSTEM_SLEEP_OFFSET #define ADRASTEA_SYSTEM_SLEEP_OFFSET ADRASTEA_SOC_SYSTEM_SLEEP_OFFSET
#define ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET (0x002c + _WIFI_RTC_REG_BASE_ADDRESS) #define ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET (0x002c + ADRASTEA_WIFI_RTC_REG_BASE_ADDRESS)
#define ADRASTEA_WLAN_RESET_CONTROL_OFFSET (0x0000 + _WIFI_RTC_REG_BASE_ADDRESS) #define ADRASTEA_WLAN_RESET_CONTROL_OFFSET (0x0000 + ADRASTEA_WIFI_RTC_REG_BASE_ADDRESS)
#define ADRASTEA_CLOCK_CONTROL_OFFSET ADRASTEA_SOC_CLOCK_CONTROL_OFFSET #define ADRASTEA_CLOCK_CONTROL_OFFSET ADRASTEA_SOC_CLOCK_CONTROL_OFFSET
#define ADRASTEA_CLOCK_CONTROL_SI0_CLK_MASK \ #define ADRASTEA_CLOCK_CONTROL_SI0_CLK_MASK \
ADRASTEA_SOC_CLOCK_CONTROL_SI0_CLK_MASK ADRASTEA_SOC_CLOCK_CONTROL_SI0_CLK_MASK
@@ -1643,7 +1643,7 @@
#define ADRASTEA_GPIO_PIN0_CONFIG_MASK ADRASTEA_WLAN_GPIO_PIN0_CONFIG_MASK #define ADRASTEA_GPIO_PIN0_CONFIG_MASK ADRASTEA_WLAN_GPIO_PIN0_CONFIG_MASK
#define ADRASTEA_GPIO_PIN1_CONFIG_MASK ADRASTEA_WLAN_GPIO_PIN1_CONFIG_MASK #define ADRASTEA_GPIO_PIN1_CONFIG_MASK ADRASTEA_WLAN_GPIO_PIN1_CONFIG_MASK
#define ADRASTEA_SI_BASE_ADDRESS 0x00000000 #define ADRASTEA_SI_BASE_ADDRESS 0x00000000
#define ADRASTEA_CPU_CLOCK_OFFSET (0x20 + _RTC_SOC_REG_BASE_ADDRESS) #define ADRASTEA_CPU_CLOCK_OFFSET (0x20 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS)
#define ADRASTEA_LPO_CAL_OFFSET ADRASTEA_SOC_LPO_CAL_OFFSET #define ADRASTEA_LPO_CAL_OFFSET ADRASTEA_SOC_LPO_CAL_OFFSET
#define ADRASTEA_GPIO_PIN10_OFFSET ADRASTEA_WLAN_GPIO_PIN10_ADDRESS #define ADRASTEA_GPIO_PIN10_OFFSET ADRASTEA_WLAN_GPIO_PIN10_ADDRESS
#define ADRASTEA_GPIO_PIN11_OFFSET ADRASTEA_WLAN_GPIO_PIN11_ADDRESS #define ADRASTEA_GPIO_PIN11_OFFSET ADRASTEA_WLAN_GPIO_PIN11_ADDRESS

5
hif/src/ce/ce_api.h
View File

@@ -296,11 +296,6 @@ unsigned int ce_recv_entries_done(struct CE_handle *copyeng);
/* Data is byte-swapped */ /* Data is byte-swapped */
#define CE_RECV_FLAG_SWAPPED 1 #define CE_RECV_FLAG_SWAPPED 1
void ce_enable_msi(struct hif_softc *scn,
unsigned int CE_id,
uint32_t msi_addr_lo,
uint32_t msi_addr_hi,
uint32_t msi_data);
/* /*
* Supply data for the next completed unprocessed receive descriptor. * Supply data for the next completed unprocessed receive descriptor.
* *

13
hif/src/ce/ce_main.c
View File

@@ -563,8 +563,9 @@ struct CE_handle *ce_init(struct hif_softc *scn,
dma_addr = src_ring->base_addr_CE_space; dma_addr = src_ring->base_addr_CE_space;
CE_SRC_RING_BASE_ADDR_SET(scn, ctrl_addr, CE_SRC_RING_BASE_ADDR_SET(scn, ctrl_addr,
(uint32_t)(dma_addr & 0xFFFFFFFF)); (uint32_t)(dma_addr & 0xFFFFFFFF));
#ifdef WLAN_ENABLE_QCA6180
{ /* if SR_BA_ADDRESS_HIGH register exists */
if (SR_BA_ADDRESS_HIGH) {
uint32_t tmp; uint32_t tmp;
tmp = CE_SRC_RING_BASE_ADDR_HIGH_GET( tmp = CE_SRC_RING_BASE_ADDR_HIGH_GET(
scn, ctrl_addr); scn, ctrl_addr);
@@ -573,7 +574,6 @@ struct CE_handle *ce_init(struct hif_softc *scn,
CE_SRC_RING_BASE_ADDR_HIGH_SET(scn, CE_SRC_RING_BASE_ADDR_HIGH_SET(scn,
ctrl_addr, (uint32_t)dma_addr); ctrl_addr, (uint32_t)dma_addr);
} }
#endif
CE_SRC_RING_SZ_SET(scn, ctrl_addr, nentries); CE_SRC_RING_SZ_SET(scn, ctrl_addr, nentries);
CE_SRC_RING_DMAX_SET(scn, ctrl_addr, attr->src_sz_max); CE_SRC_RING_DMAX_SET(scn, ctrl_addr, attr->src_sz_max);
#ifdef BIG_ENDIAN_HOST #ifdef BIG_ENDIAN_HOST
@@ -696,8 +696,9 @@ struct CE_handle *ce_init(struct hif_softc *scn,
dma_addr = dest_ring->base_addr_CE_space; dma_addr = dest_ring->base_addr_CE_space;
CE_DEST_RING_BASE_ADDR_SET(scn, ctrl_addr, CE_DEST_RING_BASE_ADDR_SET(scn, ctrl_addr,
(uint32_t)(dma_addr & 0xFFFFFFFF)); (uint32_t)(dma_addr & 0xFFFFFFFF));
#ifdef WLAN_ENABLE_QCA6180
{ /* if DR_BA_ADDRESS_HIGH exists */
if (DR_BA_ADDRESS_HIGH) {
uint32_t tmp; uint32_t tmp;
tmp = CE_DEST_RING_BASE_ADDR_HIGH_GET(scn, tmp = CE_DEST_RING_BASE_ADDR_HIGH_GET(scn,
ctrl_addr); ctrl_addr);
@@ -706,7 +707,7 @@ struct CE_handle *ce_init(struct hif_softc *scn,
CE_DEST_RING_BASE_ADDR_HIGH_SET(scn, CE_DEST_RING_BASE_ADDR_HIGH_SET(scn,
ctrl_addr, (uint32_t)dma_addr); ctrl_addr, (uint32_t)dma_addr);
} }
#endif
CE_DEST_RING_SZ_SET(scn, ctrl_addr, nentries); CE_DEST_RING_SZ_SET(scn, ctrl_addr, nentries);
#ifdef BIG_ENDIAN_HOST #ifdef BIG_ENDIAN_HOST
/* Enable Dest ring byte swap for big endian host */ /* Enable Dest ring byte swap for big endian host */

36
hif/src/ce/ce_service.c
View File

@@ -1993,42 +1993,6 @@ bool ce_check_rx_pending(struct CE_state *CE_state)
return false; return false;
} }
/**
* ce_enable_msi(): write the msi configuration to the target
* @scn: hif context
* @CE_id: which copy engine will be configured for msi interupts
* @msi_addr_lo: Hardware will write to this address to generate an interrupt
* @msi_addr_hi: Hardware will write to this address to generate an interrupt
* @msi_data: Hardware will write this data to generate an interrupt
*
* should be done in the initialization sequence so no locking would be needed
*/
void ce_enable_msi(struct hif_softc *scn, unsigned int CE_id,
uint32_t msi_addr_lo, uint32_t msi_addr_hi,
uint32_t msi_data)
{
#ifdef WLAN_ENABLE_QCA6180
struct CE_state *CE_state;
A_target_id_t targid;
u_int32_t ctrl_addr;
uint32_t tmp;
CE_state = scn->ce_id_to_state[CE_id];
if (!CE_state) {
HIF_ERROR("%s: error - CE_state = NULL", __func__);
return;
}
targid = TARGID(sc);
ctrl_addr = CE_state->ctrl_addr;
CE_MSI_ADDR_LOW_SET(scn, ctrl_addr, msi_addr_lo);
CE_MSI_ADDR_HIGH_SET(scn, ctrl_addr, msi_addr_hi);
CE_MSI_DATA_SET(scn, ctrl_addr, msi_data);
tmp = CE_CTRL_REGISTER1_GET(scn, ctrl_addr);
tmp |= (1 << CE_MSI_ENABLE_BIT);
CE_CTRL_REGISTER1_SET(scn, ctrl_addr, tmp);
#endif
}
#ifdef IPA_OFFLOAD #ifdef IPA_OFFLOAD
/** /**
* ce_ipa_get_resource() - get uc resource on copyengine * ce_ipa_get_resource() - get uc resource on copyengine

9
hif/src/hif_main.c
View File

@@ -289,8 +289,6 @@ uint32_t hif_hia_item_address(uint32_t target_type, uint32_t item_offset)
case TARGET_TYPE_AR6320: case TARGET_TYPE_AR6320:
case TARGET_TYPE_AR6320V2: case TARGET_TYPE_AR6320V2:
return AR6320_HOST_INTEREST_ADDRESS + item_offset; return AR6320_HOST_INTEREST_ADDRESS + item_offset;
case TARGET_TYPE_QCA6180:
return QCA6180_HOST_INTEREST_ADDRESS + item_offset;
case TARGET_TYPE_ADRASTEA: case TARGET_TYPE_ADRASTEA:
/* ADRASTEA doesn't have a host interest address */ /* ADRASTEA doesn't have a host interest address */
ASSERT(0); ASSERT(0);
@@ -687,19 +685,12 @@ int hif_get_device_type(uint32_t device_id,
int ret = 0; int ret = 0;
switch (device_id) { switch (device_id) {
#ifdef QCA_WIFI_3_0_ADRASTEA
case ADRASTEA_DEVICE_ID: case ADRASTEA_DEVICE_ID:
case ADRASTEA_DEVICE_ID_P2_E12: case ADRASTEA_DEVICE_ID_P2_E12:
*hif_type = HIF_TYPE_ADRASTEA; *hif_type = HIF_TYPE_ADRASTEA;
*target_type = TARGET_TYPE_ADRASTEA; *target_type = TARGET_TYPE_ADRASTEA;
break; break;
#else
case QCA6180_DEVICE_ID:
*hif_type = HIF_TYPE_QCA6180;
*target_type = TARGET_TYPE_QCA6180;
break;
#endif
case AR9888_DEVICE_ID: case AR9888_DEVICE_ID:
*hif_type = HIF_TYPE_AR9888; *hif_type = HIF_TYPE_AR9888;

5
hif/src/hif_main.h
View File

@@ -93,11 +93,6 @@
#define AR6320_FW_3_2 (0x32) #define AR6320_FW_3_2 (0x32)
#define ADRASTEA_DEVICE_ID (0xabcd) #define ADRASTEA_DEVICE_ID (0xabcd)
#define ADRASTEA_DEVICE_ID_P2_E12 (0x7021) #define ADRASTEA_DEVICE_ID_P2_E12 (0x7021)
#if (defined(QVIT))
#define QCA6180_DEVICE_ID (0xabcd)
#else
#define QCA6180_DEVICE_ID (0x041)
#endif
#define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn) #define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn)
#define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn) #define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn)

1008
hif/src/qca6180def.h
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File diff suppressed because it is too large Load Diff

9
hif/src/regtable.c
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@@ -32,7 +32,6 @@
#include "ar9888def.h" #include "ar9888def.h"
#include "ar6320def.h" #include "ar6320def.h"
#include "ar6320v2def.h" #include "ar6320v2def.h"
#include "qca6180def.h"
#include "ol_if_athvar.h" #include "ol_if_athvar.h"
#include "hif_main.h" #include "hif_main.h"
#include "adrastea_reg_def.h" #include "adrastea_reg_def.h"
@@ -52,10 +51,6 @@ void target_register_tbl_attach(struct hif_softc *scn, u32 target_type)
scn->targetdef = &ar6320v2_targetdef; scn->targetdef = &ar6320v2_targetdef;
scn->target_ce_def = &ar6320v2_ce_targetdef; scn->target_ce_def = &ar6320v2_ce_targetdef;
break; break;
case TARGET_TYPE_QCA6180:
scn->targetdef = &qca6180_targetdef;
scn->target_ce_def = &qca6180_ce_targetdef;
break;
case TARGET_TYPE_ADRASTEA: case TARGET_TYPE_ADRASTEA:
scn->targetdef = &adrastea_targetdef; scn->targetdef = &adrastea_targetdef;
scn->target_ce_def = &adrastea_ce_targetdef; scn->target_ce_def = &adrastea_ce_targetdef;
@@ -77,10 +72,6 @@ void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type)
case HIF_TYPE_AR6320V2: case HIF_TYPE_AR6320V2:
scn->hostdef = &ar6320v2_hostdef; scn->hostdef = &ar6320v2_hostdef;
break; break;
case HIF_TYPE_QCA6180:
scn->hostdef = &qca6180_hostdef;
scn->host_shadow_regs = &qca6180_host_shadow_regs;
break;
case HIF_TYPE_ADRASTEA: case HIF_TYPE_ADRASTEA:
scn->hostdef = &adrastea_hostdef; scn->hostdef = &adrastea_hostdef;
scn->host_shadow_regs = &adrastea_host_shadow_regs; scn->host_shadow_regs = &adrastea_host_shadow_regs;