qcacmn: Remove support for QCA6180

This is deprecated emulation hardware.

Change-Id: Ibafc2e55a26bcac28e88a325689a419e058997b5
CRs-Fixed: 1003804

hif/inc/hif.h

@@ -54,7 +54,6 @@ typedef void __iomem *A_target_id_t;
 #define HIF_TYPE_AR6320V2 8
 /* For attaching Peregrine 2.0 board host_reg_tbl only */
 #define HIF_TYPE_AR9888V2 8
-#define HIF_TYPE_QCA6180  9
 #define HIF_TYPE_ADRASTEA 10
 
 #define TARGET_TYPE_UNKNOWN   0
@@ -76,8 +75,6 @@ typedef void __iomem *A_target_id_t;
 #define TARGET_TYPE_AR6320V3    13
 /* For Tufello1.0 target_reg_tbl ID*/
 #define TARGET_TYPE_QCA9377V1   14
-/* For QCA6180 target */
-#define TARGET_TYPE_QCA6180     15
 /* For Adrastea target */
 #define TARGET_TYPE_ADRASTEA     16
 

hif/src/adrastea_reg_def.h

@@ -1261,28 +1261,28 @@
 #define ADRASTEA_TARG_DRAM_START                        0x00400000
 #define ADRASTEA_SOC_SYSTEM_SLEEP_OFFSET                0x000000c0
 #define ADRASTEA_SOC_RESET_CONTROL_OFFSET \
-	(0x00000000 + _RTC_SOC_REG_BASE_ADDRESS)
+	(0x00000000 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS)
 #define ADRASTEA_SOC_CLOCK_CONTROL_OFFSET \
-	(0x00000028 + _RTC_SOC_REG_BASE_ADDRESS)
+	(0x00000028 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS)
 #define ADRASTEA_SOC_CLOCK_CONTROL_SI0_CLK_MASK         0x00000001
 #define ADRASTEA_SOC_RESET_CONTROL_SI0_RST_MASK         0x00000001
 #define ADRASTEA_WLAN_GPIO_PIN0_ADDRESS \
-	(0x50 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
+	(0x50 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
 #define ADRASTEA_WLAN_GPIO_PIN1_ADDRESS \
-	(0x54 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
+	(0x54 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
 #define ADRASTEA_WLAN_GPIO_PIN0_CONFIG_MASK             0x00007800
 #define ADRASTEA_WLAN_GPIO_PIN1_CONFIG_MASK             0x00007800
 #define ADRASTEA_SOC_CPU_CLOCK_OFFSET                   0x00000020
 #define ADRASTEA_SOC_LPO_CAL_OFFSET \
-	(0xe0 + _RTC_SOC_REG_BASE_ADDRESS)
+	(0xe0 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS)
 #define ADRASTEA_WLAN_GPIO_PIN10_ADDRESS \
-	(0x78 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
+	(0x78 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
 #define ADRASTEA_WLAN_GPIO_PIN11_ADDRESS \
-	(0x7c + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
+	(0x7c + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
 #define ADRASTEA_WLAN_GPIO_PIN12_ADDRESS \
-	(0x80 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
+	(0x80 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
 #define ADRASTEA_WLAN_GPIO_PIN13_ADDRESS \
-	(0x84 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
+	(0x84 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
 #define ADRASTEA_SOC_CPU_CLOCK_STANDARD_LSB             0
 #define ADRASTEA_SOC_CPU_CLOCK_STANDARD_MASK            0x00000003
 #define ADRASTEA_SOC_LPO_CAL_ENABLE_LSB                 20
@@ -1304,12 +1304,12 @@
 #define ADRASTEA_SI_CONFIG_INACTIVE_DATA_MASK           0x00000020
 #define ADRASTEA_SI_CONFIG_DIVIDER_LSB                  0
 #define ADRASTEA_SI_CONFIG_DIVIDER_MASK                 0x0000000f
-#define ADRASTEA_SI_CONFIG_OFFSET    (0x00000000 + _SI_REG_BASE_ADDRESS)
-#define ADRASTEA_SI_TX_DATA0_OFFSET  (0x00000008 + _SI_REG_BASE_ADDRESS)
-#define ADRASTEA_SI_TX_DATA1_OFFSET  (0x0000000c + _SI_REG_BASE_ADDRESS)
-#define ADRASTEA_SI_RX_DATA0_OFFSET  (0x00000010 + _SI_REG_BASE_ADDRESS)
-#define ADRASTEA_SI_RX_DATA1_OFFSET  (0x00000014 + _SI_REG_BASE_ADDRESS)
-#define ADRASTEA_SI_CS_OFFSET        (0x00000004 + _SI_REG_BASE_ADDRESS)
+#define ADRASTEA_SI_CONFIG_OFFSET    (0x00000000 + ADRASTEA_SI_REG_BASE_ADDRESS)
+#define ADRASTEA_SI_TX_DATA0_OFFSET  (0x00000008 + ADRASTEA_SI_REG_BASE_ADDRESS)
+#define ADRASTEA_SI_TX_DATA1_OFFSET  (0x0000000c + ADRASTEA_SI_REG_BASE_ADDRESS)
+#define ADRASTEA_SI_RX_DATA0_OFFSET  (0x00000010 + ADRASTEA_SI_REG_BASE_ADDRESS)
+#define ADRASTEA_SI_RX_DATA1_OFFSET  (0x00000014 + ADRASTEA_SI_REG_BASE_ADDRESS)
+#define ADRASTEA_SI_CS_OFFSET        (0x00000004 + ADRASTEA_SI_REG_BASE_ADDRESS)
 #define ADRASTEA_SI_CS_DONE_ERR_MASK                    0x00000400
 #define ADRASTEA_SI_CS_DONE_INT_MASK                    0x00000200
 #define ADRASTEA_SI_CS_START_LSB                        8
@@ -1521,10 +1521,10 @@
 #define ADRASTEA_SOC_LF_TIMER_CONTROL0_ADDRESS               0xffffffff
 #define ADRASTEA_SOC_LF_TIMER_CONTROL0_ENABLE_MASK           0xffffffff
 #define ADRASTEA_SOC_RESET_CONTROL_ADDRESS \
-	(0x00000000 + _RTC_SOC_REG_BASE_ADDRESS)
+	(0x00000000 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS)
 #define ADRASTEA_SOC_RESET_CONTROL_CE_RST_MASK            0x0100
 #define ADRASTEA_SOC_RESET_CONTROL_CPU_WARM_RST_MASK      0x00000040
-#define ADRASTEA_CORE_CTRL_ADDRESS        (0x0000 + _SOC_CORE_REG_BASE_ADDRESS)
+#define ADRASTEA_CORE_CTRL_ADDRESS        (0x0000 + ADRASTEA_SOC_CORE_REG_BASE_ADDRESS)
 #define ADRASTEA_CORE_CTRL_CPU_INTR_MASK                  0x00002000
 #define ADRASTEA_LOCAL_SCRATCH_OFFSET                     0x00000018
 #define ADRASTEA_CLOCK_GPIO_OFFSET                        0xffffffff
@@ -1629,8 +1629,8 @@
 #define ADRASTEA_FW_INDICATOR_ADDRESS \
 	(ADRASTEA_WIFICMN_BASE_ADDRESS + ADRASTEA_SCRATCH_3_ADDRESS)
 #define ADRASTEA_SYSTEM_SLEEP_OFFSET       ADRASTEA_SOC_SYSTEM_SLEEP_OFFSET
-#define ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET  (0x002c + _WIFI_RTC_REG_BASE_ADDRESS)
-#define ADRASTEA_WLAN_RESET_CONTROL_OFFSET (0x0000 + _WIFI_RTC_REG_BASE_ADDRESS)
+#define ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET  (0x002c + ADRASTEA_WIFI_RTC_REG_BASE_ADDRESS)
+#define ADRASTEA_WLAN_RESET_CONTROL_OFFSET (0x0000 + ADRASTEA_WIFI_RTC_REG_BASE_ADDRESS)
 #define ADRASTEA_CLOCK_CONTROL_OFFSET      ADRASTEA_SOC_CLOCK_CONTROL_OFFSET
 #define ADRASTEA_CLOCK_CONTROL_SI0_CLK_MASK \
 	ADRASTEA_SOC_CLOCK_CONTROL_SI0_CLK_MASK
@@ -1643,7 +1643,7 @@
 #define ADRASTEA_GPIO_PIN0_CONFIG_MASK     ADRASTEA_WLAN_GPIO_PIN0_CONFIG_MASK
 #define ADRASTEA_GPIO_PIN1_CONFIG_MASK     ADRASTEA_WLAN_GPIO_PIN1_CONFIG_MASK
 #define ADRASTEA_SI_BASE_ADDRESS           0x00000000
-#define ADRASTEA_CPU_CLOCK_OFFSET          (0x20 + _RTC_SOC_REG_BASE_ADDRESS)
+#define ADRASTEA_CPU_CLOCK_OFFSET          (0x20 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS)
 #define ADRASTEA_LPO_CAL_OFFSET            ADRASTEA_SOC_LPO_CAL_OFFSET
 #define ADRASTEA_GPIO_PIN10_OFFSET         ADRASTEA_WLAN_GPIO_PIN10_ADDRESS
 #define ADRASTEA_GPIO_PIN11_OFFSET         ADRASTEA_WLAN_GPIO_PIN11_ADDRESS

hif/src/ce/ce_api.h

@@ -296,11 +296,6 @@ unsigned int ce_recv_entries_done(struct CE_handle *copyeng);
 /* Data is byte-swapped */
 #define CE_RECV_FLAG_SWAPPED            1
 
-void ce_enable_msi(struct hif_softc *scn,
-		   unsigned int CE_id,
-		   uint32_t msi_addr_lo,
-		   uint32_t msi_addr_hi,
-		   uint32_t msi_data);
 /*
  * Supply data for the next completed unprocessed receive descriptor.
  *

hif/src/ce/ce_main.c

@@ -563,8 +563,9 @@ struct CE_handle *ce_init(struct hif_softc *scn,
 			dma_addr = src_ring->base_addr_CE_space;
 			CE_SRC_RING_BASE_ADDR_SET(scn, ctrl_addr,
 				 (uint32_t)(dma_addr & 0xFFFFFFFF));
-#ifdef WLAN_ENABLE_QCA6180
-			{
+
+			/* if SR_BA_ADDRESS_HIGH register exists */
+			if (SR_BA_ADDRESS_HIGH) {
 				uint32_t tmp;
 				tmp = CE_SRC_RING_BASE_ADDR_HIGH_GET(
 				   scn, ctrl_addr);
@@ -573,7 +574,6 @@ struct CE_handle *ce_init(struct hif_softc *scn,
 				CE_SRC_RING_BASE_ADDR_HIGH_SET(scn,
 					 ctrl_addr, (uint32_t)dma_addr);
 			}
-#endif
 			CE_SRC_RING_SZ_SET(scn, ctrl_addr, nentries);
 			CE_SRC_RING_DMAX_SET(scn, ctrl_addr, attr->src_sz_max);
 #ifdef BIG_ENDIAN_HOST
@@ -696,8 +696,9 @@ struct CE_handle *ce_init(struct hif_softc *scn,
 			dma_addr = dest_ring->base_addr_CE_space;
 			CE_DEST_RING_BASE_ADDR_SET(scn, ctrl_addr,
 				 (uint32_t)(dma_addr & 0xFFFFFFFF));
-#ifdef WLAN_ENABLE_QCA6180
-			{
+
+			/* if DR_BA_ADDRESS_HIGH exists */
+			if (DR_BA_ADDRESS_HIGH) {
 				uint32_t tmp;
 				tmp = CE_DEST_RING_BASE_ADDR_HIGH_GET(scn,
 						ctrl_addr);
@@ -706,7 +707,7 @@ struct CE_handle *ce_init(struct hif_softc *scn,
 				CE_DEST_RING_BASE_ADDR_HIGH_SET(scn,
 					ctrl_addr, (uint32_t)dma_addr);
 			}
-#endif
+
 			CE_DEST_RING_SZ_SET(scn, ctrl_addr, nentries);
 #ifdef BIG_ENDIAN_HOST
 			/* Enable Dest ring byte swap for big endian host */

hif/src/ce/ce_service.c

@@ -1993,42 +1993,6 @@ bool ce_check_rx_pending(struct CE_state *CE_state)
 		return false;
 }
 
-/**
- * ce_enable_msi(): write the msi configuration to the target
- * @scn: hif context
- * @CE_id: which copy engine will be configured for msi interupts
- * @msi_addr_lo: Hardware will write to this address to generate an interrupt
- * @msi_addr_hi: Hardware will write to this address to generate an interrupt
- * @msi_data: Hardware will write this data to generate an interrupt
- *
- * should be done in the initialization sequence so no locking would be needed
- */
-void ce_enable_msi(struct hif_softc *scn, unsigned int CE_id,
-				   uint32_t msi_addr_lo, uint32_t msi_addr_hi,
-				   uint32_t msi_data)
-{
-#ifdef WLAN_ENABLE_QCA6180
-	struct CE_state *CE_state;
-	A_target_id_t targid;
-	u_int32_t ctrl_addr;
-	uint32_t tmp;
-
-	CE_state = scn->ce_id_to_state[CE_id];
-	if (!CE_state) {
-		HIF_ERROR("%s: error - CE_state = NULL", __func__);
-		return;
-	}
-	targid = TARGID(sc);
-	ctrl_addr = CE_state->ctrl_addr;
-	CE_MSI_ADDR_LOW_SET(scn, ctrl_addr, msi_addr_lo);
-	CE_MSI_ADDR_HIGH_SET(scn, ctrl_addr, msi_addr_hi);
-	CE_MSI_DATA_SET(scn, ctrl_addr, msi_data);
-	tmp = CE_CTRL_REGISTER1_GET(scn, ctrl_addr);
-	tmp |= (1 << CE_MSI_ENABLE_BIT);
-	CE_CTRL_REGISTER1_SET(scn, ctrl_addr, tmp);
-#endif
-}
-
 #ifdef IPA_OFFLOAD
 /**
  * ce_ipa_get_resource() - get uc resource on copyengine

hif/src/hif_main.c

@@ -289,8 +289,6 @@ uint32_t hif_hia_item_address(uint32_t target_type, uint32_t item_offset)
 	case TARGET_TYPE_AR6320:
 	case TARGET_TYPE_AR6320V2:
 		return AR6320_HOST_INTEREST_ADDRESS + item_offset;
-	case TARGET_TYPE_QCA6180:
-		return QCA6180_HOST_INTEREST_ADDRESS + item_offset;
 	case TARGET_TYPE_ADRASTEA:
 		/* ADRASTEA doesn't have a host interest address */
 		ASSERT(0);
@@ -687,19 +685,12 @@ int hif_get_device_type(uint32_t device_id,
 	int ret = 0;
 
 	switch (device_id) {
-#ifdef QCA_WIFI_3_0_ADRASTEA
 	case ADRASTEA_DEVICE_ID:
 	case ADRASTEA_DEVICE_ID_P2_E12:
 
 		*hif_type = HIF_TYPE_ADRASTEA;
 		*target_type = TARGET_TYPE_ADRASTEA;
 		break;
-#else
-	case QCA6180_DEVICE_ID:
-		*hif_type = HIF_TYPE_QCA6180;
-		*target_type = TARGET_TYPE_QCA6180;
-		break;
-#endif
 
 	case AR9888_DEVICE_ID:
 		*hif_type = HIF_TYPE_AR9888;

hif/src/hif_main.h

@@ -93,11 +93,6 @@
 #define AR6320_FW_3_2  (0x32)
 #define ADRASTEA_DEVICE_ID (0xabcd)
 #define ADRASTEA_DEVICE_ID_P2_E12 (0x7021)
-#if (defined(QVIT))
-#define QCA6180_DEVICE_ID (0xabcd)
-#else
-#define QCA6180_DEVICE_ID (0x041)
-#endif
 
 #define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn)
 #define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn)

hif/src/qca6180def.h

@@ -1,1008 +0,0 @@
-/*
- * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef _QCA6180DEF_H_
-#define _QCA6180DEF_H_
-
-#define MISSING                                        0
-#define _PCIE_LOCAL_REG_BASE_ADDRESS                   0x1E8000
-#define _WIFI_RTC_REG_BASE_ADDRESS                     0x45000
-#define _RTC_SOC_REG_BASE_ADDRESS                      0x113000
-#define _GPIO_ATHR_WLAN_REG_BASE_ADDRESS               0x85000
-#define _SI_REG_BASE_ADDRESS                           0x84000
-#define _SOC_CORE_REG_BASE_ADDRESS                     0x113000
-#define _CE_REG_CSR_BASE_ADDRESS                       0x240000
-#define _CE0_CE_REG_CSR_BASE_ADDRESS                   0
-#define _CE_WRAPPER_REG_CSR_BASE_ADDRESS               0xC000
-#define _MAC_WIFICMN_REG_BASE_ADDRESS                  MISSING
-
-/* Base Addresses */
-#define QCA6180_RTC_SOC_BASE_ADDRESS                   0x00000000
-#define QCA6180_RTC_WMAC_BASE_ADDRESS                  0x00000000
-#define QCA6180_MAC_COEX_BASE_ADDRESS                  0x0000f000
-#define QCA6180_BT_COEX_BASE_ADDRESS                   0x00002000
-#define QCA6180_SOC_PCIE_BASE_ADDRESS                  0x00130000
-#define QCA6180_SOC_CORE_BASE_ADDRESS                  0x00000000
-#define QCA6180_WLAN_UART_BASE_ADDRESS                 0x00111000
-#define QCA6180_WLAN_SI_BASE_ADDRESS                   0x00010000
-#define QCA6180_WLAN_GPIO_BASE_ADDRESS                 0x00000000
-#define QCA6180_WLAN_ANALOG_INTF_BASE_ADDRESS          0x00000000
-#define QCA6180_WLAN_MAC_BASE_ADDRESS                  0x00000000
-#define QCA6180_EFUSE_BASE_ADDRESS                     0x00024000
-#define QCA6180_FPGA_REG_BASE_ADDRESS                  0x00039000
-#define QCA6180_WLAN_UART2_BASE_ADDRESS                0x00054c00
-#define QCA6180_CE_WRAPPER_BASE_ADDRESS                0x24C000
-#define QCA6180_CE0_BASE_ADDRESS                       0x240000
-#define QCA6180_CE1_BASE_ADDRESS                       0x241000
-#define QCA6180_CE2_BASE_ADDRESS                       0x242000
-#define QCA6180_CE3_BASE_ADDRESS                       0x243000
-#define QCA6180_CE4_BASE_ADDRESS                       0x244000
-#define QCA6180_CE5_BASE_ADDRESS                       0x245000
-#define QCA6180_CE6_BASE_ADDRESS                       0x246000
-#define QCA6180_CE7_BASE_ADDRESS                       0x247000
-#define QCA6180_CE8_BASE_ADDRESS                       0x248000
-#define QCA6180_CE9_BASE_ADDRESS                       0x249000
-#define QCA6180_CE10_BASE_ADDRESS                      0x24A000
-#define QCA6180_CE11_BASE_ADDRESS                      0x24B000
-#define QCA6180_A_SOC_PCIE_SOC_PCIE_REG                0x130000
-#define QCA6180_DBI_BASE_ADDRESS                       0x0003c000
-#define QCA6180_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS     0x00007800
-#define QCA6180_WIFICMN_BASE_ADDRESS                   0x00000000
-#define QCA6180_BOARD_DATA_SZ                          MISSING
-#define QCA6180_BOARD_EXT_DATA_SZ                      MISSING
-#define QCA6180_A_SOC_PCIE_PCIE_BAR0_START \
-	(0x030 + QCA6180_A_SOC_PCIE_SOC_PCIE_REG)
-#define QCA6180_A_SOC_CORE_SCRATCH_0_ADDRESS           0x00114000
-#define QCA6180_A_SOC_CORE_SCRATCH_1_ADDRESS           0x00114004
-#define QCA6180_A_SOC_CORE_SCRATCH_2_ADDRESS           0x00114008
-#define QCA6180_A_SOC_CORE_SCRATCH_3_ADDRESS           0x0011400c
-#define QCA6180_A_SOC_CORE_SCRATCH_4_ADDRESS           0x00114010
-#define QCA6180_A_SOC_CORE_SCRATCH_5_ADDRESS           0x00114014
-#define QCA6180_A_SOC_CORE_SCRATCH_6_ADDRESS           0x00114018
-#define QCA6180_A_SOC_CORE_SCRATCH_7_ADDRESS           0x0011401c
-#define QCA6180_A_SOC_CORE_SPARE_0_REGISTER            0x00113180
-#define QCA6180_PCIE_INTR_FIRMWARE_ROUTE_MASK          0xff
-#define QCA6180_SCRATCH_3_ADDRESS                      0x00113020
-#define QCA6180_TARG_DRAM_START                        0x00400000
-#define QCA6180_SOC_SYSTEM_SLEEP_OFFSET                0x000000c0
-#define QCA6180_SOC_RESET_CONTROL_OFFSET \
-	(0x00000000 + _RTC_SOC_REG_BASE_ADDRESS)
-#define QCA6180_SOC_CLOCK_CONTROL_OFFSET \
-	(0x00000028 + _RTC_SOC_REG_BASE_ADDRESS)
-#define QCA6180_SOC_CLOCK_CONTROL_SI0_CLK_MASK         0x00000001
-#define QCA6180_SOC_RESET_CONTROL_SI0_RST_MASK         0x00000001
-#define QCA6180_WLAN_GPIO_PIN0_ADDRESS \
-	(0x50 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define QCA6180_WLAN_GPIO_PIN1_ADDRESS \
-	(0x54 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define QCA6180_WLAN_GPIO_PIN0_CONFIG_MASK             0x00007800
-#define QCA6180_WLAN_GPIO_PIN1_CONFIG_MASK             0x00007800
-#define QCA6180_SOC_CPU_CLOCK_OFFSET                   0x00000020
-#define QCA6180_SOC_LPO_CAL_OFFSET \
-	(0xe0 + _RTC_SOC_REG_BASE_ADDRESS)
-#define QCA6180_WLAN_GPIO_PIN10_ADDRESS \
-	(0x78 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define QCA6180_WLAN_GPIO_PIN11_ADDRESS \
-	(0x7c + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define QCA6180_WLAN_GPIO_PIN12_ADDRESS \
-	(0x80 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define QCA6180_WLAN_GPIO_PIN13_ADDRESS \
-	(0x84 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define QCA6180_SOC_CPU_CLOCK_STANDARD_LSB             0
-#define QCA6180_SOC_CPU_CLOCK_STANDARD_MASK            0x00000003
-#define QCA6180_SOC_LPO_CAL_ENABLE_LSB                 20
-#define QCA6180_SOC_LPO_CAL_ENABLE_MASK                0x00100000
-
-#define QCA6180_WLAN_SYSTEM_SLEEP_DISABLE_LSB          0
-#define QCA6180_WLAN_SYSTEM_SLEEP_DISABLE_MASK         0x00000001
-#define QCA6180_WLAN_RESET_CONTROL_COLD_RST_MASK       0x00000002
-#define QCA6180_WLAN_RESET_CONTROL_WARM_RST_MASK       0x00000001
-#define QCA6180_SI_CONFIG_BIDIR_OD_DATA_LSB            18
-#define QCA6180_SI_CONFIG_BIDIR_OD_DATA_MASK           0x00040000
-#define QCA6180_SI_CONFIG_I2C_LSB                      16
-#define QCA6180_SI_CONFIG_I2C_MASK                     0x00010000
-#define QCA6180_SI_CONFIG_POS_SAMPLE_LSB               7
-#define QCA6180_SI_CONFIG_POS_SAMPLE_MASK              0x00000080
-#define QCA6180_SI_CONFIG_INACTIVE_CLK_LSB             4
-#define QCA6180_SI_CONFIG_INACTIVE_CLK_MASK            0x00000010
-#define QCA6180_SI_CONFIG_INACTIVE_DATA_LSB            5
-#define QCA6180_SI_CONFIG_INACTIVE_DATA_MASK           0x00000020
-#define QCA6180_SI_CONFIG_DIVIDER_LSB                  0
-#define QCA6180_SI_CONFIG_DIVIDER_MASK                 0x0000000f
-#define QCA6180_SI_CONFIG_OFFSET    (0x00000000 + _SI_REG_BASE_ADDRESS)
-#define QCA6180_SI_TX_DATA0_OFFSET  (0x00000008 + _SI_REG_BASE_ADDRESS)
-#define QCA6180_SI_TX_DATA1_OFFSET  (0x0000000c + _SI_REG_BASE_ADDRESS)
-#define QCA6180_SI_RX_DATA0_OFFSET  (0x00000010 + _SI_REG_BASE_ADDRESS)
-#define QCA6180_SI_RX_DATA1_OFFSET  (0x00000014 + _SI_REG_BASE_ADDRESS)
-#define QCA6180_SI_CS_OFFSET        (0x00000004 + _SI_REG_BASE_ADDRESS)
-#define QCA6180_SI_CS_DONE_ERR_MASK                    0x00000400
-#define QCA6180_SI_CS_DONE_INT_MASK                    0x00000200
-#define QCA6180_SI_CS_START_LSB                        8
-#define QCA6180_SI_CS_START_MASK                       0x00000100
-#define QCA6180_SI_CS_RX_CNT_LSB                       4
-#define QCA6180_SI_CS_RX_CNT_MASK                      0x000000f0
-#define QCA6180_SI_CS_TX_CNT_LSB                       0
-#define QCA6180_SI_CS_TX_CNT_MASK                      0x0000000f
-#define QCA6180_CE_COUNT                               8
-#define QCA6180_SR_WR_INDEX_ADDRESS   (0x003C + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_DST_WATERMARK_ADDRESS (0x0050 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_RX_MSDU_END_4_FIRST_MSDU_LSB           14
-#define QCA6180_RX_MSDU_END_4_FIRST_MSDU_MASK          0x00004000
-#define QCA6180_RX_MPDU_START_0_SEQ_NUM_LSB            16
-#define QCA6180_RX_MPDU_START_0_SEQ_NUM_MASK           0x0fff0000
-#define QCA6180_RX_MPDU_START_2_PN_47_32_LSB           0
-#define QCA6180_RX_MPDU_START_2_PN_47_32_MASK          0x0000ffff
-#define QCA6180_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB    16
-#define QCA6180_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK   0xffff0000
-#define QCA6180_RX_MSDU_END_4_LAST_MSDU_LSB            15
-#define QCA6180_RX_MSDU_END_4_LAST_MSDU_MASK           0x00008000
-#define QCA6180_RX_ATTENTION_0_MCAST_BCAST_LSB         2
-#define QCA6180_RX_ATTENTION_0_MCAST_BCAST_MASK        0x00000004
-#define QCA6180_RX_ATTENTION_0_FRAGMENT_LSB            13
-#define QCA6180_RX_ATTENTION_0_FRAGMENT_MASK           0x00002000
-#define QCA6180_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK    0x08000000
-#define QCA6180_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB    16
-#define QCA6180_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK   0x00ff0000
-#define QCA6180_RX_MSDU_START_0_MSDU_LENGTH_LSB        0
-#define QCA6180_RX_MSDU_START_0_MSDU_LENGTH_MASK       0x00003fff
-
-#define QCA6180_RX_MSDU_START_2_DECAP_FORMAT_OFFSET    0x00000008
-#define QCA6180_RX_MSDU_START_2_DECAP_FORMAT_LSB       8
-#define QCA6180_RX_MSDU_START_2_DECAP_FORMAT_MASK      0x00000300
-#define QCA6180_RX_MPDU_START_0_ENCRYPTED_LSB          13
-#define QCA6180_RX_MPDU_START_0_ENCRYPTED_MASK         0x00002000
-#define QCA6180_RX_ATTENTION_0_MORE_DATA_MASK          0x00000400
-#define QCA6180_RX_ATTENTION_0_MSDU_DONE_MASK          0x80000000
-#define QCA6180_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK     0x00040000
-#define QCA6180_DST_WR_INDEX_ADDRESS  (0x0040 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_SRC_WATERMARK_ADDRESS (0x004c + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_SRC_WATERMARK_LOW_MASK                      0xffff0000
-#define QCA6180_SRC_WATERMARK_HIGH_MASK                     0x0000ffff
-#define QCA6180_DST_WATERMARK_LOW_MASK                      0xffff0000
-#define QCA6180_DST_WATERMARK_HIGH_MASK                     0x0000ffff
-#define QCA6180_CURRENT_SRRI_ADDRESS (0x0044 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_CURRENT_DRRI_ADDRESS (0x0048 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK        0x00000002
-#define QCA6180_HOST_IS_SRC_RING_LOW_WATERMARK_MASK         0x00000004
-#define QCA6180_HOST_IS_DST_RING_HIGH_WATERMARK_MASK        0x00000008
-#define QCA6180_HOST_IS_DST_RING_LOW_WATERMARK_MASK         0x00000010
-#define QCA6180_HOST_IS_ADDRESS (0x0030 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_MISC_IS_ADDRESS (0x0038 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_HOST_IS_COPY_COMPLETE_MASK                  0x00000001
-#define QCA6180_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS        0x0000
-#define QCA6180_CE_WRAPPER_INDEX_BASE_LOW                   0x0004
-#define QCA6180_CE_WRAPPER_INDEX_BASE_HIGH                  0x0008
-#define QCA6180_HOST_IE_ADDRESS (0x002C + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_HOST_IE_COPY_COMPLETE_MASK                  0x00000001
-#define QCA6180_SR_BA_ADDRESS      (0x0000 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_SR_BA_ADDRESS_HIGH (0x0004 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_SR_SIZE_ADDRESS    (0x0008 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_CE_CTRL1_ADDRESS   (0x0018 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_CE_CTRL1_DMAX_LENGTH_MASK                   0x0000ffff
-#define QCA6180_DR_BA_ADDRESS       (0x000C + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_DR_BA_ADDRESS_HIGH  (0x000C + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_DR_SIZE_ADDRESS     (0x0014 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_CE_CMD_REGISTER     (0x0020 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_CE_MSI_ADDRESS      (0x0058 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_CE_MSI_ADDRESS_HIGH (0x005C + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_CE_MSI_DATA         (0x0060 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_CE_MSI_ENABLE_BIT   16
-#define QCA6180_MISC_IE_ADDRESS     (0x0034 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_MISC_IS_AXI_ERR_MASK                        0x00000100
-#define QCA6180_MISC_IS_DST_ADDR_ERR_MASK                   0x00000200
-#define QCA6180_MISC_IS_SRC_LEN_ERR_MASK                    0x00000100
-#define QCA6180_MISC_IS_DST_MAX_LEN_VIO_MASK                0x00000080
-#define QCA6180_MISC_IS_DST_RING_OVERFLOW_MASK              0x00000040
-#define QCA6180_MISC_IS_SRC_RING_OVERFLOW_MASK              0x00000020
-#define QCA6180_WRAPPER_INTERRUPT_SUMMARY_ADDR              0x0024D000
-#define QCA6180_SRC_WATERMARK_LOW_LSB                       16
-#define QCA6180_SRC_WATERMARK_HIGH_LSB                      0
-#define QCA6180_DST_WATERMARK_LOW_LSB                       16
-#define QCA6180_DST_WATERMARK_HIGH_LSB                      0
-#define QCA6180_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK  0xfff000
-#define QCA6180_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB   12
-#define QCA6180_CE_CTRL1_DMAX_LENGTH_LSB                    0
-#define QCA6180_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK         0x00020000
-#define QCA6180_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK         0x00040000
-#define QCA6180_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB          17
-#define QCA6180_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB          18
-#define QCA6180_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK  0x0000004
-#define QCA6180_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB   2
-#define QCA6180_SOC_GLOBAL_RESET_ADDRESS \
-	(0x0008 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_RTC_STATE_ADDRESS \
-	(0x0000 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_RTC_STATE_COLD_RESET_MASK                   0x400
-
-#define QCA6180_PCIE_SOC_WAKE_RESET                         0x00000000
-#define QCA6180_PCIE_SOC_WAKE_ADDRESS (0x0004 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_PCIE_SOC_WAKE_V_MASK                        0x00000001
-
-#define QCA6180_RTC_STATE_V_MASK                            0x00000007
-#define QCA6180_RTC_STATE_V_LSB                             0
-#define QCA6180_RTC_STATE_V_ON                              5
-#define QCA6180_PCIE_LOCAL_BASE_ADDRESS                     0x0
-#define QCA6180_FW_IND_EVENT_PENDING                        1
-#define QCA6180_FW_IND_INITIALIZED                          2
-#define QCA6180_FW_IND_HELPER                               4
-
-#define QCA6180_PCIE_INTR_ENABLE_ADDRESS (0x000c + _SOC_CORE_REG_BASE_ADDRESS)
-#define QCA6180_PCIE_INTR_CLR_ADDRESS    (0x001c + _SOC_CORE_REG_BASE_ADDRESS)
-#define QCA6180_PCIE_INTR_FIRMWARE_MASK                     0x00100000
-#define QCA6180_PCIE_INTR_CE0_MASK                          0x00000100
-#define QCA6180_PCIE_INTR_CE_MASK_ALL                       0x0000ff00
-#define QCA6180_PCIE_INTR_CAUSE_ADDRESS  (0x0014 + _SOC_CORE_REG_BASE_ADDRESS)
-
-#define QCA6180_CPU_INTR_ADDRESS                            0xffffffff
-#define QCA6180_SOC_LF_TIMER_CONTROL0_ADDRESS               0xffffffff
-#define QCA6180_SOC_LF_TIMER_CONTROL0_ENABLE_MASK           0xffffffff
-#define QCA6180_SOC_RESET_CONTROL_ADDRESS \
-	(0x00000000 + _RTC_SOC_REG_BASE_ADDRESS)
-#define QCA6180_SOC_RESET_CONTROL_CE_RST_MASK            0x0100
-#define QCA6180_SOC_RESET_CONTROL_CPU_WARM_RST_MASK      0x00000040
-#define QCA6180_CORE_CTRL_ADDRESS        (0x0000 + _SOC_CORE_REG_BASE_ADDRESS)
-#define QCA6180_CORE_CTRL_CPU_INTR_MASK                  0x00002000
-#define QCA6180_LOCAL_SCRATCH_OFFSET                     0x00000018
-#define QCA6180_CLOCK_GPIO_OFFSET                        0xffffffff
-#define QCA6180_CLOCK_GPIO_BT_CLK_OUT_EN_LSB             0
-#define QCA6180_CLOCK_GPIO_BT_CLK_OUT_EN_MASK            0
-#define QCA6180_SOC_CHIP_ID_ADDRESS                      0x000000f0
-#define QCA6180_SOC_CHIP_ID_VERSION_MASK                 0xfffc0000
-#define QCA6180_SOC_CHIP_ID_VERSION_LSB                  18
-#define QCA6180_SOC_CHIP_ID_REVISION_MASK                0x00000f00
-#define QCA6180_SOC_CHIP_ID_REVISION_LSB                 8
-#define QCA6180_SOC_POWER_REG_OFFSET                     0x0000010c
-
-/* Copy Engine Debug */
-#define QCA6180_WLAN_DEBUG_INPUT_SEL_OFFSET              0x0000010c
-#define QCA6180_WLAN_DEBUG_INPUT_SEL_SRC_MSB             3
-#define QCA6180_WLAN_DEBUG_INPUT_SEL_SRC_LSB             0
-#define QCA6180_WLAN_DEBUG_INPUT_SEL_SRC_MASK            0x0000000f
-#define QCA6180_WLAN_DEBUG_CONTROL_OFFSET                0x00000108
-#define QCA6180_WLAN_DEBUG_CONTROL_ENABLE_MSB            0
-#define QCA6180_WLAN_DEBUG_CONTROL_ENABLE_LSB            0
-#define QCA6180_WLAN_DEBUG_CONTROL_ENABLE_MASK           0x00000001
-#define QCA6180_WLAN_DEBUG_OUT_OFFSET                    0x00000110
-#define QCA6180_WLAN_DEBUG_OUT_DATA_MSB                  19
-#define QCA6180_WLAN_DEBUG_OUT_DATA_LSB                  0
-#define QCA6180_WLAN_DEBUG_OUT_DATA_MASK                 0x000fffff
-#define QCA6180_AMBA_DEBUG_BUS_OFFSET                    0x0000011c
-#define QCA6180_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB        13
-#define QCA6180_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB        8
-#define QCA6180_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK       0x00003f00
-#define QCA6180_AMBA_DEBUG_BUS_SEL_MSB                   4
-#define QCA6180_AMBA_DEBUG_BUS_SEL_LSB                   0
-#define QCA6180_AMBA_DEBUG_BUS_SEL_MASK                  0x0000001f
-#define QCA6180_CE_WRAPPER_DEBUG_OFFSET                  0x0008
-#define QCA6180_CE_WRAPPER_DEBUG_SEL_MSB                 4
-#define QCA6180_CE_WRAPPER_DEBUG_SEL_LSB                 0
-#define QCA6180_CE_WRAPPER_DEBUG_SEL_MASK                0x0000001f
-#define QCA6180_CE_DEBUG_OFFSET                          0x0054
-#define QCA6180_CE_DEBUG_SEL_MSB                         5
-#define QCA6180_CE_DEBUG_SEL_LSB                         0
-#define QCA6180_CE_DEBUG_SEL_MASK                        0x0000003f
-/* End */
-
-/* PLL start */
-#define QCA6180_EFUSE_OFFSET                             0x0000032c
-#define QCA6180_EFUSE_XTAL_SEL_MSB                       10
-#define QCA6180_EFUSE_XTAL_SEL_LSB                       8
-#define QCA6180_EFUSE_XTAL_SEL_MASK                      0x00000700
-#define QCA6180_BB_PLL_CONFIG_OFFSET                     0x000002f4
-#define QCA6180_BB_PLL_CONFIG_OUTDIV_MSB                 20
-#define QCA6180_BB_PLL_CONFIG_OUTDIV_LSB                 18
-#define QCA6180_BB_PLL_CONFIG_OUTDIV_MASK                0x001c0000
-#define QCA6180_BB_PLL_CONFIG_FRAC_MSB                   17
-#define QCA6180_BB_PLL_CONFIG_FRAC_LSB                   0
-#define QCA6180_BB_PLL_CONFIG_FRAC_MASK                  0x0003ffff
-#define QCA6180_WLAN_PLL_SETTLE_TIME_MSB                 10
-#define QCA6180_WLAN_PLL_SETTLE_TIME_LSB                 0
-#define QCA6180_WLAN_PLL_SETTLE_TIME_MASK                0x000007ff
-#define QCA6180_WLAN_PLL_SETTLE_OFFSET                   0x0018
-#define QCA6180_WLAN_PLL_SETTLE_SW_MASK                  0x000007ff
-#define QCA6180_WLAN_PLL_SETTLE_RSTMASK                  0xffffffff
-#define QCA6180_WLAN_PLL_SETTLE_RESET                    0x00000400
-#define QCA6180_WLAN_PLL_CONTROL_NOPWD_MSB               18
-#define QCA6180_WLAN_PLL_CONTROL_NOPWD_LSB               18
-#define QCA6180_WLAN_PLL_CONTROL_NOPWD_MASK              0x00040000
-#define QCA6180_WLAN_PLL_CONTROL_BYPASS_MSB              16
-#define QCA6180_WLAN_PLL_CONTROL_BYPASS_LSB              16
-#define QCA6180_WLAN_PLL_CONTROL_BYPASS_MASK             0x00010000
-#define QCA6180_WLAN_PLL_CONTROL_BYPASS_RESET            0x1
-#define QCA6180_WLAN_PLL_CONTROL_CLK_SEL_MSB             15
-#define QCA6180_WLAN_PLL_CONTROL_CLK_SEL_LSB             14
-#define QCA6180_WLAN_PLL_CONTROL_CLK_SEL_MASK            0x0000c000
-#define QCA6180_WLAN_PLL_CONTROL_CLK_SEL_RESET           0x0
-#define QCA6180_WLAN_PLL_CONTROL_REFDIV_MSB              13
-#define QCA6180_WLAN_PLL_CONTROL_REFDIV_LSB              10
-#define QCA6180_WLAN_PLL_CONTROL_REFDIV_MASK             0x00003c00
-#define QCA6180_WLAN_PLL_CONTROL_REFDIV_RESET            0x0
-#define QCA6180_WLAN_PLL_CONTROL_DIV_MSB                 9
-#define QCA6180_WLAN_PLL_CONTROL_DIV_LSB                 0
-#define QCA6180_WLAN_PLL_CONTROL_DIV_MASK                0x000003ff
-#define QCA6180_WLAN_PLL_CONTROL_DIV_RESET               0x11
-#define QCA6180_WLAN_PLL_CONTROL_OFFSET                  0x0014
-#define QCA6180_WLAN_PLL_CONTROL_SW_MASK                 0x001fffff
-#define QCA6180_WLAN_PLL_CONTROL_RSTMASK                 0xffffffff
-#define QCA6180_WLAN_PLL_CONTROL_RESET                   0x00010011
-#define QCA6180_SOC_CORE_CLK_CTRL_OFFSET                 0x00000114
-#define QCA6180_SOC_CORE_CLK_CTRL_DIV_MSB                2
-#define QCA6180_SOC_CORE_CLK_CTRL_DIV_LSB                0
-#define QCA6180_SOC_CORE_CLK_CTRL_DIV_MASK               0x00000007
-#define QCA6180_RTC_SYNC_STATUS_PLL_CHANGING_MSB         5
-#define QCA6180_RTC_SYNC_STATUS_PLL_CHANGING_LSB         5
-#define QCA6180_RTC_SYNC_STATUS_PLL_CHANGING_MASK        0x00000020
-#define QCA6180_RTC_SYNC_STATUS_PLL_CHANGING_RESET       0x0
-#define QCA6180_RTC_SYNC_STATUS_OFFSET                   0x0244
-#define QCA6180_SOC_CPU_CLOCK_OFFSET                     0x00000020
-#define QCA6180_SOC_CPU_CLOCK_STANDARD_MSB               1
-#define QCA6180_SOC_CPU_CLOCK_STANDARD_LSB               0
-#define QCA6180_SOC_CPU_CLOCK_STANDARD_MASK              0x00000003
-/* PLL end */
-
-#define QCA6180_PCIE_INTR_CE_MASK(n)  (QCA6180_PCIE_INTR_CE0_MASK << (n))
-#define QCA6180_DRAM_BASE_ADDRESS     QCA6180_TARG_DRAM_START
-#define QCA6180_FW_INDICATOR_ADDRESS \
-	(QCA6180_WIFICMN_BASE_ADDRESS + QCA6180_SCRATCH_3_ADDRESS)
-#define QCA6180_SYSTEM_SLEEP_OFFSET       QCA6180_SOC_SYSTEM_SLEEP_OFFSET
-#define QCA6180_WLAN_SYSTEM_SLEEP_OFFSET  (0x002c + _WIFI_RTC_REG_BASE_ADDRESS)
-#define QCA6180_WLAN_RESET_CONTROL_OFFSET (0x0000 + _WIFI_RTC_REG_BASE_ADDRESS)
-#define QCA6180_CLOCK_CONTROL_OFFSET      QCA6180_SOC_CLOCK_CONTROL_OFFSET
-#define QCA6180_CLOCK_CONTROL_SI0_CLK_MASK \
-	QCA6180_SOC_CLOCK_CONTROL_SI0_CLK_MASK
-#define QCA6180_RESET_CONTROL_MBOX_RST_MASK 0x00000004
-#define QCA6180_RESET_CONTROL_SI0_RST_MASK \
-	QCA6180_SOC_RESET_CONTROL_SI0_RST_MASK
-#define QCA6180_GPIO_BASE_ADDRESS         QCA6180_WLAN_GPIO_BASE_ADDRESS
-#define QCA6180_GPIO_PIN0_OFFSET          QCA6180_WLAN_GPIO_PIN0_ADDRESS
-#define QCA6180_GPIO_PIN1_OFFSET          QCA6180_WLAN_GPIO_PIN1_ADDRESS
-#define QCA6180_GPIO_PIN0_CONFIG_MASK     QCA6180_WLAN_GPIO_PIN0_CONFIG_MASK
-#define QCA6180_GPIO_PIN1_CONFIG_MASK     QCA6180_WLAN_GPIO_PIN1_CONFIG_MASK
-#define QCA6180_SI_BASE_ADDRESS           0x00000000
-#define QCA6180_CPU_CLOCK_OFFSET          (0x20 + _RTC_SOC_REG_BASE_ADDRESS)
-#define QCA6180_LPO_CAL_OFFSET            QCA6180_SOC_LPO_CAL_OFFSET
-#define QCA6180_GPIO_PIN10_OFFSET         QCA6180_WLAN_GPIO_PIN10_ADDRESS
-#define QCA6180_GPIO_PIN11_OFFSET         QCA6180_WLAN_GPIO_PIN11_ADDRESS
-#define QCA6180_GPIO_PIN12_OFFSET         QCA6180_WLAN_GPIO_PIN12_ADDRESS
-#define QCA6180_GPIO_PIN13_OFFSET         QCA6180_WLAN_GPIO_PIN13_ADDRESS
-#define QCA6180_CPU_CLOCK_STANDARD_LSB    0
-#define QCA6180_CPU_CLOCK_STANDARD_MASK   0x1
-#define QCA6180_LPO_CAL_ENABLE_LSB        QCA6180_SOC_LPO_CAL_ENABLE_LSB
-#define QCA6180_LPO_CAL_ENABLE_MASK       QCA6180_SOC_LPO_CAL_ENABLE_MASK
-#define QCA6180_ANALOG_INTF_BASE_ADDRESS  QCA6180_WLAN_ANALOG_INTF_BASE_ADDRESS
-#define QCA6180_MBOX_BASE_ADDRESS         0x00008000
-#define QCA6180_INT_STATUS_ENABLE_ERROR_LSB             MISSING
-#define QCA6180_INT_STATUS_ENABLE_ERROR_MASK            MISSING
-#define QCA6180_INT_STATUS_ENABLE_CPU_LSB               MISSING
-#define QCA6180_INT_STATUS_ENABLE_CPU_MASK              MISSING
-#define QCA6180_INT_STATUS_ENABLE_COUNTER_LSB           MISSING
-#define QCA6180_INT_STATUS_ENABLE_COUNTER_MASK          MISSING
-#define QCA6180_INT_STATUS_ENABLE_MBOX_DATA_LSB         MISSING
-#define QCA6180_INT_STATUS_ENABLE_MBOX_DATA_MASK        MISSING
-#define QCA6180_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB    MISSING
-#define QCA6180_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK   MISSING
-#define QCA6180_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB     MISSING
-#define QCA6180_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK    MISSING
-#define QCA6180_COUNTER_INT_STATUS_ENABLE_BIT_LSB       MISSING
-#define QCA6180_COUNTER_INT_STATUS_ENABLE_BIT_MASK      MISSING
-#define QCA6180_INT_STATUS_ENABLE_ADDRESS               MISSING
-#define QCA6180_CPU_INT_STATUS_ENABLE_BIT_LSB           MISSING
-#define QCA6180_CPU_INT_STATUS_ENABLE_BIT_MASK          MISSING
-#define QCA6180_HOST_INT_STATUS_ADDRESS                 MISSING
-#define QCA6180_CPU_INT_STATUS_ADDRESS                  MISSING
-#define QCA6180_ERROR_INT_STATUS_ADDRESS                MISSING
-#define QCA6180_ERROR_INT_STATUS_WAKEUP_MASK            MISSING
-#define QCA6180_ERROR_INT_STATUS_WAKEUP_LSB             MISSING
-#define QCA6180_ERROR_INT_STATUS_RX_UNDERFLOW_MASK      MISSING
-#define QCA6180_ERROR_INT_STATUS_RX_UNDERFLOW_LSB       MISSING
-#define QCA6180_ERROR_INT_STATUS_TX_OVERFLOW_MASK       MISSING
-#define QCA6180_ERROR_INT_STATUS_TX_OVERFLOW_LSB        MISSING
-#define QCA6180_COUNT_DEC_ADDRESS                       MISSING
-#define QCA6180_HOST_INT_STATUS_CPU_MASK                MISSING
-#define QCA6180_HOST_INT_STATUS_CPU_LSB                 MISSING
-#define QCA6180_HOST_INT_STATUS_ERROR_MASK              MISSING
-#define QCA6180_HOST_INT_STATUS_ERROR_LSB               MISSING
-#define QCA6180_HOST_INT_STATUS_COUNTER_MASK            MISSING
-#define QCA6180_HOST_INT_STATUS_COUNTER_LSB             MISSING
-#define QCA6180_RX_LOOKAHEAD_VALID_ADDRESS              MISSING
-#define QCA6180_WINDOW_DATA_ADDRESS                     MISSING
-#define QCA6180_WINDOW_READ_ADDR_ADDRESS                MISSING
-#define QCA6180_WINDOW_WRITE_ADDR_ADDRESS               MISSING
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_0 \
-	(0x0024 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_1 \
-	(0x0028 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_2 \
-	(0x002C + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_3 \
-	(0x0030 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_4 \
-	(0x0034 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_5 \
-	(0x0038 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_6 \
-	(0x003C + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_7 \
-	(0x0040 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_8 \
-	(0x0044 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_9 \
-	(0x0048 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_10 \
-	(0x004C + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_11 \
-	(0x0050 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_12 \
-	(0x0054 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_13 \
-	(0x0058 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_14 \
-	(0x005C + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_15 \
-	(0x0060 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_16 \
-	(0x0064 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_17 \
-	(0x0068 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_18 \
-	(0x006C + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_19 \
-	(0x0070 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_20 \
-	(0x0074 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_21 \
-	(0x0078 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_22 \
-	(0x007C + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_23 \
-	(0x0080 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-
-
-/* Q6 iHelium emulation registers */
-#define QCA6180_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1	0x00113018
-#define QCA6180_A_SOC_CORE_SPARE_1_REGISTER	0x00113184
-#define QCA6180_A_SOC_CORE_PCIE_INTR_CLR_GRP1	0x00113020
-#define QCA6180_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1	0x00113010
-#define QCA6180_A_SOC_PCIE_PCIE_SCRATCH_0	0x00130040
-#define QCA6180_A_SOC_PCIE_PCIE_SCRATCH_1	0x00130044
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE0_TARGET_IE	0x00240024
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE0_TARGET_IS	0x00240028
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE1_TARGET_IE	0x00241024
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE1_TARGET_IS	0x00241028
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE2_TARGET_IE	0x00242024
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE2_TARGET_IS	0x00242028
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE3_TARGET_IE	0x00243024
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE3_TARGET_IS	0x00243028
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE4_TARGET_IE	0x00244024
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE4_TARGET_IS	0x00244028
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE5_TARGET_IE	0x00245024
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE5_TARGET_IS	0x00245028
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE6_TARGET_IE	0x00246024
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE6_TARGET_IS	0x00246028
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE7_TARGET_IE	0x00247024
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE7_TARGET_IS	0x00247028
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA	0x08
-#define QCA6180_A_SOC_PCIE_PCIE_SCRATCH_2	0x0013005C
-#define QCA6180_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK        0x0
-/* end: Q6 iHelium emulation registers */
-
-struct targetdef_s qca6180_targetdef = {
-	.d_RTC_SOC_BASE_ADDRESS = QCA6180_RTC_SOC_BASE_ADDRESS,
-	.d_RTC_WMAC_BASE_ADDRESS = QCA6180_RTC_WMAC_BASE_ADDRESS,
-	.d_SYSTEM_SLEEP_OFFSET = QCA6180_WLAN_SYSTEM_SLEEP_OFFSET,
-	.d_WLAN_SYSTEM_SLEEP_OFFSET = QCA6180_WLAN_SYSTEM_SLEEP_OFFSET,
-	.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB =
-	QCA6180_WLAN_SYSTEM_SLEEP_DISABLE_LSB,
-	.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK =
-	QCA6180_WLAN_SYSTEM_SLEEP_DISABLE_MASK,
-	.d_CLOCK_CONTROL_OFFSET = QCA6180_CLOCK_CONTROL_OFFSET,
-	.d_CLOCK_CONTROL_SI0_CLK_MASK = QCA6180_CLOCK_CONTROL_SI0_CLK_MASK,
-	.d_RESET_CONTROL_OFFSET = QCA6180_SOC_RESET_CONTROL_OFFSET,
-	.d_RESET_CONTROL_MBOX_RST_MASK = QCA6180_RESET_CONTROL_MBOX_RST_MASK,
-	.d_RESET_CONTROL_SI0_RST_MASK = QCA6180_RESET_CONTROL_SI0_RST_MASK,
-	.d_WLAN_RESET_CONTROL_OFFSET = QCA6180_WLAN_RESET_CONTROL_OFFSET,
-	.d_WLAN_RESET_CONTROL_COLD_RST_MASK =
-	QCA6180_WLAN_RESET_CONTROL_COLD_RST_MASK,
-	.d_WLAN_RESET_CONTROL_WARM_RST_MASK =
-	QCA6180_WLAN_RESET_CONTROL_WARM_RST_MASK,
-	.d_GPIO_BASE_ADDRESS = QCA6180_GPIO_BASE_ADDRESS,
-	.d_GPIO_PIN0_OFFSET = QCA6180_GPIO_PIN0_OFFSET,
-	.d_GPIO_PIN1_OFFSET = QCA6180_GPIO_PIN1_OFFSET,
-	.d_GPIO_PIN0_CONFIG_MASK = QCA6180_GPIO_PIN0_CONFIG_MASK,
-	.d_GPIO_PIN1_CONFIG_MASK = QCA6180_GPIO_PIN1_CONFIG_MASK,
-	.d_SI_CONFIG_BIDIR_OD_DATA_LSB = QCA6180_SI_CONFIG_BIDIR_OD_DATA_LSB,
-	.d_SI_CONFIG_BIDIR_OD_DATA_MASK = QCA6180_SI_CONFIG_BIDIR_OD_DATA_MASK,
-	.d_SI_CONFIG_I2C_LSB = QCA6180_SI_CONFIG_I2C_LSB,
-	.d_SI_CONFIG_I2C_MASK = QCA6180_SI_CONFIG_I2C_MASK,
-	.d_SI_CONFIG_POS_SAMPLE_LSB = QCA6180_SI_CONFIG_POS_SAMPLE_LSB,
-	.d_SI_CONFIG_POS_SAMPLE_MASK = QCA6180_SI_CONFIG_POS_SAMPLE_MASK,
-	.d_SI_CONFIG_INACTIVE_CLK_LSB = QCA6180_SI_CONFIG_INACTIVE_CLK_LSB,
-	.d_SI_CONFIG_INACTIVE_CLK_MASK = QCA6180_SI_CONFIG_INACTIVE_CLK_MASK,
-	.d_SI_CONFIG_INACTIVE_DATA_LSB = QCA6180_SI_CONFIG_INACTIVE_DATA_LSB,
-	.d_SI_CONFIG_INACTIVE_DATA_MASK = QCA6180_SI_CONFIG_INACTIVE_DATA_MASK,
-	.d_SI_CONFIG_DIVIDER_LSB = QCA6180_SI_CONFIG_DIVIDER_LSB,
-	.d_SI_CONFIG_DIVIDER_MASK = QCA6180_SI_CONFIG_DIVIDER_MASK,
-	.d_SI_BASE_ADDRESS = QCA6180_SI_BASE_ADDRESS,
-	.d_SI_CONFIG_OFFSET = QCA6180_SI_CONFIG_OFFSET,
-	.d_SI_TX_DATA0_OFFSET = QCA6180_SI_TX_DATA0_OFFSET,
-	.d_SI_TX_DATA1_OFFSET = QCA6180_SI_TX_DATA1_OFFSET,
-	.d_SI_RX_DATA0_OFFSET = QCA6180_SI_RX_DATA0_OFFSET,
-	.d_SI_RX_DATA1_OFFSET = QCA6180_SI_RX_DATA1_OFFSET,
-	.d_SI_CS_OFFSET = QCA6180_SI_CS_OFFSET,
-	.d_SI_CS_DONE_ERR_MASK = QCA6180_SI_CS_DONE_ERR_MASK,
-	.d_SI_CS_DONE_INT_MASK = QCA6180_SI_CS_DONE_INT_MASK,
-	.d_SI_CS_START_LSB = QCA6180_SI_CS_START_LSB,
-	.d_SI_CS_START_MASK = QCA6180_SI_CS_START_MASK,
-	.d_SI_CS_RX_CNT_LSB = QCA6180_SI_CS_RX_CNT_LSB,
-	.d_SI_CS_RX_CNT_MASK = QCA6180_SI_CS_RX_CNT_MASK,
-	.d_SI_CS_TX_CNT_LSB = QCA6180_SI_CS_TX_CNT_LSB,
-	.d_SI_CS_TX_CNT_MASK = QCA6180_SI_CS_TX_CNT_MASK,
-	.d_BOARD_DATA_SZ = QCA6180_BOARD_DATA_SZ,
-	.d_BOARD_EXT_DATA_SZ = QCA6180_BOARD_EXT_DATA_SZ,
-	.d_MBOX_BASE_ADDRESS = QCA6180_MBOX_BASE_ADDRESS,
-	.d_LOCAL_SCRATCH_OFFSET = QCA6180_LOCAL_SCRATCH_OFFSET,
-	.d_CPU_CLOCK_OFFSET = QCA6180_CPU_CLOCK_OFFSET,
-	.d_LPO_CAL_OFFSET = QCA6180_LPO_CAL_OFFSET,
-	.d_GPIO_PIN10_OFFSET = QCA6180_GPIO_PIN10_OFFSET,
-	.d_GPIO_PIN11_OFFSET = QCA6180_GPIO_PIN11_OFFSET,
-	.d_GPIO_PIN12_OFFSET = QCA6180_GPIO_PIN12_OFFSET,
-	.d_GPIO_PIN13_OFFSET = QCA6180_GPIO_PIN13_OFFSET,
-	.d_CLOCK_GPIO_OFFSET = QCA6180_CLOCK_GPIO_OFFSET,
-	.d_CPU_CLOCK_STANDARD_LSB = QCA6180_CPU_CLOCK_STANDARD_LSB,
-	.d_CPU_CLOCK_STANDARD_MASK = QCA6180_CPU_CLOCK_STANDARD_MASK,
-	.d_LPO_CAL_ENABLE_LSB = QCA6180_LPO_CAL_ENABLE_LSB,
-	.d_LPO_CAL_ENABLE_MASK = QCA6180_LPO_CAL_ENABLE_MASK,
-	.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = QCA6180_CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
-	.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK =
-	QCA6180_CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
-	.d_ANALOG_INTF_BASE_ADDRESS = QCA6180_ANALOG_INTF_BASE_ADDRESS,
-	.d_WLAN_MAC_BASE_ADDRESS = QCA6180_WLAN_MAC_BASE_ADDRESS,
-	.d_FW_INDICATOR_ADDRESS = QCA6180_FW_INDICATOR_ADDRESS,
-	.d_DRAM_BASE_ADDRESS = QCA6180_DRAM_BASE_ADDRESS,
-	.d_SOC_CORE_BASE_ADDRESS = QCA6180_SOC_CORE_BASE_ADDRESS,
-	.d_CORE_CTRL_ADDRESS = QCA6180_CORE_CTRL_ADDRESS,
-	.d_CE_COUNT = QCA6180_CE_COUNT,
-	.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
-	.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
-	.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
-	.d_PCIE_INTR_ENABLE_ADDRESS = QCA6180_PCIE_INTR_ENABLE_ADDRESS,
-	.d_PCIE_INTR_CLR_ADDRESS = QCA6180_PCIE_INTR_CLR_ADDRESS,
-	.d_PCIE_INTR_FIRMWARE_MASK = QCA6180_PCIE_INTR_FIRMWARE_MASK,
-	.d_PCIE_INTR_CE_MASK_ALL = QCA6180_PCIE_INTR_CE_MASK_ALL,
-	.d_CORE_CTRL_CPU_INTR_MASK = QCA6180_CORE_CTRL_CPU_INTR_MASK,
-	.d_SR_WR_INDEX_ADDRESS = QCA6180_SR_WR_INDEX_ADDRESS,
-	.d_DST_WATERMARK_ADDRESS = QCA6180_DST_WATERMARK_ADDRESS,
-	/* htt_rx.c */
-	.d_RX_MSDU_END_4_FIRST_MSDU_MASK =
-	QCA6180_RX_MSDU_END_4_FIRST_MSDU_MASK,
-	.d_RX_MSDU_END_4_FIRST_MSDU_LSB = QCA6180_RX_MSDU_END_4_FIRST_MSDU_LSB,
-	.d_RX_MPDU_START_0_SEQ_NUM_MASK = QCA6180_RX_MPDU_START_0_SEQ_NUM_MASK,
-	.d_RX_MPDU_START_0_SEQ_NUM_LSB = QCA6180_RX_MPDU_START_0_SEQ_NUM_LSB,
-	.d_RX_MPDU_START_2_PN_47_32_LSB = QCA6180_RX_MPDU_START_2_PN_47_32_LSB,
-	.d_RX_MPDU_START_2_PN_47_32_MASK =
-	QCA6180_RX_MPDU_START_2_PN_47_32_MASK,
-	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK =
-		QCA6180_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK,
-	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB =
-		QCA6180_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB,
-	.d_RX_MSDU_END_4_LAST_MSDU_MASK = QCA6180_RX_MSDU_END_4_LAST_MSDU_MASK,
-	.d_RX_MSDU_END_4_LAST_MSDU_LSB = QCA6180_RX_MSDU_END_4_LAST_MSDU_LSB,
-	.d_RX_ATTENTION_0_MCAST_BCAST_MASK =
-		QCA6180_RX_ATTENTION_0_MCAST_BCAST_MASK,
-	.d_RX_ATTENTION_0_MCAST_BCAST_LSB =
-	QCA6180_RX_ATTENTION_0_MCAST_BCAST_LSB,
-	.d_RX_ATTENTION_0_FRAGMENT_MASK = QCA6180_RX_ATTENTION_0_FRAGMENT_MASK,
-	.d_RX_ATTENTION_0_FRAGMENT_LSB = QCA6180_RX_ATTENTION_0_FRAGMENT_LSB,
-	.d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK =
-		QCA6180_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK,
-	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK =
-		QCA6180_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK,
-	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB =
-		QCA6180_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB,
-	.d_RX_MSDU_START_0_MSDU_LENGTH_MASK =
-		QCA6180_RX_MSDU_START_0_MSDU_LENGTH_MASK,
-	.d_RX_MSDU_START_0_MSDU_LENGTH_LSB =
-		QCA6180_RX_MSDU_START_0_MSDU_LENGTH_LSB,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET =
-		QCA6180_RX_MSDU_START_2_DECAP_FORMAT_OFFSET,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_MASK =
-		QCA6180_RX_MSDU_START_2_DECAP_FORMAT_MASK,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_LSB =
-		QCA6180_RX_MSDU_START_2_DECAP_FORMAT_LSB,
-	.d_RX_MPDU_START_0_ENCRYPTED_MASK =
-	QCA6180_RX_MPDU_START_0_ENCRYPTED_MASK,
-	.d_RX_MPDU_START_0_ENCRYPTED_LSB =
-	QCA6180_RX_MPDU_START_0_ENCRYPTED_LSB,
-	.d_RX_ATTENTION_0_MORE_DATA_MASK =
-	QCA6180_RX_ATTENTION_0_MORE_DATA_MASK,
-	.d_RX_ATTENTION_0_MSDU_DONE_MASK =
-	QCA6180_RX_ATTENTION_0_MSDU_DONE_MASK,
-	.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
-		QCA6180_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
-
-	/* PLL start */
-	.d_EFUSE_OFFSET = QCA6180_EFUSE_OFFSET,
-	.d_EFUSE_XTAL_SEL_MSB = QCA6180_EFUSE_XTAL_SEL_MSB,
-	.d_EFUSE_XTAL_SEL_LSB = QCA6180_EFUSE_XTAL_SEL_LSB,
-	.d_EFUSE_XTAL_SEL_MASK = QCA6180_EFUSE_XTAL_SEL_MASK,
-	.d_BB_PLL_CONFIG_OFFSET = QCA6180_BB_PLL_CONFIG_OFFSET,
-	.d_BB_PLL_CONFIG_OUTDIV_MSB = QCA6180_BB_PLL_CONFIG_OUTDIV_MSB,
-	.d_BB_PLL_CONFIG_OUTDIV_LSB = QCA6180_BB_PLL_CONFIG_OUTDIV_LSB,
-	.d_BB_PLL_CONFIG_OUTDIV_MASK = QCA6180_BB_PLL_CONFIG_OUTDIV_MASK,
-	.d_BB_PLL_CONFIG_FRAC_MSB = QCA6180_BB_PLL_CONFIG_FRAC_MSB,
-	.d_BB_PLL_CONFIG_FRAC_LSB = QCA6180_BB_PLL_CONFIG_FRAC_LSB,
-	.d_BB_PLL_CONFIG_FRAC_MASK = QCA6180_BB_PLL_CONFIG_FRAC_MASK,
-	.d_WLAN_PLL_SETTLE_TIME_MSB = QCA6180_WLAN_PLL_SETTLE_TIME_MSB,
-	.d_WLAN_PLL_SETTLE_TIME_LSB = QCA6180_WLAN_PLL_SETTLE_TIME_LSB,
-	.d_WLAN_PLL_SETTLE_TIME_MASK = QCA6180_WLAN_PLL_SETTLE_TIME_MASK,
-	.d_WLAN_PLL_SETTLE_OFFSET = QCA6180_WLAN_PLL_SETTLE_OFFSET,
-	.d_WLAN_PLL_SETTLE_SW_MASK = QCA6180_WLAN_PLL_SETTLE_SW_MASK,
-	.d_WLAN_PLL_SETTLE_RSTMASK = QCA6180_WLAN_PLL_SETTLE_RSTMASK,
-	.d_WLAN_PLL_SETTLE_RESET = QCA6180_WLAN_PLL_SETTLE_RESET,
-	.d_WLAN_PLL_CONTROL_NOPWD_MSB = QCA6180_WLAN_PLL_CONTROL_NOPWD_MSB,
-	.d_WLAN_PLL_CONTROL_NOPWD_LSB = QCA6180_WLAN_PLL_CONTROL_NOPWD_LSB,
-	.d_WLAN_PLL_CONTROL_NOPWD_MASK = QCA6180_WLAN_PLL_CONTROL_NOPWD_MASK,
-	.d_WLAN_PLL_CONTROL_BYPASS_MSB = QCA6180_WLAN_PLL_CONTROL_BYPASS_MSB,
-	.d_WLAN_PLL_CONTROL_BYPASS_LSB = QCA6180_WLAN_PLL_CONTROL_BYPASS_LSB,
-	.d_WLAN_PLL_CONTROL_BYPASS_MASK = QCA6180_WLAN_PLL_CONTROL_BYPASS_MASK,
-	.d_WLAN_PLL_CONTROL_BYPASS_RESET =
-		QCA6180_WLAN_PLL_CONTROL_BYPASS_RESET,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_MSB = QCA6180_WLAN_PLL_CONTROL_CLK_SEL_MSB,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_LSB = QCA6180_WLAN_PLL_CONTROL_CLK_SEL_LSB,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_MASK =
-		QCA6180_WLAN_PLL_CONTROL_CLK_SEL_MASK,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_RESET =
-		QCA6180_WLAN_PLL_CONTROL_CLK_SEL_RESET,
-	.d_WLAN_PLL_CONTROL_REFDIV_MSB = QCA6180_WLAN_PLL_CONTROL_REFDIV_MSB,
-	.d_WLAN_PLL_CONTROL_REFDIV_LSB = QCA6180_WLAN_PLL_CONTROL_REFDIV_LSB,
-	.d_WLAN_PLL_CONTROL_REFDIV_MASK = QCA6180_WLAN_PLL_CONTROL_REFDIV_MASK,
-	.d_WLAN_PLL_CONTROL_REFDIV_RESET =
-		QCA6180_WLAN_PLL_CONTROL_REFDIV_RESET,
-	.d_WLAN_PLL_CONTROL_DIV_MSB = QCA6180_WLAN_PLL_CONTROL_DIV_MSB,
-	.d_WLAN_PLL_CONTROL_DIV_LSB = QCA6180_WLAN_PLL_CONTROL_DIV_LSB,
-	.d_WLAN_PLL_CONTROL_DIV_MASK = QCA6180_WLAN_PLL_CONTROL_DIV_MASK,
-	.d_WLAN_PLL_CONTROL_DIV_RESET = QCA6180_WLAN_PLL_CONTROL_DIV_RESET,
-	.d_WLAN_PLL_CONTROL_OFFSET = QCA6180_WLAN_PLL_CONTROL_OFFSET,
-	.d_WLAN_PLL_CONTROL_SW_MASK = QCA6180_WLAN_PLL_CONTROL_SW_MASK,
-	.d_WLAN_PLL_CONTROL_RSTMASK = QCA6180_WLAN_PLL_CONTROL_RSTMASK,
-	.d_WLAN_PLL_CONTROL_RESET = QCA6180_WLAN_PLL_CONTROL_RESET,
-	.d_SOC_CORE_CLK_CTRL_OFFSET = QCA6180_SOC_CORE_CLK_CTRL_OFFSET,
-	.d_SOC_CORE_CLK_CTRL_DIV_MSB = QCA6180_SOC_CORE_CLK_CTRL_DIV_MSB,
-	.d_SOC_CORE_CLK_CTRL_DIV_LSB = QCA6180_SOC_CORE_CLK_CTRL_DIV_LSB,
-	.d_SOC_CORE_CLK_CTRL_DIV_MASK = QCA6180_SOC_CORE_CLK_CTRL_DIV_MASK,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_MSB =
-		QCA6180_RTC_SYNC_STATUS_PLL_CHANGING_MSB,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_LSB =
-		QCA6180_RTC_SYNC_STATUS_PLL_CHANGING_LSB,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_MASK =
-		QCA6180_RTC_SYNC_STATUS_PLL_CHANGING_MASK,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_RESET =
-		QCA6180_RTC_SYNC_STATUS_PLL_CHANGING_RESET,
-	.d_RTC_SYNC_STATUS_OFFSET = QCA6180_RTC_SYNC_STATUS_OFFSET,
-	.d_SOC_CPU_CLOCK_OFFSET = QCA6180_SOC_CPU_CLOCK_OFFSET,
-	.d_SOC_CPU_CLOCK_STANDARD_MSB = QCA6180_SOC_CPU_CLOCK_STANDARD_MSB,
-	.d_SOC_CPU_CLOCK_STANDARD_LSB = QCA6180_SOC_CPU_CLOCK_STANDARD_LSB,
-	.d_SOC_CPU_CLOCK_STANDARD_MASK = QCA6180_SOC_CPU_CLOCK_STANDARD_MASK,
-	/* PLL end */
-	.d_SOC_POWER_REG_OFFSET = QCA6180_SOC_POWER_REG_OFFSET,
-	.d_PCIE_INTR_CAUSE_ADDRESS = QCA6180_PCIE_INTR_CAUSE_ADDRESS,
-	.d_SOC_RESET_CONTROL_ADDRESS = QCA6180_SOC_RESET_CONTROL_ADDRESS,
-	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =
-		QCA6180_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
-	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB =
-		QCA6180_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
-	.d_SOC_RESET_CONTROL_CE_RST_MASK =
-		QCA6180_SOC_RESET_CONTROL_CE_RST_MASK,
-	.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
-		QCA6180_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
-	.d_CPU_INTR_ADDRESS = QCA6180_CPU_INTR_ADDRESS,
-	.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
-		QCA6180_SOC_LF_TIMER_CONTROL0_ADDRESS,
-	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
-		QCA6180_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
-	/* chip id start */
-	.d_SOC_CHIP_ID_ADDRESS = QCA6180_SOC_CHIP_ID_ADDRESS,
-	.d_SOC_CHIP_ID_VERSION_MASK = QCA6180_SOC_CHIP_ID_VERSION_MASK,
-	.d_SOC_CHIP_ID_VERSION_LSB = QCA6180_SOC_CHIP_ID_VERSION_LSB,
-	.d_SOC_CHIP_ID_REVISION_MASK = QCA6180_SOC_CHIP_ID_REVISION_MASK,
-	.d_SOC_CHIP_ID_REVISION_LSB = QCA6180_SOC_CHIP_ID_REVISION_LSB,
-	/* chip id end */
-	.d_A_SOC_CORE_SCRATCH_0_ADDRESS = QCA6180_A_SOC_CORE_SCRATCH_0_ADDRESS,
-	.d_A_SOC_CORE_SCRATCH_1_ADDRESS = QCA6180_A_SOC_CORE_SCRATCH_1_ADDRESS,
-	.d_A_SOC_CORE_SCRATCH_2_ADDRESS = QCA6180_A_SOC_CORE_SCRATCH_2_ADDRESS,
-	.d_A_SOC_CORE_SCRATCH_3_ADDRESS = QCA6180_A_SOC_CORE_SCRATCH_3_ADDRESS,
-	.d_A_SOC_CORE_SCRATCH_4_ADDRESS = QCA6180_A_SOC_CORE_SCRATCH_4_ADDRESS,
-	.d_A_SOC_CORE_SCRATCH_5_ADDRESS = QCA6180_A_SOC_CORE_SCRATCH_5_ADDRESS,
-	.d_A_SOC_CORE_SCRATCH_6_ADDRESS = QCA6180_A_SOC_CORE_SCRATCH_6_ADDRESS,
-	.d_A_SOC_CORE_SCRATCH_7_ADDRESS = QCA6180_A_SOC_CORE_SCRATCH_7_ADDRESS,
-	.d_A_SOC_CORE_SPARE_0_REGISTER = QCA6180_A_SOC_CORE_SPARE_0_REGISTER,
-	.d_PCIE_INTR_FIRMWARE_ROUTE_MASK =
-		QCA6180_PCIE_INTR_FIRMWARE_ROUTE_MASK,
-	.d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 =
-		QCA6180_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1,
-	.d_A_SOC_CORE_SPARE_1_REGISTER =
-		QCA6180_A_SOC_CORE_SPARE_1_REGISTER,
-	.d_A_SOC_CORE_PCIE_INTR_CLR_GRP1 =
-		QCA6180_A_SOC_CORE_PCIE_INTR_CLR_GRP1,
-	.d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1 =
-		QCA6180_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1,
-	.d_A_SOC_PCIE_PCIE_SCRATCH_0 =
-		QCA6180_A_SOC_PCIE_PCIE_SCRATCH_0,
-	.d_A_SOC_PCIE_PCIE_SCRATCH_1 =
-		QCA6180_A_SOC_PCIE_PCIE_SCRATCH_1,
-	.d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA =
-		QCA6180_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA,
-	.d_A_SOC_PCIE_PCIE_SCRATCH_2 = QCA6180_A_SOC_PCIE_PCIE_SCRATCH_2,
-	.d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK =
-		QCA6180_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK,
-
-	.d_WLAN_DEBUG_INPUT_SEL_OFFSET = QCA6180_WLAN_DEBUG_INPUT_SEL_OFFSET,
-	.d_WLAN_DEBUG_INPUT_SEL_SRC_MSB = QCA6180_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
-	.d_WLAN_DEBUG_INPUT_SEL_SRC_LSB = QCA6180_WLAN_DEBUG_INPUT_SEL_SRC_LSB,
-	.d_WLAN_DEBUG_INPUT_SEL_SRC_MASK =
-		QCA6180_WLAN_DEBUG_INPUT_SEL_SRC_MASK,
-	.d_WLAN_DEBUG_CONTROL_OFFSET = QCA6180_WLAN_DEBUG_CONTROL_OFFSET,
-	.d_WLAN_DEBUG_CONTROL_ENABLE_MSB =
-		QCA6180_WLAN_DEBUG_CONTROL_ENABLE_MSB,
-	.d_WLAN_DEBUG_CONTROL_ENABLE_LSB =
-		QCA6180_WLAN_DEBUG_CONTROL_ENABLE_LSB,
-	.d_WLAN_DEBUG_CONTROL_ENABLE_MASK =
-		QCA6180_WLAN_DEBUG_CONTROL_ENABLE_MASK,
-	.d_WLAN_DEBUG_OUT_OFFSET = QCA6180_WLAN_DEBUG_OUT_OFFSET,
-	.d_WLAN_DEBUG_OUT_DATA_MSB = QCA6180_WLAN_DEBUG_OUT_DATA_MSB,
-	.d_WLAN_DEBUG_OUT_DATA_LSB = QCA6180_WLAN_DEBUG_OUT_DATA_LSB,
-	.d_WLAN_DEBUG_OUT_DATA_MASK = QCA6180_WLAN_DEBUG_OUT_DATA_MASK,
-	.d_AMBA_DEBUG_BUS_OFFSET = QCA6180_AMBA_DEBUG_BUS_OFFSET,
-	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB =
-		QCA6180_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB,
-	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB =
-		QCA6180_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB,
-	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK =
-		QCA6180_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK,
-	.d_AMBA_DEBUG_BUS_SEL_MSB = QCA6180_AMBA_DEBUG_BUS_SEL_MSB,
-	.d_AMBA_DEBUG_BUS_SEL_LSB = QCA6180_AMBA_DEBUG_BUS_SEL_LSB,
-	.d_AMBA_DEBUG_BUS_SEL_MASK = QCA6180_AMBA_DEBUG_BUS_SEL_MASK,
-};
-
-struct hostdef_s qca6180_hostdef = {
-	.d_INT_STATUS_ENABLE_ERROR_LSB = QCA6180_INT_STATUS_ENABLE_ERROR_LSB,
-	.d_INT_STATUS_ENABLE_ERROR_MASK = QCA6180_INT_STATUS_ENABLE_ERROR_MASK,
-	.d_INT_STATUS_ENABLE_CPU_LSB = QCA6180_INT_STATUS_ENABLE_CPU_LSB,
-	.d_INT_STATUS_ENABLE_CPU_MASK = QCA6180_INT_STATUS_ENABLE_CPU_MASK,
-	.d_INT_STATUS_ENABLE_COUNTER_LSB =
-		QCA6180_INT_STATUS_ENABLE_COUNTER_LSB,
-	.d_INT_STATUS_ENABLE_COUNTER_MASK =
-		QCA6180_INT_STATUS_ENABLE_COUNTER_MASK,
-	.d_INT_STATUS_ENABLE_MBOX_DATA_LSB =
-		QCA6180_INT_STATUS_ENABLE_MBOX_DATA_LSB,
-	.d_INT_STATUS_ENABLE_MBOX_DATA_MASK =
-		QCA6180_INT_STATUS_ENABLE_MBOX_DATA_MASK,
-	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =
-		QCA6180_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
-	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =
-		QCA6180_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
-	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =
-		QCA6180_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
-	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =
-		QCA6180_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
-	.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB =
-		QCA6180_COUNTER_INT_STATUS_ENABLE_BIT_LSB,
-	.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK =
-		QCA6180_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
-	.d_INT_STATUS_ENABLE_ADDRESS = QCA6180_INT_STATUS_ENABLE_ADDRESS,
-	.d_CPU_INT_STATUS_ENABLE_BIT_LSB =
-		QCA6180_CPU_INT_STATUS_ENABLE_BIT_LSB,
-	.d_CPU_INT_STATUS_ENABLE_BIT_MASK =
-		QCA6180_CPU_INT_STATUS_ENABLE_BIT_MASK,
-	.d_HOST_INT_STATUS_ADDRESS = QCA6180_HOST_INT_STATUS_ADDRESS,
-	.d_CPU_INT_STATUS_ADDRESS = QCA6180_CPU_INT_STATUS_ADDRESS,
-	.d_ERROR_INT_STATUS_ADDRESS = QCA6180_ERROR_INT_STATUS_ADDRESS,
-	.d_ERROR_INT_STATUS_WAKEUP_MASK = QCA6180_ERROR_INT_STATUS_WAKEUP_MASK,
-	.d_ERROR_INT_STATUS_WAKEUP_LSB = QCA6180_ERROR_INT_STATUS_WAKEUP_LSB,
-	.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =
-		QCA6180_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
-	.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =
-		QCA6180_ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
-	.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK =
-		QCA6180_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
-	.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB =
-		QCA6180_ERROR_INT_STATUS_TX_OVERFLOW_LSB,
-	.d_COUNT_DEC_ADDRESS = QCA6180_COUNT_DEC_ADDRESS,
-	.d_HOST_INT_STATUS_CPU_MASK = QCA6180_HOST_INT_STATUS_CPU_MASK,
-	.d_HOST_INT_STATUS_CPU_LSB = QCA6180_HOST_INT_STATUS_CPU_LSB,
-	.d_HOST_INT_STATUS_ERROR_MASK = QCA6180_HOST_INT_STATUS_ERROR_MASK,
-	.d_HOST_INT_STATUS_ERROR_LSB = QCA6180_HOST_INT_STATUS_ERROR_LSB,
-	.d_HOST_INT_STATUS_COUNTER_MASK = QCA6180_HOST_INT_STATUS_COUNTER_MASK,
-	.d_HOST_INT_STATUS_COUNTER_LSB = QCA6180_HOST_INT_STATUS_COUNTER_LSB,
-	.d_RX_LOOKAHEAD_VALID_ADDRESS = QCA6180_RX_LOOKAHEAD_VALID_ADDRESS,
-	.d_WINDOW_DATA_ADDRESS = QCA6180_WINDOW_DATA_ADDRESS,
-	.d_WINDOW_READ_ADDR_ADDRESS = QCA6180_WINDOW_READ_ADDR_ADDRESS,
-	.d_WINDOW_WRITE_ADDR_ADDRESS = QCA6180_WINDOW_WRITE_ADDR_ADDRESS,
-	.d_SOC_GLOBAL_RESET_ADDRESS = QCA6180_SOC_GLOBAL_RESET_ADDRESS,
-	.d_RTC_STATE_ADDRESS = QCA6180_RTC_STATE_ADDRESS,
-	.d_RTC_STATE_COLD_RESET_MASK = QCA6180_RTC_STATE_COLD_RESET_MASK,
-	.d_PCIE_LOCAL_BASE_ADDRESS = QCA6180_PCIE_LOCAL_BASE_ADDRESS,
-	.d_PCIE_SOC_WAKE_RESET = QCA6180_PCIE_SOC_WAKE_RESET,
-	.d_PCIE_SOC_WAKE_ADDRESS = QCA6180_PCIE_SOC_WAKE_ADDRESS,
-	.d_PCIE_SOC_WAKE_V_MASK = QCA6180_PCIE_SOC_WAKE_V_MASK,
-	.d_RTC_STATE_V_MASK = QCA6180_RTC_STATE_V_MASK,
-	.d_RTC_STATE_V_LSB = QCA6180_RTC_STATE_V_LSB,
-	.d_FW_IND_EVENT_PENDING = QCA6180_FW_IND_EVENT_PENDING,
-	.d_FW_IND_INITIALIZED = QCA6180_FW_IND_INITIALIZED,
-	.d_FW_IND_HELPER = QCA6180_FW_IND_HELPER,
-	.d_RTC_STATE_V_ON = QCA6180_RTC_STATE_V_ON,
-#if defined(SDIO_3_0)
-	.d_HOST_INT_STATUS_MBOX_DATA_MASK =
-		QCA6180_HOST_INT_STATUS_MBOX_DATA_MASK,
-	.d_HOST_INT_STATUS_MBOX_DATA_LSB =
-		QCA6180_HOST_INT_STATUS_MBOX_DATA_LSB,
-#endif
-	.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
-	.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
-	.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
-	.d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS,
-	.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
-	.d_HOST_CE_COUNT = 8,
-	.d_ENABLE_MSI = 0,
-	.d_MUX_ID_MASK = 0xf000,
-	.d_TRANSACTION_ID_MASK = 0x0fff,
-	.d_DESC_DATA_FLAG_MASK = 0x1FFFE3E0,
-	.d_A_SOC_PCIE_PCIE_BAR0_START = QCA6180_A_SOC_PCIE_PCIE_BAR0_START,
-};
-
-
-struct ce_reg_def qca6180_ce_targetdef = {
-	/* copy_engine.c  */
-	.d_DST_WR_INDEX_ADDRESS = QCA6180_DST_WR_INDEX_ADDRESS,
-	.d_SRC_WATERMARK_ADDRESS = QCA6180_SRC_WATERMARK_ADDRESS,
-	.d_SRC_WATERMARK_LOW_MASK = QCA6180_SRC_WATERMARK_LOW_MASK,
-	.d_SRC_WATERMARK_HIGH_MASK = QCA6180_SRC_WATERMARK_HIGH_MASK,
-	.d_DST_WATERMARK_LOW_MASK = QCA6180_DST_WATERMARK_LOW_MASK,
-	.d_DST_WATERMARK_HIGH_MASK = QCA6180_DST_WATERMARK_HIGH_MASK,
-	.d_CURRENT_SRRI_ADDRESS = QCA6180_CURRENT_SRRI_ADDRESS,
-	.d_CURRENT_DRRI_ADDRESS = QCA6180_CURRENT_DRRI_ADDRESS,
-	.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =
-		QCA6180_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,
-	.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =
-		QCA6180_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,
-	.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =
-		QCA6180_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,
-	.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =
-		QCA6180_HOST_IS_DST_RING_LOW_WATERMARK_MASK,
-	.d_HOST_IS_ADDRESS = QCA6180_HOST_IS_ADDRESS,
-	.d_MISC_IS_ADDRESS = QCA6180_MISC_IS_ADDRESS,
-	.d_HOST_IS_COPY_COMPLETE_MASK = QCA6180_HOST_IS_COPY_COMPLETE_MASK,
-	.d_CE_WRAPPER_BASE_ADDRESS = QCA6180_CE_WRAPPER_BASE_ADDRESS,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
-		QCA6180_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS,
-	.d_CE_DDR_ADDRESS_FOR_RRI_LOW = QCA6180_CE_WRAPPER_INDEX_BASE_LOW,
-	.d_CE_DDR_ADDRESS_FOR_RRI_HIGH = QCA6180_CE_WRAPPER_INDEX_BASE_HIGH,
-	.d_HOST_IE_ADDRESS = QCA6180_HOST_IE_ADDRESS,
-	.d_HOST_IE_COPY_COMPLETE_MASK = QCA6180_HOST_IE_COPY_COMPLETE_MASK,
-	.d_SR_BA_ADDRESS = QCA6180_SR_BA_ADDRESS,
-	.d_SR_SIZE_ADDRESS = QCA6180_SR_SIZE_ADDRESS,
-	.d_CE_CTRL1_ADDRESS = QCA6180_CE_CTRL1_ADDRESS,
-	.d_CE_CTRL1_DMAX_LENGTH_MASK = QCA6180_CE_CTRL1_DMAX_LENGTH_MASK,
-	.d_DR_BA_ADDRESS = QCA6180_DR_BA_ADDRESS,
-	.d_DR_SIZE_ADDRESS = QCA6180_DR_SIZE_ADDRESS,
-	.d_CE_CMD_REGISTER = QCA6180_CE_CMD_REGISTER,
-	.d_CE_MSI_ADDRESS = QCA6180_CE_MSI_ADDRESS,
-	.d_CE_MSI_ADDRESS_HIGH = QCA6180_CE_MSI_ADDRESS_HIGH,
-	.d_CE_MSI_DATA = QCA6180_CE_MSI_DATA,
-	.d_CE_MSI_ENABLE_BIT = QCA6180_CE_MSI_ENABLE_BIT,
-	.d_MISC_IE_ADDRESS = QCA6180_MISC_IE_ADDRESS,
-	.d_MISC_IS_AXI_ERR_MASK = QCA6180_MISC_IS_AXI_ERR_MASK,
-	.d_MISC_IS_DST_ADDR_ERR_MASK = QCA6180_MISC_IS_DST_ADDR_ERR_MASK,
-	.d_MISC_IS_SRC_LEN_ERR_MASK = QCA6180_MISC_IS_SRC_LEN_ERR_MASK,
-	.d_MISC_IS_DST_MAX_LEN_VIO_MASK = QCA6180_MISC_IS_DST_MAX_LEN_VIO_MASK,
-	.d_MISC_IS_DST_RING_OVERFLOW_MASK =
-		QCA6180_MISC_IS_DST_RING_OVERFLOW_MASK,
-	.d_MISC_IS_SRC_RING_OVERFLOW_MASK =
-		QCA6180_MISC_IS_SRC_RING_OVERFLOW_MASK,
-	.d_SRC_WATERMARK_LOW_LSB = QCA6180_SRC_WATERMARK_LOW_LSB,
-	.d_SRC_WATERMARK_HIGH_LSB = QCA6180_SRC_WATERMARK_HIGH_LSB,
-	.d_DST_WATERMARK_LOW_LSB = QCA6180_DST_WATERMARK_LOW_LSB,
-	.d_DST_WATERMARK_HIGH_LSB = QCA6180_DST_WATERMARK_HIGH_LSB,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =
-		QCA6180_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =
-		QCA6180_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,
-	.d_CE_CTRL1_DMAX_LENGTH_LSB = QCA6180_CE_CTRL1_DMAX_LENGTH_LSB,
-	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =
-		QCA6180_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,
-	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =
-		QCA6180_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
-	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =
-		QCA6180_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
-	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
-		QCA6180_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
-	.d_CE_WRAPPER_DEBUG_OFFSET = QCA6180_CE_WRAPPER_DEBUG_OFFSET,
-	.d_CE_WRAPPER_DEBUG_SEL_MSB = QCA6180_CE_WRAPPER_DEBUG_SEL_MSB,
-	.d_CE_WRAPPER_DEBUG_SEL_LSB = QCA6180_CE_WRAPPER_DEBUG_SEL_LSB,
-	.d_CE_WRAPPER_DEBUG_SEL_MASK = QCA6180_CE_WRAPPER_DEBUG_SEL_MASK,
-	.d_CE_DEBUG_OFFSET = QCA6180_CE_DEBUG_OFFSET,
-	.d_CE_DEBUG_SEL_MSB = QCA6180_CE_DEBUG_SEL_MSB,
-	.d_CE_DEBUG_SEL_LSB = QCA6180_CE_DEBUG_SEL_LSB,
-	.d_CE_DEBUG_SEL_MASK = QCA6180_CE_DEBUG_SEL_MASK,
-	.d_CE0_BASE_ADDRESS = QCA6180_CE0_BASE_ADDRESS,
-	.d_CE1_BASE_ADDRESS = QCA6180_CE1_BASE_ADDRESS,
-};
-
-
-struct host_shadow_regs_s qca6180_host_shadow_regs = {
-	.d_A_LOCAL_SHADOW_REG_VALUE_0  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_0,
-	.d_A_LOCAL_SHADOW_REG_VALUE_1  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_1,
-	.d_A_LOCAL_SHADOW_REG_VALUE_2  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_2,
-	.d_A_LOCAL_SHADOW_REG_VALUE_3  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_3,
-	.d_A_LOCAL_SHADOW_REG_VALUE_4  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_4,
-	.d_A_LOCAL_SHADOW_REG_VALUE_5  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_5,
-	.d_A_LOCAL_SHADOW_REG_VALUE_6  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_6,
-	.d_A_LOCAL_SHADOW_REG_VALUE_7  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_7,
-	.d_A_LOCAL_SHADOW_REG_VALUE_8  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_8,
-	.d_A_LOCAL_SHADOW_REG_VALUE_9  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_9,
-	.d_A_LOCAL_SHADOW_REG_VALUE_10 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_10,
-	.d_A_LOCAL_SHADOW_REG_VALUE_11 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_11,
-	.d_A_LOCAL_SHADOW_REG_VALUE_12 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_12,
-	.d_A_LOCAL_SHADOW_REG_VALUE_13 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_13,
-	.d_A_LOCAL_SHADOW_REG_VALUE_14 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_14,
-	.d_A_LOCAL_SHADOW_REG_VALUE_15 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_15,
-	.d_A_LOCAL_SHADOW_REG_VALUE_16 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_16,
-	.d_A_LOCAL_SHADOW_REG_VALUE_17 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_17,
-	.d_A_LOCAL_SHADOW_REG_VALUE_18 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_18,
-	.d_A_LOCAL_SHADOW_REG_VALUE_19 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_19,
-	.d_A_LOCAL_SHADOW_REG_VALUE_20 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_20,
-	.d_A_LOCAL_SHADOW_REG_VALUE_21 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_21,
-	.d_A_LOCAL_SHADOW_REG_VALUE_22 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_22,
-	.d_A_LOCAL_SHADOW_REG_VALUE_23 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_23,
-
-};
-
-#endif /* _QCA6180DEF_H_ */

hif/src/regtable.c

@@ -32,7 +32,6 @@
 #include "ar9888def.h"
 #include "ar6320def.h"
 #include "ar6320v2def.h"
-#include "qca6180def.h"
 #include "ol_if_athvar.h"
 #include "hif_main.h"
 #include "adrastea_reg_def.h"
@@ -52,10 +51,6 @@ void target_register_tbl_attach(struct hif_softc *scn, u32 target_type)
 		scn->targetdef = &ar6320v2_targetdef;
 		scn->target_ce_def = &ar6320v2_ce_targetdef;
 		break;
-	case TARGET_TYPE_QCA6180:
-		scn->targetdef = &qca6180_targetdef;
-		scn->target_ce_def = &qca6180_ce_targetdef;
-		break;
 	case TARGET_TYPE_ADRASTEA:
 		scn->targetdef = &adrastea_targetdef;
 		scn->target_ce_def = &adrastea_ce_targetdef;
@@ -77,10 +72,6 @@ void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type)
 	case HIF_TYPE_AR6320V2:
 		scn->hostdef = &ar6320v2_hostdef;
 		break;
-	case HIF_TYPE_QCA6180:
-		scn->hostdef = &qca6180_hostdef;
-		scn->host_shadow_regs = &qca6180_host_shadow_regs;
-		break;
 	case HIF_TYPE_ADRASTEA:
 		scn->hostdef = &adrastea_hostdef;
 		scn->host_shadow_regs = &adrastea_host_shadow_regs;