ipa: update IPAv5 registers

Update IPAHAL to new IPAv5 registers according to SWI.
Remove usage of obsolete registers and use new ep registers
instead.

Change-Id: I5408c0508ff7ec26879d1cd481a04e463a2f91ab
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Signed-off-by: Amir Levy <alevy@codeaurora.org>
Signed-off-by: Ilia Lin <ilial@codeaurora.org>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>

drivers/platform/msm/ipa/ipa_common_i.h

@@ -18,6 +18,8 @@
 
 #define WARNON_RATELIMIT_BURST 1
 #define IPA_RATELIMIT_BURST 1
+#define IPA_EP_ARR_SIZE 2
+#define IPA_EP_PER_REG 32
 
 #define __FILENAME__ \
 	(strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : __FILE__)
@@ -438,7 +440,7 @@ struct ipa_tz_unlock_reg_info {
  * @dma_addr: DMA address of this Rx packet
  */
 struct ipa_tx_suspend_irq_data {
-	u32 endpoints;
+	u32 endpoints[IPA_EP_ARR_SIZE];
 };
 
 extern const char *ipa_clients_strings[];

drivers/platform/msm/ipa/ipa_v3/ipa.c

@@ -3492,10 +3492,17 @@ static int ipa3_q6_clean_q6_flt_tbls(enum ipa_ip_type ip,
 	coal_ep = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS);
 	/* IC to close the coal frame before HPS Clear if coal is enabled */
 	if (coal_ep != IPA_EP_NOT_ALLOCATED) {
+		u32 offset = 0;
+
 		reg_write_coal_close.skip_pipeline_clear = false;
 		reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR;
-		reg_write_coal_close.offset = ipahal_get_reg_ofst(
+		if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
+			offset = ipahal_get_reg_ofst(
 				IPA_AGGR_FORCE_CLOSE);
+		else
+			offset = ipahal_get_ep_reg_offset(
+				IPA_AGGR_FORCE_CLOSE_n, coal_ep);
+		reg_write_coal_close.offset = offset;
 		ipahal_get_aggr_force_close_valmask(coal_ep, &valmask);
 		reg_write_coal_close.value = valmask.val;
 		reg_write_coal_close.value_mask = valmask.mask;
@@ -3653,11 +3660,18 @@ static int ipa3_q6_clean_q6_rt_tbls(enum ipa_ip_type ip,
 
 	/* IC to close the coal frame before HPS Clear if coal is enabled */
 	if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) {
+		u32 offset = 0;
+
 		i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS);
 		reg_write_coal_close.skip_pipeline_clear = false;
 		reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR;
-		reg_write_coal_close.offset = ipahal_get_reg_ofst(
+		if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
+			offset = ipahal_get_reg_ofst(
 				IPA_AGGR_FORCE_CLOSE);
+		else
+			offset = ipahal_get_ep_reg_offset(
+				IPA_AGGR_FORCE_CLOSE_n, i);
+		reg_write_coal_close.offset = offset;
 		ipahal_get_aggr_force_close_valmask(i, &valmask);
 		reg_write_coal_close.value = valmask.val;
 		reg_write_coal_close.value_mask = valmask.mask;
@@ -3777,11 +3791,18 @@ static int ipa3_q6_clean_q6_tables(void)
 
 	/* IC to close the coal frame before HPS Clear if coal is enabled */
 	if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) {
+		u32 offset = 0;
+
 		i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS);
 		reg_write_coal_close.skip_pipeline_clear = false;
 		reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR;
-		reg_write_coal_close.offset = ipahal_get_reg_ofst(
+		if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
+			offset = ipahal_get_reg_ofst(
 				IPA_AGGR_FORCE_CLOSE);
+		else
+			offset = ipahal_get_ep_reg_offset(
+				IPA_AGGR_FORCE_CLOSE_n, i);
+		reg_write_coal_close.offset = offset;
 		ipahal_get_aggr_force_close_valmask(i, &valmask);
 		reg_write_coal_close.value = valmask.val;
 		reg_write_coal_close.value_mask = valmask.mask;
@@ -3855,11 +3876,18 @@ static int ipa3_q6_set_ex_path_to_apps(void)
 
 	/* IC to close the coal frame before HPS Clear if coal is enabled */
 	if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) {
+		u32 offset = 0;
+
 		i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS);
 		reg_write_coal_close.skip_pipeline_clear = false;
 		reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR;
-		reg_write_coal_close.offset = ipahal_get_reg_ofst(
+		if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
+			offset = ipahal_get_reg_ofst(
 				IPA_AGGR_FORCE_CLOSE);
+		else
+			offset = ipahal_get_ep_reg_offset(
+				IPA_AGGR_FORCE_CLOSE_n, i);
+		reg_write_coal_close.offset = offset;
 		ipahal_get_aggr_force_close_valmask(i, &valmask);
 		reg_write_coal_close.value = valmask.val;
 		reg_write_coal_close.value_mask = valmask.mask;
@@ -4255,11 +4283,18 @@ int _ipa_init_hdr_v3_0(void)
 
 	/* IC to close the coal frame before HPS Clear if coal is enabled */
 	if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) {
+		u32 offset = 0;
+
 		i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS);
 		reg_write_coal_close.skip_pipeline_clear = false;
 		reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR;
-		reg_write_coal_close.offset = ipahal_get_reg_ofst(
+		if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
+			offset = ipahal_get_reg_ofst(
 				IPA_AGGR_FORCE_CLOSE);
+		else
+			offset = ipahal_get_ep_reg_offset(
+				IPA_AGGR_FORCE_CLOSE_n, i);
+		reg_write_coal_close.offset = offset;
 		ipahal_get_aggr_force_close_valmask(i, &valmask);
 		reg_write_coal_close.value = valmask.val;
 		reg_write_coal_close.value_mask = valmask.mask;
@@ -5721,26 +5756,42 @@ void ipa3_suspend_handler(enum ipa_irq_type interrupt,
 				void *private_data,
 				void *interrupt_data)
 {
-	u32 suspend_data =
+	u32 *suspend_data =
 		((struct ipa_tx_suspend_irq_data *)interrupt_data)->endpoints;
 	u32 bmsk = 1;
-	u32 i = 0;
+	u32 i = 0, j = 0, ep_arr_size, ep_per_reg;
 	int res;
-	struct ipa_ep_cfg_holb holb_cfg;
 	u32 pipe_bitmask = 0;
 
-	IPADBG("interrupt=%d, interrupt_data=%u\n",
+	IPADBG("interrupt=%d\n", interrupt);
-		interrupt, suspend_data);
-	memset(&holb_cfg, 0, sizeof(holb_cfg));
 
-	for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++, bmsk = bmsk << 1)
+	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) {
-		if ((suspend_data & bmsk) && (ipa3_ctx->ep[i].valid))
+		ep_arr_size = IPA_EP_ARR_SIZE;
+		ep_per_reg = IPA_EP_PER_REG;
+	} else {
+		ep_arr_size = 1;
+		ep_per_reg = ipa3_ctx->ipa_num_pipes;
+	}
+
+	j = 0;
+	for (i = 0; i < ipa3_ctx->ipa_num_pipes && j < ep_arr_size; i++) {
+		if ((suspend_data[j] & bmsk) && (ipa3_ctx->ep[i].valid))
 			pipe_bitmask |= bmsk;
-	res = ipa_pm_handle_suspend(pipe_bitmask);
+		bmsk = bmsk << 1;
+
+		if ((i % IPA_EP_PER_REG) == (ep_per_reg - 1)) {
+			IPADBG("interrupt data: %u\n", suspend_data[j]);
+			res = ipa_pm_handle_suspend(pipe_bitmask, j);
 			if (res) {
-		IPAERR("ipa_pm_handle_suspend failed %d\n", res);
+				IPAERR(
+				"ipa_pm_handle_suspend failed %d\n", res);
 				return;
 			}
+			pipe_bitmask = 0;
+			bmsk = 1;
+			j++;
+		}
+	}
 }
 
 /**

drivers/platform/msm/ipa/ipa_v3/ipa_client.c

@@ -1625,9 +1625,18 @@ int ipa3_xdci_suspend(u32 ul_clnt_hdl, u32 dl_clnt_hdl,
 	}
 
 	if (!dl_data_pending) {
-		aggr_active_bitmap = ipahal_read_reg(IPA_STATE_AGGR_ACTIVE);
+		if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) {
-		if (aggr_active_bitmap & (1 << dl_clnt_hdl)) {
+			aggr_active_bitmap =
-			IPADBG("DL/DPL data pending due to open aggr. frame\n");
+				ipahal_read_ep_reg(IPA_STATE_AGGR_ACTIVE_n,
+					dl_clnt_hdl);
+		} else {
+			aggr_active_bitmap =
+				ipahal_read_reg(IPA_STATE_AGGR_ACTIVE);
+		}
+		if (ipahal_test_ep_bit(aggr_active_bitmap, dl_clnt_hdl)) {
+			IPADBG(
+				"DL/DPL data pending due to open aggr. frame\n"
+			);
 			dl_data_pending = true;
 		}
 	}

drivers/platform/msm/ipa/ipa_v3/ipa_flt.c

@@ -580,11 +580,18 @@ int __ipa_commit_flt_v3(enum ipa_ip_type ip)
 
 	/* IC to close the coal frame before HPS Clear if coal is enabled */
 	if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) {
+		u32 offset = 0;
+
 		i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS);
 		reg_write_coal_close.skip_pipeline_clear = false;
 		reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR;
-		reg_write_coal_close.offset = ipahal_get_reg_ofst(
+		if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
+			offset = ipahal_get_reg_ofst(
 				IPA_AGGR_FORCE_CLOSE);
+		else
+			offset = ipahal_get_ep_reg_offset(
+				IPA_AGGR_FORCE_CLOSE_n, i);
+		reg_write_coal_close.offset = offset;
 		ipahal_get_aggr_force_close_valmask(i, &valmask);
 		reg_write_coal_close.value = valmask.val;
 		reg_write_coal_close.value_mask = valmask.mask;

drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c

@@ -195,11 +195,18 @@ int __ipa_commit_hdr_v3_0(void)
 
 	/* IC to close the coal frame before HPS Clear if coal is enabled */
 	if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) {
+		u32 offset = 0;
+
 		i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS);
 		reg_write_coal_close.skip_pipeline_clear = false;
 		reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR;
-		reg_write_coal_close.offset = ipahal_get_reg_ofst(
+		if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
+			offset = ipahal_get_reg_ofst(
 				IPA_AGGR_FORCE_CLOSE);
+		else
+			offset = ipahal_get_ep_reg_offset(
+				IPA_AGGR_FORCE_CLOSE_n, i);
+		reg_write_coal_close.offset = offset;
 		ipahal_get_aggr_force_close_valmask(i, &valmask);
 		reg_write_coal_close.value = valmask.val;
 		reg_write_coal_close.value_mask = valmask.mask;

drivers/platform/msm/ipa/ipa_v3/ipa_hw_stats.c

@@ -257,12 +257,18 @@ static void ipa_close_coal_frame(struct ipahal_imm_cmd_pyld **coal_cmd_pyld)
 	int i;
 	struct ipahal_reg_valmask valmask;
 	struct ipahal_imm_cmd_register_write reg_write_coal_close;
+	u32 offset = 0;
 
 	i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS);
 	reg_write_coal_close.skip_pipeline_clear = false;
 	reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR;
-	reg_write_coal_close.offset = ipahal_get_reg_ofst(
+	if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
+		offset = ipahal_get_reg_ofst(
 			IPA_AGGR_FORCE_CLOSE);
+	else
+		offset = ipahal_get_ep_reg_offset(
+			IPA_AGGR_FORCE_CLOSE_n, i);
+	reg_write_coal_close.offset = offset;
 	ipahal_get_aggr_force_close_valmask(i, &valmask);
 	reg_write_coal_close.value = valmask.val;
 	reg_write_coal_close.value_mask = valmask.mask;
@@ -306,6 +312,7 @@ int ipa_init_quota_stats(u32 pipe_bitmask)
 	dma_addr_t dma_address;
 	int ret;
 	int num_cmd = 0;
+	int ipa_ep_idx = IPA_EP_NOT_ALLOCATED;
 
 	if (!ipa3_ctx->hw_stats.enabled)
 		return 0;
@@ -338,8 +345,8 @@ int ipa_init_quota_stats(u32 pipe_bitmask)
 	}
 
 	/* IC to close the coal frame before HPS Clear if coal is enabled */
-	if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) !=
+	ipa_ep_idx = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS);
-		IPA_EP_NOT_ALLOCATED) {
+	if (ipa_ep_idx != IPA_EP_NOT_ALLOCATED) {
 		ipa_close_coal_frame(&coal_cmd_pyld);
 		if (!coal_cmd_pyld) {
 			IPAERR("failed to construct coal close IC\n");
@@ -353,8 +360,19 @@ int ipa_init_quota_stats(u32 pipe_bitmask)
 	/* setting the registers and init the stats pyld are done atomically */
 	quota_mask.skip_pipeline_clear = false;
 	quota_mask.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR;
+	if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) {
 		quota_mask.offset = ipahal_get_reg_n_ofst(IPA_STAT_QUOTA_MASK_n,
 			ipa3_ctx->ee);
+	} else {
+		if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) {
+			ret = -EFAULT;
+			goto destroy_coal_cmd;
+		}
+		quota_mask.offset = ipahal_get_ep_reg_n_offset(
+			IPA_STAT_QUOTA_MASK_EE_n_REG_k,
+			ipa3_ctx->ee,
+			ipa_ep_idx);
+	}
 	quota_mask.value = pipe_bitmask;
 	quota_mask.value_mask = ~0;
 	quota_mask_pyld = ipahal_construct_imm_cmd(IPA_IMM_CMD_REGISTER_WRITE,

drivers/platform/msm/ipa/ipa_v3/ipa_interrupts.c

@@ -85,13 +85,15 @@ static void ipa3_deferred_interrupt_work(struct work_struct *work)
 	kfree(work_data);
 }
 
-static bool ipa3_is_valid_ep(u32 ep_suspend_data)
+static bool ipa3_is_valid_ep(u32 ep_suspend_data, u8 ep_reg_idx)
 {
 	u32 bmsk = 1;
 	u32 i = 0;
+	u32 reg_add = ep_reg_idx << 5;
 
 	for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) {
-		if ((ep_suspend_data & bmsk) && (ipa3_ctx->ep[i].valid))
+		if ((ep_suspend_data & bmsk) &&
+			(ipa3_ctx->ep[i + reg_add].valid))
 			return true;
 		bmsk = bmsk << 1;
 	}
@@ -102,10 +104,11 @@ static int ipa3_handle_interrupt(int irq_num, bool isr_context)
 {
 	struct ipa3_interrupt_info interrupt_info;
 	struct ipa3_interrupt_work_wrap *work_data;
-	u32 suspend_data;
+	u32 suspend_data[IPA_EP_ARR_SIZE];
 	void *interrupt_data = NULL;
 	struct ipa_tx_suspend_irq_data *suspend_interrupt_data = NULL;
-	int res;
+	int res, i;
+	bool valid;
 
 	interrupt_info = ipa_interrupt_to_cb[irq_num];
 	if (interrupt_info.handler == NULL) {
@@ -118,16 +121,37 @@ static int ipa3_handle_interrupt(int irq_num, bool isr_context)
 	case IPA_TX_SUSPEND_IRQ:
 		IPADBG_LOW("processing TX_SUSPEND interrupt\n");
 		ipa3_tx_suspend_interrupt_wa();
-		suspend_data = ipahal_read_reg_n(IPA_SUSPEND_IRQ_INFO_EE_n,
+		valid = 0;
+		if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) {
+			for (i = 0; i < IPA_EP_ARR_SIZE; i++) {
+				suspend_data[i] = ipahal_read_reg_nk(
+					IPA_SUSPEND_IRQ_INFO_EE_n_REG_k,
+					ipa_ee, i);
+				if (ipa3_is_valid_ep(suspend_data[i], i))
+					valid = true;
+				IPADBG_LOW("get interrupt %d\n",
+					suspend_data[i]);
+
+				/* Clearing L2 interrupts status */
+				ipahal_write_reg_nk(
+					IPA_SUSPEND_IRQ_CLR_EE_n_REG_k,
+					ipa_ee, i, suspend_data[i]);
+			}
+		} else {
+			suspend_data[0] = ipahal_read_reg_n(
+				IPA_SUSPEND_IRQ_INFO_EE_n,
 				ipa_ee);
-		IPADBG_LOW("get interrupt %d\n", suspend_data);
+			if (ipa3_is_valid_ep(suspend_data[0], 0))
+				valid = true;
+			IPADBG_LOW("get interrupt %d\n", suspend_data[0]);
 
 			if (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_1) {
 				/* Clearing L2 interrupts status */
 				ipahal_write_reg_n(IPA_SUSPEND_IRQ_CLR_EE_n,
-				ipa_ee, suspend_data);
+					ipa_ee, suspend_data[0]);
 			}
-		if (!ipa3_is_valid_ep(suspend_data))
+		}
+		if (!valid)
 			return 0;
 
 		suspend_interrupt_data =
@@ -136,7 +160,9 @@ static int ipa3_handle_interrupt(int irq_num, bool isr_context)
 			IPAERR("failed allocating suspend_interrupt_data\n");
 			return -ENOMEM;
 		}
-		suspend_interrupt_data->endpoints = suspend_data;
+
+		for (i = 0; i < IPA_EP_ARR_SIZE; i++)
+			suspend_interrupt_data->endpoints[i] = suspend_data[i];
 		interrupt_data = suspend_interrupt_data;
 		break;
 	default:
@@ -370,7 +396,8 @@ int ipa3_add_interrupt_handler(enum ipa_irq_type interrupt,
 		bool deferred_flag,
 		void *private_data)
 {
-	u32 val;
+	u32 val, i;
+	u32 pipe_bmsk[IPA_EP_ARR_SIZE] = {0, 0};
 	u32 bmsk;
 	int irq_num;
 	int client_idx, ep_idx;
@@ -405,22 +432,48 @@ int ipa3_add_interrupt_handler(enum ipa_irq_type interrupt,
 	/* register SUSPEND_IRQ_EN_EE_n_ADDR for L2 interrupt*/
 	if ((interrupt == IPA_TX_SUSPEND_IRQ) &&
 		(ipa3_ctx->ipa_hw_type >= IPA_HW_v3_1)) {
+		if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) {
+			for (client_idx = 0;
+				client_idx < IPA_CLIENT_MAX;
+				client_idx++) {
+				ep_idx = ipa3_get_ep_mapping(client_idx);
+				if ((ep_idx != IPA_EP_NOT_ALLOCATED) &&
+					!(IPA_CLIENT_IS_Q6_CONS(client_idx) ||
+					IPA_CLIENT_IS_Q6_PROD(client_idx))) {
+				pipe_bmsk[ipahal_get_ep_reg_idx(ep_idx)] |=
+					ipahal_get_ep_bit(ep_idx);
+				}
+			}
+			for (i = 0; i < IPA_EP_ARR_SIZE; i++) {
+				ipahal_write_reg_nk(
+					IPA_SUSPEND_IRQ_EN_EE_n_REG_k,
+					ipa_ee, i, pipe_bmsk[i]);
+				IPADBG(
+					"wrote IPA_SUSPEND_IRQ_EN_EE_n_REG_k m = %u pipe_bmsk[i] = %d\n"
+					, i, pipe_bmsk[i]);
+			}
+		} else {
 			val = ~0;
-		for (client_idx = 0; client_idx < IPA_CLIENT_MAX; client_idx++)
+			for (client_idx = 0;
+				client_idx < IPA_CLIENT_MAX;
+				client_idx++) {
 				if (IPA_CLIENT_IS_Q6_CONS(client_idx) ||
 					IPA_CLIENT_IS_Q6_PROD(client_idx)) {
 					ep_idx = ipa3_get_ep_mapping(client_idx);
-				IPADBG("modem ep_idx(%d) client_idx = %d\n",
+					IPADBG(
-					ep_idx, client_idx);
+						"modem ep_idx(%d) client_idx = %d\n"
+						, ep_idx, client_idx);
 					if (ep_idx == -1)
 						IPADBG("Invalid IPA client\n");
 					else
 						val &= ~(1 << ep_idx);
 				}
+			}
 
 			ipahal_write_reg_n(IPA_SUSPEND_IRQ_EN_EE_n, ipa_ee, val);
 			IPADBG("wrote IPA_SUSPEND_IRQ_EN_EE_n reg = %d\n", val);
 		}
+	}
 	return 0;
 }
 
@@ -432,7 +485,7 @@ int ipa3_add_interrupt_handler(enum ipa_irq_type interrupt,
  */
 int ipa3_remove_interrupt_handler(enum ipa_irq_type interrupt)
 {
-	u32 val;
+	u32 val, i;
 	u32 bmsk;
 	int irq_num;
 
@@ -458,9 +511,20 @@ int ipa3_remove_interrupt_handler(enum ipa_irq_type interrupt)
 	/* clean SUSPEND_IRQ_EN_EE_n_ADDR for L2 interrupt */
 	if ((interrupt == IPA_TX_SUSPEND_IRQ) &&
 		(ipa3_ctx->ipa_hw_type >= IPA_HW_v3_1)) {
+		if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) {
+			for (i = 0; i < IPA_EP_ARR_SIZE; i++) {
+				ipahal_write_reg_nk(
+					IPA_SUSPEND_IRQ_EN_EE_n_REG_k,
+					ipa_ee, i, 0);
+				IPADBG(
+					"wrote IPA_SUSPEND_IRQ_EN_EE_n_REG_k k %u val = %d\n"
+					, i, 0);
+			}
+		} else {
 			ipahal_write_reg_n(IPA_SUSPEND_IRQ_EN_EE_n, ipa_ee, 0);
 			IPADBG("wrote IPA_SUSPEND_IRQ_EN_EE_n reg = %d\n", 0);
 		}
+	}
 
 	val = ipahal_read_reg_n(IPA_IRQ_EN_EE_n, ipa_ee);
 	bmsk = 1 << irq_num;
@@ -570,11 +634,26 @@ void ipa3_suspend_active_aggr_wa(u32 clnt_hdl)
 	struct ipa3_interrupt_work_wrap *work_data;
 	struct ipa_tx_suspend_irq_data *suspend_interrupt_data;
 	int irq_num;
-	int aggr_active_bitmap = ipahal_read_reg(IPA_STATE_AGGR_ACTIVE);
+	int aggr_active_bitmap;
 
-	if (aggr_active_bitmap & (1 << clnt_hdl)) {
+	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) {
+		aggr_active_bitmap =
+			ipahal_read_ep_reg(IPA_STATE_AGGR_ACTIVE_n,
+				clnt_hdl);
+	} else {
+		aggr_active_bitmap =
+			ipahal_read_reg(IPA_STATE_AGGR_ACTIVE);
+	}
+
+	if (ipahal_test_ep_bit(aggr_active_bitmap, clnt_hdl)) {
 		/* force close aggregation */
-		ipahal_write_reg(IPA_AGGR_FORCE_CLOSE, (1 << clnt_hdl));
+		if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0)
+			ipahal_write_ep_reg(IPA_AGGR_FORCE_CLOSE_n,
+				clnt_hdl,
+				ipahal_get_ep_bit(clnt_hdl));
+		else
+			ipahal_write_reg(IPA_AGGR_FORCE_CLOSE,
+				ipahal_get_ep_bit(clnt_hdl));
 
 		/* simulate suspend IRQ */
 		irq_num = ipa3_irq_mapping[IPA_TX_SUSPEND_IRQ];
@@ -590,7 +669,10 @@ void ipa3_suspend_active_aggr_wa(u32 clnt_hdl)
 			IPAERR("failed allocating suspend_interrupt_data\n");
 			return;
 		}
-		suspend_interrupt_data->endpoints = 1 << clnt_hdl;
+		suspend_interrupt_data->endpoints[
+			ipahal_get_ep_reg_idx(clnt_hdl)
+		] =
+			ipahal_get_ep_bit(clnt_hdl);
 
 		work_data = kzalloc(sizeof(struct ipa3_interrupt_work_wrap),
 				GFP_ATOMIC);

drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c

@@ -721,19 +721,25 @@ bool ipa3_has_open_aggr_frame(enum ipa_client_type client)
 	u32 aggr_state_active;
 	int ipa_ep_idx;
 
-	aggr_state_active = ipahal_read_reg(IPA_STATE_AGGR_ACTIVE);
-	IPA_MHI_DBG_LOW("IPA_STATE_AGGR_ACTIVE_OFST 0x%x\n", aggr_state_active);
-
 	ipa_ep_idx = ipa_get_ep_mapping(client);
 	if (ipa_ep_idx == -1) {
 		ipa_assert();
 		return false;
 	}
 
-	if ((1 << ipa_ep_idx) & aggr_state_active)
+	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) {
-		return true;
+		aggr_state_active =
+			ipahal_read_ep_reg(IPA_STATE_AGGR_ACTIVE_n,
+				ipa_ep_idx);
+	} else {
+		aggr_state_active =
+			ipahal_read_reg(IPA_STATE_AGGR_ACTIVE);
+	}
 
-	return false;
+	IPA_MHI_DBG_LOW("IPA_STATE_AGGR_ACTIVE_OFST 0x%x, ep_idx %d\n",
+		ipa_ep_idx, aggr_state_active);
+
+	return ipahal_test_ep_bit(aggr_state_active, ipa_ep_idx);
 }
 EXPORT_SYMBOL(ipa3_has_open_aggr_frame);
 

drivers/platform/msm/ipa/ipa_v3/ipa_mpm.c

@@ -495,11 +495,18 @@ static int ipa_mpm_set_dma_mode(enum ipa_client_type src_pipe,
 
 	/* First step is to clear IPA Pipeline before changing DMA mode */
 	if (ipa3_get_ep_mapping(src_pipe) != IPA_EP_NOT_ALLOCATED) {
+		u32 offset = 0;
+
 		i = ipa3_get_ep_mapping(src_pipe);
 		reg_write_coal_close.skip_pipeline_clear = false;
 		reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR;
-		reg_write_coal_close.offset = ipahal_get_reg_ofst(
+		if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
+			offset = ipahal_get_reg_ofst(
 				IPA_AGGR_FORCE_CLOSE);
+		else
+			offset = ipahal_get_ep_reg_offset(
+				IPA_AGGR_FORCE_CLOSE_n, i);
+		reg_write_coal_close.offset = offset;
 		ipahal_get_aggr_force_close_valmask(i, &valmask);
 		reg_write_coal_close.value = valmask.val;
 		reg_write_coal_close.value_mask = valmask.mask;

drivers/platform/msm/ipa/ipa_v3/ipa_nat.c

@@ -1156,11 +1156,18 @@ static int ipa3_nat_send_init_cmd(struct ipahal_imm_cmd_ip_v4_nat_init *cmd,
 
 	/* IC to close the coal frame before HPS Clear if coal is enabled */
 	if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) {
+		u32 offset = 0;
+
 		i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS);
 		reg_write_coal_close.skip_pipeline_clear = false;
 		reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR;
-		reg_write_coal_close.offset = ipahal_get_reg_ofst(
+		if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
+			offset = ipahal_get_reg_ofst(
 				IPA_AGGR_FORCE_CLOSE);
+		else
+			offset = ipahal_get_ep_reg_offset(
+				IPA_AGGR_FORCE_CLOSE_n, i);
+		reg_write_coal_close.offset = offset;
 		ipahal_get_aggr_force_close_valmask(i, &valmask);
 		reg_write_coal_close.value = valmask.val;
 		reg_write_coal_close.value_mask = valmask.mask;
@@ -1259,11 +1266,17 @@ static int ipa3_ipv6ct_send_init_cmd(struct ipahal_imm_cmd_ip_v6_ct_init *cmd)
 
 	/* IC to close the coal frame before HPS Clear if coal is enabled */
 	if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) {
+		u32 offset = 0;
 		i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS);
 		reg_write_coal_close.skip_pipeline_clear = false;
 		reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR;
-		reg_write_coal_close.offset = ipahal_get_reg_ofst(
+		if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
+			offset = ipahal_get_reg_ofst(
 				IPA_AGGR_FORCE_CLOSE);
+		else
+			offset = ipahal_get_ep_reg_offset(
+				IPA_AGGR_FORCE_CLOSE_n, i);
+		reg_write_coal_close.offset = offset;
 		ipahal_get_aggr_force_close_valmask(i, &valmask);
 		reg_write_coal_close.value = valmask.val;
 		reg_write_coal_close.value_mask = valmask.mask;
@@ -1932,11 +1945,18 @@ int ipa3_table_dma_cmd(
 
 	/* IC to close the coal frame before HPS Clear if coal is enabled */
 	if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) {
+		u32 offset = 0;
+
 		i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS);
 		reg_write_coal_close.skip_pipeline_clear = false;
 		reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR;
-		reg_write_coal_close.offset = ipahal_get_reg_ofst(
+		if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
+			offset = ipahal_get_reg_ofst(
 				IPA_AGGR_FORCE_CLOSE);
+		else
+			offset = ipahal_get_ep_reg_offset(
+				IPA_AGGR_FORCE_CLOSE_n, i);
+		reg_write_coal_close.offset = offset;
 		ipahal_get_aggr_force_close_valmask(i, &valmask);
 		reg_write_coal_close.value = valmask.val;
 		reg_write_coal_close.value_mask = valmask.mask;

drivers/platform/msm/ipa/ipa_v3/ipa_pm.c

@@ -1201,14 +1201,17 @@ EXPORT_SYMBOL(ipa_pm_deactivate_sync);
 /**
  * ipa_pm_handle_suspend(): calls the callbacks of suspended clients to wake up
  * @pipe_bitmask: the bits represent the indexes of the clients to be woken up
+ * @pipe_arr_idx: if larger than 0 add to pipe num 32 * pipe_arr_idx
  *
  * Returns: 0 on success, negative on failure
  */
-int ipa_pm_handle_suspend(u32 pipe_bitmask)
+int ipa_pm_handle_suspend(u32 pipe_bitmask, u32 pipe_arr_idx)
 {
 	int i;
 	struct ipa_pm_client *client;
 	bool client_notified[IPA_PM_MAX_CLIENTS] = { false };
+	u32 pipe_add;
+	u32 max_pipes;
 
 	if (ipa_pm_ctx == NULL) {
 		IPA_PM_ERR("PM_ctx is null\n");
@@ -1220,10 +1223,12 @@ int ipa_pm_handle_suspend(u32 pipe_bitmask)
 	if (pipe_bitmask == 0)
 		return 0;
 
+	pipe_add = pipe_arr_idx * 32;
+	max_pipes = IPA3_MAX_NUM_PIPES;
 	mutex_lock(&ipa_pm_ctx->client_mutex);
-	for (i = 0; i < IPA3_MAX_NUM_PIPES; i++) {
+	for (i = 0; i < IPA_EP_PER_REG && (i + pipe_add) < max_pipes; i++) {
 		if (pipe_bitmask & (1 << i)) {
-			client = ipa_pm_ctx->clients_by_pipe[i];
+			client = ipa_pm_ctx->clients_by_pipe[i + pipe_add];
 			if (client && !client_notified[client->hdl]) {
 				if (client->callback) {
 					client->callback(client->callback_params

drivers/platform/msm/ipa/ipa_v3/ipa_pm.h

@@ -96,7 +96,7 @@ int ipa_pm_deregister(u32 hdl);
 /* IPA Internal Functions */
 int ipa_pm_init(struct ipa_pm_init_params *params);
 int ipa_pm_destroy(void);
-int ipa_pm_handle_suspend(u32 pipe_bitmask);
+int ipa_pm_handle_suspend(u32 pipe_bitmask, u32 pipe_arr_idx);
 int ipa_pm_deactivate_all_deferred(void);
 int ipa_pm_stat(char *buf, int size);
 int ipa_pm_exceptions_stat(char *buf, int size);
@@ -157,7 +157,7 @@ static inline int ipa_pm_destroy(void)
 	return -EPERM;
 }
 
-static inline int ipa_pm_handle_suspend(u32 pipe_bitmask)
+static inline int ipa_pm_handle_suspend(u32 pipe_bitmask, u32 pipe_arr_idx)
 {
 	return -EPERM;
 }

drivers/platform/msm/ipa/ipa_v3/ipa_rt.c

@@ -570,11 +570,18 @@ int __ipa_commit_rt_v3(enum ipa_ip_type ip)
 
 	/* IC to close the coal frame before HPS Clear if coal is enabled */
 	if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) {
+		u32 offset = 0;
+
 		i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS);
 		reg_write_coal_close.skip_pipeline_clear = false;
 		reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR;
-		reg_write_coal_close.offset = ipahal_get_reg_ofst(
+		if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
+			offset = ipahal_get_reg_ofst(
 				IPA_AGGR_FORCE_CLOSE);
+		else
+			offset = ipahal_get_ep_reg_offset(
+				IPA_AGGR_FORCE_CLOSE_n, i);
+		reg_write_coal_close.offset = offset;
 		ipahal_get_aggr_force_close_valmask(i, &valmask);
 		reg_write_coal_close.value = valmask.val;
 		reg_write_coal_close.value_mask = valmask.mask;

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

@@ -4734,6 +4734,7 @@ static void ipa_cfg_qtime(void)
 	gran_cfg.gran_0 = IPA_TIMERS_TIME_GRAN_100_USEC;
 	gran_cfg.gran_1 = IPA_TIMERS_TIME_GRAN_1_MSEC;
 	gran_cfg.gran_2 = IPA_TIMERS_TIME_GRAN_1_MSEC;
+	gran_cfg.gran_3 = IPA_TIMERS_TIME_GRAN_1_MSEC;
 	val = ipahal_read_reg(IPA_TIMERS_PULSE_GRAN_CFG);
 	IPADBG("timer pulse granularity before cfg: 0x%x\n", val);
 	ipahal_write_reg_fields(IPA_TIMERS_PULSE_GRAN_CFG, &gran_cfg);
@@ -5845,7 +5846,7 @@ static int ipa3_process_timer_cfg(u32 time_us,
 
 	gran0_step = ipa3_time_gran_usec_step(gran_cfg.gran_0);
 	gran1_step = ipa3_time_gran_usec_step(gran_cfg.gran_1);
-	/* gran_2 is not used by AP */
+	/* gran_2 and gran_3 are not used by AP */
 
 	IPADBG("gran0 usec step=%u  gran1 usec step=%u\n",
 		gran0_step, gran1_step);
@@ -7235,11 +7236,18 @@ int ipa3_tag_process(struct ipa3_desc desc[],
 
 	/* IC to close the coal frame before HPS Clear if coal is enabled */
 	if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) {
+		u32 offset = 0;
+
 		ep_idx = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS);
 		reg_write_coal_close.skip_pipeline_clear = false;
 		reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR;
-		reg_write_coal_close.offset = ipahal_get_reg_ofst(
+		if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
+			offset = ipahal_get_reg_ofst(
 				IPA_AGGR_FORCE_CLOSE);
+		else
+			offset = ipahal_get_ep_reg_offset(
+				IPA_AGGR_FORCE_CLOSE_n, ep_idx);
+		reg_write_coal_close.offset = offset;
 		ipahal_get_aggr_force_close_valmask(ep_idx, &valmask);
 		reg_write_coal_close.value = valmask.val;
 		reg_write_coal_close.value_mask = valmask.mask;
@@ -7423,6 +7431,7 @@ static int ipa3_tag_generate_force_close_desc(struct ipa3_desc desc[],
 	struct ipahal_imm_cmd_register_write reg_write_agg_close;
 	struct ipahal_imm_cmd_pyld *cmd_pyld;
 	struct ipahal_reg_valmask valmask;
+	u32 offset = 0;
 
 	for (i = start_pipe; i < end_pipe; i++) {
 		ipahal_read_reg_n_fields(IPA_ENDP_INIT_AGGR_n, i, &ep_aggr);
@@ -7438,8 +7447,13 @@ static int ipa3_tag_generate_force_close_desc(struct ipa3_desc desc[],
 		reg_write_agg_close.skip_pipeline_clear = false;
 		reg_write_agg_close.pipeline_clear_options =
 			IPAHAL_FULL_PIPELINE_CLEAR;
-		reg_write_agg_close.offset =
+		if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
-			ipahal_get_reg_ofst(IPA_AGGR_FORCE_CLOSE);
+			offset = ipahal_get_reg_ofst(
+				IPA_AGGR_FORCE_CLOSE);
+		else
+			offset = ipahal_get_ep_reg_offset(
+				IPA_AGGR_FORCE_CLOSE_n, i);
+		reg_write_agg_close.offset = offset;
 		ipahal_get_aggr_force_close_valmask(i, &valmask);
 		reg_write_agg_close.value = valmask.val;
 		reg_write_agg_close.value_mask = valmask.mask;
@@ -7634,6 +7648,12 @@ EXPORT_SYMBOL(ipa3_get_transport_type);
 
 u32 ipa3_get_num_pipes(void)
 {
+	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) {
+		struct ipahal_ipa_flavor_0 ipa_flavor;
+
+		ipahal_read_reg_fields(IPA_FLAVOR_0, &ipa_flavor);
+		return ipa_flavor.ipa_pipes;
+	}
 	return ipahal_read_reg(IPA_ENABLED_PIPES);
 }
 
@@ -8539,7 +8559,7 @@ void ipa3_force_close_coal(void)
 
 int ipa3_suspend_apps_pipes(bool suspend)
 {
-	int res;
+	int res, i;
 
 	/* As per HPG first need start/stop coalescing channel
 	 * then default one. Coalescing client number was greater then
@@ -8585,6 +8605,18 @@ int ipa3_suspend_apps_pipes(bool suspend)
 
 		usleep_range(IPA_TAG_SLEEP_MIN_USEC, IPA_TAG_SLEEP_MAX_USEC);
 
+		if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) {
+			for (i = 0; i < IPA_EP_ARR_SIZE; i++) {
+				res = ipahal_read_reg_nk(
+					IPA_SUSPEND_IRQ_INFO_EE_n_REG_k,
+					ipa3_ctx->ee, i);
+				if (res) {
+					IPADBG("suspend irq is pending 0x%x\n",
+						res);
+					goto undo_qmap_cons;
+				}
+			}
+		} else {
 			res = ipahal_read_reg_n(IPA_SUSPEND_IRQ_INFO_EE_n,
 				ipa3_ctx->ee);
 			if (res) {
@@ -8592,6 +8624,7 @@ int ipa3_suspend_apps_pipes(bool suspend)
 				goto undo_qmap_cons;
 			}
 		}
+	}
 do_prod:
 	res = _ipa_suspend_resume_pipe(IPA_CLIENT_APPS_LAN_PROD, suspend);
 	if (res == -EAGAIN)
@@ -8680,6 +8713,7 @@ int ipa3_allocate_coal_close_frame(void)
 	struct ipahal_imm_cmd_register_write reg_write_cmd = { 0 };
 	struct ipahal_reg_valmask valmask;
 	int ep_idx;
+	u32 offset = 0;
 
 	ep_idx = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS);
 	if (ep_idx == IPA_EP_NOT_ALLOCATED)
@@ -8687,7 +8721,13 @@ int ipa3_allocate_coal_close_frame(void)
 	IPADBG("Allocate coal close frame cmd\n");
 	reg_write_cmd.skip_pipeline_clear = false;
 	reg_write_cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR;
-	reg_write_cmd.offset = ipahal_get_reg_ofst(IPA_AGGR_FORCE_CLOSE);
+	if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
+		offset = ipahal_get_reg_ofst(
+			IPA_AGGR_FORCE_CLOSE);
+	else
+		offset = ipahal_get_ep_reg_offset(
+			IPA_AGGR_FORCE_CLOSE_n, ep_idx);
+	reg_write_cmd.offset = offset;
 	ipahal_get_aggr_force_close_valmask(ep_idx, &valmask);
 	reg_write_cmd.value = valmask.val;
 	reg_write_cmd.value_mask = valmask.mask;

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h

@@ -142,6 +142,13 @@ enum ipahal_reg_name {
 	IPA_ENDP_GSI_CFG_TLV_n,
 	IPA_COAL_EVICT_LRU,
 	IPA_COAL_QMAP_CFG,
+	IPA_FLAVOR_0,
+	IPA_STATE_AGGR_ACTIVE_n,
+	IPA_AGGR_FORCE_CLOSE_n,
+	IPA_STAT_QUOTA_MASK_EE_n_REG_k,
+	IPA_SUSPEND_IRQ_INFO_EE_n_REG_k,
+	IPA_SUSPEND_IRQ_CLR_EE_n_REG_k,
+	IPA_SUSPEND_IRQ_EN_EE_n_REG_k,
 	IPA_REG_MAX,
 };
 
@@ -333,6 +340,7 @@ struct ipahal_reg_timers_pulse_gran_cfg {
 	enum ipa_timers_time_gran_type gran_0;
 	enum ipa_timers_time_gran_type gran_1;
 	enum ipa_timers_time_gran_type gran_2;
+	enum ipa_timers_time_gran_type gran_3;
 };
 
 /*
@@ -633,6 +641,7 @@ struct ipahal_reg_tx_cfg {
 	u32 pa_mask_en;
 	bool dual_tx_enable;
 	bool sspnd_pa_no_start_state;
+	bool holb_sticky_drop_en;
 };
 
 /*
@@ -697,6 +706,20 @@ struct ipahal_reg_coal_qmap_cfg {
 	u32 mux_id_byte_sel;
 };
 
+/*
+ * struct ipahal_ipa_flavor_0 - IPA_FLAVOR_0 register
+ * @ipa_pipes: Number of supported pipes
+ * @ipa_cons_pipes: Number of consumer pipes
+ * @ipa_prod_pipes: Number of producer pipes
+ * @ipa_prod_lowest: Number of first producer pipe
+ */
+struct ipahal_ipa_flavor_0 {
+	u8 ipa_pipes;
+	u8 ipa_cons_pipes;
+	u8 ipa_prod_pipes;
+	u8 ipa_prod_lowest;
+};
+
 /*
  * ipahal_print_all_regs() - Loop and read and print all the valid registers
  *  Parameterized registers are also printed for all the valid ranges.
@@ -720,11 +743,33 @@ u32 ipahal_read_reg_n(enum ipahal_reg_name reg, u32 n);
  */
 u32 ipahal_read_reg_mn(enum ipahal_reg_name reg, u32 m, u32 n);
 
+/*
+* ipahal_read_reg_nk() - Read from n/k parameterized reg
+*/
+static inline u32 ipahal_read_reg_nk(enum ipahal_reg_name reg, u32 n, u32 k)
+{
+	return ipahal_read_reg_mn(reg, k, n);
+}
+
+/*
+* ipahal_read_ep_reg_n() - Get n parameterized reg value according to ep
+*/
+u32 ipahal_read_ep_reg_n(enum ipahal_reg_name reg, u32 n, u32 ep_num);
+
 /*
  * ipahal_write_reg_mn() - Write to m/n parameterized reg a raw value
  */
 void ipahal_write_reg_mn(enum ipahal_reg_name reg, u32 m, u32 n, u32 val);
 
+/*
+* ipahal_write_reg_nk() - Write to n/k parameterized reg a raw value
+*/
+static inline void ipahal_write_reg_nk(
+	enum ipahal_reg_name reg, u32 n, u32 k, u32 val)
+{
+	ipahal_write_reg_mn(reg, k, n, val);
+}
+
 /*
  * ipahal_write_reg_n() - Write to n parameterized reg a raw value
  */
@@ -753,6 +798,26 @@ static inline u32 ipahal_read_reg(enum ipahal_reg_name reg)
 	return ipahal_read_reg_n(reg, 0);
 }
 
+/*
+ * ipahal_read_ep_reg() - Get the raw value of a ep reg
+ */
+u32 ipahal_read_ep_reg(enum ipahal_reg_name reg, u32 ep_num);
+
+/*
+ * ipahal_test_ep_bit() - return true if a ep bit is set
+ */
+bool ipahal_test_ep_bit(u32 reg_val, u32 ep_num);
+
+/*
+ * ipahal_get_ep_bit() - get ep bit set in the right offset
+ */
+u32 ipahal_get_ep_bit(u32 ep_num);
+
+/*
+ * ipahal_get_ep_reg_idx() - get ep reg index according to ep num
+ */
+u32 ipahal_get_ep_reg_idx(u32 ep_num);
+
 /*
  * ipahal_write_reg() - Write to reg a raw value
  */
@@ -779,11 +844,26 @@ static inline void ipahal_write_reg_fields(enum ipahal_reg_name reg,
 	ipahal_write_reg_n_fields(reg, 0, fields);
 }
 
+/*
+ * ipahal_write_ep_reg() - Write to ep reg a raw value
+ */
+void ipahal_write_ep_reg(enum ipahal_reg_name reg, u32 ep_num, u32 val);
+
+/*
+ * ipahal_write_ep_reg_n() - Write to ep reg a raw value
+ */
+void ipahal_write_ep_reg_n(enum ipahal_reg_name reg, u32 n, u32 ep_num, u32 val);
+
 /*
  * Get the offset of a m/n parameterized register
  */
 u32 ipahal_get_reg_mn_ofst(enum ipahal_reg_name reg, u32 m, u32 n);
 
+/*
+* Get the offset of a ep n register according to ep index and n
+*/
+u32 ipahal_get_ep_reg_n_offset(enum ipahal_reg_name reg, u32 n, u32 ep_num);
+
 /*
  * Get the offset of a n parameterized register
  */
@@ -792,6 +872,11 @@ static inline u32 ipahal_get_reg_n_ofst(enum ipahal_reg_name reg, u32 n)
 	return ipahal_get_reg_mn_ofst(reg, 0, n);
 }
 
+/*
+ * Get the offset of a ep register according to ep index
+ */
+u32 ipahal_get_ep_reg_offset(enum ipahal_reg_name reg, u32 ep_num);
+
 /*
  * Get the offset of a register
  */

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h

@@ -14,8 +14,20 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type);
 #define IPA_GETFIELD_FROM_REG(reg, shift, mask) \
 		(((reg) & (mask)) >> (shift))
 
-
 /* IPA_ROUTE register */
+#define IPA_ROUTE_ROUTE_DEF_PIPE_SHFT_v5_0 0
+#define IPA_ROUTE_ROUTE_DEF_PIPE_BMSK_v5_0 0xFF
+#define IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_SHFT_v5_0 8
+#define IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_BMSK_v5_0 0xFF00
+#define IPA_ROUTE_ROUTE_DEF_HDR_OFST_SHFT_v5_0 16
+#define IPA_ROUTE_ROUTE_DEF_HDR_OFST_BMSK_v5_0 0x3ff00
+#define IPA_ROUTE_ROUTE_DEF_HDR_TABLE_SHFT_v5_0 26
+#define IPA_ROUTE_ROUTE_DEF_HDR_TABLE_BMSK_v5_0 0X4000000
+#define IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_SHFT_v5_0 27
+#define IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_BMSK_v5_0  0x8000000
+#define IPA_ROUTE_ROUTE_DIS_SHFT_v5_0 28
+#define IPA_ROUTE_ROUTE_DIS_BMSK_v5_0 0x10000000
+
 #define IPA_ROUTE_ROUTE_DIS_SHFT 0x0
 #define IPA_ROUTE_ROUTE_DIS_BMSK 0x1
 #define IPA_ROUTE_ROUTE_DEF_PIPE_SHFT 0x1
@@ -91,6 +103,11 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type);
 #define IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_SHFT_v4_5 0x14
 #define IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_BMSK_v4_5 0x300000
 
+#define IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_VALID_SHFT_v5_0 0x16
+#define IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_VALID_BMSK_v5_0 0x400000
+#define IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_SHFT_v5_0 0x18
+#define IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_BMSK_v5_0 0xFF000000
+
 /* IPA_ENDP_INIT_AGGR_n register */
 #define IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_BMSK	0x1000000
 #define IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_SHFT	0x18
@@ -139,8 +156,11 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type);
 #define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_2 0
 #define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_5 0x7fffffff
 #define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_5 0
-#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_7 0x7fffff
+#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_9 0x7fffff
-#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_7 0
+#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_9 0
+#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_v5_0 0xffffffff
+#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_2_v5_0 0xf
+#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V5_0 0
 
 /* IPA_ENDP_INIT_ROUTE_n register */
 #define IPA_ENDP_INIT_ROUTE_n_ROUTE_TABLE_INDEX_BMSK 0x1f
@@ -173,6 +193,9 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type);
 #define IPA_ENDP_INIT_MODE_n_MODE_BMSK_V4_5 0x7
 #define IPA_ENDP_INIT_MODE_n_MODE_SHFT_V4_5 0x0
 
+#define IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK_V5_0 0xff0
+#define IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT_V5_0 0x4
+
 /* IPA_ENDP_INIT_NAT_n register */
 #define IPA_ENDP_INIT_NAT_n_NAT_EN_BMSK 0x3
 #define IPA_ENDP_INIT_NAT_n_NAT_EN_SHFT 0x0
@@ -210,7 +233,12 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type);
 #define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_BMSK_V4_5 0x1F
 #define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_SHFT_V4_5 0
 #define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_BMSK_V4_5 0x100
-#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_SHFT_V4_5 8
+#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_SHFT_V4_5 0x8
+
+#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_BMSK_V5_0 0x1F
+#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_SHFT_V5_0 0
+#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_BMSK_V5_0 0x300
+#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_SHFT_V5_0 0x8
 
 /* IPA_ENDP_INIT_DEAGGR_n register */
 #define IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_BMSK 0xFFFF0000
@@ -269,6 +297,8 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type);
 #define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v4_5 0
 #define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v4_9 0x3
 #define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v4_9 0
+#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v5_0 0x7
+#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v5_0 0
 
 /* IPA_SHARED_MEM_SIZE register */
 #define IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_BMSK 0xffff0000
@@ -323,6 +353,9 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type);
 #define IPA_ENDP_STATUS_n_STATUS_EN_BMSK 0x1
 #define IPA_ENDP_STATUS_n_STATUS_EN_SHFT 0x0
 
+#define IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK_V5_0 0x1fe
+#define IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT_V5_0 0x1
+
 /* IPA_CLKON_CFG register */
 #define IPA_CLKON_CFG_CGC_OPEN_DPL_FIFO_BMSK_V4_5  0x40000000
 #define IPA_CLKON_CFG_CGC_OPEN_DPL_FIFO_SHFT_V4_5 30
@@ -501,6 +534,8 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type);
 #define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_BMSK_V3_5 (0x1C)
 #define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_SHFT_V3_5 (2)
 
+#define IPA_TX_CFG_HOLB_STICKY_DROP_EN_BMSK_v5_0 (0x100000)
+#define IPA_TX_CFG_HOLB_STICKY_DROP_EN_SHFT_v5_0 (0x14)
 #define IPA_TX_CFG_SSPND_PA_NO_START_STATE_BMSK_V4_9 (0x40000)
 #define IPA_TX_CFG_SSPND_PA_NO_START_STATE_SHFT_V4_9 (0x12)
 #define IPA_TX_CFG_DUAL_TX_ENABLE_BMSK_V4_5 (0x20000)
@@ -703,4 +738,31 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type);
 #define IPA_STATE_TX_WRAPPER_TX0_IDLE_BMSK_v4_7 0x1
 #define IPA_STATE_TX_WRAPPER_TX0_IDLE_SHFT_v4_7 0
 
+/* IPA 5.0 */
+
+#define IPA_FLAVOR_0_IPA_PROD_LOWEST_BMSK 0xFF000000
+#define IPA_FLAVOR_0_IPA_PROD_LOWEST_SHFT 24
+#define IPA_FLAVOR_0_IPA_PROD_PIPES_BMSK 0xFF0000
+#define IPA_FLAVOR_0_IPA_PROD_PIPES_SHFT 16
+#define IPA_FLAVOR_0_IPA_CONS_PIPES_BMSK 0xFF00
+#define IPA_FLAVOR_0_IPA_CONS_PIPES_SHFT 8
+#define IPA_FLAVOR_0_IPA_PIPES_BMSK 0xFF
+#define IPA_FLAVOR_0_IPA_PIPES_SHFT 0
+
+#define IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_BMSK_v5_0 0x80000000
+#define IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_SHFT_v5_0 31
+#define IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_BMSK_v5_0 0x40000000
+#define IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_SHFT_v5_0 30
+#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK_v5_0 0xFC00000
+#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT_v5_0 22
+#define IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_BMSK_v5_0 0x200000
+#define IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_SHFT_v5_0 21
+#define IPA_COMP_CFG_GENQMB_AOOOWR_BMSK_v5_0 0x100000
+#define IPA_COMP_CFG_GENQMB_AOOOWR_SHFT_v5_0 20
+#define IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_BMSK_v5_0 0x80000
+#define IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_SHFT_v5_0 19
+#define IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v5_0 0x20000
+#define IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v5_0 17
+#define IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_BMSK_v5_0 0x1
+#define IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_SHFT_v5_0 0
 #endif /* _IPAHAL_REG_I_H_ */

drivers/platform/msm/ipa/test/ipa_pm_ut.c

@@ -448,10 +448,11 @@ static int ipa_pm_ut_two_clients_activate(void *priv)
 {
 	int rc = 0;
 	int hdl_USB, hdl_WLAN, vote;
-	u32 pipes;
+	u32 pipes[IPA_EP_ARR_SIZE] = {0, 0};
 	struct callback_param user_data_USB;
 	struct callback_param user_data_WLAN;
 	bool wait_for_completion;
+	int ep, i;
 
 	struct ipa_pm_init_params init_params = {
 		.threshold_size = 2,
@@ -598,13 +599,23 @@ static int ipa_pm_ut_two_clients_activate(void *priv)
 		return -EFAULT;
 	}
 
-	pipes = 1 << ipa_get_ep_mapping(IPA_CLIENT_USB_CONS);
+	ep = ipa_get_ep_mapping(IPA_CLIENT_USB_CONS);
-	pipes |= 1 << ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS);
+	if (ep != IPA_EP_NOT_ALLOCATED)
-	pipes |= 1 << ipa_get_ep_mapping(IPA_CLIENT_USB_DPL_CONS);
+		pipes[ipahal_get_ep_reg_idx(ep)] |= ipahal_get_ep_bit(ep);
 
-	IPA_UT_DBG("pipes = %d\n", pipes);
+	ep = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS);
+	if (ep != IPA_EP_NOT_ALLOCATED)
+		pipes[ipahal_get_ep_reg_idx(ep)] |= ipahal_get_ep_bit(ep);
 
-	rc = ipa_pm_handle_suspend(pipes);
+	ep = ipa_get_ep_mapping(IPA_CLIENT_USB_DPL_CONS);
+	if (ep != IPA_EP_NOT_ALLOCATED)
+		pipes[ipahal_get_ep_reg_idx(ep)] |= ipahal_get_ep_bit(ep);
+
+	for (i = 0; i < IPA_EP_ARR_SIZE; i++) {
+		IPA_UT_DBG("pipes[%d] = %d\n", i, pipes[i]);
+		if (pipes[i])
+			ipa_pm_handle_suspend(pipes[i], i);
+	}
 
 	if (!wait_for_completion_timeout(&user_data_USB.complete,
 		msecs_to_jiffies(2000))) {
@@ -648,9 +659,18 @@ static int ipa_pm_ut_two_clients_activate(void *priv)
 		return -EFAULT;
 	}
 
-	pipes = 1 << ipa_get_ep_mapping(IPA_CLIENT_USB_CONS);
+	for (i = 0; i < IPA_EP_ARR_SIZE; i++)
+		pipes[i] = 0;
 
-	rc = ipa_pm_handle_suspend(pipes);
+	ep = ipa_get_ep_mapping(IPA_CLIENT_USB_CONS);
+	if (ep != IPA_EP_NOT_ALLOCATED)
+		pipes[ipahal_get_ep_reg_idx(ep)] |= ipahal_get_ep_bit(ep);
+
+	for (i = 0; i < IPA_EP_ARR_SIZE; i++) {
+		IPA_UT_DBG("pipes[%d] = %d\n", i, pipes[i]);
+		if (pipes[i])
+			ipa_pm_handle_suspend(pipes[i], i);
+	}
 
 	if (!wait_for_completion_timeout(&user_data_USB.complete,
 		msecs_to_jiffies(2000))) {

drivers/platform/msm/ipa/test/ipa_test_mhi.c

@@ -1798,6 +1798,7 @@ static int ipa_mhi_test_create_aggr_open_frame(void)
 	int rc;
 	int i;
 	u32 aggr_state_active;
+	enum ipa_hw_type ipa_ver;
 
 	IPA_UT_LOG("Entry\n");
 
@@ -1854,7 +1855,16 @@ static int ipa_mhi_test_create_aggr_open_frame(void)
 
 	msleep(20);
 
-	aggr_state_active = ipahal_read_reg(IPA_STATE_AGGR_ACTIVE);
+	ipa_ver = ipa_get_hw_type();
+	if (ipa_ver >= IPA_HW_v5_0) {
+		aggr_state_active =
+			ipahal_read_ep_reg(IPA_STATE_AGGR_ACTIVE_n,
+				test_mhi_ctx->cons_hdl);
+	} else {
+		aggr_state_active =
+			ipahal_read_reg(IPA_STATE_AGGR_ACTIVE);
+	}
+
 	IPA_UT_LOG("IPA_STATE_AGGR_ACTIVE  0x%x\n", aggr_state_active);
 	if (aggr_state_active == 0) {
 		IPA_UT_LOG("No aggregation frame open!\n");
@@ -1924,7 +1934,13 @@ static int ipa_mhi_test_suspend_aggr_open(bool force)
 		IPA_UT_LOG("AFTER resume\n");
 	}
 
-	ipahal_write_reg(IPA_AGGR_FORCE_CLOSE, (1 << test_mhi_ctx->cons_hdl));
+	if (ipa_get_hw_type() >= IPA_HW_v5_0)
+		ipahal_write_ep_reg(IPA_AGGR_FORCE_CLOSE_n,
+			test_mhi_ctx->cons_hdl,
+			ipahal_get_ep_bit(test_mhi_ctx->cons_hdl));
+	else
+		ipahal_write_reg(IPA_AGGR_FORCE_CLOSE,
+			ipahal_get_ep_bit(test_mhi_ctx->cons_hdl));
 
 	IPA_MHI_TEST_CHECK_MSI_INTR(false, timeout);
 	if (timeout) {
@@ -2282,6 +2298,7 @@ static int ipa_mhi_test_channel_reset_aggr_open(void)
 	int rc;
 	u32 aggr_state_active;
 	struct ipa_ep_cfg_aggr ep_aggr;
+	enum ipa_hw_type ipa_ver;
 
 	IPA_UT_LOG("Entry\n");
 
@@ -2299,7 +2316,16 @@ static int ipa_mhi_test_channel_reset_aggr_open(void)
 		return rc;
 	}
 
-	aggr_state_active = ipahal_read_reg(IPA_STATE_AGGR_ACTIVE);
+	ipa_ver = ipa_get_hw_type();
+	if (ipa_ver >= IPA_HW_v5_0) {
+		aggr_state_active =
+			ipahal_read_ep_reg(IPA_STATE_AGGR_ACTIVE_n,
+				test_mhi_ctx->cons_hdl);
+	} else {
+		aggr_state_active =
+			ipahal_read_reg(IPA_STATE_AGGR_ACTIVE);
+	}
+
 	IPADBG("IPA_STATE_AGGR_ACTIVE 0x%x\n", aggr_state_active);
 	if (aggr_state_active != 0) {
 		IPA_UT_LOG("aggregation frame open after reset!\n");