diff --git a/drivers/platform/msm/ipa/ipa_common_i.h b/drivers/platform/msm/ipa/ipa_common_i.h index 96baecb8c5..1567650dbb 100644 --- a/drivers/platform/msm/ipa/ipa_common_i.h +++ b/drivers/platform/msm/ipa/ipa_common_i.h @@ -18,6 +18,8 @@ #define WARNON_RATELIMIT_BURST 1 #define IPA_RATELIMIT_BURST 1 +#define IPA_EP_ARR_SIZE 2 +#define IPA_EP_PER_REG 32 #define __FILENAME__ \ (strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : __FILE__) @@ -438,7 +440,7 @@ struct ipa_tz_unlock_reg_info { * @dma_addr: DMA address of this Rx packet */ struct ipa_tx_suspend_irq_data { - u32 endpoints; + u32 endpoints[IPA_EP_ARR_SIZE]; }; extern const char *ipa_clients_strings[]; diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c index 3eb8c2b793..9cc22fe10b 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -3492,10 +3492,17 @@ static int ipa3_q6_clean_q6_flt_tbls(enum ipa_ip_type ip, coal_ep = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); /* IC to close the coal frame before HPS Clear if coal is enabled */ if (coal_ep != IPA_EP_NOT_ALLOCATED) { + u32 offset = 0; + reg_write_coal_close.skip_pipeline_clear = false; reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; - reg_write_coal_close.offset = ipahal_get_reg_ofst( - IPA_AGGR_FORCE_CLOSE); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, coal_ep); + reg_write_coal_close.offset = offset; ipahal_get_aggr_force_close_valmask(coal_ep, &valmask); reg_write_coal_close.value = valmask.val; reg_write_coal_close.value_mask = valmask.mask; @@ -3653,11 +3660,18 @@ static int ipa3_q6_clean_q6_rt_tbls(enum ipa_ip_type ip, /* IC to close the coal frame before HPS Clear if coal is enabled */ if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) { + u32 offset = 0; + i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); reg_write_coal_close.skip_pipeline_clear = false; reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; - reg_write_coal_close.offset = ipahal_get_reg_ofst( - IPA_AGGR_FORCE_CLOSE); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; ipahal_get_aggr_force_close_valmask(i, &valmask); reg_write_coal_close.value = valmask.val; reg_write_coal_close.value_mask = valmask.mask; @@ -3777,11 +3791,18 @@ static int ipa3_q6_clean_q6_tables(void) /* IC to close the coal frame before HPS Clear if coal is enabled */ if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) { + u32 offset = 0; + i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); reg_write_coal_close.skip_pipeline_clear = false; reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; - reg_write_coal_close.offset = ipahal_get_reg_ofst( - IPA_AGGR_FORCE_CLOSE); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; ipahal_get_aggr_force_close_valmask(i, &valmask); reg_write_coal_close.value = valmask.val; reg_write_coal_close.value_mask = valmask.mask; @@ -3855,11 +3876,18 @@ static int ipa3_q6_set_ex_path_to_apps(void) /* IC to close the coal frame before HPS Clear if coal is enabled */ if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) { + u32 offset = 0; + i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); reg_write_coal_close.skip_pipeline_clear = false; reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; - reg_write_coal_close.offset = ipahal_get_reg_ofst( - IPA_AGGR_FORCE_CLOSE); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; ipahal_get_aggr_force_close_valmask(i, &valmask); reg_write_coal_close.value = valmask.val; reg_write_coal_close.value_mask = valmask.mask; @@ -4255,11 +4283,18 @@ int _ipa_init_hdr_v3_0(void) /* IC to close the coal frame before HPS Clear if coal is enabled */ if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) { + u32 offset = 0; + i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); reg_write_coal_close.skip_pipeline_clear = false; reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; - reg_write_coal_close.offset = ipahal_get_reg_ofst( - IPA_AGGR_FORCE_CLOSE); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; ipahal_get_aggr_force_close_valmask(i, &valmask); reg_write_coal_close.value = valmask.val; reg_write_coal_close.value_mask = valmask.mask; @@ -5721,25 +5756,41 @@ void ipa3_suspend_handler(enum ipa_irq_type interrupt, void *private_data, void *interrupt_data) { - u32 suspend_data = + u32 *suspend_data = ((struct ipa_tx_suspend_irq_data *)interrupt_data)->endpoints; u32 bmsk = 1; - u32 i = 0; + u32 i = 0, j = 0, ep_arr_size, ep_per_reg; int res; - struct ipa_ep_cfg_holb holb_cfg; u32 pipe_bitmask = 0; - IPADBG("interrupt=%d, interrupt_data=%u\n", - interrupt, suspend_data); - memset(&holb_cfg, 0, sizeof(holb_cfg)); + IPADBG("interrupt=%d\n", interrupt); - for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++, bmsk = bmsk << 1) - if ((suspend_data & bmsk) && (ipa3_ctx->ep[i].valid)) + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + ep_arr_size = IPA_EP_ARR_SIZE; + ep_per_reg = IPA_EP_PER_REG; + } else { + ep_arr_size = 1; + ep_per_reg = ipa3_ctx->ipa_num_pipes; + } + + j = 0; + for (i = 0; i < ipa3_ctx->ipa_num_pipes && j < ep_arr_size; i++) { + if ((suspend_data[j] & bmsk) && (ipa3_ctx->ep[i].valid)) pipe_bitmask |= bmsk; - res = ipa_pm_handle_suspend(pipe_bitmask); - if (res) { - IPAERR("ipa_pm_handle_suspend failed %d\n", res); - return; + bmsk = bmsk << 1; + + if ((i % IPA_EP_PER_REG) == (ep_per_reg - 1)) { + IPADBG("interrupt data: %u\n", suspend_data[j]); + res = ipa_pm_handle_suspend(pipe_bitmask, j); + if (res) { + IPAERR( + "ipa_pm_handle_suspend failed %d\n", res); + return; + } + pipe_bitmask = 0; + bmsk = 1; + j++; + } } } diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_client.c b/drivers/platform/msm/ipa/ipa_v3/ipa_client.c index ccafe882a8..f0acd04541 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_client.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_client.c @@ -1625,9 +1625,18 @@ int ipa3_xdci_suspend(u32 ul_clnt_hdl, u32 dl_clnt_hdl, } if (!dl_data_pending) { - aggr_active_bitmap = ipahal_read_reg(IPA_STATE_AGGR_ACTIVE); - if (aggr_active_bitmap & (1 << dl_clnt_hdl)) { - IPADBG("DL/DPL data pending due to open aggr. frame\n"); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + aggr_active_bitmap = + ipahal_read_ep_reg(IPA_STATE_AGGR_ACTIVE_n, + dl_clnt_hdl); + } else { + aggr_active_bitmap = + ipahal_read_reg(IPA_STATE_AGGR_ACTIVE); + } + if (ipahal_test_ep_bit(aggr_active_bitmap, dl_clnt_hdl)) { + IPADBG( + "DL/DPL data pending due to open aggr. frame\n" + ); dl_data_pending = true; } } diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c b/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c index 0391380371..14089027d9 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c @@ -580,11 +580,18 @@ int __ipa_commit_flt_v3(enum ipa_ip_type ip) /* IC to close the coal frame before HPS Clear if coal is enabled */ if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) { + u32 offset = 0; + i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); reg_write_coal_close.skip_pipeline_clear = false; reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; - reg_write_coal_close.offset = ipahal_get_reg_ofst( - IPA_AGGR_FORCE_CLOSE); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; ipahal_get_aggr_force_close_valmask(i, &valmask); reg_write_coal_close.value = valmask.val; reg_write_coal_close.value_mask = valmask.mask; diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c b/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c index ab04374b3a..bac1af9429 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c @@ -195,11 +195,18 @@ int __ipa_commit_hdr_v3_0(void) /* IC to close the coal frame before HPS Clear if coal is enabled */ if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) { + u32 offset = 0; + i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); reg_write_coal_close.skip_pipeline_clear = false; reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; - reg_write_coal_close.offset = ipahal_get_reg_ofst( - IPA_AGGR_FORCE_CLOSE); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; ipahal_get_aggr_force_close_valmask(i, &valmask); reg_write_coal_close.value = valmask.val; reg_write_coal_close.value_mask = valmask.mask; diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_hw_stats.c b/drivers/platform/msm/ipa/ipa_v3/ipa_hw_stats.c index 4fd5ccc760..cb80c9387b 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_hw_stats.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_hw_stats.c @@ -257,12 +257,18 @@ static void ipa_close_coal_frame(struct ipahal_imm_cmd_pyld **coal_cmd_pyld) int i; struct ipahal_reg_valmask valmask; struct ipahal_imm_cmd_register_write reg_write_coal_close; + u32 offset = 0; i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); reg_write_coal_close.skip_pipeline_clear = false; reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; - reg_write_coal_close.offset = ipahal_get_reg_ofst( - IPA_AGGR_FORCE_CLOSE); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; ipahal_get_aggr_force_close_valmask(i, &valmask); reg_write_coal_close.value = valmask.val; reg_write_coal_close.value_mask = valmask.mask; @@ -306,6 +312,7 @@ int ipa_init_quota_stats(u32 pipe_bitmask) dma_addr_t dma_address; int ret; int num_cmd = 0; + int ipa_ep_idx = IPA_EP_NOT_ALLOCATED; if (!ipa3_ctx->hw_stats.enabled) return 0; @@ -338,8 +345,8 @@ int ipa_init_quota_stats(u32 pipe_bitmask) } /* IC to close the coal frame before HPS Clear if coal is enabled */ - if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != - IPA_EP_NOT_ALLOCATED) { + ipa_ep_idx = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); + if (ipa_ep_idx != IPA_EP_NOT_ALLOCATED) { ipa_close_coal_frame(&coal_cmd_pyld); if (!coal_cmd_pyld) { IPAERR("failed to construct coal close IC\n"); @@ -353,8 +360,19 @@ int ipa_init_quota_stats(u32 pipe_bitmask) /* setting the registers and init the stats pyld are done atomically */ quota_mask.skip_pipeline_clear = false; quota_mask.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR; - quota_mask.offset = ipahal_get_reg_n_ofst(IPA_STAT_QUOTA_MASK_n, - ipa3_ctx->ee); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) { + quota_mask.offset = ipahal_get_reg_n_ofst(IPA_STAT_QUOTA_MASK_n, + ipa3_ctx->ee); + } else { + if (ipa_ep_idx == IPA_EP_NOT_ALLOCATED) { + ret = -EFAULT; + goto destroy_coal_cmd; + } + quota_mask.offset = ipahal_get_ep_reg_n_offset( + IPA_STAT_QUOTA_MASK_EE_n_REG_k, + ipa3_ctx->ee, + ipa_ep_idx); + } quota_mask.value = pipe_bitmask; quota_mask.value_mask = ~0; quota_mask_pyld = ipahal_construct_imm_cmd(IPA_IMM_CMD_REGISTER_WRITE, diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_interrupts.c b/drivers/platform/msm/ipa/ipa_v3/ipa_interrupts.c index 102962aec8..e8e9c89907 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_interrupts.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_interrupts.c @@ -85,13 +85,15 @@ static void ipa3_deferred_interrupt_work(struct work_struct *work) kfree(work_data); } -static bool ipa3_is_valid_ep(u32 ep_suspend_data) +static bool ipa3_is_valid_ep(u32 ep_suspend_data, u8 ep_reg_idx) { u32 bmsk = 1; u32 i = 0; + u32 reg_add = ep_reg_idx << 5; for (i = 0; i < ipa3_ctx->ipa_num_pipes; i++) { - if ((ep_suspend_data & bmsk) && (ipa3_ctx->ep[i].valid)) + if ((ep_suspend_data & bmsk) && + (ipa3_ctx->ep[i + reg_add].valid)) return true; bmsk = bmsk << 1; } @@ -102,10 +104,11 @@ static int ipa3_handle_interrupt(int irq_num, bool isr_context) { struct ipa3_interrupt_info interrupt_info; struct ipa3_interrupt_work_wrap *work_data; - u32 suspend_data; + u32 suspend_data[IPA_EP_ARR_SIZE]; void *interrupt_data = NULL; struct ipa_tx_suspend_irq_data *suspend_interrupt_data = NULL; - int res; + int res, i; + bool valid; interrupt_info = ipa_interrupt_to_cb[irq_num]; if (interrupt_info.handler == NULL) { @@ -118,16 +121,37 @@ static int ipa3_handle_interrupt(int irq_num, bool isr_context) case IPA_TX_SUSPEND_IRQ: IPADBG_LOW("processing TX_SUSPEND interrupt\n"); ipa3_tx_suspend_interrupt_wa(); - suspend_data = ipahal_read_reg_n(IPA_SUSPEND_IRQ_INFO_EE_n, - ipa_ee); - IPADBG_LOW("get interrupt %d\n", suspend_data); + valid = 0; + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + for (i = 0; i < IPA_EP_ARR_SIZE; i++) { + suspend_data[i] = ipahal_read_reg_nk( + IPA_SUSPEND_IRQ_INFO_EE_n_REG_k, + ipa_ee, i); + if (ipa3_is_valid_ep(suspend_data[i], i)) + valid = true; + IPADBG_LOW("get interrupt %d\n", + suspend_data[i]); - if (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_1) { - /* Clearing L2 interrupts status */ - ipahal_write_reg_n(IPA_SUSPEND_IRQ_CLR_EE_n, - ipa_ee, suspend_data); + /* Clearing L2 interrupts status */ + ipahal_write_reg_nk( + IPA_SUSPEND_IRQ_CLR_EE_n_REG_k, + ipa_ee, i, suspend_data[i]); + } + } else { + suspend_data[0] = ipahal_read_reg_n( + IPA_SUSPEND_IRQ_INFO_EE_n, + ipa_ee); + if (ipa3_is_valid_ep(suspend_data[0], 0)) + valid = true; + IPADBG_LOW("get interrupt %d\n", suspend_data[0]); + + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_1) { + /* Clearing L2 interrupts status */ + ipahal_write_reg_n(IPA_SUSPEND_IRQ_CLR_EE_n, + ipa_ee, suspend_data[0]); + } } - if (!ipa3_is_valid_ep(suspend_data)) + if (!valid) return 0; suspend_interrupt_data = @@ -136,7 +160,9 @@ static int ipa3_handle_interrupt(int irq_num, bool isr_context) IPAERR("failed allocating suspend_interrupt_data\n"); return -ENOMEM; } - suspend_interrupt_data->endpoints = suspend_data; + + for (i = 0; i < IPA_EP_ARR_SIZE; i++) + suspend_interrupt_data->endpoints[i] = suspend_data[i]; interrupt_data = suspend_interrupt_data; break; default: @@ -370,7 +396,8 @@ int ipa3_add_interrupt_handler(enum ipa_irq_type interrupt, bool deferred_flag, void *private_data) { - u32 val; + u32 val, i; + u32 pipe_bmsk[IPA_EP_ARR_SIZE] = {0, 0}; u32 bmsk; int irq_num; int client_idx, ep_idx; @@ -405,21 +432,47 @@ int ipa3_add_interrupt_handler(enum ipa_irq_type interrupt, /* register SUSPEND_IRQ_EN_EE_n_ADDR for L2 interrupt*/ if ((interrupt == IPA_TX_SUSPEND_IRQ) && (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_1)) { - val = ~0; - for (client_idx = 0; client_idx < IPA_CLIENT_MAX; client_idx++) - if (IPA_CLIENT_IS_Q6_CONS(client_idx) || - IPA_CLIENT_IS_Q6_PROD(client_idx)) { + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + for (client_idx = 0; + client_idx < IPA_CLIENT_MAX; + client_idx++) { ep_idx = ipa3_get_ep_mapping(client_idx); - IPADBG("modem ep_idx(%d) client_idx = %d\n", - ep_idx, client_idx); - if (ep_idx == -1) - IPADBG("Invalid IPA client\n"); - else - val &= ~(1 << ep_idx); - } + if ((ep_idx != IPA_EP_NOT_ALLOCATED) && + !(IPA_CLIENT_IS_Q6_CONS(client_idx) || + IPA_CLIENT_IS_Q6_PROD(client_idx))) { + pipe_bmsk[ipahal_get_ep_reg_idx(ep_idx)] |= + ipahal_get_ep_bit(ep_idx); + } + } + for (i = 0; i < IPA_EP_ARR_SIZE; i++) { + ipahal_write_reg_nk( + IPA_SUSPEND_IRQ_EN_EE_n_REG_k, + ipa_ee, i, pipe_bmsk[i]); + IPADBG( + "wrote IPA_SUSPEND_IRQ_EN_EE_n_REG_k m = %u pipe_bmsk[i] = %d\n" + , i, pipe_bmsk[i]); + } + } else { + val = ~0; + for (client_idx = 0; + client_idx < IPA_CLIENT_MAX; + client_idx++) { + if (IPA_CLIENT_IS_Q6_CONS(client_idx) || + IPA_CLIENT_IS_Q6_PROD(client_idx)) { + ep_idx = ipa3_get_ep_mapping(client_idx); + IPADBG( + "modem ep_idx(%d) client_idx = %d\n" + , ep_idx, client_idx); + if (ep_idx == -1) + IPADBG("Invalid IPA client\n"); + else + val &= ~(1 << ep_idx); + } + } - ipahal_write_reg_n(IPA_SUSPEND_IRQ_EN_EE_n, ipa_ee, val); - IPADBG("wrote IPA_SUSPEND_IRQ_EN_EE_n reg = %d\n", val); + ipahal_write_reg_n(IPA_SUSPEND_IRQ_EN_EE_n, ipa_ee, val); + IPADBG("wrote IPA_SUSPEND_IRQ_EN_EE_n reg = %d\n", val); + } } return 0; } @@ -432,7 +485,7 @@ int ipa3_add_interrupt_handler(enum ipa_irq_type interrupt, */ int ipa3_remove_interrupt_handler(enum ipa_irq_type interrupt) { - u32 val; + u32 val, i; u32 bmsk; int irq_num; @@ -458,8 +511,19 @@ int ipa3_remove_interrupt_handler(enum ipa_irq_type interrupt) /* clean SUSPEND_IRQ_EN_EE_n_ADDR for L2 interrupt */ if ((interrupt == IPA_TX_SUSPEND_IRQ) && (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_1)) { - ipahal_write_reg_n(IPA_SUSPEND_IRQ_EN_EE_n, ipa_ee, 0); - IPADBG("wrote IPA_SUSPEND_IRQ_EN_EE_n reg = %d\n", 0); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + for (i = 0; i < IPA_EP_ARR_SIZE; i++) { + ipahal_write_reg_nk( + IPA_SUSPEND_IRQ_EN_EE_n_REG_k, + ipa_ee, i, 0); + IPADBG( + "wrote IPA_SUSPEND_IRQ_EN_EE_n_REG_k k %u val = %d\n" + , i, 0); + } + } else { + ipahal_write_reg_n(IPA_SUSPEND_IRQ_EN_EE_n, ipa_ee, 0); + IPADBG("wrote IPA_SUSPEND_IRQ_EN_EE_n reg = %d\n", 0); + } } val = ipahal_read_reg_n(IPA_IRQ_EN_EE_n, ipa_ee); @@ -570,11 +634,26 @@ void ipa3_suspend_active_aggr_wa(u32 clnt_hdl) struct ipa3_interrupt_work_wrap *work_data; struct ipa_tx_suspend_irq_data *suspend_interrupt_data; int irq_num; - int aggr_active_bitmap = ipahal_read_reg(IPA_STATE_AGGR_ACTIVE); + int aggr_active_bitmap; - if (aggr_active_bitmap & (1 << clnt_hdl)) { + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + aggr_active_bitmap = + ipahal_read_ep_reg(IPA_STATE_AGGR_ACTIVE_n, + clnt_hdl); + } else { + aggr_active_bitmap = + ipahal_read_reg(IPA_STATE_AGGR_ACTIVE); + } + + if (ipahal_test_ep_bit(aggr_active_bitmap, clnt_hdl)) { /* force close aggregation */ - ipahal_write_reg(IPA_AGGR_FORCE_CLOSE, (1 << clnt_hdl)); + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) + ipahal_write_ep_reg(IPA_AGGR_FORCE_CLOSE_n, + clnt_hdl, + ipahal_get_ep_bit(clnt_hdl)); + else + ipahal_write_reg(IPA_AGGR_FORCE_CLOSE, + ipahal_get_ep_bit(clnt_hdl)); /* simulate suspend IRQ */ irq_num = ipa3_irq_mapping[IPA_TX_SUSPEND_IRQ]; @@ -590,7 +669,10 @@ void ipa3_suspend_active_aggr_wa(u32 clnt_hdl) IPAERR("failed allocating suspend_interrupt_data\n"); return; } - suspend_interrupt_data->endpoints = 1 << clnt_hdl; + suspend_interrupt_data->endpoints[ + ipahal_get_ep_reg_idx(clnt_hdl) + ] = + ipahal_get_ep_bit(clnt_hdl); work_data = kzalloc(sizeof(struct ipa3_interrupt_work_wrap), GFP_ATOMIC); diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c b/drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c index c25e8f00e1..104e7cc99f 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c @@ -721,19 +721,25 @@ bool ipa3_has_open_aggr_frame(enum ipa_client_type client) u32 aggr_state_active; int ipa_ep_idx; - aggr_state_active = ipahal_read_reg(IPA_STATE_AGGR_ACTIVE); - IPA_MHI_DBG_LOW("IPA_STATE_AGGR_ACTIVE_OFST 0x%x\n", aggr_state_active); - ipa_ep_idx = ipa_get_ep_mapping(client); if (ipa_ep_idx == -1) { ipa_assert(); return false; } - if ((1 << ipa_ep_idx) & aggr_state_active) - return true; + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + aggr_state_active = + ipahal_read_ep_reg(IPA_STATE_AGGR_ACTIVE_n, + ipa_ep_idx); + } else { + aggr_state_active = + ipahal_read_reg(IPA_STATE_AGGR_ACTIVE); + } - return false; + IPA_MHI_DBG_LOW("IPA_STATE_AGGR_ACTIVE_OFST 0x%x, ep_idx %d\n", + ipa_ep_idx, aggr_state_active); + + return ipahal_test_ep_bit(aggr_state_active, ipa_ep_idx); } EXPORT_SYMBOL(ipa3_has_open_aggr_frame); diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_mpm.c b/drivers/platform/msm/ipa/ipa_v3/ipa_mpm.c index 8902c93ca0..8e539e26a9 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_mpm.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_mpm.c @@ -495,11 +495,18 @@ static int ipa_mpm_set_dma_mode(enum ipa_client_type src_pipe, /* First step is to clear IPA Pipeline before changing DMA mode */ if (ipa3_get_ep_mapping(src_pipe) != IPA_EP_NOT_ALLOCATED) { + u32 offset = 0; + i = ipa3_get_ep_mapping(src_pipe); reg_write_coal_close.skip_pipeline_clear = false; reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; - reg_write_coal_close.offset = ipahal_get_reg_ofst( - IPA_AGGR_FORCE_CLOSE); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; ipahal_get_aggr_force_close_valmask(i, &valmask); reg_write_coal_close.value = valmask.val; reg_write_coal_close.value_mask = valmask.mask; diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_nat.c b/drivers/platform/msm/ipa/ipa_v3/ipa_nat.c index 467294965a..5e3030968d 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_nat.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_nat.c @@ -1156,11 +1156,18 @@ static int ipa3_nat_send_init_cmd(struct ipahal_imm_cmd_ip_v4_nat_init *cmd, /* IC to close the coal frame before HPS Clear if coal is enabled */ if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) { + u32 offset = 0; + i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); reg_write_coal_close.skip_pipeline_clear = false; reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; - reg_write_coal_close.offset = ipahal_get_reg_ofst( - IPA_AGGR_FORCE_CLOSE); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; ipahal_get_aggr_force_close_valmask(i, &valmask); reg_write_coal_close.value = valmask.val; reg_write_coal_close.value_mask = valmask.mask; @@ -1259,11 +1266,17 @@ static int ipa3_ipv6ct_send_init_cmd(struct ipahal_imm_cmd_ip_v6_ct_init *cmd) /* IC to close the coal frame before HPS Clear if coal is enabled */ if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) { + u32 offset = 0; i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); reg_write_coal_close.skip_pipeline_clear = false; reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; - reg_write_coal_close.offset = ipahal_get_reg_ofst( - IPA_AGGR_FORCE_CLOSE); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; ipahal_get_aggr_force_close_valmask(i, &valmask); reg_write_coal_close.value = valmask.val; reg_write_coal_close.value_mask = valmask.mask; @@ -1932,11 +1945,18 @@ int ipa3_table_dma_cmd( /* IC to close the coal frame before HPS Clear if coal is enabled */ if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) { + u32 offset = 0; + i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); reg_write_coal_close.skip_pipeline_clear = false; reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; - reg_write_coal_close.offset = ipahal_get_reg_ofst( - IPA_AGGR_FORCE_CLOSE); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; ipahal_get_aggr_force_close_valmask(i, &valmask); reg_write_coal_close.value = valmask.val; reg_write_coal_close.value_mask = valmask.mask; diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_pm.c b/drivers/platform/msm/ipa/ipa_v3/ipa_pm.c index d7866fcceb..ba864fa135 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_pm.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_pm.c @@ -1201,14 +1201,17 @@ EXPORT_SYMBOL(ipa_pm_deactivate_sync); /** * ipa_pm_handle_suspend(): calls the callbacks of suspended clients to wake up * @pipe_bitmask: the bits represent the indexes of the clients to be woken up + * @pipe_arr_idx: if larger than 0 add to pipe num 32 * pipe_arr_idx * * Returns: 0 on success, negative on failure */ -int ipa_pm_handle_suspend(u32 pipe_bitmask) +int ipa_pm_handle_suspend(u32 pipe_bitmask, u32 pipe_arr_idx) { int i; struct ipa_pm_client *client; bool client_notified[IPA_PM_MAX_CLIENTS] = { false }; + u32 pipe_add; + u32 max_pipes; if (ipa_pm_ctx == NULL) { IPA_PM_ERR("PM_ctx is null\n"); @@ -1220,10 +1223,12 @@ int ipa_pm_handle_suspend(u32 pipe_bitmask) if (pipe_bitmask == 0) return 0; + pipe_add = pipe_arr_idx * 32; + max_pipes = IPA3_MAX_NUM_PIPES; mutex_lock(&ipa_pm_ctx->client_mutex); - for (i = 0; i < IPA3_MAX_NUM_PIPES; i++) { + for (i = 0; i < IPA_EP_PER_REG && (i + pipe_add) < max_pipes; i++) { if (pipe_bitmask & (1 << i)) { - client = ipa_pm_ctx->clients_by_pipe[i]; + client = ipa_pm_ctx->clients_by_pipe[i + pipe_add]; if (client && !client_notified[client->hdl]) { if (client->callback) { client->callback(client->callback_params diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_pm.h b/drivers/platform/msm/ipa/ipa_v3/ipa_pm.h index 2468a330ac..15935867ac 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_pm.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_pm.h @@ -96,7 +96,7 @@ int ipa_pm_deregister(u32 hdl); /* IPA Internal Functions */ int ipa_pm_init(struct ipa_pm_init_params *params); int ipa_pm_destroy(void); -int ipa_pm_handle_suspend(u32 pipe_bitmask); +int ipa_pm_handle_suspend(u32 pipe_bitmask, u32 pipe_arr_idx); int ipa_pm_deactivate_all_deferred(void); int ipa_pm_stat(char *buf, int size); int ipa_pm_exceptions_stat(char *buf, int size); @@ -157,7 +157,7 @@ static inline int ipa_pm_destroy(void) return -EPERM; } -static inline int ipa_pm_handle_suspend(u32 pipe_bitmask) +static inline int ipa_pm_handle_suspend(u32 pipe_bitmask, u32 pipe_arr_idx) { return -EPERM; } diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c b/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c index 2131845902..dbf79372f1 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c @@ -570,11 +570,18 @@ int __ipa_commit_rt_v3(enum ipa_ip_type ip) /* IC to close the coal frame before HPS Clear if coal is enabled */ if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) { + u32 offset = 0; + i = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); reg_write_coal_close.skip_pipeline_clear = false; reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; - reg_write_coal_close.offset = ipahal_get_reg_ofst( - IPA_AGGR_FORCE_CLOSE); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_coal_close.offset = offset; ipahal_get_aggr_force_close_valmask(i, &valmask); reg_write_coal_close.value = valmask.val; reg_write_coal_close.value_mask = valmask.mask; diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c index 4025c3fd8d..008511786d 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c @@ -4734,6 +4734,7 @@ static void ipa_cfg_qtime(void) gran_cfg.gran_0 = IPA_TIMERS_TIME_GRAN_100_USEC; gran_cfg.gran_1 = IPA_TIMERS_TIME_GRAN_1_MSEC; gran_cfg.gran_2 = IPA_TIMERS_TIME_GRAN_1_MSEC; + gran_cfg.gran_3 = IPA_TIMERS_TIME_GRAN_1_MSEC; val = ipahal_read_reg(IPA_TIMERS_PULSE_GRAN_CFG); IPADBG("timer pulse granularity before cfg: 0x%x\n", val); ipahal_write_reg_fields(IPA_TIMERS_PULSE_GRAN_CFG, &gran_cfg); @@ -5845,7 +5846,7 @@ static int ipa3_process_timer_cfg(u32 time_us, gran0_step = ipa3_time_gran_usec_step(gran_cfg.gran_0); gran1_step = ipa3_time_gran_usec_step(gran_cfg.gran_1); - /* gran_2 is not used by AP */ + /* gran_2 and gran_3 are not used by AP */ IPADBG("gran0 usec step=%u gran1 usec step=%u\n", gran0_step, gran1_step); @@ -7235,11 +7236,18 @@ int ipa3_tag_process(struct ipa3_desc desc[], /* IC to close the coal frame before HPS Clear if coal is enabled */ if (ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS) != -1) { + u32 offset = 0; + ep_idx = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); reg_write_coal_close.skip_pipeline_clear = false; reg_write_coal_close.pipeline_clear_options = IPAHAL_HPS_CLEAR; - reg_write_coal_close.offset = ipahal_get_reg_ofst( - IPA_AGGR_FORCE_CLOSE); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, ep_idx); + reg_write_coal_close.offset = offset; ipahal_get_aggr_force_close_valmask(ep_idx, &valmask); reg_write_coal_close.value = valmask.val; reg_write_coal_close.value_mask = valmask.mask; @@ -7423,6 +7431,7 @@ static int ipa3_tag_generate_force_close_desc(struct ipa3_desc desc[], struct ipahal_imm_cmd_register_write reg_write_agg_close; struct ipahal_imm_cmd_pyld *cmd_pyld; struct ipahal_reg_valmask valmask; + u32 offset = 0; for (i = start_pipe; i < end_pipe; i++) { ipahal_read_reg_n_fields(IPA_ENDP_INIT_AGGR_n, i, &ep_aggr); @@ -7438,8 +7447,13 @@ static int ipa3_tag_generate_force_close_desc(struct ipa3_desc desc[], reg_write_agg_close.skip_pipeline_clear = false; reg_write_agg_close.pipeline_clear_options = IPAHAL_FULL_PIPELINE_CLEAR; - reg_write_agg_close.offset = - ipahal_get_reg_ofst(IPA_AGGR_FORCE_CLOSE); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, i); + reg_write_agg_close.offset = offset; ipahal_get_aggr_force_close_valmask(i, &valmask); reg_write_agg_close.value = valmask.val; reg_write_agg_close.value_mask = valmask.mask; @@ -7634,6 +7648,12 @@ EXPORT_SYMBOL(ipa3_get_transport_type); u32 ipa3_get_num_pipes(void) { + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + struct ipahal_ipa_flavor_0 ipa_flavor; + + ipahal_read_reg_fields(IPA_FLAVOR_0, &ipa_flavor); + return ipa_flavor.ipa_pipes; + } return ipahal_read_reg(IPA_ENABLED_PIPES); } @@ -8539,7 +8559,7 @@ void ipa3_force_close_coal(void) int ipa3_suspend_apps_pipes(bool suspend) { - int res; + int res, i; /* As per HPG first need start/stop coalescing channel * then default one. Coalescing client number was greater then @@ -8585,11 +8605,24 @@ int ipa3_suspend_apps_pipes(bool suspend) usleep_range(IPA_TAG_SLEEP_MIN_USEC, IPA_TAG_SLEEP_MAX_USEC); - res = ipahal_read_reg_n(IPA_SUSPEND_IRQ_INFO_EE_n, - ipa3_ctx->ee); - if (res) { - IPADBG("suspend irq is pending 0x%x\n", res); - goto undo_qmap_cons; + if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) { + for (i = 0; i < IPA_EP_ARR_SIZE; i++) { + res = ipahal_read_reg_nk( + IPA_SUSPEND_IRQ_INFO_EE_n_REG_k, + ipa3_ctx->ee, i); + if (res) { + IPADBG("suspend irq is pending 0x%x\n", + res); + goto undo_qmap_cons; + } + } + } else { + res = ipahal_read_reg_n(IPA_SUSPEND_IRQ_INFO_EE_n, + ipa3_ctx->ee); + if (res) { + IPADBG("suspend irq is pending 0x%x\n", res); + goto undo_qmap_cons; + } } } do_prod: @@ -8680,6 +8713,7 @@ int ipa3_allocate_coal_close_frame(void) struct ipahal_imm_cmd_register_write reg_write_cmd = { 0 }; struct ipahal_reg_valmask valmask; int ep_idx; + u32 offset = 0; ep_idx = ipa3_get_ep_mapping(IPA_CLIENT_APPS_WAN_COAL_CONS); if (ep_idx == IPA_EP_NOT_ALLOCATED) @@ -8687,7 +8721,13 @@ int ipa3_allocate_coal_close_frame(void) IPADBG("Allocate coal close frame cmd\n"); reg_write_cmd.skip_pipeline_clear = false; reg_write_cmd.pipeline_clear_options = IPAHAL_HPS_CLEAR; - reg_write_cmd.offset = ipahal_get_reg_ofst(IPA_AGGR_FORCE_CLOSE); + if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0) + offset = ipahal_get_reg_ofst( + IPA_AGGR_FORCE_CLOSE); + else + offset = ipahal_get_ep_reg_offset( + IPA_AGGR_FORCE_CLOSE_n, ep_idx); + reg_write_cmd.offset = offset; ipahal_get_aggr_force_close_valmask(ep_idx, &valmask); reg_write_cmd.value = valmask.val; reg_write_cmd.value_mask = valmask.mask; diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c index 5bead39363..cc50920086 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c @@ -13,6 +13,10 @@ #define IPA_MAX_MSG_LEN 4096 +#define IPA_BIT_MAP_CELL_NUM(num) ((num) >> 5) +#define IPA_BIT_MAP_CELL_MSK(num) \ + (1 << (num - (IPA_BIT_MAP_CELL_NUM(num) << 5))) + static const char *ipareg_name_to_str[IPA_REG_MAX] = { __stringify(IPA_ROUTE), __stringify(IPA_IRQ_STTS_EE_n), @@ -140,7 +144,14 @@ static const char *ipareg_name_to_str[IPA_REG_MAX] = { __stringify(IPA_ENDP_GSI_CFG_AOS_n), __stringify(IPA_ENDP_GSI_CFG_TLV_n), __stringify(IPA_COAL_EVICT_LRU), - __stringify(IPA_COAL_QMAP_CFG) + __stringify(IPA_COAL_QMAP_CFG), + __stringify(IPA_FLAVOR_0), + __stringify(IPA_STATE_AGGR_ACTIVE_n), + __stringify(IPA_AGGR_FORCE_CLOSE_n), + __stringify(IPA_STAT_QUOTA_MASK_EE_n_REG_k), + __stringify(IPA_SUSPEND_IRQ_INFO_EE_n_REG_k), + __stringify(IPA_SUSPEND_IRQ_CLR_EE_n_REG_k), + __stringify(IPA_SUSPEND_IRQ_EN_EE_n_REG_k), }; static void ipareg_construct_dummy(enum ipahal_reg_name reg, @@ -318,6 +329,27 @@ static void ipareg_construct_rsrg_grp_xy_v4_5( IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK_V3_5); } +static void ipareg_construct_rsrg_grp_xy_v5_0( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_rsrc_grp_cfg *grp = + (struct ipahal_reg_rsrc_grp_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, grp->x_min, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT_V3_5, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_BMSK_V3_5); + IPA_SETFIELD_IN_REG(*val, grp->x_max, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_SHFT_V3_5, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_BMSK_V3_5); + + IPA_SETFIELD_IN_REG(*val, grp->y_min, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_SHFT_V3_5, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_BMSK_V3_5); + IPA_SETFIELD_IN_REG(*val, grp->y_max, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_SHFT_V3_5, + IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK_V3_5); +} + static void ipareg_construct_hash_cfg_n( enum ipahal_reg_name reg, const void *fields, u32 *val) { @@ -501,6 +533,25 @@ static void ipareg_construct_endp_status_n_v4_5( IPA_ENDP_STATUS_n_STATUS_PKT_SUPPRESS_BMSK); } +static void ipareg_construct_endp_status_n_v5_0( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_ep_cfg_status *ep_status = + (struct ipahal_reg_ep_cfg_status *)fields; + + IPA_SETFIELD_IN_REG(*val, ep_status->status_en, + IPA_ENDP_STATUS_n_STATUS_EN_SHFT, + IPA_ENDP_STATUS_n_STATUS_EN_BMSK); + + IPA_SETFIELD_IN_REG(*val, ep_status->status_ep, + IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT_V5_0, + IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK_V5_0); + + IPA_SETFIELD_IN_REG(*val, ep_status->status_pkt_suppress, + IPA_ENDP_STATUS_n_STATUS_PKT_SUPPRESS_SHFT, + IPA_ENDP_STATUS_n_STATUS_PKT_SUPPRESS_BMSK); +} + static void ipareg_construct_clkon_cfg_common( const struct ipahal_reg_clkon_cfg *clkon_cfg, u32 *val) { @@ -887,6 +938,20 @@ static void ipareg_construct_timers_pulse_gran_cfg( IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_BMSK(2)); } +static void ipareg_construct_timers_pulse_gran_cfg_v5_0( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + const struct ipahal_reg_timers_pulse_gran_cfg *gran_cfg = + (const struct ipahal_reg_timers_pulse_gran_cfg *)fields; + + ipareg_construct_timers_pulse_gran_cfg(reg, fields, val); + + IPA_SETFIELD_IN_REG(*val, + ipareg_timers_pulse_gran_code(gran_cfg->gran_3), + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_SHFT(3), + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_BMSK(3)); +} + static void ipareg_parse_timers_pulse_gran_cfg( enum ipahal_reg_name reg, void *fields, u32 val) { @@ -910,6 +975,21 @@ static void ipareg_parse_timers_pulse_gran_cfg( gran_cfg->gran_2 = ipareg_timers_pulse_gran_decode(code); } +static void ipareg_parse_timers_pulse_gran_cfg_v5_0( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + u8 code; + struct ipahal_reg_timers_pulse_gran_cfg *gran_cfg = + (struct ipahal_reg_timers_pulse_gran_cfg *)fields; + + ipareg_parse_timers_pulse_gran_cfg(reg, fields, val); + + code = IPA_GETFIELD_FROM_REG(val, + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_SHFT(3), + IPA_TIMERS_PULSE_GRAN_CFG_GRAN_X_BMSK(3)); + gran_cfg->gran_3 = ipareg_timers_pulse_gran_decode(code); +} + static void ipareg_construct_timers_xo_clk_div_cfg( enum ipahal_reg_name reg, const void *fields, u32 *val) { @@ -1118,6 +1198,55 @@ static void ipareg_construct_comp_cfg_v4_9( } +static void ipareg_construct_comp_cfg_v5_0( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_comp_cfg *comp_cfg = + (struct ipahal_reg_comp_cfg *)fields; + + ipareg_construct_comp_cfg_comon(comp_cfg, val); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gen_qmb_0_dynamic_asize, + IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_SHFT_v5_0, + IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gen_qmb_1_dynamic_asize, + IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_SHFT_v5_0, + IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->ipa_atomic_fetcher_arb_lock_dis, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT_v5_0, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->gsi_if_out_of_buf_stop_reset_mask_enable, + IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_SHFT_v5_0, + IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->genqmb_aooowr, + IPA_COMP_CFG_GENQMB_AOOOWR_SHFT_v5_0, + IPA_COMP_CFG_GENQMB_AOOOWR_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->qmb_ram_rd_cache_disable, + IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_SHFT_v5_0, + IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->ipa_full_flush_wait_rsc_closure_en, + IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v5_0, + IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, + !!comp_cfg->ram_arb_priority_client_samp_fix_disable, + IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_SHFT_v5_0, + IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_BMSK_v5_0); +} + static void ipareg_parse_comp_cfg_common( struct ipahal_reg_comp_cfg *comp_cfg, u32 val) { @@ -1293,6 +1422,56 @@ static void ipareg_parse_comp_cfg_v4_9( } +static void ipareg_parse_comp_cfg_v5_0( + enum ipahal_reg_name reg, void *fields, u32 val) +{ + struct ipahal_reg_comp_cfg *comp_cfg = + (struct ipahal_reg_comp_cfg *)fields; + + ipareg_parse_comp_cfg_common(comp_cfg, val); + + comp_cfg->gen_qmb_0_dynamic_asize = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_SHFT_v5_0, + IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_BMSK_v5_0); + + comp_cfg->gen_qmb_1_dynamic_asize = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_SHFT_v5_0, + IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_BMSK_v5_0); + + comp_cfg->ipa_atomic_fetcher_arb_lock_dis = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT_v5_0, + IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK_v5_0); + + comp_cfg->gsi_if_out_of_buf_stop_reset_mask_enable = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_SHFT_v5_0, + IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_BMSK_v5_0); + + comp_cfg->genqmb_aooowr = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_GENQMB_AOOOWR_SHFT_v5_0, + IPA_COMP_CFG_GENQMB_AOOOWR_BMSK_v5_0); + + comp_cfg->qmb_ram_rd_cache_disable = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_SHFT_v5_0, + IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_BMSK_v5_0); + + comp_cfg->ipa_full_flush_wait_rsc_closure_en = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v5_0, + IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v5_0); + + comp_cfg->ram_arb_priority_client_samp_fix_disable = + IPA_GETFIELD_FROM_REG(val, + IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_SHFT_v5_0, + IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_BMSK_v5_0); + +} + static void ipareg_parse_state_tx_wrapper_v4_5( enum ipahal_reg_name reg, void *fields, u32 val) { @@ -1594,6 +1773,17 @@ static void ipareg_construct_endp_init_rsrc_grp_n_v4_9( IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v4_9); } +static void ipareg_construct_endp_init_rsrc_grp_n_v5_0( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipahal_reg_endp_init_rsrc_grp *rsrc_grp = + (struct ipahal_reg_endp_init_rsrc_grp *)fields; + + IPA_SETFIELD_IN_REG(*val, rsrc_grp->rsrc_grp, + IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v5_0, + IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v5_0); +} + static void ipareg_construct_endp_init_hdr_metadata_n( enum ipahal_reg_name reg, const void *fields, u32 *val) { @@ -1767,6 +1957,21 @@ static void ipareg_construct_endp_init_hol_block_timer_n_v4_5( IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_BMSK_V4_5); } +static void ipareg_construct_endp_init_hol_block_timer_n_v5_0( + enum ipahal_reg_name reg, const void *fields, u32 *val) +{ + struct ipa_ep_cfg_holb *ep_holb = + (struct ipa_ep_cfg_holb *)fields; + + IPA_SETFIELD_IN_REG(*val, ep_holb->scaled_time, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_SHFT_V5_0, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_BMSK_V5_0); + + IPA_SETFIELD_IN_REG(*val, ep_holb->pulse_generator, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_SHFT_V5_0, + IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_BMSK_V5_0); +} + static void ipareg_construct_endp_init_ctrl_n(enum ipahal_reg_name reg, const void *fields, u32 *val) { @@ -1873,6 +2078,21 @@ static void ipareg_construct_endp_init_mode_n_v4_5(enum ipahal_reg_name reg, IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK_V4_5); } +static void ipareg_construct_endp_init_mode_n_v5_0(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_endp_init_mode *init_mode = + (struct ipahal_reg_endp_init_mode *)fields; + + IPA_SETFIELD_IN_REG(*val, init_mode->ep_mode.mode, + IPA_ENDP_INIT_MODE_n_MODE_SHFT_V4_5, + IPA_ENDP_INIT_MODE_n_MODE_BMSK_V4_5); + + IPA_SETFIELD_IN_REG(*val, init_mode->dst_pipe_number, + IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT_V5_0, + IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK_V5_0); +} + static void ipareg_construct_endp_init_route_n(enum ipahal_reg_name reg, const void *fields, u32 *val) { @@ -2133,6 +2353,23 @@ static void ipareg_construct_endp_init_hdr_ext_n_v4_5(enum ipahal_reg_name reg, ); } +static void ipareg_construct_endp_init_hdr_ext_n_v5_0(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + const struct ipa_ep_cfg_hdr_ext *ep_hdr_ext = + (const struct ipa_ep_cfg_hdr_ext *)fields; + + ipareg_construct_endp_init_hdr_ext_n_v4_5(reg, fields, val); + + IPA_SETFIELD_IN_REG(*val, ep_hdr_ext->hdr_bytes_to_remove_valid, + IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_VALID_SHFT_v5_0, + IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_VALID_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, ep_hdr_ext->hdr_bytes_to_remove, + IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_SHFT_v5_0, + IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_BMSK_v5_0); +} + static void ipareg_construct_endp_init_hdr_n(enum ipahal_reg_name reg, const void *fields, u32 *val) { @@ -2281,6 +2518,38 @@ static void ipareg_construct_route(enum ipahal_reg_name reg, IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_BMSK); } +static void ipareg_construct_route_v5_0(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_route *route; + + route = (struct ipahal_reg_route *)fields; + + IPA_SETFIELD_IN_REG(*val, route->route_dis, + IPA_ROUTE_ROUTE_DIS_SHFT_v5_0, + IPA_ROUTE_ROUTE_DIS_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, route->route_def_pipe, + IPA_ROUTE_ROUTE_DEF_PIPE_SHFT_v5_0, + IPA_ROUTE_ROUTE_DEF_PIPE_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, route->route_def_hdr_table, + IPA_ROUTE_ROUTE_DEF_HDR_TABLE_SHFT_v5_0, + IPA_ROUTE_ROUTE_DEF_HDR_TABLE_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, route->route_def_hdr_ofst, + IPA_ROUTE_ROUTE_DEF_HDR_OFST_SHFT_v5_0, + IPA_ROUTE_ROUTE_DEF_HDR_OFST_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, route->route_frag_def_pipe, + IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_SHFT_v5_0, + IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_BMSK_v5_0); + + IPA_SETFIELD_IN_REG(*val, route->route_def_retain_hdr, + IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_SHFT_v5_0, + IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_BMSK_v5_0); +} + static void ipareg_construct_qsb_max_writes(enum ipahal_reg_name reg, const void *fields, u32 *val) { @@ -2451,6 +2720,20 @@ static void ipareg_parse_tx_cfg_v4_9(enum ipahal_reg_name reg, IPA_TX_CFG_SSPND_PA_NO_START_STATE_BMSK_V4_9); } +static void ipareg_parse_tx_cfg_v5_0(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_reg_tx_cfg *tx_cfg; + + ipareg_parse_tx_cfg_v4_9(reg, fields, val); + + tx_cfg = (struct ipahal_reg_tx_cfg *)fields; + + tx_cfg->holb_sticky_drop_en = IPA_GETFIELD_FROM_REG(val, + IPA_TX_CFG_HOLB_STICKY_DROP_EN_SHFT_v5_0, + IPA_TX_CFG_HOLB_STICKY_DROP_EN_BMSK_v5_0); +} + static void ipareg_construct_tx_cfg(enum ipahal_reg_name reg, const void *fields, u32 *val) { @@ -2535,6 +2818,20 @@ static void ipareg_construct_tx_cfg_v4_9(enum ipahal_reg_name reg, IPA_TX_CFG_SSPND_PA_NO_START_STATE_BMSK_V4_9); } +static void ipareg_construct_tx_cfg_v5_0(enum ipahal_reg_name reg, + const void *fields, u32 *val) +{ + struct ipahal_reg_tx_cfg *tx_cfg; + + ipareg_construct_tx_cfg_v4_9(reg, fields, val); + + tx_cfg = (struct ipahal_reg_tx_cfg *)fields; + + IPA_SETFIELD_IN_REG(*val, tx_cfg->holb_sticky_drop_en, + IPA_TX_CFG_HOLB_STICKY_DROP_EN_SHFT_v5_0, + IPA_TX_CFG_HOLB_STICKY_DROP_EN_BMSK_v5_0); +} + static void ipareg_construct_idle_indication_cfg(enum ipahal_reg_name reg, const void *fields, u32 *val) { @@ -2721,6 +3018,28 @@ static void ipareg_parse_coal_qmap_cfg(enum ipahal_reg_name reg, IPA_COAL_QMAP_CFG_SHFT, IPA_COAL_QMAP_CFG_BMSK); } +static void ipareg_parse_ipa_flavor_0(enum ipahal_reg_name reg, + void *fields, u32 val) +{ + struct ipahal_ipa_flavor_0 *ipa_flavor = + (struct ipahal_ipa_flavor_0 *)fields; + + memset(ipa_flavor, 0, sizeof(*ipa_flavor)); + + ipa_flavor->ipa_pipes = IPA_GETFIELD_FROM_REG(val, + IPA_FLAVOR_0_IPA_PIPES_SHFT, + IPA_FLAVOR_0_IPA_PIPES_BMSK); + ipa_flavor->ipa_cons_pipes = IPA_GETFIELD_FROM_REG(val, + IPA_FLAVOR_0_IPA_CONS_PIPES_SHFT, + IPA_FLAVOR_0_IPA_CONS_PIPES_BMSK); + ipa_flavor->ipa_prod_pipes = IPA_GETFIELD_FROM_REG(val, + IPA_FLAVOR_0_IPA_PROD_PIPES_SHFT, + IPA_FLAVOR_0_IPA_PROD_PIPES_BMSK); + ipa_flavor->ipa_prod_lowest = IPA_GETFIELD_FROM_REG(val, + IPA_FLAVOR_0_IPA_PROD_LOWEST_SHFT, + IPA_FLAVOR_0_IPA_PROD_LOWEST_BMSK); +} + /* * struct ipahal_reg_obj - Register H/W information for specific IPA version * @construct - CB to construct register value from abstracted structure @@ -2741,6 +3060,7 @@ struct ipahal_reg_obj { int n_start; int n_end; bool en_print; + u32 m_ofst; }; /* @@ -2758,865 +3078,1206 @@ static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = { /* IPAv3 */ [IPA_HW_v3_0][IPA_ROUTE] = { ipareg_construct_route, ipareg_parse_dummy, - 0x00000048, 0, 0, 0, 0}, + 0x00000048, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_IRQ_STTS_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003008, 0x1000, 0, 0, 0}, + 0x00003008, 0x1000, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_IRQ_EN_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000300c, 0x1000, 0, 0, 0}, + 0x0000300c, 0x1000, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_IRQ_CLR_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003010, 0x1000, 0, 0, 0}, + 0x00003010, 0x1000, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_SUSPEND_IRQ_INFO_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003098, 0x1000, 0, 0, 0}, + 0x00003098, 0x1000, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_BCR] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000001D0, 0, 0, 0, 0}, + 0x000001D0, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENABLED_PIPES] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000038, 0, 0, 0, 0}, + 0x00000038, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_VERSION] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000034, 0, 0, 0, 0}, + 0x00000034, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_TAG_TIMER] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000060, 0, 0, 0, 0}, + 0x00000060, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_COMP_HW_VERSION] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000030, 0, 0, 0, 0}, + 0x00000030, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_COMP_CFG] = { ipareg_construct_comp_cfg, ipareg_parse_comp_cfg, - 0x0000003C, 0, 0, 0, 0}, + 0x0000003C, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_STATE_AGGR_ACTIVE] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000010C, 0, 0, 0, 0}, + 0x0000010C, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_INIT_HDR_n] = { ipareg_construct_endp_init_hdr_n, ipareg_parse_dummy, - 0x00000810, 0x70, 0, 0, 0}, + 0x00000810, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_INIT_HDR_EXT_n] = { ipareg_construct_endp_init_hdr_ext_n, ipareg_parse_dummy, - 0x00000814, 0x70, 0, 0, 0}, + 0x00000814, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_INIT_AGGR_n] = { ipareg_construct_endp_init_aggr_n, ipareg_parse_endp_init_aggr_n, - 0x00000824, 0x70, 0, 0, 0}, + 0x00000824, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_AGGR_FORCE_CLOSE] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000001EC, 0, 0, 0, 0}, + 0x000001EC, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_INIT_ROUTE_n] = { ipareg_construct_endp_init_route_n, ipareg_parse_dummy, - 0x00000828, 0x70, 0, 0, 0}, + 0x00000828, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_INIT_MODE_n] = { ipareg_construct_endp_init_mode_n, ipareg_parse_dummy, - 0x00000820, 0x70, 0, 0, 0}, + 0x00000820, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_INIT_NAT_n] = { ipareg_construct_endp_init_nat_n, ipareg_parse_dummy, - 0x0000080C, 0x70, 0, 0, 0}, + 0x0000080C, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_INIT_CTRL_n] = { ipareg_construct_endp_init_ctrl_n, ipareg_parse_endp_init_ctrl_n, - 0x00000800, 0x70, 0, 0, 0}, + 0x00000800, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_INIT_CTRL_SCND_n] = { ipareg_construct_endp_init_ctrl_scnd_n, ipareg_parse_dummy, - 0x00000804, 0x70, 0, 0, 0}, + 0x00000804, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_INIT_HOL_BLOCK_EN_n] = { ipareg_construct_endp_init_hol_block_en_n, ipareg_parse_dummy, - 0x0000082c, 0x70, 0, 0, 0}, + 0x0000082c, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_INIT_HOL_BLOCK_TIMER_n] = { ipareg_construct_endp_init_hol_block_timer_n, ipareg_parse_dummy, - 0x00000830, 0x70, 0, 0, 0}, + 0x00000830, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_INIT_DEAGGR_n] = { ipareg_construct_endp_init_deaggr_n, ipareg_parse_dummy, - 0x00000834, 0x70, 0, 0, 0}, + 0x00000834, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_INIT_SEQ_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000083C, 0x70, 0, 0, 0}, + 0x0000083C, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_DEBUG_CNT_REG_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000600, 0x4, 0, 0, 0}, + 0x00000600, 0x4, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_INIT_CFG_n] = { ipareg_construct_endp_init_cfg_n, ipareg_parse_dummy, - 0x00000808, 0x70, 0, 0, 0}, + 0x00000808, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_IRQ_EE_UC_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000301c, 0x1000, 0, 0, 0}, + 0x0000301c, 0x1000, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_INIT_HDR_METADATA_MASK_n] = { ipareg_construct_endp_init_hdr_metadata_mask_n, ipareg_parse_dummy, - 0x00000818, 0x70, 0, 0, 0}, + 0x00000818, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_INIT_HDR_METADATA_n] = { ipareg_construct_endp_init_hdr_metadata_n, ipareg_parse_dummy, - 0x0000081c, 0x70, 0, 0, 0}, + 0x0000081c, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_INIT_RSRC_GRP_n] = { ipareg_construct_endp_init_rsrc_grp_n, ipareg_parse_dummy, - 0x00000838, 0x70, 0, 0, 0}, + 0x00000838, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_SHARED_MEM_SIZE] = { ipareg_construct_dummy, ipareg_parse_shared_mem_size, - 0x00000054, 0, 0, 0, 0}, + 0x00000054, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_SW_AREA_RAM_DIRECT_ACCESS_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00007000, 0x4, 0, 0, 0}, + 0x00007000, 0x4, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_DEBUG_CNT_CTRL_n] = { ipareg_construct_debug_cnt_ctrl_n, ipareg_parse_dummy, - 0x00000640, 0x4, 0, 0, 0}, + 0x00000640, 0x4, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_UC_MAILBOX_m_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00032000, 0x4, 0, 0, 0}, + 0x00032000, 0x4, 0, 0, 0, 0x80}, [IPA_HW_v3_0][IPA_FILT_ROUT_HASH_FLUSH] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000090, 0, 0, 0, 0}, + 0x00000090, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_SINGLE_NDP_MODE] = { ipareg_construct_single_ndp_mode, ipareg_parse_single_ndp_mode, - 0x00000068, 0, 0, 0, 0}, + 0x00000068, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_QCNCM] = { ipareg_construct_qcncm, ipareg_parse_qcncm, - 0x00000064, 0, 0, 0, 0}, + 0x00000064, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_SYS_PKT_PROC_CNTXT_BASE] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000001e0, 0, 0, 0, 0}, + 0x000001e0, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_LOCAL_PKT_PROC_CNTXT_BASE] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000001e8, 0, 0, 0, 0}, + 0x000001e8, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_STATUS_n] = { ipareg_construct_endp_status_n, ipareg_parse_dummy, - 0x00000840, 0x70, 0, 0, 0}, + 0x00000840, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_ENDP_FILTER_ROUTER_HSH_CFG_n] = { ipareg_construct_hash_cfg_n, ipareg_parse_hash_cfg_n, - 0x0000085C, 0x70, 0, 0, 0}, + 0x0000085C, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy, ipareg_parse_dummy, - 0x00000400, 0x20, 0, 0, 0}, + 0x00000400, 0x20, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy, ipareg_parse_dummy, - 0x00000404, 0x20, 0, 0, 0}, + 0x00000404, 0x20, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy, ipareg_parse_dummy, - 0x00000408, 0x20, 0, 0, 0}, + 0x00000408, 0x20, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy, ipareg_parse_dummy, - 0x0000040C, 0x20, 0, 0, 0}, + 0x0000040C, 0x20, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_DST_RSRC_GRP_01_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy, ipareg_parse_dummy, - 0x00000500, 0x20, 0, 0, 0}, + 0x00000500, 0x20, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_DST_RSRC_GRP_23_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy, ipareg_parse_dummy, - 0x00000504, 0x20, 0, 0, 0}, + 0x00000504, 0x20, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_DST_RSRC_GRP_45_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy, ipareg_parse_dummy, - 0x00000508, 0x20, 0, 0, 0}, + 0x00000508, 0x20, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_DST_RSRC_GRP_67_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy, ipareg_parse_dummy, - 0x0000050c, 0x20, 0, 0, 0}, + 0x0000050c, 0x20, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_RX_HPS_CLIENTS_MIN_DEPTH_0] = { ipareg_construct_rx_hps_clients_depth0, ipareg_parse_dummy, - 0x000023C4, 0, 0, 0, 0}, + 0x000023C4, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_RX_HPS_CLIENTS_MIN_DEPTH_1] = { ipareg_construct_rx_hps_clients_depth1, ipareg_parse_dummy, - 0x000023C8, 0, 0, 0, 0}, + 0x000023C8, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_RX_HPS_CLIENTS_MAX_DEPTH_0] = { ipareg_construct_rx_hps_clients_depth0, ipareg_parse_dummy, - 0x000023CC, 0, 0, 0, 0}, + 0x000023CC, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_RX_HPS_CLIENTS_MAX_DEPTH_1] = { ipareg_construct_rx_hps_clients_depth1, ipareg_parse_dummy, - 0x000023D0, 0, 0, 0, 0}, + 0x000023D0, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_QSB_MAX_WRITES] = { ipareg_construct_qsb_max_writes, ipareg_parse_dummy, - 0x00000074, 0, 0, 0, 0}, + 0x00000074, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_QSB_MAX_READS] = { ipareg_construct_qsb_max_reads, ipareg_parse_dummy, - 0x00000078, 0, 0, 0, 0}, + 0x00000078, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_DPS_SEQUENCER_FIRST] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0001e000, 0, 0, 0, 0}, + 0x0001e000, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_DPS_SEQUENCER_LAST] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0001e07c, 0, 0, 0, 0}, + 0x0001e07c, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_HPS_SEQUENCER_FIRST] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0001e080, 0, 0, 0, 0}, + 0x0001e080, 0, 0, 0, 0, 0}, [IPA_HW_v3_0][IPA_HPS_SEQUENCER_LAST] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0001e26c, 0, 0, 0, 0}, + 0x0001e26c, 0, 0, 0, 0, 0}, /* IPAv3.1 */ [IPA_HW_v3_1][IPA_SUSPEND_IRQ_INFO_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003030, 0x1000, 0, 0, 0}, + 0x00003030, 0x1000, 0, 0, 0, 0}, [IPA_HW_v3_1][IPA_SUSPEND_IRQ_EN_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003034, 0x1000, 0, 0, 0}, + 0x00003034, 0x1000, 0, 0, 0, 0}, [IPA_HW_v3_1][IPA_SUSPEND_IRQ_CLR_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003038, 0x1000, 0, 0, 0}, + 0x00003038, 0x1000, 0, 0, 0, 0}, /* IPAv3.5 */ [IPA_HW_v3_5][IPA_TX_CFG] = { ipareg_construct_tx_cfg, ipareg_parse_tx_cfg, - 0x000001FC, 0, 0, 0, 0}, + 0x000001FC, 0, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy_v3_5, ipareg_parse_dummy, - 0x00000400, 0x20, 0, 0, 0}, + 0x00000400, 0x20, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy_v3_5, ipareg_parse_dummy, - 0x00000404, 0x20, 0, 0, 0}, + 0x00000404, 0x20, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_DST_RSRC_GRP_01_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy_v3_5, ipareg_parse_dummy, - 0x00000500, 0x20, 0, 0, 0}, + 0x00000500, 0x20, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_DST_RSRC_GRP_23_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy_v3_5, ipareg_parse_dummy, - 0x00000504, 0x20, 0, 0, 0}, + 0x00000504, 0x20, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_DST_RSRC_GRP_45_RSRC_TYPE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_DST_RSRC_GRP_67_RSRC_TYPE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_ENDP_INIT_RSRC_GRP_n] = { ipareg_construct_endp_init_rsrc_grp_n_v3_5, ipareg_parse_dummy, - 0x00000838, 0x70, 0, 0, 0}, + 0x00000838, 0x70, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_RX_HPS_CLIENTS_MIN_DEPTH_0] = { ipareg_construct_rx_hps_clients_depth0_v3_5, ipareg_parse_dummy, - 0x000023C4, 0, 0, 0, 0}, + 0x000023C4, 0, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_RX_HPS_CLIENTS_MIN_DEPTH_1] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_RX_HPS_CLIENTS_MAX_DEPTH_0] = { ipareg_construct_rx_hps_clients_depth0_v3_5, ipareg_parse_dummy, - 0x000023CC, 0, 0, 0, 0}, + 0x000023CC, 0, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_RX_HPS_CLIENTS_MAX_DEPTH_1] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_IDLE_INDICATION_CFG] = { ipareg_construct_idle_indication_cfg, ipareg_parse_dummy, - 0x00000220, 0, 0, 0, 0}, + 0x00000220, 0, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_HPS_FTCH_ARB_QUEUE_WEIGHT] = { ipareg_construct_hps_queue_weights, - ipareg_parse_hps_queue_weights, 0x000005a4, 0, 0, 0, 0}, + ipareg_parse_hps_queue_weights, 0x000005a4, 0, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_COUNTER_CFG] = { ipareg_construct_counter_cfg, ipareg_parse_counter_cfg, - 0x000001F0, 0, 0, 0, 0}, + 0x000001F0, 0, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_ENDP_GSI_CFG1_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00002794, 0x4, 0, 0, 0 }, + 0x00002794, 0x4, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_ENDP_GSI_CFG_AOS_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000029A8, 0x4, 0, 0, 0 }, + 0x000029A8, 0x4, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_ENDP_GSI_CFG_TLV_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00002924, 0x4, 0, 0, 0 }, + 0x00002924, 0x4, 0, 0, 0, 0}, [IPA_HW_v3_5][IPA_HPS_SEQUENCER_LAST] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0001e1fc, 0, 0, 0, 0}, + 0x0001e1fc, 0, 0, 0, 0, 0}, /* IPAv4.0 */ [IPA_HW_v4_0][IPA_SUSPEND_IRQ_INFO_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003030, 0x1000, 0, 0, 1}, + 0x00003030, 0x1000, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_SUSPEND_IRQ_EN_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003034, 0x1000, 0, 0, 1}, + 0x00003034, 0x1000, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_SUSPEND_IRQ_CLR_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003038, 0x1000, 0, 0, 1}, + 0x00003038, 0x1000, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_IRQ_EN_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000300c, 0x1000, 0, 0, 1}, + 0x0000300c, 0x1000, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_TAG_TIMER] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000060, 0, 0, 0, 1}, + 0x00000060, 0, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_CTRL_n] = { ipareg_construct_endp_init_ctrl_n_v4_0, ipareg_parse_dummy, - 0x00000800, 0x70, 0, 22, 1}, + 0x00000800, 0x70, 0, 22, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_HDR_EXT_n] = { ipareg_construct_endp_init_hdr_ext_n, ipareg_parse_dummy, - 0x00000814, 0x70, 0, 22, 1}, + 0x00000814, 0x70, 0, 22, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_AGGR_n] = { ipareg_construct_endp_init_aggr_n, ipareg_parse_endp_init_aggr_n, - 0x00000824, 0x70, 0, 22, 1}, + 0x00000824, 0x70, 0, 22, 1, 0}, [IPA_HW_v4_0][IPA_TX_CFG] = { ipareg_construct_tx_cfg_v4_0, ipareg_parse_tx_cfg_v4_0, - 0x000001FC, 0, 0, 0, 0}, + 0x000001FC, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_DEBUG_CNT_REG_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_DEBUG_CNT_CTRL_n] = { ipareg_construct_debug_cnt_ctrl_n, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_QCNCM] = { ipareg_construct_qcncm, ipareg_parse_qcncm, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_SINGLE_NDP_MODE] = { ipareg_construct_single_ndp_mode, ipareg_parse_single_ndp_mode, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_QSB_MAX_READS] = { ipareg_construct_qsb_max_reads_v4_0, ipareg_parse_dummy, - 0x00000078, 0, 0, 0, 0}, + 0x00000078, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_FILT_ROUT_HASH_FLUSH] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000014c, 0, 0, 0, 0}, + 0x0000014c, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_HDR_n] = { ipareg_construct_endp_init_hdr_n, ipareg_parse_dummy, - 0x00000810, 0x70, 0, 22, 1}, + 0x00000810, 0x70, 0, 22, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_ROUTE_n] = { ipareg_construct_endp_init_route_n, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_MODE_n] = { ipareg_construct_endp_init_mode_n, ipareg_parse_dummy, - 0x00000820, 0x70, 0, 9, 1}, + 0x00000820, 0x70, 0, 9, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_NAT_n] = { ipareg_construct_endp_init_nat_n, ipareg_parse_dummy, - 0x0000080C, 0x70, 0, 9, 1}, + 0x0000080C, 0x70, 0, 9, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_STATUS_n] = { ipareg_construct_endp_status_n_v4_0, ipareg_parse_dummy, - 0x00000840, 0x70, 0, 22, 1}, + 0x00000840, 0x70, 0, 22, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_FILTER_ROUTER_HSH_CFG_n] = { ipareg_construct_hash_cfg_n, ipareg_parse_hash_cfg_n, - 0x0000085C, 0x70, 0, 31, 1}, + 0x0000085C, 0x70, 0, 31, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_CONN_TRACK_n] = { ipareg_construct_endp_init_conn_track_n, ipareg_parse_dummy, - 0x00000850, 0x70, 0, 9, 1}, + 0x00000850, 0x70, 0, 9, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_CTRL_SCND_n] = { ipareg_construct_endp_init_ctrl_scnd_n, ipareg_parse_dummy, - 0x00000804, 0x70, 0, 22, 1}, + 0x00000804, 0x70, 0, 22, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_HOL_BLOCK_EN_n] = { ipareg_construct_endp_init_hol_block_en_n, ipareg_parse_dummy, - 0x0000082c, 0x70, 10, 22, 1}, + 0x0000082c, 0x70, 10, 22, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_HOL_BLOCK_TIMER_n] = { ipareg_construct_endp_init_hol_block_timer_n, ipareg_parse_dummy, - 0x00000830, 0x70, 10, 22, 1}, + 0x00000830, 0x70, 10, 22, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_DEAGGR_n] = { ipareg_construct_endp_init_deaggr_n, ipareg_parse_dummy, - 0x00000834, 0x70, 0, 9, 1}, + 0x00000834, 0x70, 0, 9, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_SEQ_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000083C, 0x70, 0, 9, 1}, + 0x0000083C, 0x70, 0, 9, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_CFG_n] = { ipareg_construct_endp_init_cfg_n, ipareg_parse_dummy, - 0x00000808, 0x70, 0, 22, 1}, + 0x00000808, 0x70, 0, 22, 1, 0}, [IPA_HW_v4_0][IPA_IRQ_EE_UC_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000301c, 0x1000, 0, 0, 1}, + 0x0000301c, 0x1000, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_HDR_METADATA_MASK_n] = { ipareg_construct_endp_init_hdr_metadata_mask_n, ipareg_parse_dummy, - 0x00000818, 0x70, 10, 22, 1}, + 0x00000818, 0x70, 10, 22, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_HDR_METADATA_n] = { ipareg_construct_endp_init_hdr_metadata_n, ipareg_parse_dummy, - 0x0000081c, 0x70, 0, 9, 1}, + 0x0000081c, 0x70, 0, 9, 1, 0}, [IPA_HW_v4_0][IPA_CLKON_CFG] = { ipareg_construct_clkon_cfg, ipareg_parse_clkon_cfg, - 0x00000044, 0, 0, 0, 0}, + 0x00000044, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_QUOTA_BASE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000700, 0x4, 0, 0, 0}, + 0x00000700, 0x4, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_QUOTA_MASK_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000708, 0x4, 0, 0, 0}, + 0x00000708, 0x4, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_TETHERING_BASE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000710, 0x4, 0, 0, 0}, + 0x00000710, 0x4, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_TETHERING_MASK_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000718, 0x4, 0, 0, 0}, + 0x00000718, 0x4, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_FILTER_IPV4_BASE] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000720, 0, 0, 0, 0}, + 0x00000720, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_FILTER_IPV6_BASE] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000724, 0, 0, 0, 0}, + 0x00000724, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_ROUTER_IPV4_BASE] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000728, 0, 0, 0, 0}, + 0x00000728, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_ROUTER_IPV6_BASE] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000072C, 0, 0, 0, 0}, + 0x0000072C, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_FILTER_IPV4_START_ID] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000730, 0, 0, 0, 0}, + 0x00000730, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_FILTER_IPV6_START_ID] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000734, 0, 0, 0, 0}, + 0x00000734, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_ROUTER_IPV4_START_ID] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000738, 0, 0, 0, 0}, + 0x00000738, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_ROUTER_IPV6_START_ID] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000073C, 0, 0, 0, 0}, + 0x0000073C, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_FILTER_IPV4_END_ID] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000740, 0, 0, 0, 0}, + 0x00000740, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_FILTER_IPV6_END_ID] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000744, 0, 0, 0, 0}, + 0x00000744, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_ROUTER_IPV4_END_ID] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000748, 0, 0, 0, 0}, + 0x00000748, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_ROUTER_IPV6_END_ID] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000074C, 0, 0, 0, 0}, + 0x0000074C, 0, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_STAT_DROP_CNT_BASE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000750, 0x4, 0, 0, 1}, + 0x00000750, 0x4, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_STAT_DROP_CNT_MASK_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000758, 0x4, 0, 0, 1}, + 0x00000758, 0x4, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_STATE_TX_WRAPPER] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000090, 0, 0, 0, 1}, + 0x00000090, 0, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_STATE_TX1] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000094, 0, 0, 0, 1}, + 0x00000094, 0, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_STATE_FETCHER] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000098, 0, 0, 0, 1}, + 0x00000098, 0, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_STATE_FETCHER_MASK] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000009C, 0, 0, 0, 1}, + 0x0000009C, 0, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_STATE_DFETCHER] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000000A0, 0, 0, 0, 1}, + 0x000000A0, 0, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_STATE_ACL] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000000A4, 0, 0, 0, 1}, + 0x000000A4, 0, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_STATE] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000000A8, 0, 0, 0, 1}, + 0x000000A8, 0, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_STATE_RX_ACTIVE] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000000AC, 0, 0, 0, 1}, + 0x000000AC, 0, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_STATE_TX0] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000000B0, 0, 0, 0, 1}, + 0x000000B0, 0, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_STATE_AGGR_ACTIVE] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000000B4, 0, 0, 0, 1}, + 0x000000B4, 0, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_STATE_GSI_TLV] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000000B8, 0, 0, 0, 1}, + 0x000000B8, 0, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_STATE_GSI_AOS] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000000BC, 0, 0, 0, 1}, + 0x000000BC, 0, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_STATE_GSI_IF] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000000C0, 0, 0, 0, 1}, + 0x000000C0, 0, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_STATE_GSI_SKIP] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000000C4, 0, 0, 0, 1}, + 0x000000C4, 0, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_SNOC_FEC_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003018, 0x1000, 0, 0, 1}, + 0x00003018, 0x1000, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_FEC_ADDR_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003020, 0x1000, 0, 0, 1}, + 0x00003020, 0x1000, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_FEC_ADDR_MSB_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003024, 0x1000, 0, 0, 1}, + 0x00003024, 0x1000, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_FEC_ATTR_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003028, 0x1000, 0, 0, 1}, + 0x00003028, 0x1000, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_HOLB_DROP_IRQ_INFO_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000303C, 0x1000, 0, 0, 1}, + 0x0000303C, 0x1000, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_HOLB_DROP_IRQ_EN_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003040, 0x1000, 0, 0, 1}, + 0x00003040, 0x1000, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_HOLB_DROP_IRQ_CLR_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003044, 0x1000, 0, 0, 1}, + 0x00003044, 0x1000, 0, 0, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_CTRL_STATUS_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000864, 0x70, 0, 22, 1}, + 0x00000864, 0x70, 0, 22, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_PROD_CFG_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000CC8, 0x70, 10, 22, 1}, + 0x00000CC8, 0x70, 10, 22, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_INIT_RSRC_GRP_n] = { ipareg_construct_endp_init_rsrc_grp_n_v3_5, ipareg_parse_dummy, - 0x00000838, 0x70, 0, 22, 1}, + 0x00000838, 0x70, 0, 22, 1, 0}, [IPA_HW_v4_0][IPA_ENDP_YELLOW_RED_MARKER_CFG_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000CC0, 0x70, 10, 22, 1}, + 0x00000CC0, 0x70, 10, 22, 1, 0}, /* IPA4.2 */ [IPA_HW_v4_2][IPA_IDLE_INDICATION_CFG] = { ipareg_construct_idle_indication_cfg, ipareg_parse_dummy, - 0x00000240, 0, 0, 0, 0}, + 0x00000240, 0, 0, 0, 0, 0}, [IPA_HW_v4_2][IPA_ENDP_INIT_HOL_BLOCK_TIMER_n] = { ipareg_construct_endp_init_hol_block_timer_n_v4_2, ipareg_parse_dummy, - 0x00000830, 0x70, 8, 16, 1}, + 0x00000830, 0x70, 8, 16, 1, 0}, [IPA_HW_v4_2][IPA_ENDP_FILTER_ROUTER_HSH_CFG_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_2][IPA_HPS_FTCH_ARB_QUEUE_WEIGHT] = { ipareg_construct_dummy, - ipareg_parse_dummy, -1, 0, 0, 0, 0}, + ipareg_parse_dummy, -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_2][IPA_FILT_ROUT_HASH_EN] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000148, 0, 0, 0, 0}, + 0x00000148, 0, 0, 0, 0, 0}, /* IPA4.5 */ [IPA_HW_v4_5][IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy, - 0x00000400, 0x20, 0, 0, 0}, + 0x00000400, 0x20, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy, - 0x00000404, 0x20, 0, 0, 0}, + 0x00000404, 0x20, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy, - 0x00000408, 0x20, 0, 0, 0}, + 0x00000408, 0x20, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_DST_RSRC_GRP_01_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy, - 0x00000500, 0x20, 0, 0, 0}, + 0x00000500, 0x20, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_DST_RSRC_GRP_23_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy, - 0x00000504, 0x20, 0, 0, 0}, + 0x00000504, 0x20, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_DST_RSRC_GRP_45_RSRC_TYPE_n] = { ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy, - 0x00000508, 0x20, 0, 0, 0}, + 0x00000508, 0x20, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_RX_HPS_CLIENTS_MIN_DEPTH_0] = { ipareg_construct_rx_hps_clients_depth0_v4_5, ipareg_parse_dummy, - 0x000023c4, 0, 0, 0, 0}, + 0x000023c4, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_RX_HPS_CLIENTS_MAX_DEPTH_0] = { ipareg_construct_rx_hps_clients_depth0_v4_5, ipareg_parse_dummy, - 0x000023cc, 0, 0, 0, 0}, + 0x000023cc, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_BCR] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_COMP_CFG] = { ipareg_construct_comp_cfg_v4_5, ipareg_parse_comp_cfg_v4_5, - 0x0000003C, 0, 0, 0, 0}, + 0x0000003C, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STATE_TX_WRAPPER] = { ipareg_construct_dummy, ipareg_parse_state_tx_wrapper_v4_5, - 0x00000090, 0, 0, 0, 1 }, + 0x00000090, 0, 0, 0, 1, 0}, [IPA_HW_v4_5][IPA_STATE_FETCHER_MASK] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STATE_FETCHER_MASK_0] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000009C, 0, 0, 0, 1}, + 0x0000009C, 0, 0, 0, 1, 0}, [IPA_HW_v4_5][IPA_STATE_FETCHER_MASK_1] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000000CC, 0, 0, 0, 1}, + 0x000000CC, 0, 0, 0, 1, 0}, [IPA_HW_v4_5][IPA_COUNTER_CFG] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STATE_GSI_IF_CONS] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000000C8, 0, 0, 0, 1}, + 0x000000C8, 0, 0, 0, 1, 0}, [IPA_HW_v4_5][IPA_STATE_DPL_FIFO] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000000D0, 0, 0, 0, 1}, + 0x000000D0, 0, 0, 0, 1, 0}, [IPA_HW_v4_5][IPA_STATE_COAL_MASTER] = { ipareg_construct_dummy, ipareg_parse_state_coal_master, - 0x000000D4, 0, 0, 0, 1}, + 0x000000D4, 0, 0, 0, 1, 0}, [IPA_HW_v4_5][IPA_GENERIC_RAM_ARBITER_PRIORITY] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000000D8, 0, 0, 0, 1}, + 0x000000D8, 0, 0, 0, 1, 0}, [IPA_HW_v4_5][IPA_STATE_NLO_AGGR] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000000DC, 0, 0, 0, 1}, + 0x000000DC, 0, 0, 0, 1, 0}, [IPA_HW_v4_5][IPA_STATE_COAL_MASTER_1] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000000E0, 0, 0, 0, 1}, + 0x000000E0, 0, 0, 0, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_YELLOW_RED_MARKER_CFG_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000860, 0x70, 13, 30, 1}, + 0x00000860, 0x70, 13, 30, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_MODE_n] = { ipareg_construct_endp_init_mode_n_v4_5, ipareg_parse_dummy, - 0x00000820, 0x70, 0, 12, 1}, + 0x00000820, 0x70, 0, 12, 1, 0}, [IPA_HW_v4_5][IPA_TX_CFG] = { ipareg_construct_tx_cfg_v4_5, ipareg_parse_tx_cfg_v4_5, - 0x000001FC, 0, 0, 0, 0}, + 0x000001FC, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_CLKON_CFG] = { ipareg_construct_clkon_cfg_v4_5, ipareg_parse_clkon_cfg_v4_5, - 0x00000044, 0, 0, 0, 0}, + 0x00000044, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_QTIME_TIMESTAMP_CFG] = { ipareg_construct_qtime_timestamp_cfg, ipareg_parse_dummy, - 0x00000024c, 0, 0, 0, 1}, + 0x00000024c, 0, 0, 0, 1, 0}, [IPA_HW_v4_5][IPA_TIMERS_PULSE_GRAN_CFG] = { ipareg_construct_timers_pulse_gran_cfg, ipareg_parse_timers_pulse_gran_cfg, - 0x000000254, 0, 0, 0, 1}, + 0x000000254, 0, 0, 0, 1, 0}, [IPA_HW_v4_5][IPA_TIMERS_XO_CLK_DIV_CFG] = { ipareg_construct_timers_xo_clk_div_cfg, ipareg_parse_timers_xo_clk_div_cfg, - 0x000000250, 0, 0, 0, 1}, + 0x000000250, 0, 0, 0, 1, 0}, [IPA_HW_v4_5][IPA_STAT_QUOTA_BASE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000700, 0x4, 0, 0, 0}, + 0x00000700, 0x4, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STAT_QUOTA_MASK_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000708, 0x4, 0, 0, 0}, + 0x00000708, 0x4, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STAT_TETHERING_BASE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000710, 0x4, 0, 0, 0}, + 0x00000710, 0x4, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STAT_TETHERING_MASK_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000718, 0x4, 0, 0, 0}, + 0x00000718, 0x4, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STAT_FILTER_IPV4_BASE] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000720, 0, 0, 0, 0}, + 0x00000720, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STAT_FILTER_IPV6_BASE] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000724, 0, 0, 0, 0}, + 0x00000724, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STAT_ROUTER_IPV4_BASE] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000728, 0, 0, 0, 0}, + 0x00000728, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STAT_ROUTER_IPV6_BASE] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000072C, 0, 0, 0, 0}, + 0x0000072C, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STAT_DROP_CNT_BASE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000750, 0x4, 0, 0, 1}, + 0x00000750, 0x4, 0, 0, 1, 0}, [IPA_HW_v4_5][IPA_STAT_DROP_CNT_MASK_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000758, 0x4, 0, 0, 1}, + 0x00000758, 0x4, 0, 0, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_SEQ_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000083C, 0x70, 0, 12, 1}, + 0x0000083C, 0x70, 0, 12, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_CFG_n] = { ipareg_construct_endp_init_cfg_n, ipareg_parse_dummy, - 0x00000808, 0x70, 0, 30, 1}, + 0x00000808, 0x70, 0, 30, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_DEAGGR_n] = { ipareg_construct_endp_init_deaggr_n_v4_5, ipareg_parse_dummy, - 0x00000834, 0x70, 0, 12, 1}, + 0x00000834, 0x70, 0, 12, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_CTRL_n] = { ipareg_construct_endp_init_ctrl_n_v4_0, ipareg_parse_dummy, - 0x00000800, 0x70, 0, 30, 1}, + 0x00000800, 0x70, 0, 30, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_CTRL_SCND_n] = { ipareg_construct_endp_init_ctrl_scnd_n, ipareg_parse_dummy, - 0x00000804, 0x70, 0, 30, 1}, + 0x00000804, 0x70, 0, 30, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_CTRL_STATUS_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000864, 0x70, 0, 30, 1}, + 0x00000864, 0x70, 0, 30, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_PROD_CFG_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000CC8, 0x70, 13, 30, 1}, + 0x00000CC8, 0x70, 13, 30, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_FILTER_ROUTER_HSH_CFG_n] = { ipareg_construct_hash_cfg_n, ipareg_parse_hash_cfg_n, - 0x0000085C, 0x70, 0, 31, 1}, + 0x0000085C, 0x70, 0, 31, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_STATUS_n] = { ipareg_construct_endp_status_n_v4_5, ipareg_parse_dummy, - 0x00000840, 0x70, 0, 30, 1}, + 0x00000840, 0x70, 0, 30, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_NAT_n] = { ipareg_construct_endp_init_nat_n, ipareg_parse_dummy, - 0x0000080C, 0x70, 0, 12, 1}, + 0x0000080C, 0x70, 0, 12, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_CONN_TRACK_n] = { ipareg_construct_endp_init_conn_track_n, ipareg_parse_dummy, - 0x00000850, 0x70, 0, 12, 1}, + 0x00000850, 0x70, 0, 12, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_RSRC_GRP_n] = { ipareg_construct_endp_init_rsrc_grp_n_v4_5, ipareg_parse_dummy, - 0x00000838, 0x70, 0, 30, 1}, + 0x00000838, 0x70, 0, 30, 1, 0}, [IPA_HW_v4_5][IPA_STAT_FILTER_IPV4_START_ID] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STAT_FILTER_IPV6_START_ID] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STAT_ROUTER_IPV4_START_ID] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STAT_ROUTER_IPV6_START_ID] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STAT_FILTER_IPV4_END_ID] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STAT_FILTER_IPV6_END_ID] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STAT_ROUTER_IPV4_END_ID] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_STAT_ROUTER_IPV6_END_ID] = { ipareg_construct_dummy, ipareg_parse_dummy, - -1, 0, 0, 0, 0}, + -1, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_DPS_SEQUENCER_FIRST] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00002570, 0, 0, 0, 0}, + 0x00002570, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_DPS_SEQUENCER_LAST] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00002574, 0, 0, 0, 0}, + 0x00002574, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_HPS_SEQUENCER_FIRST] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00002578, 0, 0, 0, 0}, + 0x00002578, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_HPS_SEQUENCER_LAST] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000257c, 0, 0, 0, 0}, + 0x0000257c, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_NAT_TIMER] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00000058, 0, 0, 0, 1}, + 0x00000058, 0, 0, 0, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_HOL_BLOCK_EN_n] = { ipareg_construct_endp_init_hol_block_en_n, ipareg_parse_dummy, - 0x0000082c, 0x70, 13, 30, 1}, + 0x0000082c, 0x70, 13, 30, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_HOL_BLOCK_TIMER_n] = { ipareg_construct_endp_init_hol_block_timer_n_v4_5, ipareg_parse_dummy, - 0x00000830, 0x70, 13, 30, 1}, + 0x00000830, 0x70, 13, 30, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_AGGR_n] = { ipareg_construct_endp_init_aggr_n_v4_5, ipareg_parse_endp_init_aggr_n_v4_5, - 0x00000824, 0x70, 0, 30, 1}, + 0x00000824, 0x70, 0, 30, 1, 0}, [IPA_HW_v4_5][IPA_SW_AREA_RAM_DIRECT_ACCESS_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000010000, 0x4, 0, 0, 0}, + 0x000010000, 0x4, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_HDR_n] = { ipareg_construct_endp_init_hdr_n_v4_5, ipareg_parse_dummy, - 0x00000810, 0x70, 0, 30, 1}, + 0x00000810, 0x70, 0, 30, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_HDR_EXT_n] = { ipareg_construct_endp_init_hdr_ext_n_v4_5, ipareg_parse_dummy, - 0x00000814, 0x70, 0, 30, 1}, + 0x00000814, 0x70, 0, 30, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_HDR_METADATA_n] = { ipareg_construct_endp_init_hdr_metadata_n, ipareg_parse_dummy, - 0x0000081c, 0x70, 0, 12, 1}, + 0x0000081c, 0x70, 0, 12, 1, 0}, [IPA_HW_v4_5][IPA_ENDP_INIT_HDR_METADATA_MASK_n] = { ipareg_construct_endp_init_hdr_metadata_mask_n, ipareg_parse_dummy, - 0x00000818, 0x70, 13, 30, 1}, + 0x00000818, 0x70, 13, 30, 1, 0}, [IPA_HW_v4_5][IPA_UC_MAILBOX_m_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00082000, 0x4, 0, 0, 0}, + 0x00082000, 0x4, 0, 0, 0, 0x80}, [IPA_HW_v4_5][IPA_COAL_EVICT_LRU] = { ipareg_construct_coal_evict_lru, ipareg_parse_coal_evict_lru, - 0x0000180C, 0, 0, 0, 0}, + 0x0000180C, 0, 0, 0, 0, 0}, [IPA_HW_v4_5][IPA_COAL_QMAP_CFG] = { ipareg_construct_coal_qmap_cfg, ipareg_parse_coal_qmap_cfg, - 0x00001810, 0, 0, 0, 0}, + 0x00001810, 0, 0, 0, 0, 0}, [IPA_HW_v4_7][IPA_STATE_TX_WRAPPER] = { ipareg_construct_dummy, ipareg_parse_state_tx_wrapper_v4_7, - 0x00000090, 0, 0, 0, 1 }, + 0x00000090, 0, 0, 0, 1, 0}, /* IPA4.9 */ - /*IPA_DEBUG*/ + /* IPA_DEBUG */ [IPA_HW_v4_9][IPA_ENDP_GSI_CFG1_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000026C0, 0x4, 0, 30, 0 }, + 0x000026C0, 0x4, 0, 30, 0, 0}, [IPA_HW_v4_9][IPA_ENDP_GSI_CFG_TLV_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00002758, 0x4, 0, 30, 0 }, + 0x00002758, 0x4, 0, 30, 0, 0}, [IPA_HW_v4_9][IPA_ENDP_GSI_CFG_AOS_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x000027D4, 0x4, 0, 30, 0 }, + 0x000027D4, 0x4, 0, 30, 0, 0}, - /*IPA_CFG*/ + /* IPA_CFG */ [IPA_HW_v4_9][IPA_COMP_CFG] = { ipareg_construct_comp_cfg_v4_9, ipareg_parse_comp_cfg_v4_9, - 0x0000003C, 0, 0, 0, 0}, + 0x0000003C, 0, 0, 0, 0, 0}, [IPA_HW_v4_9][IPA_QSB_MAX_READS] = { ipareg_construct_qsb_max_reads_v4_0, ipareg_parse_qsb_max_reads, - 0x00000078, 0, 0, 0, 0}, + 0x00000078, 0, 0, 0, 0, 0}, [IPA_HW_v4_9][IPA_QSB_MAX_WRITES] = { ipareg_construct_qsb_max_writes, ipareg_parse_qsb_max_writes, - 0x00000074, 0, 0, 0, 0}, + 0x00000074, 0, 0, 0, 0, 0}, [IPA_HW_v4_9][IPA_TX_CFG] = { ipareg_construct_tx_cfg_v4_9, ipareg_parse_tx_cfg_v4_9, - 0x000001FC, 0, 0, 0, 0}, + 0x000001FC, 0, 0, 0, 0, 0}, [IPA_HW_v4_9][IPA_ENDP_INIT_NAT_n] = { ipareg_construct_endp_init_nat_n, ipareg_parse_dummy, - 0x0000080C, 0x70, 0, 10, 0}, + 0x0000080C, 0x70, 0, 10, 0, 0}, [IPA_HW_v4_9][IPA_ENDP_INIT_HDR_n] = { ipareg_construct_endp_init_hdr_n_v4_9, ipareg_parse_dummy, - 0x00000810, 0x70, 0, 30, 0}, + 0x00000810, 0x70, 0, 30, 0, 0}, [IPA_HW_v4_9][IPA_ENDP_INIT_HDR_METADATA_n] = { ipareg_construct_endp_init_hdr_metadata_n, ipareg_parse_dummy, - 0x0000081c, 0x70, 0, 10, 0}, + 0x0000081c, 0x70, 0, 10, 0, 0}, [IPA_HW_v4_9][IPA_ENDP_INIT_MODE_n] = { ipareg_construct_endp_init_mode_n_v4_5, ipareg_parse_dummy, - 0x00000820, 0x70, 0, 10, 0}, + 0x00000820, 0x70, 0, 10, 0, 0}, [IPA_HW_v4_9][IPA_ENDP_INIT_DEAGGR_n] = { ipareg_construct_endp_init_deaggr_n_v4_5, ipareg_parse_dummy, - 0x00000834, 0x70, 0, 10, 0}, + 0x00000834, 0x70, 0, 10, 0, 0}, [IPA_HW_v4_9][IPA_ENDP_INIT_RSRC_GRP_n] = { ipareg_construct_endp_init_rsrc_grp_n_v4_9, ipareg_parse_dummy, - 0x00000838, 0x70, 0, 30, 0}, + 0x00000838, 0x70, 0, 30, 0, 0}, [IPA_HW_v4_9][IPA_ENDP_INIT_SEQ_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000083C, 0x70, 0, 10, 0}, + 0x0000083C, 0x70, 0, 10, 0, 0}, [IPA_HW_v4_9][IPA_ENDP_INIT_CONN_TRACK_n] = { ipareg_construct_endp_init_conn_track_n, ipareg_parse_dummy, - 0x00000850, 0x70, 0, 10, 0}, + 0x00000850, 0x70, 0, 10, 0, 0}, + [IPA_HW_v4_9][IPA_GENERIC_RAM_ARBITER_PRIORITY] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000DC, 0, 0, 0, 1, 0}, - /*IPA_EE*/ + /* IPA_EE */ [IPA_HW_v4_9][IPA_IRQ_STTS_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00004008, 0x1000, 0, 0, 0}, + 0x00004008, 0x1000, 0, 0, 0, 0}, [IPA_HW_v4_9][IPA_IRQ_EN_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000400c, 0x1000, 0, 0, 0}, + 0x0000400c, 0x1000, 0, 0, 0, 0}, [IPA_HW_v4_9][IPA_IRQ_CLR_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00004010, 0x1000, 0, 0, 0}, + 0x00004010, 0x1000, 0, 0, 0, 0}, [IPA_HW_v4_9][IPA_SNOC_FEC_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00004018, 0x1000, 0, 0, 0}, + 0x00004018, 0x1000, 0, 0, 0, 0}, [IPA_HW_v4_9][IPA_SUSPEND_IRQ_INFO_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00004030, 0x1000, 0, 0, 0}, + 0x00004030, 0x1000, 0, 0, 0, 0}, [IPA_HW_v4_9][IPA_SUSPEND_IRQ_EN_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00004034, 0x1000, 0, 0, 0}, + 0x00004034, 0x1000, 0, 0, 0, 0}, [IPA_HW_v4_9][IPA_SUSPEND_IRQ_CLR_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00004038, 0x1000, 0, 0, 0}, + 0x00004038, 0x1000, 0, 0, 0, 0}, [IPA_HW_v4_9][IPA_HOLB_DROP_IRQ_INFO_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000403C, 0x1000, 0, 0, 0}, + 0x0000403C, 0x1000, 0, 0, 0, 0}, [IPA_HW_v4_9][IPA_HOLB_DROP_IRQ_EN_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00004040, 0x1000, 0, 0, 0}, + 0x00004040, 0x1000, 0, 0, 0, 0}, [IPA_HW_v4_9][IPA_HOLB_DROP_IRQ_CLR_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00004044, 0x1000, 0, 0, 0}, + 0x00004044, 0x1000, 0, 0, 0, 0}, [IPA_HW_v4_9][IPA_IRQ_EE_UC_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000401c, 0x1000, 0, 0, 1}, + 0x0000401c, 0x1000, 0, 0, 1, 0}, [IPA_HW_v4_9][IPA_FEC_ADDR_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00004020, 0x1000, 0, 0, 1}, + 0x00004020, 0x1000, 0, 0, 1, 0}, [IPA_HW_v4_9][IPA_FEC_ADDR_MSB_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00004024, 0x1000, 0, 0, 1}, + 0x00004024, 0x1000, 0, 0, 1, 0}, [IPA_HW_v4_9][IPA_FEC_ATTR_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00004028, 0x1000, 0, 0, 1}, + 0x00004028, 0x1000, 0, 0, 1, 0}, + + /* IPA5.0 */ + + /* IPA_CFG */ + [IPA_HW_v5_0][IPA_COMP_HW_VERSION] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000024, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_VERSION] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000028, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_FLAVOR_0] = { + ipareg_construct_dummy, ipareg_parse_ipa_flavor_0, + 0x00000000, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_ENABLED_PIPES] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_COMP_CFG] = { + ipareg_construct_comp_cfg_v5_0, ipareg_parse_comp_cfg_v5_0, + 0x0000002C, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_CLKON_CFG] = { + ipareg_construct_clkon_cfg_v4_5, ipareg_parse_clkon_cfg_v4_5, + 0x00000034, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_ROUTE] = { + ipareg_construct_route_v5_0, ipareg_parse_dummy, + 0x00000038, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SHARED_MEM_SIZE] = { + ipareg_construct_dummy, ipareg_parse_shared_mem_size, + 0x00000040, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_NAT_TIMER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000048, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_TAG_TIMER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000044, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_QSB_MAX_WRITES] = { + ipareg_construct_qsb_max_writes, ipareg_parse_qsb_max_writes, + 0x00000054, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_QSB_MAX_READS] = { + ipareg_construct_qsb_max_reads_v4_0, ipareg_parse_qsb_max_reads, + 0x00000058, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STATE_TX1] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000098, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_FETCHER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000A4, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_FETCHER_MASK_0] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000A8, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_DFETCHER] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000AC, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_ACL] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000B0, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000B4, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_RX_ACTIVE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_TX0] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000094, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_AGGR_ACTIVE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_AGGR_ACTIVE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000100, 0x4, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_GSI_TLV] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_GSI_AOS] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000B8, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_GENERIC_RAM_ARBITER_PRIORITY] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000004DC, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STATE_COAL_MASTER_1] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000000DC, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_FILT_ROUT_HASH_EN] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_FILT_ROUT_HASH_FLUSH] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SYS_PKT_PROC_CNTXT_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000470, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_LOCAL_PKT_PROC_CNTXT_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000478, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_AGGR_FORCE_CLOSE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_AGGR_FORCE_CLOSE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000006B0, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_TX_CFG] = { + ipareg_construct_tx_cfg_v5_0, ipareg_parse_tx_cfg_v5_0, + 0x00000488, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_IDLE_INDICATION_CFG] = { + ipareg_construct_idle_indication_cfg, ipareg_parse_dummy, + 0x000004A8, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_QTIME_TIMESTAMP_CFG] = { + ipareg_construct_qtime_timestamp_cfg, ipareg_parse_dummy, + 0x0000004Ac, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_TIMERS_XO_CLK_DIV_CFG] = { + ipareg_construct_timers_xo_clk_div_cfg, + ipareg_parse_timers_xo_clk_div_cfg, + 0x0000004B0, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_TIMERS_PULSE_GRAN_CFG] = { + ipareg_construct_timers_pulse_gran_cfg_v5_0, + ipareg_parse_timers_pulse_gran_cfg_v5_0, + 0x0000004B4, 0, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000500, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000504, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_DST_RSRC_GRP_01_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000600, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_DST_RSRC_GRP_23_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000604, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000508, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x0000050C, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_DST_RSRC_GRP_45_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x00000608, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_DST_RSRC_GRP_67_RSRC_TYPE_n] = { + ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy, + 0x0000060C, 0x20, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_QUOTA_BASE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000006D0, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_QUOTA_MASK_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_QUOTA_MASK_EE_n_REG_k] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000710, 0x4, 0, 0, 0, 0x8}, + [IPA_HW_v5_0][IPA_STAT_TETHERING_BASE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000006E0, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_TETHERING_MASK_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x4, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_FILTER_IPV4_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000700, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_FILTER_IPV6_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000704, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_ROUTER_IPV4_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00000708, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_ROUTER_IPV6_BASE] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000070C, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_STAT_DROP_CNT_BASE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000006F0, 0x4, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_STAT_DROP_CNT_MASK_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x4, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_CTRL_n] = { + ipareg_construct_endp_init_ctrl_n_v4_0, ipareg_parse_dummy, + 0x00001000, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_CTRL_SCND_n] = { + ipareg_construct_endp_init_ctrl_scnd_n, ipareg_parse_dummy, + 0x00001004, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_CFG_n] = { + ipareg_construct_endp_init_cfg_n, ipareg_parse_dummy, + 0x00001008, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_NAT_n] = { + ipareg_construct_endp_init_nat_n, ipareg_parse_dummy, + 0x0000100C, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_HDR_n] = { + ipareg_construct_endp_init_hdr_n_v4_9, ipareg_parse_dummy, + 0x00001010, 0x80, 0, 30, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_HDR_EXT_n] = { + ipareg_construct_endp_init_hdr_ext_n_v5_0, ipareg_parse_dummy, + 0x00001014, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_HDR_METADATA_n] = { + ipareg_construct_endp_init_hdr_metadata_n, + ipareg_parse_dummy, + 0x0000101c, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_MODE_n] = { + ipareg_construct_endp_init_mode_n_v5_0, ipareg_parse_dummy, + 0x00001020, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_AGGR_n] = { + ipareg_construct_endp_init_aggr_n_v4_5, + ipareg_parse_endp_init_aggr_n_v4_5, + 0x00001024, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_DEAGGR_n] = { + ipareg_construct_endp_init_deaggr_n, + ipareg_parse_dummy, + 0x00001034, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_RSRC_GRP_n] = { + ipareg_construct_endp_init_rsrc_grp_n_v5_0, + ipareg_parse_dummy, + 0x00001038, 0x80, 0, 30, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_SEQ_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000103C, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_STATUS_n] = { + ipareg_construct_endp_status_n_v5_0, ipareg_parse_dummy, + 0x00001040, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_CONN_TRACK_n] = { + ipareg_construct_endp_init_conn_track_n, + ipareg_parse_dummy, + 0x00001050, 0x80, 0, 10, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_FILTER_ROUTER_HSH_CFG_n] = { + ipareg_construct_hash_cfg_n, ipareg_parse_hash_cfg_n, + -1, 0x70, 0, 31, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_CTRL_STATUS_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00001064, 0x80, 0, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_HDR_METADATA_MASK_n] = { + ipareg_construct_endp_init_hdr_metadata_mask_n, + ipareg_parse_dummy, + 0x00001018, 0x80, 13, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_HOL_BLOCK_EN_n] = { + ipareg_construct_endp_init_hol_block_en_n, + ipareg_parse_dummy, + 0x0000102c, 0x80, 13, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_HOL_BLOCK_TIMER_n] = { + ipareg_construct_endp_init_hol_block_timer_n_v5_0, + ipareg_parse_dummy, + 0x00001030, 0x80, 13, 30, 1, 0}, + [IPA_HW_v5_0][IPA_ENDP_INIT_PROD_CFG_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00001068, 0x80, 13, 30, 1, 0}, + [IPA_HW_v5_0][IPA_COAL_EVICT_LRU] = { + ipareg_construct_coal_evict_lru, ipareg_parse_coal_evict_lru, + 0x00000918, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_COAL_QMAP_CFG] = { + ipareg_construct_coal_qmap_cfg, ipareg_parse_coal_qmap_cfg, + 0x0000091c, 0, 0, 0, 0, 0}, + + /* IPA_DEBUG */ + [IPA_HW_v5_0][IPA_RX_HPS_CLIENTS_MIN_DEPTH_1] = { //TODO contstruct not matching previous version + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000082C8, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_RX_HPS_CLIENTS_MAX_DEPTH_1] = { //TODO contstruct not matching previous version + ipareg_construct_dummy, ipareg_parse_dummy, + 0x000082D0, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_RX_HPS_CLIENTS_MIN_DEPTH_0] = { + ipareg_construct_rx_hps_clients_depth0_v4_5, + ipareg_parse_dummy, + 0x000082c4, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_RX_HPS_CLIENTS_MAX_DEPTH_0] = { + ipareg_construct_rx_hps_clients_depth0_v4_5, + ipareg_parse_dummy, + 0x000082CC, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_DPS_SEQUENCER_FIRST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00008584, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_DPS_SEQUENCER_LAST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00008588, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_HPS_SEQUENCER_FIRST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000858C, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_HPS_SEQUENCER_LAST] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00008590, 0, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_GSI_CFG1_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00008800, 0x4, 0, 30, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_GSI_CFG_TLV_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00009000, 0x4, 0, 30, 0, 0}, + [IPA_HW_v5_0][IPA_ENDP_GSI_CFG_AOS_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x00009400, 0x4, 0, 30, 0, 0}, + + /* IPA_EE */ + [IPA_HW_v5_0][IPA_IRQ_STTS_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C008, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C00c, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_IRQ_CLR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C010, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SNOC_FEC_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C018, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SUSPEND_IRQ_INFO_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SUSPEND_IRQ_INFO_EE_n_REG_k] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C030, 0x1000, 0, 0, 0, 0x4}, + [IPA_HW_v5_0][IPA_SUSPEND_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SUSPEND_IRQ_EN_EE_n_REG_k] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C050, 0x1000, 0, 0, 0, 0x4}, + [IPA_HW_v5_0][IPA_SUSPEND_IRQ_CLR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_SUSPEND_IRQ_CLR_EE_n_REG_k] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C070, 0x1000, 0, 0, 0, 0x4}, + [IPA_HW_v5_0][IPA_HOLB_DROP_IRQ_INFO_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_HOLB_DROP_IRQ_EN_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_HOLB_DROP_IRQ_CLR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + -1, 0x1000, 0, 0, 0, 0}, + [IPA_HW_v5_0][IPA_IRQ_EE_UC_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C01c, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_FEC_ADDR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C020, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_FEC_ADDR_MSB_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C024, 0x1000, 0, 0, 1, 0}, + [IPA_HW_v5_0][IPA_FEC_ATTR_EE_n] = { + ipareg_construct_dummy, ipareg_parse_dummy, + 0x0000C028, 0x1000, 0, 0, 1, 0}, }; /* @@ -3707,7 +4368,8 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type) * explicitly overridden register. * Check validity */ - if (!ipahal_reg_objs[i+1][j].offset) { + if (!ipahal_reg_objs[i+1][j].offset && + (i + 1 < IPA_HW_v5_0 || j != IPA_FLAVOR_0)) { IPAHAL_ERR( "reg=%s with zero offset ipa_ver=%d\n", ipahal_reg_name_str(j), i+1); @@ -3773,6 +4435,38 @@ u32 ipahal_read_reg_n(enum ipahal_reg_name reg, u32 n) return ioread32(ipahal_ctx->base + offset); } +/* +* ipahal_read_ep_reg() - Get the raw value of a ep reg +*/ +u32 ipahal_read_ep_reg(enum ipahal_reg_name reg, u32 ep_num) +{ + return ipahal_read_reg_n(reg, IPA_BIT_MAP_CELL_NUM(ep_num)); +} + +/* + * ipahal_test_ep_bit() - return true if a ep bit is set + */ +bool ipahal_test_ep_bit(u32 reg_val, u32 ep_num) +{ + return !!(reg_val & IPA_BIT_MAP_CELL_MSK(ep_num)); +} + +/* + * ipahal_get_ep_bit() - get ep bit set in the right offset + */ +u32 ipahal_get_ep_bit(u32 ep_num) +{ + return IPA_BIT_MAP_CELL_MSK(ep_num); +} + +/* + * ipahal_get_ep_reg_idx() - get ep reg index according to ep num + */ +u32 ipahal_get_ep_reg_idx(u32 ep_num) +{ + return IPA_BIT_MAP_CELL_NUM(ep_num); +} + /* * ipahal_read_reg_mn() - Get mn parameterized reg value */ @@ -3795,17 +4489,20 @@ u32 ipahal_read_reg_mn(enum ipahal_reg_name reg, u32 m, u32 n) WARN_ON_ONCE(1); return -EPERM; } - /* - * Currently there is one register with m and n parameters - * IPA_UC_MAILBOX_m_n. The m value of it is 0x80. - * If more such registers will be added in the future, - * we can move the m parameter to the table above. - */ - offset += 0x80 * m; + + offset += ipahal_reg_objs[ipahal_ctx->hw_type][reg].m_ofst * m; offset += ipahal_reg_objs[ipahal_ctx->hw_type][reg].n_ofst * n; return ioread32(ipahal_ctx->base + offset); } +/* +* ipahal_read_ep_reg_n() - Get n parameterized reg value according to ep +*/ +u32 ipahal_read_ep_reg_n(enum ipahal_reg_name reg, u32 n, u32 ep_num) +{ + return ipahal_read_reg_mn(reg, IPA_BIT_MAP_CELL_NUM(ep_num), n); +} + /* * ipahal_write_reg_mn() - Write to m/n parameterized reg a raw value */ @@ -3828,17 +4525,28 @@ void ipahal_write_reg_mn(enum ipahal_reg_name reg, u32 m, u32 n, u32 val) WARN_ON(1); return; } - /* - * Currently there is one register with m and n parameters - * IPA_UC_MAILBOX_m_n. The m value of it is 0x80. - * If more such registers will be added in the future, - * we can move the m parameter to the table above. - */ - offset += 0x80 * m; + + offset += ipahal_reg_objs[ipahal_ctx->hw_type][reg].m_ofst * m; offset += ipahal_reg_objs[ipahal_ctx->hw_type][reg].n_ofst * n; iowrite32(val, ipahal_ctx->base + offset); } +/* + * ipahal_write_ep_reg() - Write to ep reg a raw value + */ +void ipahal_write_ep_reg(enum ipahal_reg_name reg, u32 ep_num, u32 val) +{ + return ipahal_write_reg_n(reg, IPA_BIT_MAP_CELL_NUM(ep_num), val); +} + +/* + * ipahal_write_ep_reg_n() - Write to ep reg a raw value + */ +void ipahal_write_ep_reg_n(enum ipahal_reg_name reg, u32 n, u32 ep_num, u32 val) +{ + return ipahal_write_reg_mn(reg, IPA_BIT_MAP_CELL_NUM(ep_num), n, val); +} + /* * ipahal_read_reg_n_fields() - Get the parsed value of n parameterized reg */ @@ -3933,18 +4641,29 @@ u32 ipahal_get_reg_mn_ofst(enum ipahal_reg_name reg, u32 m, u32 n) WARN_ON(1); return -EPERM; } - /* - * Currently there is one register with m and n parameters - * IPA_UC_MAILBOX_m_n. The m value of it is 0x80. - * If more such registers will be added in the future, - * we can move the m parameter to the table above. - */ - offset += 0x80 * m; + + offset += ipahal_reg_objs[ipahal_ctx->hw_type][reg].m_ofst * m; offset += ipahal_reg_objs[ipahal_ctx->hw_type][reg].n_ofst * n; return offset; } +/* + * Get the offset of a ep register according to ep index + */ +u32 ipahal_get_ep_reg_offset(enum ipahal_reg_name reg, u32 ep_num) +{ + return ipahal_get_reg_mn_ofst(reg, 0, IPA_BIT_MAP_CELL_NUM(ep_num)); +} + +/* +* Get the offset of a ep n register according to ep index and n +*/ +u32 ipahal_get_ep_reg_n_offset(enum ipahal_reg_name reg, u32 n, u32 ep_num) +{ + return ipahal_get_reg_mn_ofst(reg, IPA_BIT_MAP_CELL_NUM(ep_num), n); +} + u32 ipahal_get_reg_base(void) { return 0x00040000; @@ -3997,11 +4716,25 @@ void ipahal_get_aggr_force_close_valmask(int ep_idx, IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_5; bmsk = IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_5; - } else if (ipahal_ctx->hw_type <= IPA_HW_v4_7) { + } else if (ipahal_ctx->hw_type <= IPA_HW_v4_9) { shft = - IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_7; + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_9; bmsk = - IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_7; + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_9; + } else if (ipahal_ctx->hw_type <= IPA_HW_v5_0) { + u8 reg_idx; + + shft = + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V5_0; + + reg_idx = IPA_BIT_MAP_CELL_NUM(ep_idx); + bmsk = (reg_idx ? + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_2_v5_0 : + IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_v5_0); + } else { + IPAHAL_ERR("unknown ipa ver %d\n", ipahal_ctx->hw_type); + ipa_assert(); + return; } if (ep_idx > (sizeof(valmask->val) * 8 - 1)) { @@ -4009,7 +4742,9 @@ void ipahal_get_aggr_force_close_valmask(int ep_idx, ipa_assert(); return; } - IPA_SETFIELD_IN_REG(valmask->val, 1 << ep_idx, shft, bmsk); + IPA_SETFIELD_IN_REG(valmask->val, + IPA_BIT_MAP_CELL_MSK(ep_idx), + shft, bmsk); valmask->mask = bmsk; } diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h index de5a70c6ef..5dad4375ca 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h @@ -142,6 +142,13 @@ enum ipahal_reg_name { IPA_ENDP_GSI_CFG_TLV_n, IPA_COAL_EVICT_LRU, IPA_COAL_QMAP_CFG, + IPA_FLAVOR_0, + IPA_STATE_AGGR_ACTIVE_n, + IPA_AGGR_FORCE_CLOSE_n, + IPA_STAT_QUOTA_MASK_EE_n_REG_k, + IPA_SUSPEND_IRQ_INFO_EE_n_REG_k, + IPA_SUSPEND_IRQ_CLR_EE_n_REG_k, + IPA_SUSPEND_IRQ_EN_EE_n_REG_k, IPA_REG_MAX, }; @@ -333,6 +340,7 @@ struct ipahal_reg_timers_pulse_gran_cfg { enum ipa_timers_time_gran_type gran_0; enum ipa_timers_time_gran_type gran_1; enum ipa_timers_time_gran_type gran_2; + enum ipa_timers_time_gran_type gran_3; }; /* @@ -633,6 +641,7 @@ struct ipahal_reg_tx_cfg { u32 pa_mask_en; bool dual_tx_enable; bool sspnd_pa_no_start_state; + bool holb_sticky_drop_en; }; /* @@ -697,6 +706,20 @@ struct ipahal_reg_coal_qmap_cfg { u32 mux_id_byte_sel; }; +/* + * struct ipahal_ipa_flavor_0 - IPA_FLAVOR_0 register + * @ipa_pipes: Number of supported pipes + * @ipa_cons_pipes: Number of consumer pipes + * @ipa_prod_pipes: Number of producer pipes + * @ipa_prod_lowest: Number of first producer pipe + */ +struct ipahal_ipa_flavor_0 { + u8 ipa_pipes; + u8 ipa_cons_pipes; + u8 ipa_prod_pipes; + u8 ipa_prod_lowest; +}; + /* * ipahal_print_all_regs() - Loop and read and print all the valid registers * Parameterized registers are also printed for all the valid ranges. @@ -720,11 +743,33 @@ u32 ipahal_read_reg_n(enum ipahal_reg_name reg, u32 n); */ u32 ipahal_read_reg_mn(enum ipahal_reg_name reg, u32 m, u32 n); +/* +* ipahal_read_reg_nk() - Read from n/k parameterized reg +*/ +static inline u32 ipahal_read_reg_nk(enum ipahal_reg_name reg, u32 n, u32 k) +{ + return ipahal_read_reg_mn(reg, k, n); +} + +/* +* ipahal_read_ep_reg_n() - Get n parameterized reg value according to ep +*/ +u32 ipahal_read_ep_reg_n(enum ipahal_reg_name reg, u32 n, u32 ep_num); + /* * ipahal_write_reg_mn() - Write to m/n parameterized reg a raw value */ void ipahal_write_reg_mn(enum ipahal_reg_name reg, u32 m, u32 n, u32 val); +/* +* ipahal_write_reg_nk() - Write to n/k parameterized reg a raw value +*/ +static inline void ipahal_write_reg_nk( + enum ipahal_reg_name reg, u32 n, u32 k, u32 val) +{ + ipahal_write_reg_mn(reg, k, n, val); +} + /* * ipahal_write_reg_n() - Write to n parameterized reg a raw value */ @@ -753,6 +798,26 @@ static inline u32 ipahal_read_reg(enum ipahal_reg_name reg) return ipahal_read_reg_n(reg, 0); } +/* + * ipahal_read_ep_reg() - Get the raw value of a ep reg + */ +u32 ipahal_read_ep_reg(enum ipahal_reg_name reg, u32 ep_num); + +/* + * ipahal_test_ep_bit() - return true if a ep bit is set + */ +bool ipahal_test_ep_bit(u32 reg_val, u32 ep_num); + +/* + * ipahal_get_ep_bit() - get ep bit set in the right offset + */ +u32 ipahal_get_ep_bit(u32 ep_num); + +/* + * ipahal_get_ep_reg_idx() - get ep reg index according to ep num + */ +u32 ipahal_get_ep_reg_idx(u32 ep_num); + /* * ipahal_write_reg() - Write to reg a raw value */ @@ -779,11 +844,26 @@ static inline void ipahal_write_reg_fields(enum ipahal_reg_name reg, ipahal_write_reg_n_fields(reg, 0, fields); } +/* + * ipahal_write_ep_reg() - Write to ep reg a raw value + */ +void ipahal_write_ep_reg(enum ipahal_reg_name reg, u32 ep_num, u32 val); + +/* + * ipahal_write_ep_reg_n() - Write to ep reg a raw value + */ +void ipahal_write_ep_reg_n(enum ipahal_reg_name reg, u32 n, u32 ep_num, u32 val); + /* * Get the offset of a m/n parameterized register */ u32 ipahal_get_reg_mn_ofst(enum ipahal_reg_name reg, u32 m, u32 n); +/* +* Get the offset of a ep n register according to ep index and n +*/ +u32 ipahal_get_ep_reg_n_offset(enum ipahal_reg_name reg, u32 n, u32 ep_num); + /* * Get the offset of a n parameterized register */ @@ -792,6 +872,11 @@ static inline u32 ipahal_get_reg_n_ofst(enum ipahal_reg_name reg, u32 n) return ipahal_get_reg_mn_ofst(reg, 0, n); } +/* + * Get the offset of a ep register according to ep index + */ +u32 ipahal_get_ep_reg_offset(enum ipahal_reg_name reg, u32 ep_num); + /* * Get the offset of a register */ diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h index cf9df3f492..f8dc9a34b8 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h @@ -14,8 +14,20 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); #define IPA_GETFIELD_FROM_REG(reg, shift, mask) \ (((reg) & (mask)) >> (shift)) - /* IPA_ROUTE register */ +#define IPA_ROUTE_ROUTE_DEF_PIPE_SHFT_v5_0 0 +#define IPA_ROUTE_ROUTE_DEF_PIPE_BMSK_v5_0 0xFF +#define IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_SHFT_v5_0 8 +#define IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_BMSK_v5_0 0xFF00 +#define IPA_ROUTE_ROUTE_DEF_HDR_OFST_SHFT_v5_0 16 +#define IPA_ROUTE_ROUTE_DEF_HDR_OFST_BMSK_v5_0 0x3ff00 +#define IPA_ROUTE_ROUTE_DEF_HDR_TABLE_SHFT_v5_0 26 +#define IPA_ROUTE_ROUTE_DEF_HDR_TABLE_BMSK_v5_0 0X4000000 +#define IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_SHFT_v5_0 27 +#define IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_BMSK_v5_0 0x8000000 +#define IPA_ROUTE_ROUTE_DIS_SHFT_v5_0 28 +#define IPA_ROUTE_ROUTE_DIS_BMSK_v5_0 0x10000000 + #define IPA_ROUTE_ROUTE_DIS_SHFT 0x0 #define IPA_ROUTE_ROUTE_DIS_BMSK 0x1 #define IPA_ROUTE_ROUTE_DEF_PIPE_SHFT 0x1 @@ -91,6 +103,11 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); #define IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_SHFT_v4_5 0x14 #define IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_BMSK_v4_5 0x300000 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_VALID_SHFT_v5_0 0x16 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_VALID_BMSK_v5_0 0x400000 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_SHFT_v5_0 0x18 +#define IPA_ENDP_INIT_HDR_EXT_n_HDR_BYTES_TO_REMOVE_BMSK_v5_0 0xFF000000 + /* IPA_ENDP_INIT_AGGR_n register */ #define IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_BMSK 0x1000000 #define IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_SHFT 0x18 @@ -139,8 +156,11 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); #define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_2 0 #define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_5 0x7fffffff #define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_5 0 -#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_7 0x7fffff -#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_7 0 +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_9 0x7fffff +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_9 0 +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_v5_0 0xffffffff +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_2_v5_0 0xf +#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V5_0 0 /* IPA_ENDP_INIT_ROUTE_n register */ #define IPA_ENDP_INIT_ROUTE_n_ROUTE_TABLE_INDEX_BMSK 0x1f @@ -173,6 +193,9 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); #define IPA_ENDP_INIT_MODE_n_MODE_BMSK_V4_5 0x7 #define IPA_ENDP_INIT_MODE_n_MODE_SHFT_V4_5 0x0 +#define IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK_V5_0 0xff0 +#define IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT_V5_0 0x4 + /* IPA_ENDP_INIT_NAT_n register */ #define IPA_ENDP_INIT_NAT_n_NAT_EN_BMSK 0x3 #define IPA_ENDP_INIT_NAT_n_NAT_EN_SHFT 0x0 @@ -210,7 +233,12 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); #define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_BMSK_V4_5 0x1F #define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_SHFT_V4_5 0 #define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_BMSK_V4_5 0x100 -#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_SHFT_V4_5 8 +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_SHFT_V4_5 0x8 + +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_BMSK_V5_0 0x1F +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIME_LIMIT_SHFT_V5_0 0 +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_BMSK_V5_0 0x300 +#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_GRAN_SEL_SHFT_V5_0 0x8 /* IPA_ENDP_INIT_DEAGGR_n register */ #define IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_BMSK 0xFFFF0000 @@ -269,6 +297,8 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); #define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v4_5 0 #define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v4_9 0x3 #define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v4_9 0 +#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v5_0 0x7 +#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v5_0 0 /* IPA_SHARED_MEM_SIZE register */ #define IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_BMSK 0xffff0000 @@ -323,6 +353,9 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); #define IPA_ENDP_STATUS_n_STATUS_EN_BMSK 0x1 #define IPA_ENDP_STATUS_n_STATUS_EN_SHFT 0x0 +#define IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK_V5_0 0x1fe +#define IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT_V5_0 0x1 + /* IPA_CLKON_CFG register */ #define IPA_CLKON_CFG_CGC_OPEN_DPL_FIFO_BMSK_V4_5 0x40000000 #define IPA_CLKON_CFG_CGC_OPEN_DPL_FIFO_SHFT_V4_5 30 @@ -501,6 +534,8 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); #define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_BMSK_V3_5 (0x1C) #define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_SHFT_V3_5 (2) +#define IPA_TX_CFG_HOLB_STICKY_DROP_EN_BMSK_v5_0 (0x100000) +#define IPA_TX_CFG_HOLB_STICKY_DROP_EN_SHFT_v5_0 (0x14) #define IPA_TX_CFG_SSPND_PA_NO_START_STATE_BMSK_V4_9 (0x40000) #define IPA_TX_CFG_SSPND_PA_NO_START_STATE_SHFT_V4_9 (0x12) #define IPA_TX_CFG_DUAL_TX_ENABLE_BMSK_V4_5 (0x20000) @@ -703,4 +738,31 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); #define IPA_STATE_TX_WRAPPER_TX0_IDLE_BMSK_v4_7 0x1 #define IPA_STATE_TX_WRAPPER_TX0_IDLE_SHFT_v4_7 0 +/* IPA 5.0 */ + +#define IPA_FLAVOR_0_IPA_PROD_LOWEST_BMSK 0xFF000000 +#define IPA_FLAVOR_0_IPA_PROD_LOWEST_SHFT 24 +#define IPA_FLAVOR_0_IPA_PROD_PIPES_BMSK 0xFF0000 +#define IPA_FLAVOR_0_IPA_PROD_PIPES_SHFT 16 +#define IPA_FLAVOR_0_IPA_CONS_PIPES_BMSK 0xFF00 +#define IPA_FLAVOR_0_IPA_CONS_PIPES_SHFT 8 +#define IPA_FLAVOR_0_IPA_PIPES_BMSK 0xFF +#define IPA_FLAVOR_0_IPA_PIPES_SHFT 0 + +#define IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_BMSK_v5_0 0x80000000 +#define IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_SHFT_v5_0 31 +#define IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_BMSK_v5_0 0x40000000 +#define IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_SHFT_v5_0 30 +#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK_v5_0 0xFC00000 +#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT_v5_0 22 +#define IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_BMSK_v5_0 0x200000 +#define IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_SHFT_v5_0 21 +#define IPA_COMP_CFG_GENQMB_AOOOWR_BMSK_v5_0 0x100000 +#define IPA_COMP_CFG_GENQMB_AOOOWR_SHFT_v5_0 20 +#define IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_BMSK_v5_0 0x80000 +#define IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_SHFT_v5_0 19 +#define IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v5_0 0x20000 +#define IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v5_0 17 +#define IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_BMSK_v5_0 0x1 +#define IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_SHFT_v5_0 0 #endif /* _IPAHAL_REG_I_H_ */ diff --git a/drivers/platform/msm/ipa/test/ipa_pm_ut.c b/drivers/platform/msm/ipa/test/ipa_pm_ut.c index 07864065ce..38bf104734 100644 --- a/drivers/platform/msm/ipa/test/ipa_pm_ut.c +++ b/drivers/platform/msm/ipa/test/ipa_pm_ut.c @@ -448,10 +448,11 @@ static int ipa_pm_ut_two_clients_activate(void *priv) { int rc = 0; int hdl_USB, hdl_WLAN, vote; - u32 pipes; + u32 pipes[IPA_EP_ARR_SIZE] = {0, 0}; struct callback_param user_data_USB; struct callback_param user_data_WLAN; bool wait_for_completion; + int ep, i; struct ipa_pm_init_params init_params = { .threshold_size = 2, @@ -598,13 +599,23 @@ static int ipa_pm_ut_two_clients_activate(void *priv) return -EFAULT; } - pipes = 1 << ipa_get_ep_mapping(IPA_CLIENT_USB_CONS); - pipes |= 1 << ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS); - pipes |= 1 << ipa_get_ep_mapping(IPA_CLIENT_USB_DPL_CONS); + ep = ipa_get_ep_mapping(IPA_CLIENT_USB_CONS); + if (ep != IPA_EP_NOT_ALLOCATED) + pipes[ipahal_get_ep_reg_idx(ep)] |= ipahal_get_ep_bit(ep); - IPA_UT_DBG("pipes = %d\n", pipes); + ep = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS); + if (ep != IPA_EP_NOT_ALLOCATED) + pipes[ipahal_get_ep_reg_idx(ep)] |= ipahal_get_ep_bit(ep); - rc = ipa_pm_handle_suspend(pipes); + ep = ipa_get_ep_mapping(IPA_CLIENT_USB_DPL_CONS); + if (ep != IPA_EP_NOT_ALLOCATED) + pipes[ipahal_get_ep_reg_idx(ep)] |= ipahal_get_ep_bit(ep); + + for (i = 0; i < IPA_EP_ARR_SIZE; i++) { + IPA_UT_DBG("pipes[%d] = %d\n", i, pipes[i]); + if (pipes[i]) + ipa_pm_handle_suspend(pipes[i], i); + } if (!wait_for_completion_timeout(&user_data_USB.complete, msecs_to_jiffies(2000))) { @@ -648,9 +659,18 @@ static int ipa_pm_ut_two_clients_activate(void *priv) return -EFAULT; } - pipes = 1 << ipa_get_ep_mapping(IPA_CLIENT_USB_CONS); + for (i = 0; i < IPA_EP_ARR_SIZE; i++) + pipes[i] = 0; - rc = ipa_pm_handle_suspend(pipes); + ep = ipa_get_ep_mapping(IPA_CLIENT_USB_CONS); + if (ep != IPA_EP_NOT_ALLOCATED) + pipes[ipahal_get_ep_reg_idx(ep)] |= ipahal_get_ep_bit(ep); + + for (i = 0; i < IPA_EP_ARR_SIZE; i++) { + IPA_UT_DBG("pipes[%d] = %d\n", i, pipes[i]); + if (pipes[i]) + ipa_pm_handle_suspend(pipes[i], i); + } if (!wait_for_completion_timeout(&user_data_USB.complete, msecs_to_jiffies(2000))) { diff --git a/drivers/platform/msm/ipa/test/ipa_test_mhi.c b/drivers/platform/msm/ipa/test/ipa_test_mhi.c index 9cbaf1e117..7609ca2665 100644 --- a/drivers/platform/msm/ipa/test/ipa_test_mhi.c +++ b/drivers/platform/msm/ipa/test/ipa_test_mhi.c @@ -1798,6 +1798,7 @@ static int ipa_mhi_test_create_aggr_open_frame(void) int rc; int i; u32 aggr_state_active; + enum ipa_hw_type ipa_ver; IPA_UT_LOG("Entry\n"); @@ -1854,7 +1855,16 @@ static int ipa_mhi_test_create_aggr_open_frame(void) msleep(20); - aggr_state_active = ipahal_read_reg(IPA_STATE_AGGR_ACTIVE); + ipa_ver = ipa_get_hw_type(); + if (ipa_ver >= IPA_HW_v5_0) { + aggr_state_active = + ipahal_read_ep_reg(IPA_STATE_AGGR_ACTIVE_n, + test_mhi_ctx->cons_hdl); + } else { + aggr_state_active = + ipahal_read_reg(IPA_STATE_AGGR_ACTIVE); + } + IPA_UT_LOG("IPA_STATE_AGGR_ACTIVE 0x%x\n", aggr_state_active); if (aggr_state_active == 0) { IPA_UT_LOG("No aggregation frame open!\n"); @@ -1924,7 +1934,13 @@ static int ipa_mhi_test_suspend_aggr_open(bool force) IPA_UT_LOG("AFTER resume\n"); } - ipahal_write_reg(IPA_AGGR_FORCE_CLOSE, (1 << test_mhi_ctx->cons_hdl)); + if (ipa_get_hw_type() >= IPA_HW_v5_0) + ipahal_write_ep_reg(IPA_AGGR_FORCE_CLOSE_n, + test_mhi_ctx->cons_hdl, + ipahal_get_ep_bit(test_mhi_ctx->cons_hdl)); + else + ipahal_write_reg(IPA_AGGR_FORCE_CLOSE, + ipahal_get_ep_bit(test_mhi_ctx->cons_hdl)); IPA_MHI_TEST_CHECK_MSI_INTR(false, timeout); if (timeout) { @@ -2282,6 +2298,7 @@ static int ipa_mhi_test_channel_reset_aggr_open(void) int rc; u32 aggr_state_active; struct ipa_ep_cfg_aggr ep_aggr; + enum ipa_hw_type ipa_ver; IPA_UT_LOG("Entry\n"); @@ -2299,7 +2316,16 @@ static int ipa_mhi_test_channel_reset_aggr_open(void) return rc; } - aggr_state_active = ipahal_read_reg(IPA_STATE_AGGR_ACTIVE); + ipa_ver = ipa_get_hw_type(); + if (ipa_ver >= IPA_HW_v5_0) { + aggr_state_active = + ipahal_read_ep_reg(IPA_STATE_AGGR_ACTIVE_n, + test_mhi_ctx->cons_hdl); + } else { + aggr_state_active = + ipahal_read_reg(IPA_STATE_AGGR_ACTIVE); + } + IPADBG("IPA_STATE_AGGR_ACTIVE 0x%x\n", aggr_state_active); if (aggr_state_active != 0) { IPA_UT_LOG("aggregation frame open after reset!\n");