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Add 'qcom/opensource/video-driver/' from commit 'd0f80c27eee09bc53817f8cfd085691c88989c7e'

ソースを参照 
git-subtree-dir: qcom/opensource/video-driver
git-subtree-mainline: e44c5532de
git-subtree-split: d0f80c27ee
Change-Id:
repo: https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver
tag: VIDEO.LA.4.0.r2-06100-lanai.0
このコミットが含まれているのは:
David Wronek
2024-10-06 16:45:47 +02:00
親 e44c5532de d0f80c27ee
コミット f1b172d58b
119個のファイルの変更、79982行の追加、0行の削除
Patchファイルをダウンロード Diffファイルをダウンロード すべてのファイルを展開 すべてのファイルを折り畳む

22
qcom/opensource/video-driver/driver/variant/common/inc/msm_vidc_variant.h ノーマルファイル
ファイルの表示

@@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _MSM_VIDC_VARIANT_H_
#define _MSM_VIDC_VARIANT_H_
#include <linux/types.h>
struct msm_vidc_core;
int __write_register_masked(struct msm_vidc_core *core, u32 reg, u32 value,
u32 mask);
int __write_register(struct msm_vidc_core *core, u32 reg, u32 value);
int __read_register(struct msm_vidc_core *core, u32 reg, u32 *value);
int __read_register_with_poll_timeout(struct msm_vidc_core *core, u32 reg,
u32 mask, u32 exp_val, u32 sleep_us, u32 timeout_us);
int __set_registers(struct msm_vidc_core *core);
#endif

161
qcom/opensource/video-driver/driver/variant/common/src/msm_vidc_variant.c ノーマルファイル
ファイルの表示

@@ -0,0 +1,161 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/errno.h>
#include <linux/iopoll.h>
#include "msm_vidc_core.h"
#include "msm_vidc_driver.h"
#include "msm_vidc_state.h"
#include "msm_vidc_debug.h"
#include "msm_vidc_variant.h"
#include "msm_vidc_platform.h"
#include "venus_hfi.h"
int __write_register(struct msm_vidc_core *core, u32 reg, u32 value)
{
u32 hwiosymaddr = reg;
u8 *base_addr;
int rc = 0;
rc = __strict_check(core, __func__);
if (rc)
return rc;
if (!is_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE)) {
d_vpr_e("HFI Write register failed : Power is OFF\n");
return -EINVAL;
}
base_addr = core->resource->register_base_addr;
d_vpr_l("regwrite(%pK + %#x) = %#x\n", base_addr, hwiosymaddr, value);
base_addr += hwiosymaddr;
writel_relaxed(value, base_addr);
/* Memory barrier to make sure value is written into the register */
wmb();
return rc;
}
/*
* Argument mask is used to specify which bits to update. In case mask is 0x11,
* only bits 0 & 4 will be updated with corresponding bits from value. To update
* entire register with value, set mask = 0xFFFFFFFF.
*/
int __write_register_masked(struct msm_vidc_core *core, u32 reg, u32 value,
u32 mask)
{
u32 prev_val, new_val;
u8 *base_addr;
int rc = 0;
rc = __strict_check(core, __func__);
if (rc)
return rc;
if (!is_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE)) {
d_vpr_e("%s: register write failed, power is off\n",
__func__);
return -EINVAL;
}
base_addr = core->resource->register_base_addr;
base_addr += reg;
prev_val = readl_relaxed(base_addr);
/*
* Memory barrier to ensure register read is correct
*/
rmb();
new_val = (prev_val & ~mask) | (value & mask);
d_vpr_l(
"Base addr: %pK, writing to: %#x, previous-value: %#x, value: %#x, mask: %#x, new-value: %#x...\n",
base_addr, reg, prev_val, value, mask, new_val);
writel_relaxed(new_val, base_addr);
/*
* Memory barrier to make sure value is written into the register.
*/
wmb();
return rc;
}
int __read_register(struct msm_vidc_core *core, u32 reg, u32 *value)
{
int rc = 0;
u8 *base_addr;
if (!is_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE)) {
d_vpr_e("HFI Read register failed : Power is OFF\n");
return -EINVAL;
}
base_addr = core->resource->register_base_addr;
*value = readl_relaxed(base_addr + reg);
/*
* Memory barrier to make sure value is read correctly from the
* register.
*/
rmb();
d_vpr_l("regread(%pK + %#x) = %#x\n", base_addr, reg, *value);
return rc;
}
int __read_register_with_poll_timeout(struct msm_vidc_core *core, u32 reg,
u32 mask, u32 exp_val, u32 sleep_us,
u32 timeout_us)
{
int rc = 0;
u32 val = 0;
u8 *addr;
if (!is_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE)) {
d_vpr_e("%s failed: Power is OFF\n", __func__);
return -EINVAL;
}
addr = (u8 *)core->resource->register_base_addr + reg;
rc = readl_relaxed_poll_timeout(addr, val, ((val & mask) == exp_val), sleep_us, timeout_us);
/*
* Memory barrier to make sure value is read correctly from the
* register.
*/
rmb();
d_vpr_l(
"regread(%pK + %#x) = %#x. rc %d, mask %#x, exp_val %#x, cond %u, sleep %u, timeout %u\n",
core->resource->register_base_addr, reg, val, rc, mask, exp_val,
((val & mask) == exp_val), sleep_us, timeout_us);
return rc;
}
int __set_registers(struct msm_vidc_core *core)
{
const struct reg_preset_table *reg_prst;
unsigned int prst_count;
int cnt, rc = 0;
reg_prst = core->platform->data.reg_prst_tbl;
prst_count = core->platform->data.reg_prst_tbl_size;
/* skip if there is no preset reg available */
if (!reg_prst || !prst_count)
return 0;
for (cnt = 0; cnt < prst_count; cnt++) {
rc = __write_register_masked(core, reg_prst[cnt].reg,
reg_prst[cnt].value, reg_prst[cnt].mask);
if (rc)
return rc;
}
return rc;
}

1458
qcom/opensource/video-driver/driver/variant/iris2/inc/hfi_buffer_iris2.h ノーマルファイル
ファイルの表示

ファイル差分が大きすぎるため省略します 差分を読み込み

19
qcom/opensource/video-driver/driver/variant/iris2/inc/msm_vidc_buffer_iris2.h ノーマルファイル
ファイルの表示

@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __H_MSM_VIDC_BUFFER_IRIS2_H__
#define __H_MSM_VIDC_BUFFER_IRIS2_H__
#include "msm_vidc_inst.h"
int msm_buffer_size_iris2(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type);
int msm_buffer_min_count_iris2(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type);
int msm_buffer_extra_count_iris2(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type);
#endif // __H_MSM_VIDC_BUFFER_IRIS2_H__

27
qcom/opensource/video-driver/driver/variant/iris2/inc/msm_vidc_iris2.h ノーマルファイル
ファイルの表示

@@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _MSM_VIDC_IRIS2_H_
#define _MSM_VIDC_IRIS2_H_
#include "msm_vidc_core.h"
#if defined(CONFIG_MSM_VIDC_VOLCANO)
int msm_vidc_init_iris2(struct msm_vidc_core *core);
int msm_vidc_adjust_blur_type_iris2(void *instance, struct v4l2_ctrl *ctrl);
#else
static inline int msm_vidc_init_iris2(struct msm_vidc_core *core)
{
return -EINVAL;
}
static inline int msm_vidc_adjust_blur_type_iris2(void *instance, struct v4l2_ctrl *ctrl)
{
return -EINVAL;
}
#endif
#endif // _MSM_VIDC_IRIS2_H_

17
qcom/opensource/video-driver/driver/variant/iris2/inc/msm_vidc_power_iris2.h ノーマルファイル
ファイルの表示

@@ -0,0 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __H_MSM_VIDC_POWER_IRIS2_H__
#define __H_MSM_VIDC_POWER_IRIS2_H__
#include "msm_vidc_inst.h"
#include "msm_vidc_power.h"
u64 msm_vidc_calc_freq_iris2(struct msm_vidc_inst *inst, u32 data_size);
int msm_vidc_calc_bw_iris2(struct msm_vidc_inst *inst,
struct vidc_bus_vote_data *vote_data);
#endif

582
qcom/opensource/video-driver/driver/variant/iris2/src/msm_vidc_buffer_iris2.c ノーマルファイル
ファイルの表示

@@ -0,0 +1,582 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "hfi_property.h"
#include "hfi_buffer_iris2.h"
#include "msm_vidc_buffer_iris2.h"
#include "msm_vidc_buffer.h"
#include "msm_vidc_inst.h"
#include "msm_vidc_core.h"
#include "msm_vidc_driver.h"
#include "msm_media_info.h"
#include "msm_vidc_platform.h"
#include "msm_vidc_debug.h"
static u32 msm_vidc_decoder_bin_size_iris2(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
u32 size = 0;
u32 width, height, num_vpp_pipes;
struct v4l2_format *f;
bool is_interlaced;
u32 vpp_delay;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
if (inst->decode_vpp_delay.enable)
vpp_delay = inst->decode_vpp_delay.size;
else
vpp_delay = DEFAULT_BSE_VPP_DELAY;
if (inst->capabilities[CODED_FRAMES].value ==
CODED_FRAMES_PROGRESSIVE)
is_interlaced = false;
else
is_interlaced = true;
f = &inst->fmts[INPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_BIN_H264D(size, width, height,
is_interlaced, vpp_delay, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_BIN_H265D(size, width, height,
0, vpp_delay, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_VP9)
HFI_BUFFER_BIN_VP9D(size, width, height,
0, num_vpp_pipes);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_comv_size_iris2(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 width, height, out_min_count, vpp_delay;
struct v4l2_format *f;
f = &inst->fmts[INPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (inst->decode_vpp_delay.enable)
vpp_delay = inst->decode_vpp_delay.size;
else
vpp_delay = DEFAULT_BSE_VPP_DELAY;
out_min_count = inst->buffers.output.min_count;
out_min_count = max(vpp_delay + 1, out_min_count);
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_COMV_H264D(size, width, height, out_min_count);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_COMV_H265D(size, width, height, out_min_count);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_non_comv_size_iris2(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 width, height, num_vpp_pipes;
struct msm_vidc_core *core;
struct v4l2_format *f;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
f = &inst->fmts[INPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_NON_COMV_H264D(size, width, height, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_NON_COMV_H265D(size, width, height, num_vpp_pipes);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_line_size_iris2(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
u32 size = 0;
u32 width, height, out_min_count, num_vpp_pipes, vpp_delay;
struct v4l2_format *f;
bool is_opb;
u32 color_fmt;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
color_fmt = v4l2_colorformat_to_driver(inst,
inst->fmts[OUTPUT_PORT].fmt.pix_mp.pixelformat, __func__);
if (is_linear_colorformat(color_fmt))
is_opb = true;
else
is_opb = false;
/*
* assume worst case, since color format is unknown at this
* time
*/
is_opb = true;
if (inst->decode_vpp_delay.enable)
vpp_delay = inst->decode_vpp_delay.size;
else
vpp_delay = DEFAULT_BSE_VPP_DELAY;
f = &inst->fmts[INPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
out_min_count = inst->buffers.output.min_count;
out_min_count = max(vpp_delay + 1, out_min_count);
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_LINE_H264D(size, width, height, is_opb,
num_vpp_pipes);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_LINE_H265D(size, width, height, is_opb,
num_vpp_pipes);
else if (inst->codec == MSM_VIDC_VP9)
HFI_BUFFER_LINE_VP9D(size, width, height, out_min_count,
is_opb, num_vpp_pipes);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_persist_size_iris2(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 rpu_enabled = 0;
if (inst->capabilities[META_DOLBY_RPU].value)
rpu_enabled = 1;
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_PERSIST_H264D(size, rpu_enabled);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_PERSIST_H265D(size, rpu_enabled);
else if (inst->codec == MSM_VIDC_VP9)
HFI_BUFFER_PERSIST_VP9D(size);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_dpb_size_iris2(struct msm_vidc_inst *inst)
{
u32 color_fmt, width, height, size = 0;
struct v4l2_format *f;
color_fmt = inst->capabilities[PIX_FMTS].value;
if (!is_linear_colorformat(color_fmt))
return size;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (color_fmt == MSM_VIDC_FMT_NV12) {
color_fmt = MSM_VIDC_FMT_NV12C;
HFI_NV12_UBWC_IL_CALC_BUF_SIZE_V2(size, width, height,
video_y_stride_bytes(color_fmt, width),
video_y_scanlines(color_fmt, height),
video_uv_stride_bytes(color_fmt, width),
video_uv_scanlines(color_fmt, height),
video_y_meta_stride(color_fmt, width),
video_y_meta_scanlines(color_fmt, height),
video_uv_meta_stride(color_fmt, width),
video_uv_meta_scanlines(color_fmt, height));
} else if (color_fmt == MSM_VIDC_FMT_P010) {
color_fmt = MSM_VIDC_FMT_TP10C;
HFI_YUV420_TP10_UBWC_CALC_BUF_SIZE(size,
video_y_stride_bytes(color_fmt, width),
video_y_scanlines(color_fmt, height),
video_uv_stride_bytes(color_fmt, width),
video_uv_scanlines(color_fmt, height),
video_y_meta_stride(color_fmt, width),
video_y_meta_scanlines(color_fmt, height),
video_uv_meta_stride(color_fmt, width),
video_uv_meta_scanlines(color_fmt, height));
}
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
/* encoder internal buffers */
static u32 msm_vidc_encoder_bin_size_iris2(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
u32 size = 0;
u32 width, height, num_vpp_pipes, stage;
struct v4l2_format *f;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
stage = inst->capabilities[STAGE].value;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_BIN_H264E(size, inst->hfi_rc_type, width,
height, stage, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_BIN_H265E(size, inst->hfi_rc_type, width,
height, stage, num_vpp_pipes);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_get_recon_buf_count(struct msm_vidc_inst *inst)
{
u32 num_buf_recon = 0;
s32 n_bframe, ltr_count, hp_layers = 0, hb_layers = 0;
bool is_hybrid_hp = false;
u32 hfi_codec = 0;
n_bframe = inst->capabilities[B_FRAME].value;
ltr_count = inst->capabilities[LTR_COUNT].value;
if (inst->hfi_layer_type == HFI_HIER_B) {
hb_layers = inst->capabilities[ENH_LAYER_COUNT].value + 1;
} else {
hp_layers = inst->capabilities[ENH_LAYER_COUNT].value + 1;
if (inst->hfi_layer_type == HFI_HIER_P_HYBRID_LTR)
is_hybrid_hp = true;
}
if (inst->codec == MSM_VIDC_H264)
hfi_codec = HFI_CODEC_ENCODE_AVC;
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
hfi_codec = HFI_CODEC_ENCODE_HEVC;
HFI_IRIS2_ENC_RECON_BUF_COUNT(num_buf_recon, n_bframe, ltr_count,
hp_layers, hb_layers, is_hybrid_hp, hfi_codec);
return num_buf_recon;
}
static u32 msm_vidc_encoder_comv_size_iris2(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 width, height, num_recon = 0;
struct v4l2_format *f;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
num_recon = msm_vidc_get_recon_buf_count(inst);
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_COMV_H264E(size, width, height, num_recon);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_COMV_H265E(size, width, height, num_recon);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_non_comv_size_iris2(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
u32 size = 0;
u32 width, height, num_vpp_pipes;
struct v4l2_format *f;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_NON_COMV_H264E(size, width, height, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_NON_COMV_H265E(size, width, height, num_vpp_pipes);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_line_size_iris2(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
u32 size = 0;
u32 width, height, pixfmt, num_vpp_pipes;
bool is_tenbit = false;
struct v4l2_format *f;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
pixfmt = inst->capabilities[PIX_FMTS].value;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
is_tenbit = (pixfmt == MSM_VIDC_FMT_P010 || pixfmt == MSM_VIDC_FMT_TP10C);
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_LINE_H264E(size, width, height, is_tenbit, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_LINE_H265E(size, width, height, is_tenbit, num_vpp_pipes);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_dpb_size_iris2(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 width, height, pixfmt;
struct v4l2_format *f;
bool is_tenbit;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
pixfmt = inst->capabilities[PIX_FMTS].value;
is_tenbit = (pixfmt == MSM_VIDC_FMT_P010 || pixfmt == MSM_VIDC_FMT_TP10C);
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_DPB_H264E(size, width, height);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_DPB_H265E(size, width, height, is_tenbit);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_arp_size_iris2(struct msm_vidc_inst *inst)
{
u32 size = 0;
HFI_BUFFER_ARP_ENC(size);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_vpss_size_iris2(struct msm_vidc_inst *inst)
{
u32 size = 0;
bool ds_enable = false, is_tenbit = false, blur = false;
u32 rotation_val = HFI_ROTATION_NONE;
u32 width, height, driver_colorfmt;
struct v4l2_format *f;
ds_enable = is_scaling_enabled(inst);
msm_vidc_v4l2_to_hfi_enum(inst, ROTATION, &rotation_val);
f = &inst->fmts[OUTPUT_PORT];
if (is_rotation_90_or_270(inst)) {
/*
* output width and height are rotated,
* so unrotate them to use as arguments to
* HFI_BUFFER_VPSS_ENC.
*/
width = f->fmt.pix_mp.height;
height = f->fmt.pix_mp.width;
} else {
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
}
f = &inst->fmts[INPUT_PORT];
driver_colorfmt = v4l2_colorformat_to_driver(inst,
f->fmt.pix_mp.pixelformat, __func__);
is_tenbit = is_10bit_colorformat(driver_colorfmt);
if (inst->capabilities[BLUR_TYPES].value != MSM_VIDC_BLUR_NONE)
blur = true;
HFI_BUFFER_VPSS_ENC(size, width, height, ds_enable, blur, is_tenbit);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
struct msm_vidc_buf_type_handle {
enum msm_vidc_buffer_type type;
u32 (*handle)(struct msm_vidc_inst *inst);
};
int msm_buffer_size_iris2(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type)
{
int i;
u32 size = 0, buf_type_handle_size = 0;
const struct msm_vidc_buf_type_handle *buf_type_handle_arr = NULL;
static const struct msm_vidc_buf_type_handle dec_buf_type_handle[] = {
{MSM_VIDC_BUF_INPUT, msm_vidc_decoder_input_size },
{MSM_VIDC_BUF_OUTPUT, msm_vidc_decoder_output_size },
{MSM_VIDC_BUF_INPUT_META, msm_vidc_decoder_input_meta_size },
{MSM_VIDC_BUF_OUTPUT_META, msm_vidc_decoder_output_meta_size },
{MSM_VIDC_BUF_BIN, msm_vidc_decoder_bin_size_iris2 },
{MSM_VIDC_BUF_COMV, msm_vidc_decoder_comv_size_iris2 },
{MSM_VIDC_BUF_NON_COMV, msm_vidc_decoder_non_comv_size_iris2 },
{MSM_VIDC_BUF_LINE, msm_vidc_decoder_line_size_iris2 },
{MSM_VIDC_BUF_PERSIST, msm_vidc_decoder_persist_size_iris2 },
{MSM_VIDC_BUF_DPB, msm_vidc_decoder_dpb_size_iris2 },
};
static const struct msm_vidc_buf_type_handle enc_buf_type_handle[] = {
{MSM_VIDC_BUF_INPUT, msm_vidc_encoder_input_size },
{MSM_VIDC_BUF_OUTPUT, msm_vidc_encoder_output_size },
{MSM_VIDC_BUF_INPUT_META, msm_vidc_encoder_input_meta_size },
{MSM_VIDC_BUF_OUTPUT_META, msm_vidc_encoder_output_meta_size },
{MSM_VIDC_BUF_BIN, msm_vidc_encoder_bin_size_iris2 },
{MSM_VIDC_BUF_COMV, msm_vidc_encoder_comv_size_iris2 },
{MSM_VIDC_BUF_NON_COMV, msm_vidc_encoder_non_comv_size_iris2 },
{MSM_VIDC_BUF_LINE, msm_vidc_encoder_line_size_iris2 },
{MSM_VIDC_BUF_DPB, msm_vidc_encoder_dpb_size_iris2 },
{MSM_VIDC_BUF_ARP, msm_vidc_encoder_arp_size_iris2 },
{MSM_VIDC_BUF_VPSS, msm_vidc_encoder_vpss_size_iris2 },
};
if (is_decode_session(inst)) {
buf_type_handle_size = ARRAY_SIZE(dec_buf_type_handle);
buf_type_handle_arr = dec_buf_type_handle;
} else if (is_encode_session(inst)) {
buf_type_handle_size = ARRAY_SIZE(enc_buf_type_handle);
buf_type_handle_arr = enc_buf_type_handle;
}
/* handle invalid session */
if (!buf_type_handle_arr || !buf_type_handle_size) {
i_vpr_e(inst, "%s: invalid session %d\n", __func__, inst->domain);
return size;
}
/* fetch buffer size */
for (i = 0; i < buf_type_handle_size; i++) {
if (buf_type_handle_arr[i].type == buffer_type) {
size = buf_type_handle_arr[i].handle(inst);
break;
}
}
/* handle unknown buffer type */
if (i == buf_type_handle_size) {
i_vpr_e(inst, "%s: unknown buffer type %#x\n", __func__, buffer_type);
goto exit;
}
i_vpr_l(inst, "buffer_size: type: %11s, size: %9u\n", buf_name(buffer_type), size);
exit:
return size;
}
static int msm_vidc_input_min_count_iris2(struct msm_vidc_inst *inst)
{
u32 input_min_count = 0;
u32 total_hb_layer = 0;
if (is_decode_session(inst)) {
input_min_count = MIN_DEC_INPUT_BUFFERS;
} else if (is_encode_session(inst)) {
total_hb_layer = is_hierb_type_requested(inst) ?
inst->capabilities[ENH_LAYER_COUNT].value + 1 : 0;
if (inst->codec == MSM_VIDC_H264 &&
!inst->capabilities[LAYER_ENABLE].value) {
total_hb_layer = 0;
}
HFI_IRIS2_ENC_MIN_INPUT_BUF_COUNT(input_min_count,
total_hb_layer);
} else {
i_vpr_e(inst, "%s: invalid domain %d\n", __func__, inst->domain);
return 0;
}
if (is_thumbnail_session(inst) || is_image_session(inst))
input_min_count = 1;
return input_min_count;
}
static int msm_buffer_dpb_count(struct msm_vidc_inst *inst)
{
int count = 0;
u32 color_fmt;
/* decoder dpb buffer count */
if (is_decode_session(inst)) {
color_fmt = inst->capabilities[PIX_FMTS].value;
if (is_linear_colorformat(color_fmt)) {
count = inst->fw_min_count ?
inst->fw_min_count : inst->buffers.output.min_count;
}
return count;
}
/* encoder dpb buffer count */
return msm_vidc_get_recon_buf_count(inst);
}
int msm_buffer_min_count_iris2(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type)
{
int count = 0;
switch (buffer_type) {
case MSM_VIDC_BUF_INPUT:
case MSM_VIDC_BUF_INPUT_META:
count = msm_vidc_input_min_count_iris2(inst);
break;
case MSM_VIDC_BUF_OUTPUT:
case MSM_VIDC_BUF_OUTPUT_META:
count = msm_vidc_output_min_count(inst);
break;
case MSM_VIDC_BUF_BIN:
case MSM_VIDC_BUF_COMV:
case MSM_VIDC_BUF_NON_COMV:
case MSM_VIDC_BUF_LINE:
case MSM_VIDC_BUF_PERSIST:
case MSM_VIDC_BUF_ARP:
case MSM_VIDC_BUF_VPSS:
count = msm_vidc_internal_buffer_count(inst, buffer_type);
break;
case MSM_VIDC_BUF_DPB:
count = msm_buffer_dpb_count(inst);
break;
default:
break;
}
i_vpr_l(inst, " min_count: type: %11s, count: %9u\n", buf_name(buffer_type), count);
return count;
}
int msm_buffer_extra_count_iris2(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type)
{
int count = 0;
switch (buffer_type) {
case MSM_VIDC_BUF_INPUT:
case MSM_VIDC_BUF_INPUT_META:
count = msm_vidc_input_extra_count(inst);
break;
case MSM_VIDC_BUF_OUTPUT:
case MSM_VIDC_BUF_OUTPUT_META:
count = msm_vidc_output_extra_count(inst);
break;
default:
break;
}
i_vpr_l(inst, "extra_count: type: %11s, count: %9u\n", buf_name(buffer_type), count);
return count;
}

960
qcom/opensource/video-driver/driver/variant/iris2/src/msm_vidc_iris2.c ノーマルファイル
ファイルの表示

@@ -0,0 +1,960 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "msm_vidc_iris2.h"
#include "msm_vidc_buffer_iris2.h"
#include "msm_vidc_power_iris2.h"
#include "msm_vidc_inst.h"
#include "msm_vidc_core.h"
#include "msm_vidc_driver.h"
#include "msm_vidc_platform.h"
#include "msm_vidc_internal.h"
#include "msm_vidc_buffer.h"
#include "msm_vidc_state.h"
#include "msm_vidc_debug.h"
#include "msm_vidc_variant.h"
#include "venus_hfi.h"
#define VIDEO_ARCH_LX 1
#define VCODEC_BASE_OFFS_IRIS2 0x00000000
#define AON_MVP_NOC_RESET 0x0001F000
#define CPU_BASE_OFFS_IRIS2 0x000A0000
#define AON_BASE_OFFS 0x000E0000
#define CPU_CS_BASE_OFFS_IRIS2 (CPU_BASE_OFFS_IRIS2)
#define CPU_IC_BASE_OFFS_IRIS2 (CPU_BASE_OFFS_IRIS2)
#define CPU_CS_A2HSOFTINTCLR_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x1C)
#define CPU_CS_VCICMD_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x20)
#define CPU_CS_VCICMDARG0_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x24)
#define CPU_CS_VCICMDARG1_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x28)
#define CPU_CS_VCICMDARG2_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x2C)
#define CPU_CS_VCICMDARG3_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x30)
#define CPU_CS_VMIMSG_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x34)
#define CPU_CS_VMIMSGAG0_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x38)
#define CPU_CS_VMIMSGAG1_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x3C)
#define CPU_CS_SCIACMD_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x48)
#define CPU_CS_H2XSOFTINTEN_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x148)
/* HFI_CTRL_STATUS */
#define CPU_CS_SCIACMDARG0_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x4C)
#define CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_BMSK_IRIS2 0xfe
#define CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY_IRIS2 0x100
#define CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK_IRIS2 0x40000000
/* HFI_QTBL_INFO */
#define CPU_CS_SCIACMDARG1_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x50)
/* HFI_QTBL_ADDR */
#define CPU_CS_SCIACMDARG2_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x54)
/* HFI_VERSION_INFO */
#define CPU_CS_SCIACMDARG3_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x58)
/* SFR_ADDR */
#define CPU_CS_SCIBCMD_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x5C)
/* MMAP_ADDR */
#define CPU_CS_SCIBCMDARG0_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x60)
/* UC_REGION_ADDR */
#define CPU_CS_SCIBARG1_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x64)
/* UC_REGION_ADDR */
#define CPU_CS_SCIBARG2_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x68)
#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS_IRIS2 + 0x160)
#define CPU_CS_AHB_BRIDGE_SYNC_RESET_STATUS (CPU_CS_BASE_OFFS_IRIS2 + 0x164)
/* FAL10 Feature Control */
#define CPU_CS_X2RPMh_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x168)
#define CPU_CS_X2RPMh_MASK0_BMSK_IRIS2 0x1
#define CPU_CS_X2RPMh_MASK0_SHFT_IRIS2 0x0
#define CPU_CS_X2RPMh_MASK1_BMSK_IRIS2 0x2
#define CPU_CS_X2RPMh_MASK1_SHFT_IRIS2 0x1
#define CPU_CS_X2RPMh_SWOVERRIDE_BMSK_IRIS2 0x4
#define CPU_CS_X2RPMh_SWOVERRIDE_SHFT_IRIS2 0x3
#define CPU_IC_SOFTINT_IRIS2 (CPU_IC_BASE_OFFS_IRIS2 + 0x150)
#define CPU_IC_SOFTINT_H2A_SHFT_IRIS2 0x0
/*
* --------------------------------------------------------------------------
* MODULE: AON_MVP_NOC_RESET_REGISTERS
* --------------------------------------------------------------------------
*/
#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
/*
* --------------------------------------------------------------------------
* MODULE: wrapper
* --------------------------------------------------------------------------
*/
#define WRAPPER_BASE_OFFS_IRIS2 0x000B0000
#define WRAPPER_INTR_STATUS_IRIS2 (WRAPPER_BASE_OFFS_IRIS2 + 0x0C)
#define WRAPPER_INTR_STATUS_A2HWD_BMSK_IRIS2 0x8
#define WRAPPER_INTR_STATUS_A2H_BMSK_IRIS2 0x4
#define WRAPPER_INTR_MASK_IRIS2 (WRAPPER_BASE_OFFS_IRIS2 + 0x10)
#define WRAPPER_INTR_MASK_A2HWD_BMSK_IRIS2 0x8
#define WRAPPER_INTR_MASK_A2HCPU_BMSK_IRIS2 0x4
#define WRAPPER_CPU_CLOCK_CONFIG_IRIS2 (WRAPPER_BASE_OFFS_IRIS2 + 0x2000)
#define WRAPPER_CPU_CGC_DIS_IRIS2 (WRAPPER_BASE_OFFS_IRIS2 + 0x2010)
#define WRAPPER_CPU_STATUS_IRIS2 (WRAPPER_BASE_OFFS_IRIS2 + 0x2014)
#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_IRIS2 (WRAPPER_BASE_OFFS_IRIS2 + 0x54)
#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS_IRIS2 (WRAPPER_BASE_OFFS_IRIS2 + 0x58)
#define WRAPPER_CORE_CLOCK_CONFIG_IRIS2 (WRAPPER_BASE_OFFS_IRIS2 + 0x88)
/*
* --------------------------------------------------------------------------
* MODULE: tz_wrapper
* --------------------------------------------------------------------------
*/
#define WRAPPER_TZ_BASE_OFFS 0x000C0000
#define WRAPPER_TZ_CPU_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS)
#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
#define CTRL_INIT_IRIS2 CPU_CS_SCIACMD_IRIS2
#define CTRL_STATUS_IRIS2 CPU_CS_SCIACMDARG0_IRIS2
#define CTRL_ERROR_STATUS__M_IRIS2 \
CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_BMSK_IRIS2
#define CTRL_INIT_IDLE_MSG_BMSK_IRIS2 \
CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK_IRIS2
#define CTRL_STATUS_PC_READY_IRIS2 \
CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY_IRIS2
#define QTBL_INFO_IRIS2 CPU_CS_SCIACMDARG1_IRIS2
#define QTBL_ADDR_IRIS2 CPU_CS_SCIACMDARG2_IRIS2
#define VERSION_INFO_IRIS2 CPU_CS_SCIACMDARG3_IRIS2
#define SFR_ADDR_IRIS2 CPU_CS_SCIBCMD_IRIS2
#define MMAP_ADDR_IRIS2 CPU_CS_SCIBCMDARG0_IRIS2
#define UC_REGION_ADDR_IRIS2 CPU_CS_SCIBARG1_IRIS2
#define UC_REGION_SIZE_IRIS2 CPU_CS_SCIBARG2_IRIS2
#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
/*
* --------------------------------------------------------------------------
* MODULE: VCODEC_SS registers
* --------------------------------------------------------------------------
*/
#define VCODEC_SS_IDLE_STATUSn (VCODEC_BASE_OFFS_IRIS2 + 0x70)
/*
* --------------------------------------------------------------------------
* MODULE: vcodec noc error log registers (iris2)
* --------------------------------------------------------------------------
*/
#define VCODEC_NOC_VIDEO_A_NOC_BASE_OFFS 0x00010000
#define VCODEC_NOC_ERL_MAIN_SWID_LOW 0x00011200
#define VCODEC_NOC_ERL_MAIN_SWID_HIGH 0x00011204
#define VCODEC_NOC_ERL_MAIN_MAINCTL_LOW 0x00011208
#define VCODEC_NOC_ERL_MAIN_ERRVLD_LOW 0x00011210
#define VCODEC_NOC_ERL_MAIN_ERRCLR_LOW 0x00011218
#define VCODEC_NOC_ERL_MAIN_ERRLOG0_LOW 0x00011220
#define VCODEC_NOC_ERL_MAIN_ERRLOG0_HIGH 0x00011224
#define VCODEC_NOC_ERL_MAIN_ERRLOG1_LOW 0x00011228
#define VCODEC_NOC_ERL_MAIN_ERRLOG1_HIGH 0x0001122C
#define VCODEC_NOC_ERL_MAIN_ERRLOG2_LOW 0x00011230
#define VCODEC_NOC_ERL_MAIN_ERRLOG2_HIGH 0x00011234
#define VCODEC_NOC_ERL_MAIN_ERRLOG3_LOW 0x00011238
#define VCODEC_NOC_ERL_MAIN_ERRLOG3_HIGH 0x0001123C
static int __interrupt_init_iris2(struct msm_vidc_core *core)
{
u32 mask_val = 0;
int rc = 0;
/* All interrupts should be disabled initially 0x1F6 : Reset value */
rc = __read_register(core, WRAPPER_INTR_MASK_IRIS2, &mask_val);
if (rc)
return rc;
/* Write 0 to unmask CPU and WD interrupts */
mask_val &= ~(WRAPPER_INTR_MASK_A2HWD_BMSK_IRIS2 |
WRAPPER_INTR_MASK_A2HCPU_BMSK_IRIS2);
rc = __write_register(core, WRAPPER_INTR_MASK_IRIS2, mask_val);
if (rc)
return rc;
return 0;
}
static int __setup_ucregion_memory_map_iris2(struct msm_vidc_core *core)
{
u32 value;
int rc = 0;
value = (u32)core->iface_q_table.align_device_addr;
rc = __write_register(core, UC_REGION_ADDR_IRIS2, value);
if (rc)
return rc;
value = SHARED_QSIZE;
rc = __write_register(core, UC_REGION_SIZE_IRIS2, value);
if (rc)
return rc;
value = (u32)core->iface_q_table.align_device_addr;
rc = __write_register(core, QTBL_ADDR_IRIS2, value);
if (rc)
return rc;
rc = __write_register(core, QTBL_INFO_IRIS2, 0x01);
if (rc)
return rc;
/* update queues vaddr for debug purpose */
value = (u32)((u64)core->iface_q_table.align_virtual_addr);
rc = __write_register(core, CPU_CS_VCICMDARG0_IRIS2, value);
if (rc)
return rc;
value = (u32)((u64)core->iface_q_table.align_virtual_addr >> 32);
rc = __write_register(core, CPU_CS_VCICMDARG1_IRIS2, value);
if (rc)
return rc;
if (core->sfr.align_device_addr) {
value = (u32)core->sfr.align_device_addr + VIDEO_ARCH_LX;
rc = __write_register(core, SFR_ADDR_IRIS2, value);
if (rc)
return rc;
}
return 0;
}
static int __power_off_iris2_hardware(struct msm_vidc_core *core)
{
int rc = 0, i;
u32 value = 0;
if (is_core_sub_state(core, CORE_SUBSTATE_FW_PWR_CTRL)) {
d_vpr_h("%s: hardware power control enabled\n", __func__);
goto disable_power;
}
/*
* check to make sure core clock branch enabled else
* we cannot read vcodec top idle register
*/
rc = __read_register(core, WRAPPER_CORE_CLOCK_CONFIG_IRIS2, &value);
if (rc)
return rc;
if (value) {
d_vpr_h("%s: core clock config not enabled, enabling it to read vcodec registers\n",
__func__);
rc = __write_register(core, WRAPPER_CORE_CLOCK_CONFIG_IRIS2, 0);
if (rc)
return rc;
}
/*
* add MNoC idle check before collapsing MVS0 per HPG update
* poll for NoC DMA idle -> HPG 6.1.1
*/
for (i = 0; i < core->capabilities[NUM_VPP_PIPE].value; i++) {
rc = __read_register_with_poll_timeout(core, VCODEC_SS_IDLE_STATUSn + 4*i,
0x400000, 0x400000, 2000, 20000);
if (rc)
d_vpr_h("%s: VCODEC_SS_IDLE_STATUSn (%d) is not idle (%#x)\n",
__func__, i, value);
}
/* Apply partial reset on MSF interface and wait for ACK */
rc = __write_register(core, AON_WRAPPER_MVP_NOC_RESET_REQ, 0x3);
if (rc)
return rc;
rc = __read_register_with_poll_timeout(core, AON_WRAPPER_MVP_NOC_RESET_ACK,
0x3, 0x3, 200, 2000);
if (rc)
d_vpr_h("%s: AON_WRAPPER_MVP_NOC_RESET assert failed\n", __func__);
/* De-assert partial reset on MSF interface and wait for ACK */
rc = __write_register(core, AON_WRAPPER_MVP_NOC_RESET_REQ, 0x0);
if (rc)
return rc;
rc = __read_register_with_poll_timeout(core, AON_WRAPPER_MVP_NOC_RESET_ACK,
0x3, 0x0, 200, 2000);
if (rc)
d_vpr_h("%s: AON_WRAPPER_MVP_NOC_RESET de-assert failed\n", __func__);
/*
* Reset both sides of 2 ahb2ahb_bridges (TZ and non-TZ)
* do we need to check status register here?
*/
rc = __write_register(core, CPU_CS_AHB_BRIDGE_SYNC_RESET, 0x3);
if (rc)
return rc;
rc = __write_register(core, CPU_CS_AHB_BRIDGE_SYNC_RESET, 0x2);
if (rc)
return rc;
rc = __write_register(core, CPU_CS_AHB_BRIDGE_SYNC_RESET, 0x0);
if (rc)
return rc;
disable_power:
/* power down process */
rc = call_res_op(core, gdsc_off, core, "vcodec");
if (rc) {
d_vpr_e("%s: disable regulator vcodec failed\n", __func__);
rc = 0;
}
rc = call_res_op(core, clk_disable, core, "video_cc_mvs0_clk");
if (rc) {
d_vpr_e("%s: disable unprepare video_cc_mvs0_clk failed\n", __func__);
rc = 0;
}
return rc;
}
static int __power_off_iris2_controller(struct msm_vidc_core *core)
{
int rc = 0;
/*
* mask fal10_veto QLPAC error since fal10_veto can go 1
* when pwwait == 0 and clamped to 0 -> HPG 6.1.2
*/
rc = __write_register(core, CPU_CS_X2RPMh_IRIS2, 0x3);
if (rc)
return rc;
/* set MNoC to low power, set PD_NOC_QREQ (bit 0) */
rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
0x1, BIT(0));
if (rc)
return rc;
rc = __read_register_with_poll_timeout(core, AON_WRAPPER_MVP_NOC_LPI_STATUS,
0x1, 0x1, 200, 2000);
if (rc)
d_vpr_h("%s: AON_WRAPPER_MVP_NOC_LPI_CONTROL failed\n", __func__);
/* Set Debug bridge Low power */
rc = __write_register(core, WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_IRIS2, 0x7);
if (rc)
return rc;
rc = __read_register_with_poll_timeout(core, WRAPPER_DEBUG_BRIDGE_LPI_STATUS_IRIS2,
0x7, 0x7, 200, 2000);
if (rc)
d_vpr_h("%s: debug bridge low power failed\n", __func__);
/* Debug bridge LPI release */
rc = __write_register(core, WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_IRIS2, 0x0);
if (rc)
return rc;
rc = __read_register_with_poll_timeout(core, WRAPPER_DEBUG_BRIDGE_LPI_STATUS_IRIS2,
0xffffffff, 0x0, 200, 2000);
if (rc)
d_vpr_h("%s: debug bridge release failed\n", __func__);
/* Turn off MVP MVS0C core clock */
rc = call_res_op(core, clk_disable, core, "video_cc_mvs0c_clk");
if (rc) {
d_vpr_e("%s: disable unprepare video_cc_mvs0c_clk failed\n", __func__);
rc = 0;
}
/* Disable gcc_video_axi0_clk clock */
rc = call_res_op(core, clk_disable, core, "gcc_video_axi0_clk");
if (rc) {
d_vpr_e("%s: disable unprepare gcc_video_axi0_clk failed\n", __func__);
rc = 0;
}
rc = call_res_op(core, reset_bridge, core);
if (rc) {
d_vpr_e("%s: reset bridge failed\n", __func__);
rc = 0;
}
/* power down process */
rc = call_res_op(core, gdsc_off, core, "iris-ctl");
if (rc) {
d_vpr_e("%s: disable regulator iris-ctl failed\n", __func__);
rc = 0;
}
return rc;
}
static int __power_off_iris2(struct msm_vidc_core *core)
{
int rc = 0;
if (!is_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE))
return 0;
/**
* Reset video_cc_mvs0_clk_src value to resolve MMRM high video
* clock projection issue.
*/
rc = call_res_op(core, set_clks, core, 0);
if (rc)
d_vpr_e("%s: resetting clocks failed\n", __func__);
if (__power_off_iris2_hardware(core))
d_vpr_e("%s: failed to power off hardware\n", __func__);
if (__power_off_iris2_controller(core))
d_vpr_e("%s: failed to power off controller\n", __func__);
rc = call_res_op(core, set_bw, core, 0, 0);
if (rc)
d_vpr_e("%s: failed to unvote buses\n", __func__);
if (!call_venus_op(core, watchdog, core, core->intr_status))
disable_irq_nosync(core->resource->irq);
msm_vidc_change_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE, 0, __func__);
return rc;
}
static int __power_on_iris2_controller(struct msm_vidc_core *core)
{
int rc = 0;
rc = call_res_op(core, gdsc_on, core, "iris-ctl");
if (rc)
goto fail_regulator;
rc = call_res_op(core, reset_bridge, core);
if (rc)
goto fail_reset_ahb2axi;
rc = call_res_op(core, clk_enable, core, "gcc_video_axi0_clk");
if (rc)
goto fail_clk_axi;
rc = call_res_op(core, clk_enable, core, "video_cc_mvs0c_clk");
if (rc)
goto fail_clk_controller;
return 0;
fail_clk_controller:
call_res_op(core, clk_disable, core, "gcc_video_axi0_clk");
fail_clk_axi:
fail_reset_ahb2axi:
call_res_op(core, gdsc_off, core, "iris-ctl");
fail_regulator:
return rc;
}
static int __power_on_iris2_hardware(struct msm_vidc_core *core)
{
int rc = 0;
rc = call_res_op(core, gdsc_on, core, "vcodec");
if (rc)
goto fail_regulator;
rc = call_res_op(core, clk_enable, core, "video_cc_mvs0_clk");
if (rc)
goto fail_clk_controller;
return 0;
fail_clk_controller:
call_res_op(core, gdsc_off, core, "vcodec");
fail_regulator:
return rc;
}
static int __power_on_iris2(struct msm_vidc_core *core)
{
struct frequency_table *freq_tbl;
u32 freq = 0;
int rc = 0;
if (is_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE))
return 0;
if (!core_in_valid_state(core)) {
d_vpr_e("%s: invalid core state %s\n",
__func__, core_state_name(core->state));
return -EINVAL;
}
/* Vote for all hardware resources */
rc = call_res_op(core, set_bw, core, INT_MAX, INT_MAX);
if (rc) {
d_vpr_e("%s: failed to vote buses, rc %d\n", __func__, rc);
goto fail_vote_buses;
}
rc = __power_on_iris2_controller(core);
if (rc) {
d_vpr_e("%s: failed to power on iris2 controller\n", __func__);
goto fail_power_on_controller;
}
rc = __power_on_iris2_hardware(core);
if (rc) {
d_vpr_e("%s: failed to power on iris2 hardware\n", __func__);
goto fail_power_on_hardware;
}
/* video controller and hardware powered on successfully */
rc = msm_vidc_change_core_sub_state(core, 0, CORE_SUBSTATE_POWER_ENABLE, __func__);
if (rc)
goto fail_power_on_substate;
freq_tbl = core->resource->freq_set.freq_tbl;
freq = core->power.clk_freq ? core->power.clk_freq :
freq_tbl[0].freq;
rc = call_res_op(core, set_clks, core, freq);
if (rc) {
d_vpr_e("%s: failed to scale clocks\n", __func__);
rc = 0;
}
core->power.clk_freq = freq;
/*
* Re-program all of the registers that get reset as a result of
* regulator_disable() and _enable()
*/
__set_registers(core);
__interrupt_init_iris2(core);
core->intr_status = 0;
enable_irq(core->resource->irq);
return rc;
fail_power_on_substate:
__power_off_iris2_hardware(core);
fail_power_on_hardware:
__power_off_iris2_controller(core);
fail_power_on_controller:
call_res_op(core, set_bw, core, 0, 0);
fail_vote_buses:
msm_vidc_change_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE, 0, __func__);
return rc;
}
static int __prepare_pc_iris2(struct msm_vidc_core *core)
{
int rc = 0;
u32 wfi_status = 0, idle_status = 0, pc_ready = 0;
u32 ctrl_status = 0;
rc = __read_register(core, CTRL_STATUS_IRIS2, &ctrl_status);
if (rc)
return rc;
pc_ready = ctrl_status & CTRL_STATUS_PC_READY_IRIS2;
idle_status = ctrl_status & BIT(30);
if (pc_ready) {
d_vpr_h("Already in pc_ready state\n");
return 0;
}
rc = __read_register(core, WRAPPER_TZ_CPU_STATUS, &wfi_status);
if (rc)
return rc;
wfi_status &= BIT(0);
if (!wfi_status || !idle_status) {
d_vpr_e("Skipping PC, wfi status not set\n");
goto skip_power_off;
}
rc = __prepare_pc(core);
if (rc) {
d_vpr_e("Failed __prepare_pc %d\n", rc);
goto skip_power_off;
}
rc = __read_register_with_poll_timeout(core, CTRL_STATUS_IRIS2,
CTRL_STATUS_PC_READY_IRIS2, CTRL_STATUS_PC_READY_IRIS2, 250, 2500);
if (rc) {
d_vpr_e("%s: Skip PC. Ctrl status not set\n", __func__);
goto skip_power_off;
}
rc = __read_register_with_poll_timeout(core, WRAPPER_TZ_CPU_STATUS,
BIT(0), 0x1, 250, 2500);
if (rc) {
d_vpr_e("%s: Skip PC. Wfi status not set\n", __func__);
goto skip_power_off;
}
return rc;
skip_power_off:
rc = __read_register(core, CTRL_STATUS_IRIS2, &ctrl_status);
if (rc)
return rc;
rc = __read_register(core, WRAPPER_TZ_CPU_STATUS, &wfi_status);
if (rc)
return rc;
wfi_status &= BIT(0);
d_vpr_e("Skip PC, wfi=%#x, idle=%#x, pcr=%#x, ctrl=%#x)\n",
wfi_status, idle_status, pc_ready, ctrl_status);
return -EAGAIN;
}
static int __raise_interrupt_iris2(struct msm_vidc_core *core)
{
int rc = 0;
rc = __write_register(core, CPU_IC_SOFTINT_IRIS2, 1 << CPU_IC_SOFTINT_H2A_SHFT_IRIS2);
if (rc)
return rc;
return 0;
}
static int __watchdog_iris2(struct msm_vidc_core *core, u32 intr_status)
{
int rc = 0;
if (intr_status & WRAPPER_INTR_STATUS_A2HWD_BMSK_IRIS2) {
d_vpr_e("%s: received watchdog interrupt\n", __func__);
rc = 1;
}
return rc;
}
static int __noc_error_info_iris2(struct msm_vidc_core *core)
{
/*
* we are not supposed to access vcodec subsystem registers
* unless vcodec core clock WRAPPER_CORE_CLOCK_CONFIG_IRIS2 is enabled.
* core clock might have been disabled by video firmware as part of
* inter frame power collapse (power plane control feature).
*/
/*
val = __read_register(core, VCODEC_NOC_ERL_MAIN_SWID_LOW);
d_vpr_e("VCODEC_NOC_ERL_MAIN_SWID_LOW: %#x\n", val);
val = __read_register(core, VCODEC_NOC_ERL_MAIN_SWID_HIGH);
d_vpr_e("VCODEC_NOC_ERL_MAIN_SWID_HIGH: %#x\n", val);
val = __read_register(core, VCODEC_NOC_ERL_MAIN_MAINCTL_LOW);
d_vpr_e("VCODEC_NOC_ERL_MAIN_MAINCTL_LOW: %#x\n", val);
val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRVLD_LOW);
d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRVLD_LOW: %#x\n", val);
val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRCLR_LOW);
d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRCLR_LOW: %#x\n", val);
val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG0_LOW);
d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG0_LOW: %#x\n", val);
val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG0_HIGH);
d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG0_HIGH: %#x\n", val);
val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG1_LOW);
d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG1_LOW: %#x\n", val);
val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG1_HIGH);
d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG1_HIGH: %#x\n", val);
val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG2_LOW);
d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG2_LOW: %#x\n", val);
val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG2_HIGH);
d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG2_HIGH: %#x\n", val);
val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG3_LOW);
d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG3_LOW: %#x\n", val);
val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG3_HIGH);
d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG3_HIGH: %#x\n", val);
*/
return 0;
}
static int __clear_interrupt_iris2(struct msm_vidc_core *core)
{
u32 intr_status = 0, mask = 0;
int rc = 0;
rc = __read_register(core, WRAPPER_INTR_STATUS_IRIS2, &intr_status);
if (rc)
return rc;
mask = (WRAPPER_INTR_STATUS_A2H_BMSK_IRIS2|
WRAPPER_INTR_STATUS_A2HWD_BMSK_IRIS2|
CTRL_INIT_IDLE_MSG_BMSK_IRIS2);
if (intr_status & mask) {
core->intr_status |= intr_status;
core->reg_count++;
d_vpr_l("INTERRUPT: times: %d interrupt_status: %d\n",
core->reg_count, intr_status);
} else {
core->spur_count++;
}
rc = __write_register(core, CPU_CS_A2HSOFTINTCLR_IRIS2, 1);
if (rc)
return rc;
return 0;
}
static int __boot_firmware_iris2(struct msm_vidc_core *core)
{
int rc = 0;
u32 ctrl_init_val = 0, ctrl_status = 0, count = 0, max_tries = 1000;
rc = __setup_ucregion_memory_map_iris2(core);
if (rc)
return rc;
ctrl_init_val = BIT(0);
rc = __write_register(core, CTRL_INIT_IRIS2, ctrl_init_val);
if (rc)
return rc;
while (!ctrl_status && count < max_tries) {
rc = __read_register(core, CTRL_STATUS_IRIS2, &ctrl_status);
if (rc)
return rc;
if ((ctrl_status & CTRL_ERROR_STATUS__M_IRIS2) == 0x4) {
d_vpr_e("invalid setting for UC_REGION\n");
break;
}
usleep_range(50, 100);
count++;
}
if (count >= max_tries) {
d_vpr_e("Error booting up vidc firmware\n");
return -ETIME;
}
/* Enable interrupt before sending commands to venus */
rc = __write_register(core, CPU_CS_H2XSOFTINTEN_IRIS2, 0x1);
if (rc)
return rc;
rc = __write_register(core, CPU_CS_X2RPMh_IRIS2, 0x0);
if (rc)
return rc;
return rc;
}
int msm_vidc_decide_work_mode_iris2(struct msm_vidc_inst *inst)
{
u32 work_mode;
struct v4l2_format *inp_f;
u32 width, height;
bool res_ok = false;
work_mode = MSM_VIDC_STAGE_2;
inp_f = &inst->fmts[INPUT_PORT];
if (is_image_decode_session(inst))
work_mode = MSM_VIDC_STAGE_1;
if (is_image_session(inst))
goto exit;
if (is_decode_session(inst)) {
height = inp_f->fmt.pix_mp.height;
width = inp_f->fmt.pix_mp.width;
res_ok = res_is_less_than(width, height, 1280, 720);
if (inst->capabilities[CODED_FRAMES].value ==
CODED_FRAMES_INTERLACE ||
inst->capabilities[LOWLATENCY_MODE].value ||
res_ok) {
work_mode = MSM_VIDC_STAGE_1;
}
} else if (is_encode_session(inst)) {
height = inst->crop.height;
width = inst->crop.width;
res_ok = !res_is_greater_than(width, height, 4096, 2160);
if (res_ok &&
(inst->capabilities[LOWLATENCY_MODE].value)) {
work_mode = MSM_VIDC_STAGE_1;
}
if (inst->capabilities[SLICE_MODE].value ==
V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES) {
work_mode = MSM_VIDC_STAGE_1;
}
if (inst->capabilities[LOSSLESS].value)
work_mode = MSM_VIDC_STAGE_2;
if (!inst->capabilities[GOP_SIZE].value)
work_mode = MSM_VIDC_STAGE_2;
} else {
i_vpr_e(inst, "%s: invalid session type\n", __func__);
return -EINVAL;
}
exit:
i_vpr_h(inst, "Configuring work mode = %u low latency = %u, gop size = %u\n",
work_mode, inst->capabilities[LOWLATENCY_MODE].value,
inst->capabilities[GOP_SIZE].value);
msm_vidc_update_cap_value(inst, STAGE, work_mode, __func__);
return 0;
}
int msm_vidc_decide_work_route_iris2(struct msm_vidc_inst *inst)
{
u32 work_route;
struct msm_vidc_core *core;
core = inst->core;
work_route = core->capabilities[NUM_VPP_PIPE].value;
if (is_image_session(inst))
goto exit;
if (is_decode_session(inst)) {
if (inst->capabilities[CODED_FRAMES].value ==
CODED_FRAMES_INTERLACE)
work_route = MSM_VIDC_PIPE_1;
} else if (is_encode_session(inst)) {
u32 slice_mode;
slice_mode = inst->capabilities[SLICE_MODE].value;
/*TODO Pipe=1 for legacy CBR*/
if (slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES)
work_route = MSM_VIDC_PIPE_1;
} else {
i_vpr_e(inst, "%s: invalid session type\n", __func__);
return -EINVAL;
}
exit:
i_vpr_h(inst, "Configuring work route = %u", work_route);
msm_vidc_update_cap_value(inst, PIPE, work_route, __func__);
return 0;
}
int msm_vidc_adjust_blur_type_iris2(void *instance, struct v4l2_ctrl *ctrl)
{
s32 adjusted_value;
struct msm_vidc_inst *inst = (struct msm_vidc_inst *)instance;
s32 rc_type = -1, cac = -1;
s32 pix_fmts = -1, min_quality = -1;
adjusted_value = ctrl ? ctrl->val :
inst->capabilities[BLUR_TYPES].value;
if (adjusted_value == MSM_VIDC_BLUR_NONE)
return 0;
if (msm_vidc_get_parent_value(inst, BLUR_TYPES, BITRATE_MODE,
&rc_type, __func__) ||
msm_vidc_get_parent_value(inst, BLUR_TYPES,
CONTENT_ADAPTIVE_CODING, &cac, __func__) ||
msm_vidc_get_parent_value(inst, BLUR_TYPES, PIX_FMTS,
&pix_fmts, __func__) ||
msm_vidc_get_parent_value(inst, BLUR_TYPES, MIN_QUALITY,
&min_quality, __func__))
return -EINVAL;
if (adjusted_value == MSM_VIDC_BLUR_EXTERNAL) {
if (is_scaling_enabled(inst) || min_quality)
adjusted_value = MSM_VIDC_BLUR_NONE;
} else if (adjusted_value == MSM_VIDC_BLUR_ADAPTIVE) {
if (is_scaling_enabled(inst) || min_quality ||
(rc_type != HFI_RC_VBR_CFR) ||
!cac ||
is_10bit_colorformat(pix_fmts)) {
adjusted_value = MSM_VIDC_BLUR_NONE;
}
}
msm_vidc_update_cap_value(inst, BLUR_TYPES,
adjusted_value, __func__);
return 0;
}
int msm_vidc_decide_quality_mode_iris2(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
u32 mbpf, mbps, max_hq_mbpf, max_hq_mbps;
u32 mode = MSM_VIDC_POWER_SAVE_MODE;
if (!is_encode_session(inst))
return 0;
/* image session always runs at quality mode */
if (is_image_session(inst)) {
mode = MSM_VIDC_MAX_QUALITY_MODE;
goto exit;
}
mbpf = msm_vidc_get_mbs_per_frame(inst);
mbps = mbpf * msm_vidc_get_fps(inst);
core = inst->core;
max_hq_mbpf = core->capabilities[MAX_MBPF_HQ].value;;
max_hq_mbps = core->capabilities[MAX_MBPS_HQ].value;;
/* NRT session to have max quality unless client configures lesser complexity */
if (!is_realtime_session(inst) && mbpf <= max_hq_mbpf) {
mode = MSM_VIDC_MAX_QUALITY_MODE;
if (inst->capabilities[COMPLEXITY].value < DEFAULT_COMPLEXITY)
mode = MSM_VIDC_POWER_SAVE_MODE;
goto exit;
}
/* Power saving always disabled for CQ and LOSSLESS RC modes. */
if (inst->capabilities[LOSSLESS].value ||
(mbpf <= max_hq_mbpf && mbps <= max_hq_mbps))
mode = MSM_VIDC_MAX_QUALITY_MODE;
exit:
msm_vidc_update_cap_value(inst, QUALITY_MODE, mode, __func__);
return 0;
}
static struct msm_vidc_venus_ops iris2_ops = {
.boot_firmware = __boot_firmware_iris2,
.raise_interrupt = __raise_interrupt_iris2,
.clear_interrupt = __clear_interrupt_iris2,
.power_on = __power_on_iris2,
.power_off = __power_off_iris2,
.prepare_pc = __prepare_pc_iris2,
.watchdog = __watchdog_iris2,
.noc_error_info = __noc_error_info_iris2,
};
static struct msm_vidc_session_ops msm_session_ops = {
.buffer_size = msm_buffer_size_iris2,
.min_count = msm_buffer_min_count_iris2,
.extra_count = msm_buffer_extra_count_iris2,
.calc_freq = msm_vidc_calc_freq_iris2,
.calc_bw = msm_vidc_calc_bw_iris2,
.decide_work_route = msm_vidc_decide_work_route_iris2,
.decide_work_mode = msm_vidc_decide_work_mode_iris2,
.decide_quality_mode = msm_vidc_decide_quality_mode_iris2,
};
int msm_vidc_init_iris2(struct msm_vidc_core *core)
{
d_vpr_h("%s()\n", __func__);
core->venus_ops = &iris2_ops;
core->session_ops = &msm_session_ops;
return 0;
}

706
qcom/opensource/video-driver/driver/variant/iris2/src/msm_vidc_power_iris2.c ノーマルファイル
ファイルの表示

@@ -0,0 +1,706 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "msm_vidc_power_iris2.h"
#include "msm_vidc_inst.h"
#include "msm_vidc_driver.h"
#include "msm_vidc_core.h"
#include "msm_vidc_debug.h"
u64 msm_vidc_calc_freq_iris2(struct msm_vidc_inst *inst, u32 data_size)
{
u64 freq = 0;
struct msm_vidc_core *core;
u64 vsp_cycles = 0, vpp_cycles = 0, fw_cycles = 0;
u64 fw_vpp_cycles = 0, bitrate = 0;
u32 vpp_cycles_per_mb;
u32 mbs_per_second;
u32 operating_rate, vsp_factor_num = 1, vsp_factor_den = 1;
u32 base_cycles = 0;
u32 fps, mbpf;
core = inst->core;
mbpf = msm_vidc_get_mbs_per_frame(inst);
fps = inst->max_rate;
mbs_per_second = mbpf * fps;
/*
* Calculate vpp, vsp, fw cycles separately for encoder and decoder.
* Even though, most part is common now, in future it may change
* between them.
*/
fw_cycles = fps * inst->capabilities[MB_CYCLES_FW].value;
fw_vpp_cycles = fps * inst->capabilities[MB_CYCLES_FW_VPP].value;
if (is_encode_session(inst)) {
vpp_cycles_per_mb = is_low_power_session(inst) ?
inst->capabilities[MB_CYCLES_LP].value :
inst->capabilities[MB_CYCLES_VPP].value;
vpp_cycles = mbs_per_second * vpp_cycles_per_mb /
inst->capabilities[PIPE].value;
/* Factor 1.25 for IbP and 1.375 for I1B2b1P GOP structure */
if (inst->capabilities[B_FRAME].value > 1)
vpp_cycles += (vpp_cycles / 4) + (vpp_cycles / 8);
else if (inst->capabilities[B_FRAME].value)
vpp_cycles += vpp_cycles / 4;
/* 21 / 20 is minimum overhead factor */
vpp_cycles += max(div_u64(vpp_cycles, 20), fw_vpp_cycles);
/* 1.01 is multi-pipe overhead */
if (inst->capabilities[PIPE].value > 1)
vpp_cycles += div_u64(vpp_cycles, 100);
/*
* 1080p@480fps usecase needs exactly 338MHz
* without any margin left. Hence, adding 2 percent
* extra to bump it to next level (366MHz).
*/
if (fps == 480)
vpp_cycles += div_u64(vpp_cycles * 2, 100);
/*
* Add 5 percent extra for 720p@960fps use case
* to bump it to next level (366MHz).
*/
if (fps == 960)
vpp_cycles += div_u64(vpp_cycles * 5, 100);
/* VSP */
/* bitrate is based on fps, scale it using operating rate */
operating_rate = inst->capabilities[OPERATING_RATE].value >> 16;
if (operating_rate >
(inst->capabilities[FRAME_RATE].value >> 16) &&
(inst->capabilities[FRAME_RATE].value >> 16)) {
vsp_factor_num = operating_rate;
vsp_factor_den = inst->capabilities[FRAME_RATE].value >> 16;
}
vsp_cycles = div_u64(((u64)inst->capabilities[BIT_RATE].value *
vsp_factor_num), vsp_factor_den);
base_cycles = inst->capabilities[MB_CYCLES_VSP].value;
if (inst->codec == MSM_VIDC_VP9) {
vsp_cycles = div_u64(vsp_cycles * 170, 100);
} else if (inst->capabilities[ENTROPY_MODE].value ==
V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC) {
vsp_cycles = div_u64(vsp_cycles * 135, 100);
} else {
base_cycles = 0;
vsp_cycles = div_u64(vsp_cycles, 2);
}
/* VSP FW Overhead 1.05 */
vsp_cycles = div_u64(vsp_cycles * 21, 20);
if (inst->capabilities[STAGE].value == MSM_VIDC_STAGE_1)
vsp_cycles = vsp_cycles * 3;
vsp_cycles += mbs_per_second * base_cycles;
} else if (is_decode_session(inst)) {
/* VPP */
vpp_cycles = mbs_per_second * inst->capabilities[MB_CYCLES_VPP].value /
inst->capabilities[PIPE].value;
/* 21 / 20 is minimum overhead factor */
vpp_cycles += max(vpp_cycles / 20, fw_vpp_cycles);
/* 1.059 is multi-pipe overhead */
if (inst->capabilities[PIPE].value > 1)
vpp_cycles += div_u64(vpp_cycles * 59, 1000);
/* VSP */
base_cycles = inst->has_bframe ?
80 : inst->capabilities[MB_CYCLES_VSP].value;
bitrate = fps * data_size * 8;
vsp_cycles = bitrate;
if (inst->codec == MSM_VIDC_VP9) {
vsp_cycles = div_u64(vsp_cycles * 170, 100);
} else if (inst->capabilities[ENTROPY_MODE].value ==
V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC) {
vsp_cycles = div_u64(vsp_cycles * 135, 100);
} else {
base_cycles = 0;
vsp_cycles = div_u64(vsp_cycles, 2);
}
/* VSP FW overhead 1.05 */
vsp_cycles = div_u64(vsp_cycles * 21, 20);
if (inst->capabilities[STAGE].value == MSM_VIDC_STAGE_1)
vsp_cycles = vsp_cycles * 3;
vsp_cycles += mbs_per_second * base_cycles;
/* Add 25 percent extra for 960fps use case */
if (fps >= 960)
vsp_cycles += div_u64(vpp_cycles * 25, 100);
if (inst->codec == MSM_VIDC_VP9 &&
inst->capabilities[STAGE].value ==
MSM_VIDC_STAGE_2 &&
inst->capabilities[PIPE].value == 4 &&
bitrate > 90000000)
vsp_cycles = msm_vidc_max_freq(inst);
} else {
i_vpr_e(inst, "%s: Unknown session type\n", __func__);
return msm_vidc_max_freq(inst);
}
freq = max(vpp_cycles, vsp_cycles);
freq = max(freq, fw_cycles);
i_vpr_p(inst, "%s: filled len %d, required freq %llu, fps %u, mbpf %u\n",
__func__, data_size, freq, fps, mbpf);
return freq;
}
static u64 __calculate_decoder(struct vidc_bus_vote_data *d)
{
/*
* XXX: Don't fool around with any of the hardcoded numbers unless you
* know /exactly/ what you're doing. Many of these numbers are
* measured heuristics and hardcoded numbers taken from the firmware.
*/
/* Decoder parameters */
int width, height, lcu_size, fps, dpb_bpp;
bool unified_dpb_opb, dpb_compression_enabled = true,
opb_compression_enabled = false,
llc_ref_read_l2_cache_enabled = false,
llc_top_line_buf_enabled = false;
fp_t dpb_read_compression_factor, dpb_opb_scaling_ratio,
dpb_write_compression_factor, opb_write_compression_factor,
qsmmu_bw_overhead_factor;
bool is_h264_category = true;
/* Derived parameters */
int lcu_per_frame, collocated_bytes_per_lcu, tnbr_per_lcu;
unsigned long bitrate;
unsigned int num_vpp_pipes;
fp_t bins_to_bit_factor, vsp_read_factor, vsp_write_factor,
dpb_factor, dpb_write_factor, y_bw_no_ubwc_8bpp;
fp_t y_bw_no_ubwc_10bpp = 0, y_bw_10bpp_p010 = 0,
motion_vector_complexity = 0;
fp_t dpb_total = 0;
/* Output parameters */
struct {
fp_t vsp_read, vsp_write, collocated_read, collocated_write,
dpb_read, dpb_write, opb_read, opb_write,
line_buffer_read, line_buffer_write,
total;
} ddr = {0};
struct {
fp_t dpb_read, line_buffer_read, line_buffer_write, total;
} llc = {0};
unsigned long ret = 0;
unsigned int integer_part, frac_part;
width = max(d->input_width, BASELINE_DIMENSIONS.width);
height = max(d->input_height, BASELINE_DIMENSIONS.height);
fps = d->fps;
lcu_size = d->lcu_size;
dpb_bpp = __bpp(d->color_formats[0]);
unified_dpb_opb = d->num_formats == 1;
dpb_opb_scaling_ratio = fp_div(FP_INT(d->input_width * d->input_height),
FP_INT(d->output_width * d->output_height));
opb_compression_enabled = d->num_formats >= 2 &&
__ubwc(d->color_formats[1]);
integer_part = Q16_INT(d->compression_ratio);
frac_part = Q16_FRAC(d->compression_ratio);
dpb_read_compression_factor = FP(integer_part, frac_part, 100);
integer_part = Q16_INT(d->complexity_factor);
frac_part = Q16_FRAC(d->complexity_factor);
motion_vector_complexity = FP(integer_part, frac_part, 100);
dpb_write_compression_factor = dpb_read_compression_factor;
opb_write_compression_factor = opb_compression_enabled ?
dpb_write_compression_factor : FP_ONE;
num_vpp_pipes = d->num_vpp_pipes;
if (d->codec == MSM_VIDC_HEVC ||
d->codec == MSM_VIDC_HEIC ||
d->codec == MSM_VIDC_VP9) {
/* H264, VP8, MPEG2 use the same settings */
/* HEVC, VP9 use the same setting */
is_h264_category = false;
}
if (d->use_sys_cache) {
llc_ref_read_l2_cache_enabled = true;
if (is_h264_category)
llc_top_line_buf_enabled = true;
}
/* Derived parameters setup */
lcu_per_frame = DIV_ROUND_UP(width, lcu_size) *
DIV_ROUND_UP(height, lcu_size);
bitrate = DIV_ROUND_UP(d->bitrate, 1000000);
bins_to_bit_factor = FP_INT(4);
vsp_write_factor = bins_to_bit_factor;
vsp_read_factor = bins_to_bit_factor + FP_INT(2);
collocated_bytes_per_lcu = lcu_size == 16 ? 16 :
lcu_size == 32 ? 64 : 256;
dpb_factor = FP(1, 50, 100);
dpb_write_factor = FP(1, 5, 100);
/* This change is applicable for all IRIS2 targets,
* But currently being done only for IRIS2 with 2 pipe
* and 1 pipe due to timeline constraints.
*/
if (num_vpp_pipes != 4)
tnbr_per_lcu = lcu_size == 16 ? 64 :
lcu_size == 32 ? 64 : 128;
else
tnbr_per_lcu = lcu_size == 16 ? 128 :
lcu_size == 32 ? 64 : 128;
/* .... For DDR & LLC ...... */
ddr.vsp_read = fp_div(fp_mult(FP_INT(bitrate),
vsp_read_factor), FP_INT(8));
ddr.vsp_write = fp_div(fp_mult(FP_INT(bitrate),
vsp_write_factor), FP_INT(8));
ddr.collocated_read = fp_div(FP_INT(lcu_per_frame *
collocated_bytes_per_lcu * fps), FP_INT(bps(1)));
ddr.collocated_write = ddr.collocated_read;
y_bw_no_ubwc_8bpp = fp_div(FP_INT(width * height * fps),
FP_INT(1000 * 1000));
if (dpb_bpp != 8) {
y_bw_no_ubwc_10bpp =
fp_div(fp_mult(y_bw_no_ubwc_8bpp, FP_INT(256)),
FP_INT(192));
y_bw_10bpp_p010 = y_bw_no_ubwc_8bpp * 2;
}
ddr.dpb_read = dpb_bpp == 8 ? y_bw_no_ubwc_8bpp : y_bw_no_ubwc_10bpp;
ddr.dpb_read = fp_div(fp_mult(ddr.dpb_read,
fp_mult(dpb_factor, motion_vector_complexity)),
dpb_read_compression_factor);
ddr.dpb_write = dpb_bpp == 8 ? y_bw_no_ubwc_8bpp : y_bw_no_ubwc_10bpp;
ddr.dpb_write = fp_div(fp_mult(ddr.dpb_write,
fp_mult(dpb_factor, dpb_write_factor)),
dpb_write_compression_factor);
dpb_total = ddr.dpb_read + ddr.dpb_write;
if (llc_ref_read_l2_cache_enabled) {
ddr.dpb_read = fp_div(ddr.dpb_read, is_h264_category ?
FP(1, 30, 100) : FP(1, 14, 100));
llc.dpb_read = dpb_total - ddr.dpb_write - ddr.dpb_read;
}
ddr.opb_read = FP_ZERO;
ddr.opb_write = unified_dpb_opb ? FP_ZERO : (dpb_bpp == 8 ?
y_bw_no_ubwc_8bpp : (opb_compression_enabled ?
y_bw_no_ubwc_10bpp : y_bw_10bpp_p010));
ddr.opb_write = fp_div(fp_mult(dpb_factor, ddr.opb_write),
fp_mult(dpb_opb_scaling_ratio, opb_write_compression_factor));
ddr.line_buffer_read =
fp_div(FP_INT(tnbr_per_lcu * lcu_per_frame * fps),
FP_INT(bps(1)));
ddr.line_buffer_write = ddr.line_buffer_read;
if (llc_top_line_buf_enabled) {
llc.line_buffer_read = ddr.line_buffer_read;
llc.line_buffer_write = ddr.line_buffer_write;
ddr.line_buffer_write = ddr.line_buffer_read = FP_ZERO;
}
ddr.total = ddr.vsp_read + ddr.vsp_write +
ddr.collocated_read + ddr.collocated_write +
ddr.dpb_read + ddr.dpb_write +
ddr.opb_read + ddr.opb_write +
ddr.line_buffer_read + ddr.line_buffer_write;
qsmmu_bw_overhead_factor = FP(1, 3, 100);
ddr.total = fp_mult(ddr.total, qsmmu_bw_overhead_factor);
llc.total = llc.dpb_read + llc.line_buffer_read +
llc.line_buffer_write + ddr.total;
/* Add 25 percent extra for 960fps use case */
if (fps >= 960) {
ddr.total += div_u64(ddr.total * 25, 100);
llc.total += div_u64(llc.total * 25, 100);
}
/* Dump all the variables for easier debugging */
if (msm_vidc_debug & VIDC_BUS) {
struct dump dump[] = {
{"DECODER PARAMETERS", "", DUMP_HEADER_MAGIC},
{"lcu size", "%d", lcu_size},
{"dpb bitdepth", "%d", dpb_bpp},
{"frame rate", "%d", fps},
{"dpb/opb unified", "%d", unified_dpb_opb},
{"dpb/opb downscaling ratio", DUMP_FP_FMT,
dpb_opb_scaling_ratio},
{"dpb compression", "%d", dpb_compression_enabled},
{"opb compression", "%d", opb_compression_enabled},
{"dpb read compression factor", DUMP_FP_FMT,
dpb_read_compression_factor},
{"dpb write compression factor", DUMP_FP_FMT,
dpb_write_compression_factor},
{"frame width", "%d", width},
{"frame height", "%d", height},
{"llc ref read l2 cache enabled", "%d",
llc_ref_read_l2_cache_enabled},
{"llc top line buf enabled", "%d",
llc_top_line_buf_enabled},
{"DERIVED PARAMETERS (1)", "", DUMP_HEADER_MAGIC},
{"lcus/frame", "%d", lcu_per_frame},
{"bitrate (Mbit/sec)", "%d", bitrate},
{"bins to bit factor", DUMP_FP_FMT, bins_to_bit_factor},
{"dpb write factor", DUMP_FP_FMT, dpb_write_factor},
{"vsp read factor", DUMP_FP_FMT, vsp_read_factor},
{"vsp write factor", DUMP_FP_FMT, vsp_write_factor},
{"tnbr/lcu", "%d", tnbr_per_lcu},
{"collocated bytes/LCU", "%d", collocated_bytes_per_lcu},
{"bw for NV12 8bpc)", DUMP_FP_FMT, y_bw_no_ubwc_8bpp},
{"bw for NV12 10bpc)", DUMP_FP_FMT, y_bw_no_ubwc_10bpp},
{"DERIVED PARAMETERS (2)", "", DUMP_HEADER_MAGIC},
{"mv complexity", DUMP_FP_FMT, motion_vector_complexity},
{"qsmmu_bw_overhead_factor", DUMP_FP_FMT,
qsmmu_bw_overhead_factor},
{"INTERMEDIATE DDR B/W", "", DUMP_HEADER_MAGIC},
{"vsp read", DUMP_FP_FMT, ddr.vsp_read},
{"vsp write", DUMP_FP_FMT, ddr.vsp_write},
{"collocated read", DUMP_FP_FMT, ddr.collocated_read},
{"collocated write", DUMP_FP_FMT, ddr.collocated_write},
{"line buffer read", DUMP_FP_FMT, ddr.line_buffer_read},
{"line buffer write", DUMP_FP_FMT, ddr.line_buffer_write},
{"opb read", DUMP_FP_FMT, ddr.opb_read},
{"opb write", DUMP_FP_FMT, ddr.opb_write},
{"dpb read", DUMP_FP_FMT, ddr.dpb_read},
{"dpb write", DUMP_FP_FMT, ddr.dpb_write},
{"dpb total", DUMP_FP_FMT, dpb_total},
{"INTERMEDIATE LLC B/W", "", DUMP_HEADER_MAGIC},
{"llc dpb read", DUMP_FP_FMT, llc.dpb_read},
{"llc line buffer read", DUMP_FP_FMT, llc.line_buffer_read},
{"llc line buffer write", DUMP_FP_FMT, llc.line_buffer_write},
};
__dump(dump, ARRAY_SIZE(dump));
}
d->calc_bw_ddr = kbps(fp_round(ddr.total));
d->calc_bw_llcc = kbps(fp_round(llc.total));
return ret;
}
static u64 __calculate_encoder(struct vidc_bus_vote_data *d)
{
/*
* XXX: Don't fool around with any of the hardcoded numbers unless you
* know /exactly/ what you're doing. Many of these numbers are
* measured heuristics and hardcoded numbers taken from the firmware.
*/
/* Encoder Parameters */
int width, height, fps, lcu_size, bitrate, lcu_per_frame,
collocated_bytes_per_lcu, tnbr_per_lcu, dpb_bpp,
original_color_format, vertical_tile_width, rotation;
bool work_mode_1, original_compression_enabled,
low_power, cropping_or_scaling,
b_frames_enabled = false,
llc_ref_chroma_cache_enabled = false,
llc_top_line_buf_enabled = false,
llc_vpss_rot_line_buf_enabled = false;
unsigned int bins_to_bit_factor;
fp_t dpb_compression_factor,
original_compression_factor,
original_compression_factor_y,
y_bw_no_ubwc_8bpp, y_bw_no_ubwc_10bpp = 0, y_bw_10bpp_p010 = 0,
input_compression_factor,
downscaling_ratio,
ref_y_read_bw_factor, ref_cbcr_read_bw_factor,
recon_write_bw_factor,
total_ref_read_crcb,
qsmmu_bw_overhead_factor;
fp_t integer_part, frac_part;
unsigned long ret = 0;
/* Output parameters */
struct {
fp_t vsp_read, vsp_write, collocated_read, collocated_write,
ref_read_y, ref_read_crcb, ref_write,
ref_write_overlap, orig_read,
line_buffer_read, line_buffer_write,
total;
} ddr = {0};
struct {
fp_t ref_read_crcb, line_buffer, total;
} llc = {0};
/* Encoder Parameters setup */
rotation = d->rotation;
cropping_or_scaling = false;
vertical_tile_width = 960;
/*
* recon_write_bw_factor varies according to resolution and bit-depth,
* here use 1.08(1.075) for worst case.
* Similar for ref_y_read_bw_factor, it can reach 1.375 for worst case,
* here use 1.3 for average case, and can somewhat balance the
* worst case assumption for UBWC CR factors.
*/
recon_write_bw_factor = FP(1, 8, 100);
ref_y_read_bw_factor = FP(1, 30, 100);
ref_cbcr_read_bw_factor = FP(1, 50, 100);
/* Derived Parameters */
fps = d->fps;
width = max(d->output_width, BASELINE_DIMENSIONS.width);
height = max(d->output_height, BASELINE_DIMENSIONS.height);
downscaling_ratio = fp_div(FP_INT(d->input_width * d->input_height),
FP_INT(d->output_width * d->output_height));
downscaling_ratio = max(downscaling_ratio, FP_ONE);
bitrate = d->bitrate > 0 ? DIV_ROUND_UP(d->bitrate, 1000000) :
__lut(width, height, fps)->bitrate;
lcu_size = d->lcu_size;
lcu_per_frame = DIV_ROUND_UP(width, lcu_size) *
DIV_ROUND_UP(height, lcu_size);
tnbr_per_lcu = 16;
dpb_bpp = __bpp(d->color_formats[0]);
y_bw_no_ubwc_8bpp = fp_div(FP_INT(width * height * fps),
FP_INT(1000 * 1000));
if (dpb_bpp != 8) {
y_bw_no_ubwc_10bpp = fp_div(fp_mult(y_bw_no_ubwc_8bpp,
FP_INT(256)), FP_INT(192));
y_bw_10bpp_p010 = y_bw_no_ubwc_8bpp * 2;
}
b_frames_enabled = d->b_frames_enabled;
original_color_format = d->num_formats >= 1 ?
d->color_formats[0] : MSM_VIDC_FMT_NV12C;
original_compression_enabled = __ubwc(original_color_format);
work_mode_1 = d->work_mode == MSM_VIDC_STAGE_1;
low_power = d->power_mode == VIDC_POWER_LOW;
bins_to_bit_factor = 4;
if (d->use_sys_cache) {
llc_ref_chroma_cache_enabled = true;
llc_top_line_buf_enabled = true,
llc_vpss_rot_line_buf_enabled = true;
}
integer_part = Q16_INT(d->compression_ratio);
frac_part = Q16_FRAC(d->compression_ratio);
dpb_compression_factor = FP(integer_part, frac_part, 100);
integer_part = Q16_INT(d->input_cr);
frac_part = Q16_FRAC(d->input_cr);
input_compression_factor = FP(integer_part, frac_part, 100);
original_compression_factor = original_compression_factor_y =
!original_compression_enabled ? FP_ONE :
__compression_ratio(__lut(width, height, fps), dpb_bpp);
/* use input cr if it is valid (not 1), otherwise use lut */
if (original_compression_enabled &&
input_compression_factor != FP_ONE) {
original_compression_factor = input_compression_factor;
/* Luma usually has lower compression factor than Chroma,
* input cf is overall cf, add 1.08 factor for Luma cf
*/
original_compression_factor_y =
input_compression_factor > FP(1, 8, 100) ?
fp_div(input_compression_factor, FP(1, 8, 100)) :
input_compression_factor;
}
ddr.vsp_read = fp_div(FP_INT(bitrate * bins_to_bit_factor), FP_INT(8));
ddr.vsp_write = ddr.vsp_read + fp_div(FP_INT(bitrate), FP_INT(8));
collocated_bytes_per_lcu = lcu_size == 16 ? 16 :
lcu_size == 32 ? 64 : 256;
ddr.collocated_read = fp_div(FP_INT(lcu_per_frame *
collocated_bytes_per_lcu * fps), FP_INT(bps(1)));
ddr.collocated_write = ddr.collocated_read;
ddr.ref_read_y = dpb_bpp == 8 ?
y_bw_no_ubwc_8bpp : y_bw_no_ubwc_10bpp;
if (b_frames_enabled)
ddr.ref_read_y = ddr.ref_read_y * 2;
ddr.ref_read_y = fp_div(ddr.ref_read_y, dpb_compression_factor);
ddr.ref_read_crcb = fp_mult((ddr.ref_read_y / 2),
ref_cbcr_read_bw_factor);
if (width > vertical_tile_width) {
ddr.ref_read_y = fp_mult(ddr.ref_read_y,
ref_y_read_bw_factor);
}
if (llc_ref_chroma_cache_enabled) {
total_ref_read_crcb = ddr.ref_read_crcb;
ddr.ref_read_crcb = fp_div(ddr.ref_read_crcb,
ref_cbcr_read_bw_factor);
llc.ref_read_crcb = total_ref_read_crcb - ddr.ref_read_crcb;
}
ddr.ref_write = dpb_bpp == 8 ? y_bw_no_ubwc_8bpp : y_bw_no_ubwc_10bpp;
ddr.ref_write = fp_div(fp_mult(ddr.ref_write, FP(1, 50, 100)),
dpb_compression_factor);
if (width > vertical_tile_width) {
ddr.ref_write_overlap = fp_mult(ddr.ref_write,
(recon_write_bw_factor - FP_ONE));
ddr.ref_write = fp_mult(ddr.ref_write, recon_write_bw_factor);
}
ddr.orig_read = dpb_bpp == 8 ? y_bw_no_ubwc_8bpp :
(original_compression_enabled ? y_bw_no_ubwc_10bpp :
y_bw_10bpp_p010);
ddr.orig_read = fp_div(fp_mult(fp_mult(ddr.orig_read, FP(1, 50, 100)),
downscaling_ratio), original_compression_factor);
if (rotation == 90 || rotation == 270)
ddr.orig_read *= lcu_size == 32 ? (dpb_bpp == 8 ? 1 : 3) : 2;
ddr.line_buffer_read =
fp_div(FP_INT(tnbr_per_lcu * lcu_per_frame * fps),
FP_INT(bps(1)));
ddr.line_buffer_write = ddr.line_buffer_read;
if (llc_top_line_buf_enabled) {
llc.line_buffer = ddr.line_buffer_read + ddr.line_buffer_write;
ddr.line_buffer_read = ddr.line_buffer_write = FP_ZERO;
}
ddr.total = ddr.vsp_read + ddr.vsp_write +
ddr.collocated_read + ddr.collocated_write +
ddr.ref_read_y + ddr.ref_read_crcb +
ddr.ref_write + ddr.ref_write_overlap +
ddr.orig_read +
ddr.line_buffer_read + ddr.line_buffer_write;
qsmmu_bw_overhead_factor = FP(1, 3, 100);
ddr.total = fp_mult(ddr.total, qsmmu_bw_overhead_factor);
llc.total = llc.ref_read_crcb + llc.line_buffer + ddr.total;
if (msm_vidc_debug & VIDC_BUS) {
struct dump dump[] = {
{"ENCODER PARAMETERS", "", DUMP_HEADER_MAGIC},
{"width", "%d", width},
{"height", "%d", height},
{"fps", "%d", fps},
{"dpb bitdepth", "%d", dpb_bpp},
{"input downscaling ratio", DUMP_FP_FMT, downscaling_ratio},
{"rotation", "%d", rotation},
{"cropping or scaling", "%d", cropping_or_scaling},
{"low power mode", "%d", low_power},
{"work Mode", "%d", work_mode_1},
{"B frame enabled", "%d", b_frames_enabled},
{"original frame format", "%#x", original_color_format},
{"original compression enabled", "%d",
original_compression_enabled},
{"dpb compression factor", DUMP_FP_FMT,
dpb_compression_factor},
{"input compression factor", DUMP_FP_FMT,
input_compression_factor},
{"llc ref chroma cache enabled", DUMP_FP_FMT,
llc_ref_chroma_cache_enabled},
{"llc top line buf enabled", DUMP_FP_FMT,
llc_top_line_buf_enabled},
{"llc vpss rot line buf enabled ", DUMP_FP_FMT,
llc_vpss_rot_line_buf_enabled},
{"DERIVED PARAMETERS", "", DUMP_HEADER_MAGIC},
{"lcu size", "%d", lcu_size},
{"bitrate (Mbit/sec)", "%lu", bitrate},
{"bins to bit factor", "%u", bins_to_bit_factor},
{"original compression factor", DUMP_FP_FMT,
original_compression_factor},
{"original compression factor y", DUMP_FP_FMT,
original_compression_factor_y},
{"qsmmu_bw_overhead_factor",
DUMP_FP_FMT, qsmmu_bw_overhead_factor},
{"bw for NV12 8bpc)", DUMP_FP_FMT, y_bw_no_ubwc_8bpp},
{"bw for NV12 10bpc)", DUMP_FP_FMT, y_bw_no_ubwc_10bpp},
{"INTERMEDIATE B/W DDR", "", DUMP_HEADER_MAGIC},
{"vsp read", DUMP_FP_FMT, ddr.vsp_read},
{"vsp write", DUMP_FP_FMT, ddr.vsp_write},
{"collocated read", DUMP_FP_FMT, ddr.collocated_read},
{"collocated write", DUMP_FP_FMT, ddr.collocated_write},
{"ref read y", DUMP_FP_FMT, ddr.ref_read_y},
{"ref read crcb", DUMP_FP_FMT, ddr.ref_read_crcb},
{"ref write", DUMP_FP_FMT, ddr.ref_write},
{"ref write overlap", DUMP_FP_FMT, ddr.ref_write_overlap},
{"original read", DUMP_FP_FMT, ddr.orig_read},
{"line buffer read", DUMP_FP_FMT, ddr.line_buffer_read},
{"line buffer write", DUMP_FP_FMT, ddr.line_buffer_write},
{"INTERMEDIATE LLC B/W", "", DUMP_HEADER_MAGIC},
{"llc ref read crcb", DUMP_FP_FMT, llc.ref_read_crcb},
{"llc line buffer", DUMP_FP_FMT, llc.line_buffer},
};
__dump(dump, ARRAY_SIZE(dump));
}
d->calc_bw_ddr = kbps(fp_round(ddr.total));
d->calc_bw_llcc = kbps(fp_round(llc.total));
return ret;
}
static u64 __calculate(struct msm_vidc_inst *inst, struct vidc_bus_vote_data *d)
{
u64 value = 0;
switch (d->domain) {
case MSM_VIDC_ENCODER:
value = __calculate_encoder(d);
break;
case MSM_VIDC_DECODER:
value = __calculate_decoder(d);
break;
default:
i_vpr_e(inst, "%s: Unknown Domain %#x", __func__, d->domain);
}
return value;
}
int msm_vidc_calc_bw_iris2(struct msm_vidc_inst *inst,
struct vidc_bus_vote_data *vidc_data)
{
int value = 0;
if (!vidc_data)
return value;
value = __calculate(inst, vidc_data);
return value;
}

1800
qcom/opensource/video-driver/driver/variant/iris3/inc/hfi_buffer_iris3.h ノーマルファイル
ファイルの表示

ファイル差分が大きすぎるため省略します 差分を読み込み

19
qcom/opensource/video-driver/driver/variant/iris3/inc/msm_vidc_buffer_iris3.h ノーマルファイル
ファイルの表示

@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __H_MSM_VIDC_BUFFER_IRIS3_H__
#define __H_MSM_VIDC_BUFFER_IRIS3_H__
#include "msm_vidc_inst.h"
int msm_buffer_size_iris3(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type);
int msm_buffer_min_count_iris3(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type);
int msm_buffer_extra_count_iris3(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type);
#endif // __H_MSM_VIDC_BUFFER_IRIS3_H__

27
qcom/opensource/video-driver/driver/variant/iris3/inc/msm_vidc_iris3.h ノーマルファイル
ファイルの表示

@@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _MSM_VIDC_IRIS3_H_
#define _MSM_VIDC_IRIS3_H_
#include "msm_vidc_core.h"
#if defined(CONFIG_MSM_VIDC_KALAMA)
int msm_vidc_init_iris3(struct msm_vidc_core *core);
int msm_vidc_adjust_bitrate_boost_iris3(void *instance, struct v4l2_ctrl *ctrl);
#else
static inline int msm_vidc_init_iris3(struct msm_vidc_core *core)
{
return -EINVAL;
}
static inline int msm_vidc_adjust_bitrate_boost_iris3(void *instance, struct v4l2_ctrl *ctrl)
{
return -EINVAL;
}
#endif
#endif // _MSM_VIDC_IRIS3_H_

19
qcom/opensource/video-driver/driver/variant/iris3/inc/msm_vidc_power_iris3.h ノーマルファイル
ファイルの表示

@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __H_MSM_VIDC_POWER_IRIS3_H__
#define __H_MSM_VIDC_POWER_IRIS3_H__
#include "msm_vidc_inst.h"
#include "msm_vidc_power.h"
#define ENABLE_LEGACY_POWER_CALCULATIONS 0
u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size);
int msm_vidc_calc_bw_iris3(struct msm_vidc_inst *inst,
struct vidc_bus_vote_data *vote_data);
#endif

736
qcom/opensource/video-driver/driver/variant/iris3/src/msm_vidc_buffer_iris3.c ノーマルファイル
ファイルの表示

@@ -0,0 +1,736 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "msm_vidc_buffer_iris3.h"
#include "msm_vidc_buffer.h"
#include "msm_vidc_inst.h"
#include "msm_vidc_core.h"
#include "msm_vidc_driver.h"
#include "msm_vidc_debug.h"
#include "msm_media_info.h"
#include "msm_vidc_platform.h"
#include "hfi_property.h"
#include "hfi_buffer_iris3.h"
static u32 msm_vidc_decoder_bin_size_iris3(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
u32 size = 0;
u32 width, height, num_vpp_pipes;
struct v4l2_format *f;
bool is_interlaced;
u32 vpp_delay;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
if (inst->decode_vpp_delay.enable)
vpp_delay = inst->decode_vpp_delay.size;
else
vpp_delay = DEFAULT_BSE_VPP_DELAY;
if (inst->capabilities[CODED_FRAMES].value ==
CODED_FRAMES_PROGRESSIVE)
is_interlaced = false;
else
is_interlaced = true;
f = &inst->fmts[INPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_BIN_H264D(size, width, height,
is_interlaced, vpp_delay, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_BIN_H265D(size, width, height,
0, vpp_delay, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_VP9)
HFI_BUFFER_BIN_VP9D(size, width, height,
0, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_AV1)
HFI_BUFFER_BIN_AV1D(size, width, height, is_interlaced,
0, num_vpp_pipes);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_comv_size_iris3(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 width, height, num_comv, vpp_delay;
struct v4l2_format *f;
f = &inst->fmts[INPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (inst->codec == MSM_VIDC_AV1) {
/*
* AV1 requires larger COMV buffer size to meet performance
* for certain use cases. Increase the COMV buffer size by
* increasing COMV bufcount. Use lower count for 8k to
* achieve performance but save memory.
*/
if (res_is_greater_than(width, height, 4096, 2176))
num_comv = inst->buffers.output.min_count + 3;
else
num_comv = inst->buffers.output.min_count + 7;
} else {
num_comv = inst->buffers.output.min_count;
}
msm_vidc_update_cap_value(inst, NUM_COMV, num_comv, __func__);
if (inst->codec == MSM_VIDC_HEIC
&& is_thumbnail_session(inst)) {
vpp_delay = 0;
} else {
if (inst->decode_vpp_delay.enable)
vpp_delay = inst->decode_vpp_delay.size;
else
vpp_delay = DEFAULT_BSE_VPP_DELAY;
}
num_comv = max(vpp_delay + 1, num_comv);
if (inst->codec == MSM_VIDC_H264) {
HFI_BUFFER_COMV_H264D(size, width, height, num_comv);
} else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC) {
HFI_BUFFER_COMV_H265D(size, width, height, num_comv);
} else if (inst->codec == MSM_VIDC_AV1) {
/*
* When DRAP is enabled, COMV buffer is part of PERSIST buffer and
* should not be allocated separately.
* When DRAP is disabled, COMV buffer must be allocated.
*/
if (inst->capabilities[DRAP].value)
size = 0;
else
HFI_BUFFER_COMV_AV1D(size, width, height, num_comv);
}
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_non_comv_size_iris3(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 width, height, num_vpp_pipes;
struct msm_vidc_core *core;
struct v4l2_format *f;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
f = &inst->fmts[INPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_NON_COMV_H264D(size, width, height, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_NON_COMV_H265D(size, width, height, num_vpp_pipes);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_line_size_iris3(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
u32 size = 0;
u32 width, height, out_min_count, num_vpp_pipes, vpp_delay;
struct v4l2_format *f;
bool is_opb;
u32 color_fmt;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
color_fmt = v4l2_colorformat_to_driver(inst,
inst->fmts[OUTPUT_PORT].fmt.pix_mp.pixelformat, __func__);
if (is_linear_colorformat(color_fmt))
is_opb = true;
else
is_opb = false;
/*
* assume worst case, since color format is unknown at this
* time.
*/
is_opb = true;
if (inst->decode_vpp_delay.enable)
vpp_delay = inst->decode_vpp_delay.size;
else
vpp_delay = DEFAULT_BSE_VPP_DELAY;
f = &inst->fmts[INPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
out_min_count = inst->buffers.output.min_count;
out_min_count = max(vpp_delay + 1, out_min_count);
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_LINE_H264D(size, width, height, is_opb,
num_vpp_pipes);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_LINE_H265D(size, width, height, is_opb,
num_vpp_pipes);
else if (inst->codec == MSM_VIDC_VP9)
HFI_BUFFER_LINE_VP9D(size, width, height, out_min_count,
is_opb, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_AV1)
HFI_BUFFER_LINE_AV1D(size, width, height, is_opb,
num_vpp_pipes);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_partial_data_size_iris3(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 width, height;
struct v4l2_format *f;
f = &inst->fmts[INPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (inst->codec == MSM_VIDC_AV1)
HFI_BUFFER_IBC_AV1D(size, width, height);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_persist_size_iris3(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 rpu_enabled = 0;
if (inst->capabilities[META_DOLBY_RPU].value)
rpu_enabled = 1;
if (inst->codec == MSM_VIDC_H264) {
HFI_BUFFER_PERSIST_H264D(size, rpu_enabled);
} else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC) {
HFI_BUFFER_PERSIST_H265D(size, rpu_enabled);
} else if (inst->codec == MSM_VIDC_VP9) {
HFI_BUFFER_PERSIST_VP9D(size);
} else if (inst->codec == MSM_VIDC_AV1) {
/*
* When DRAP is enabled, COMV buffer is part of PERSIST buffer and
* should not be allocated separately. PERSIST buffer should include
* COMV buffer calculated with width, height, refcount.
* When DRAP is disabled, COMV buffer should not be included in PERSIST
* buffer.
*/
if (inst->capabilities[DRAP].value)
HFI_BUFFER_PERSIST_AV1D(size,
inst->capabilities[FRAME_WIDTH].max,
inst->capabilities[FRAME_HEIGHT].max, 16);
else
HFI_BUFFER_PERSIST_AV1D(size, 0, 0, 0);
}
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_dpb_size_iris3(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 color_fmt;
u32 width, height;
struct v4l2_format *f;
/*
* For legacy codecs (non-AV1), DPB is calculated only
* for linear formats. For AV1, DPB is needed for film-grain
* enabled bitstreams (UBWC & linear).
*/
color_fmt = inst->capabilities[PIX_FMTS].value;
if (!is_linear_colorformat(color_fmt)) {
if (inst->codec != MSM_VIDC_AV1)
return size;
if (inst->codec == MSM_VIDC_AV1 &&
!inst->capabilities[FILM_GRAIN].value)
return size;
}
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (color_fmt == MSM_VIDC_FMT_NV12 ||
color_fmt == MSM_VIDC_FMT_NV12C) {
color_fmt = MSM_VIDC_FMT_NV12C;
HFI_NV12_UBWC_IL_CALC_BUF_SIZE_V2(size, width, height,
video_y_stride_bytes(color_fmt, width),
video_y_scanlines(color_fmt, height),
video_uv_stride_bytes(color_fmt, width),
video_uv_scanlines(color_fmt, height),
video_y_meta_stride(color_fmt, width),
video_y_meta_scanlines(color_fmt, height),
video_uv_meta_stride(color_fmt, width),
video_uv_meta_scanlines(color_fmt, height));
} else if (color_fmt == MSM_VIDC_FMT_P010 ||
color_fmt == MSM_VIDC_FMT_TP10C) {
color_fmt = MSM_VIDC_FMT_TP10C;
HFI_YUV420_TP10_UBWC_CALC_BUF_SIZE(size,
video_y_stride_bytes(color_fmt, width),
video_y_scanlines(color_fmt, height),
video_uv_stride_bytes(color_fmt, width),
video_uv_scanlines(color_fmt, height),
video_y_meta_stride(color_fmt, width),
video_y_meta_scanlines(color_fmt, height),
video_uv_meta_stride(color_fmt, width),
video_uv_meta_scanlines(color_fmt, height));
}
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
/* encoder internal buffers */
static u32 msm_vidc_encoder_bin_size_iris3(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
u32 size = 0;
u32 width, height, num_vpp_pipes, stage, profile;
struct v4l2_format *f;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
stage = inst->capabilities[STAGE].value;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
profile = inst->capabilities[PROFILE].value;
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_BIN_H264E(size, inst->hfi_rc_type, width,
height, stage, num_vpp_pipes, profile);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_BIN_H265E(size, inst->hfi_rc_type, width,
height, stage, num_vpp_pipes, profile);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_get_recon_buf_count(struct msm_vidc_inst *inst)
{
u32 num_buf_recon = 0;
s32 n_bframe, ltr_count, hp_layers = 0, hb_layers = 0;
bool is_hybrid_hp = false;
u32 hfi_codec = 0;
n_bframe = inst->capabilities[B_FRAME].value;
ltr_count = inst->capabilities[LTR_COUNT].value;
if (inst->hfi_layer_type == HFI_HIER_B) {
hb_layers = inst->capabilities[ENH_LAYER_COUNT].value + 1;
} else {
hp_layers = inst->capabilities[ENH_LAYER_COUNT].value + 1;
if (inst->hfi_layer_type == HFI_HIER_P_HYBRID_LTR)
is_hybrid_hp = true;
}
if (inst->codec == MSM_VIDC_H264)
hfi_codec = HFI_CODEC_ENCODE_AVC;
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
hfi_codec = HFI_CODEC_ENCODE_HEVC;
HFI_IRIS3_ENC_RECON_BUF_COUNT(num_buf_recon, n_bframe, ltr_count,
hp_layers, hb_layers, is_hybrid_hp, hfi_codec);
return num_buf_recon;
}
static u32 msm_vidc_encoder_comv_size_iris3(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 width, height, num_recon = 0;
struct v4l2_format *f;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
num_recon = msm_vidc_get_recon_buf_count(inst);
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_COMV_H264E(size, width, height, num_recon);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_COMV_H265E(size, width, height, num_recon);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_non_comv_size_iris3(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
u32 size = 0;
u32 width, height, num_vpp_pipes;
struct v4l2_format *f;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_NON_COMV_H264E(size, width, height, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_NON_COMV_H265E(size, width, height, num_vpp_pipes);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_line_size_iris3(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
u32 size = 0;
u32 width, height, pixfmt, num_vpp_pipes;
bool is_tenbit = false;
struct v4l2_format *f;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
pixfmt = inst->capabilities[PIX_FMTS].value;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
is_tenbit = (pixfmt == MSM_VIDC_FMT_P010 || pixfmt == MSM_VIDC_FMT_TP10C);
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_LINE_H264E(size, width, height, is_tenbit, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_LINE_H265E(size, width, height, is_tenbit, num_vpp_pipes);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_dpb_size_iris3(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 width, height, pixfmt;
struct v4l2_format *f;
bool is_tenbit;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
pixfmt = inst->capabilities[PIX_FMTS].value;
is_tenbit = (pixfmt == MSM_VIDC_FMT_P010 || pixfmt == MSM_VIDC_FMT_TP10C);
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_DPB_H264E(size, width, height);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_DPB_H265E(size, width, height, is_tenbit);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_arp_size_iris3(struct msm_vidc_inst *inst)
{
u32 size = 0;
HFI_BUFFER_ARP_ENC(size);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_vpss_size_iris3(struct msm_vidc_inst *inst)
{
u32 size = 0;
bool ds_enable = false, is_tenbit = false, blur = false;
u32 rotation_val = HFI_ROTATION_NONE;
u32 width, height, driver_colorfmt;
struct v4l2_format *f;
ds_enable = is_scaling_enabled(inst);
msm_vidc_v4l2_to_hfi_enum(inst, ROTATION, &rotation_val);
f = &inst->fmts[OUTPUT_PORT];
if (is_rotation_90_or_270(inst)) {
/*
* output width and height are rotated,
* so unrotate them to use as arguments to
* HFI_BUFFER_VPSS_ENC.
*/
width = f->fmt.pix_mp.height;
height = f->fmt.pix_mp.width;
} else {
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
}
f = &inst->fmts[INPUT_PORT];
driver_colorfmt = v4l2_colorformat_to_driver(inst,
f->fmt.pix_mp.pixelformat, __func__);
is_tenbit = is_10bit_colorformat(driver_colorfmt);
if (inst->capabilities[BLUR_TYPES].value != MSM_VIDC_BLUR_NONE)
blur = true;
HFI_BUFFER_VPSS_ENC(size, width, height, ds_enable, blur, is_tenbit);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_output_size_iris3(struct msm_vidc_inst *inst)
{
u32 frame_size;
struct v4l2_format *f;
bool is_ten_bit = false;
int bitrate_mode, frame_rc;
u32 hfi_rc_type = HFI_RC_VBR_CFR;
enum msm_vidc_codec_type codec;
f = &inst->fmts[OUTPUT_PORT];
codec = v4l2_codec_to_driver(inst, f->fmt.pix_mp.pixelformat, __func__);
if (codec == MSM_VIDC_HEVC || codec == MSM_VIDC_HEIC)
is_ten_bit = true;
bitrate_mode = inst->capabilities[BITRATE_MODE].value;
frame_rc = inst->capabilities[FRAME_RC_ENABLE].value;
if (!frame_rc && !is_image_session(inst))
hfi_rc_type = HFI_RC_OFF;
else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ)
hfi_rc_type = HFI_RC_CQ;
HFI_BUFFER_BITSTREAM_ENC(frame_size, f->fmt.pix_mp.width,
f->fmt.pix_mp.height, hfi_rc_type, is_ten_bit);
frame_size = msm_vidc_enc_delivery_mode_based_output_buf_size(inst, frame_size);
return frame_size;
}
struct msm_vidc_buf_type_handle {
enum msm_vidc_buffer_type type;
u32 (*handle)(struct msm_vidc_inst *inst);
};
int msm_buffer_size_iris3(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type)
{
int i;
u32 size = 0, buf_type_handle_size = 0;
const struct msm_vidc_buf_type_handle *buf_type_handle_arr = NULL;
static const struct msm_vidc_buf_type_handle dec_buf_type_handle[] = {
{MSM_VIDC_BUF_INPUT, msm_vidc_decoder_input_size },
{MSM_VIDC_BUF_OUTPUT, msm_vidc_decoder_output_size },
{MSM_VIDC_BUF_INPUT_META, msm_vidc_decoder_input_meta_size },
{MSM_VIDC_BUF_OUTPUT_META, msm_vidc_decoder_output_meta_size },
{MSM_VIDC_BUF_BIN, msm_vidc_decoder_bin_size_iris3 },
{MSM_VIDC_BUF_COMV, msm_vidc_decoder_comv_size_iris3 },
{MSM_VIDC_BUF_NON_COMV, msm_vidc_decoder_non_comv_size_iris3 },
{MSM_VIDC_BUF_LINE, msm_vidc_decoder_line_size_iris3 },
{MSM_VIDC_BUF_PERSIST, msm_vidc_decoder_persist_size_iris3 },
{MSM_VIDC_BUF_DPB, msm_vidc_decoder_dpb_size_iris3 },
{MSM_VIDC_BUF_PARTIAL_DATA, msm_vidc_decoder_partial_data_size_iris3 },
};
static const struct msm_vidc_buf_type_handle enc_buf_type_handle[] = {
{MSM_VIDC_BUF_INPUT, msm_vidc_encoder_input_size },
{MSM_VIDC_BUF_OUTPUT, msm_vidc_encoder_output_size_iris3 },
{MSM_VIDC_BUF_INPUT_META, msm_vidc_encoder_input_meta_size },
{MSM_VIDC_BUF_OUTPUT_META, msm_vidc_encoder_output_meta_size },
{MSM_VIDC_BUF_BIN, msm_vidc_encoder_bin_size_iris3 },
{MSM_VIDC_BUF_COMV, msm_vidc_encoder_comv_size_iris3 },
{MSM_VIDC_BUF_NON_COMV, msm_vidc_encoder_non_comv_size_iris3 },
{MSM_VIDC_BUF_LINE, msm_vidc_encoder_line_size_iris3 },
{MSM_VIDC_BUF_DPB, msm_vidc_encoder_dpb_size_iris3 },
{MSM_VIDC_BUF_ARP, msm_vidc_encoder_arp_size_iris3 },
{MSM_VIDC_BUF_VPSS, msm_vidc_encoder_vpss_size_iris3 },
};
if (is_decode_session(inst)) {
buf_type_handle_size = ARRAY_SIZE(dec_buf_type_handle);
buf_type_handle_arr = dec_buf_type_handle;
} else if (is_encode_session(inst)) {
buf_type_handle_size = ARRAY_SIZE(enc_buf_type_handle);
buf_type_handle_arr = enc_buf_type_handle;
}
/* handle invalid session */
if (!buf_type_handle_arr || !buf_type_handle_size) {
i_vpr_e(inst, "%s: invalid session %d\n", __func__, inst->domain);
return size;
}
/* fetch buffer size */
for (i = 0; i < buf_type_handle_size; i++) {
if (buf_type_handle_arr[i].type == buffer_type) {
size = buf_type_handle_arr[i].handle(inst);
break;
}
}
/* handle unknown buffer type */
if (i == buf_type_handle_size) {
i_vpr_e(inst, "%s: unknown buffer type %#x\n", __func__, buffer_type);
goto exit;
}
i_vpr_l(inst, "buffer_size: type: %11s, size: %9u\n", buf_name(buffer_type), size);
exit:
return size;
}
static int msm_vidc_input_min_count_iris3(struct msm_vidc_inst *inst)
{
u32 input_min_count = 0;
u32 total_hb_layer = 0;
if (is_decode_session(inst)) {
input_min_count = MIN_DEC_INPUT_BUFFERS;
} else if (is_encode_session(inst)) {
total_hb_layer = is_hierb_type_requested(inst) ?
inst->capabilities[ENH_LAYER_COUNT].value + 1 : 0;
if (inst->codec == MSM_VIDC_H264 &&
!inst->capabilities[LAYER_ENABLE].value) {
total_hb_layer = 0;
}
HFI_IRIS3_ENC_MIN_INPUT_BUF_COUNT(input_min_count,
total_hb_layer);
} else {
i_vpr_e(inst, "%s: invalid domain %d\n", __func__, inst->domain);
return 0;
}
if (is_thumbnail_session(inst) || is_image_session(inst))
input_min_count = 1;
return input_min_count;
}
static int msm_buffer_dpb_count(struct msm_vidc_inst *inst)
{
int count = 0;
u32 color_fmt;
/* decoder dpb buffer count */
if (is_decode_session(inst)) {
color_fmt = inst->capabilities[PIX_FMTS].value;
if (is_linear_colorformat(color_fmt) ||
(inst->codec == MSM_VIDC_AV1 &&
(inst->capabilities[FILM_GRAIN].value)))
count = inst->buffers.output.min_count;
return count;
}
/* encoder dpb buffer count */
return msm_vidc_get_recon_buf_count(inst);
}
static int msm_buffer_delivery_mode_based_min_count_iris3(struct msm_vidc_inst *inst,
uint32_t count)
{
struct v4l2_format *f;
struct msm_vidc_core *core = NULL;
u32 width, height, total_num_slices = 1;
u32 hfi_codec = 0;
u32 max_mbs_per_slice = 0;
u32 slice_mode = 0;
u32 delivery_mode = 0;
u32 num_vpp_pipes;
slice_mode = inst->capabilities[SLICE_MODE].value;
delivery_mode = inst->capabilities[DELIVERY_MODE].value;
if (slice_mode != V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB ||
(!delivery_mode))
return count;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
max_mbs_per_slice = inst->capabilities[SLICE_MAX_MB].value;
if (inst->codec == MSM_VIDC_H264)
hfi_codec = HFI_CODEC_ENCODE_AVC;
else if (inst->codec == MSM_VIDC_HEVC)
hfi_codec = HFI_CODEC_ENCODE_HEVC;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
HFI_IRIS3_ENC_MB_BASED_MULTI_SLICE_COUNT(total_num_slices, width, height,
hfi_codec, max_mbs_per_slice, num_vpp_pipes);
return (total_num_slices * count);
}
int msm_buffer_min_count_iris3(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type)
{
int count = 0;
switch (buffer_type) {
case MSM_VIDC_BUF_INPUT:
case MSM_VIDC_BUF_INPUT_META:
count = msm_vidc_input_min_count_iris3(inst);
break;
case MSM_VIDC_BUF_OUTPUT:
case MSM_VIDC_BUF_OUTPUT_META:
count = msm_vidc_output_min_count(inst);
count = msm_buffer_delivery_mode_based_min_count_iris3(inst, count);
break;
case MSM_VIDC_BUF_BIN:
case MSM_VIDC_BUF_COMV:
case MSM_VIDC_BUF_NON_COMV:
case MSM_VIDC_BUF_LINE:
case MSM_VIDC_BUF_PERSIST:
case MSM_VIDC_BUF_ARP:
case MSM_VIDC_BUF_VPSS:
case MSM_VIDC_BUF_PARTIAL_DATA:
count = msm_vidc_internal_buffer_count(inst, buffer_type);
break;
case MSM_VIDC_BUF_DPB:
count = msm_buffer_dpb_count(inst);
break;
default:
break;
}
i_vpr_l(inst, " min_count: type: %11s, count: %9u\n", buf_name(buffer_type), count);
return count;
}
int msm_buffer_extra_count_iris3(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type)
{
int count = 0;
switch (buffer_type) {
case MSM_VIDC_BUF_INPUT:
case MSM_VIDC_BUF_INPUT_META:
count = msm_vidc_input_extra_count(inst);
break;
case MSM_VIDC_BUF_OUTPUT:
case MSM_VIDC_BUF_OUTPUT_META:
count = msm_vidc_output_extra_count(inst);
break;
default:
break;
}
i_vpr_l(inst, "extra_count: type: %11s, count: %9u\n", buf_name(buffer_type), count);
return count;
}

928
qcom/opensource/video-driver/driver/variant/iris3/src/msm_vidc_bus_iris3.c ノーマルファイル
ファイルの表示

@@ -0,0 +1,928 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kalama_technology.h"
#include "msm_vidc_debug.h"
u32 calculate_number_lcus_kalama(u32 width, u32 height, u32 lcu_size)
{
u32 mbs_width = (width % lcu_size) ?
(width / lcu_size + 1) : (width / lcu_size);
u32 mbs_height = (height % lcu_size) ?
(height / lcu_size + 1) : (height / lcu_size);
return mbs_width * mbs_height;
}
u32 calculate_number_ubwctiles_kalama(
u32 width, u32 height, u32 tile_w, u32 tile_h)
{
u32 tiles_width = (width % tile_w) ?
(width / tile_w + 1) : (width / tile_w);
u32 tiles_height = (height % tile_h) ?
(height / tile_h + 1) : (height / tile_h);
return tiles_width * tiles_height;
}
struct compression_factors {
u32 dpb_cf_y;
u32 dpb_cf_cbcr;
u32 opb_cf_ycbcr;
u32 dpb_cr_y;
u32 ipb_cr_y;
u32 ipb_cr;
} compression_factor;
u32 get_compression_factors(struct compression_factors *compression_factor,
struct api_calculation_input codec_input)
{
u8 cr_index_entry, cr_index_y, cr_index_c, cr_index_uni;
u32 frame_width;
u32 frame_height;
frame_width = codec_input.frame_width;
frame_height = codec_input.frame_height;
if (frame_width * frame_height <= 1920 * 1080)
cr_index_entry = 0;
else
cr_index_entry = 1;
if (codec_input.bitdepth == CODEC_BITDEPTH_8) {
/* NOT PWC or average and power case */
if (codec_input.complexity_setting != 0) {
cr_index_y = 0;
cr_index_c = 1;
cr_index_uni = 2;
} else {
cr_index_y = 3;
cr_index_c = 4;
cr_index_uni = 5;
}
} else {
/* NOT PWC or average and power case */
if (codec_input.complexity_setting != 0) {
cr_index_y = 6;
cr_index_c = 7;
cr_index_uni = 8;
} else {
cr_index_y = 9;
cr_index_c = 10;
cr_index_uni = 11;
}
}
if (codec_input.decoder_or_encoder == CODEC_DECODER) {
compression_factor->dpb_cf_y =
dpbopb_ubwc30_cr_table_cratio_kalama[cr_index_entry][cr_index_y];
compression_factor->dpb_cf_cbcr =
dpbopb_ubwc30_cr_table_cratio_kalama[cr_index_entry][cr_index_c];
compression_factor->opb_cf_ycbcr =
dpbopb_ubwc30_cr_table_cratio_kalama[cr_index_entry][cr_index_uni];
if ((codec_input.regression_mode == 3) &&
/* input cr numbers from interface */
((codec_input.cr_dpb != 0) || (codec_input.cr_opb != 0))) {
compression_factor->dpb_cf_y = (u32)(codec_input.cr_dpb * 100);
compression_factor->dpb_cf_cbcr = (u32)(codec_input.cr_dpb * 100);
compression_factor->opb_cf_ycbcr = (u32)(codec_input.cr_opb * 100);
}
} else { /* encoder */
/*
* IPB CR Table Choice; static sheet (if framewidth<3840, use lossless table)
* (else, use lossy table)
* stick to this choice for SW purpose (no change for SW)
*/
if (frame_width < 3840) {
compression_factor->ipb_cr =
ipblossless_ubwc30_cr_table_cratio_kalama[cr_index_entry]
[cr_index_uni];
compression_factor->ipb_cr_y =
ipblossless_ubwc30_cr_table_cratio_kalama[cr_index_entry]
[cr_index_y];
} else {
compression_factor->ipb_cr =
ipblossy_ubwc30_cr_table_cratio_kalama[cr_index_entry]
[cr_index_uni];
compression_factor->ipb_cr_y =
ipblossy_ubwc30_cr_table_cratio_kalama[cr_index_entry]
[cr_index_y];
}
compression_factor->dpb_cf_y =
rpb_ubwc30_cr_table_cratio_kalama[cr_index_entry][cr_index_y];
compression_factor->dpb_cf_cbcr =
rpb_ubwc30_cr_table_cratio_kalama[cr_index_entry][cr_index_c];
if ((codec_input.regression_mode == 3) &&
/* input cr from interface */
((codec_input.cr_ipb != 0) || (codec_input.cr_rpb != 0))) {
compression_factor->dpb_cf_y = (u32)(codec_input.cr_rpb * 100);
compression_factor->dpb_cf_cbcr = (u32)(codec_input.cr_rpb * 100);
compression_factor->ipb_cr_y = (u32)(codec_input.cr_ipb * 100);
}
}
return 0;
}
static int calculate_bandwidth_decoder_iris3(
struct api_calculation_input codec_input,
struct api_calculation_bw_output *codec_output)
{
/* common control parameters */
u32 frame_width;
u32 frame_height;
u32 frame_lcu_size = 16; /* initialized to h264 */
u32 lcu_per_frame;
u32 target_bitrate;
u32 collocated_bytes_per_lcu = 16; /* initialized to h264 */
u32 av1d_segment_read_per_lcu;
u32 av1d_fe_leftlinebuffer_perlcu_tileboudary;
u32 frame420_y_bw_linear_8bpp;
u32 frame420_y_bw_no_ubwc_tile_10bpp;
u32 frame420_y_bw_linear_10bpp;
u16 ubwc_tile_w;
u16 ubwc_tile_h;
u32 dpb_compression_factor_y;
u32 dpb_compression_factor_cbcr;
u32 reconstructed_write_bw_factor_rd;
u32 reference_y_read_bw_factor;
u32 reference_cbcr_read_bw_factor;
/* decoder control parameters */
u32 decoder_vsp_read_factor = 6;
u32 bins_to_bits_factor = 4;
u32 dpb_to_opb_ratios_ds = 1;
u8 llc_enabled_ref_y_rd = 1;
u8 llc_enable_ref_crcb_rd = 1;
u8 llc_enabled_bse_tlb = 1;
/* this is for 2pipe and 1pipe LLC */
u8 llc_enable_probtable_av1d_21pipe = 0;
u32 opb_compression_factor_ycbcr;
u32 dpb_ubwc_tile_width_pixels;
u32 dpb_ubwc_tile_height_pixels;
u32 decoder_frame_complexity_factor;
u32 llc_saving = 130; /* Initialized to H264 */
u16 av1_tile_numbers;
u32 av1_collated_seg_buffer_rd_wr;
/* need divide by 1M at later step; */
u32 av1_probability_table_rdwr_bytesperframe = 22784;
u32 av1_fe_left_line_buffer_rdwr;
u32 bse_tlb_byte_per_lcu = 0;
u32 large_bw_calculation_fp = 0;
llc_enabled_ref_y_rd = (codec_input.status_llc_onoff) ? 1 : 0;
llc_enable_ref_crcb_rd = (codec_input.status_llc_onoff) ? 1 : 0;
/* H265D BSE tlb in LLC will be pored in Kailua */
llc_enabled_bse_tlb = (codec_input.status_llc_onoff) ? 1 : 0;
frame_width = codec_input.frame_width;
frame_height = codec_input.frame_height;
if ((codec_input.codec == CODEC_H264) ||
(codec_input.codec == CODEC_H264_CAVLC)) {
frame_lcu_size = 16;
collocated_bytes_per_lcu = 16;
llc_saving = 130;
} else if (codec_input.codec == CODEC_HEVC) {
if (codec_input.lcu_size == 32) {
frame_lcu_size = 32;
collocated_bytes_per_lcu = 64;
llc_saving = 114;
} else if (codec_input.lcu_size == 64) {
frame_lcu_size = 64;
collocated_bytes_per_lcu = 256;
llc_saving = 107;
}
} else if (codec_input.codec == CODEC_VP9) {
if (codec_input.lcu_size == 32) {
frame_lcu_size = 32;
collocated_bytes_per_lcu = 64;
llc_saving = 114;
} else if (codec_input.lcu_size == 64) {
frame_lcu_size = 64;
collocated_bytes_per_lcu = 256;
llc_saving = 107;
}
} else if (codec_input.codec == CODEC_AV1) {
u32 av1d_leftline_cdef = (2944 + 896 + 896);
u32 av1d_leftline_scaling = (2176 + 1408 + 1408);
u32 av1d_leftline_fg = (1280);
u32 av1d_leftline_lr = (1536 + 1024 + 1024);
av1d_fe_leftlinebuffer_perlcu_tileboudary =
av1d_leftline_cdef + av1d_leftline_scaling +
av1d_leftline_fg + av1d_leftline_lr;
if (codec_input.lcu_size == 128) {
frame_lcu_size = 128;
collocated_bytes_per_lcu = 4 * 512;
av1d_segment_read_per_lcu = 512;
llc_saving = 104;
} else if (codec_input.lcu_size == 32) {
frame_lcu_size = 32;
collocated_bytes_per_lcu = 4 * 512 / (128 * 128 / 32 / 32);
av1d_segment_read_per_lcu = 512 / (128 * 128 / 32 / 32);
av1d_fe_leftlinebuffer_perlcu_tileboudary =
av1d_fe_leftlinebuffer_perlcu_tileboudary / (128 * 128 / 32 / 32);
llc_saving = 114;
} else if (codec_input.lcu_size == 64) {
frame_lcu_size = 64;
collocated_bytes_per_lcu = 4 * 512 / (128 * 128 / 64 / 64);
av1d_segment_read_per_lcu = 512 / (128 * 128 / 64 / 64);
av1d_fe_leftlinebuffer_perlcu_tileboudary =
av1d_fe_leftlinebuffer_perlcu_tileboudary / (128 * 128 / 64 / 64);
llc_saving = 107;
}
}
lcu_per_frame =
calculate_number_lcus_kalama(frame_width, frame_height, frame_lcu_size);
target_bitrate = (u32)(codec_input.bitrate_mbps); /* Mbps */
ubwc_tile_w = (codec_input.bitdepth == CODEC_BITDEPTH_8) ? 32 : 48;
ubwc_tile_h = (codec_input.bitdepth == CODEC_BITDEPTH_8) ? 8 : 4;
frame420_y_bw_linear_8bpp =
((calculate_number_ubwctiles_kalama(frame_width, frame_height, 32, 8) *
256 * codec_input.frame_rate + 999) / 1000 + 999) / 1000;
frame420_y_bw_no_ubwc_tile_10bpp =
((calculate_number_ubwctiles_kalama(frame_width, frame_height, 48, 4) *
256 * codec_input.frame_rate + 999) / 1000 + 999) / 1000;
frame420_y_bw_linear_10bpp = ((frame_width * frame_height *
codec_input.frame_rate * 2 + 999) / 1000 + 999) / 1000;
/* TODO Integrate Compression Ratio returned by FW */
get_compression_factors(&compression_factor, codec_input);
dpb_compression_factor_y = compression_factor.dpb_cf_y;
dpb_compression_factor_cbcr = compression_factor.dpb_cf_cbcr;
opb_compression_factor_ycbcr = compression_factor.opb_cf_ycbcr;
dpb_ubwc_tile_width_pixels = ubwc_tile_w;
dpb_ubwc_tile_height_pixels = ubwc_tile_h;
decoder_frame_complexity_factor =
(codec_input.complexity_setting == 0) ?
400 : ((codec_input.complexity_setting == 1) ? 266 : 100);
reconstructed_write_bw_factor_rd = (codec_input.complexity_setting == 0) ?
105 : 100;
reference_y_read_bw_factor = llc_saving;
reference_cbcr_read_bw_factor = llc_saving;
if (codec_input.codec == CODEC_AV1) {
u8 av1tile_index_entry, av1tile_complexity;
if (frame_width * frame_height <= 1280 * 720)
av1tile_index_entry = 4;
else if (frame_width * frame_height <= 1920 * 1080)
av1tile_index_entry = 0;
else if (frame_width * frame_height <= 2560 * 1440)
av1tile_index_entry = 5;
else if (frame_width * frame_height <= 4096 * 2304)
av1tile_index_entry = 1;
else
av1tile_index_entry = 6;
/* NOT PWC //or average and power case */
if (codec_input.complexity_setting != 0)
av1tile_complexity = 1;
else
av1tile_complexity = 0;
av1_tile_numbers = av1_num_tiles_kalama[av1tile_index_entry][av1tile_complexity];
/* these bw can be ignored */
av1_collated_seg_buffer_rd_wr =
((av1d_segment_read_per_lcu * lcu_per_frame *
codec_input.frame_rate + 999) / 1000 + 999) / 1000;
av1_fe_left_line_buffer_rdwr =
(((av1d_fe_leftlinebuffer_perlcu_tileboudary *
frame_height * (av1_tile_numbers > 1 ? av1_tile_numbers / 2 : 0)
+ 999) / 1000 + 999) / 1000 + (frame_lcu_size - 1)) / frame_lcu_size;
}
if (codec_input.codec == CODEC_HEVC) {
if (codec_input.lcu_size == 32)
bse_tlb_byte_per_lcu = 64;
else if (codec_input.lcu_size == 16)
bse_tlb_byte_per_lcu = 32;
else
bse_tlb_byte_per_lcu = 128;
} else if ((codec_input.codec == CODEC_H264) ||
(codec_input.codec == CODEC_H264_CAVLC)) {
bse_tlb_byte_per_lcu = 64;
} else if (codec_input.codec == CODEC_VP9) {
bse_tlb_byte_per_lcu = 304;
} else if (codec_input.codec == CODEC_AV1) {
if (codec_input.lcu_size == 128)
bse_tlb_byte_per_lcu = 2064;
else if (codec_input.lcu_size == 64)
bse_tlb_byte_per_lcu = 1056;
else if (codec_input.lcu_size == 32)
bse_tlb_byte_per_lcu = 2064 / (128 * 128 / 32 / 32);
}
codec_output->noc_bw_rd = 0;
codec_output->noc_bw_wr = 0;
codec_output->ddr_bw_rd = 0;
codec_output->ddr_bw_wr = 0;
large_bw_calculation_fp = 0;
large_bw_calculation_fp = ((target_bitrate *
decoder_vsp_read_factor + 7) / 8);
codec_output->vsp_read_noc = large_bw_calculation_fp;
codec_output->vsp_read_ddr = codec_output->vsp_read_noc;
large_bw_calculation_fp = ((target_bitrate *
bins_to_bits_factor + 7) / 8);
codec_output->vsp_write_noc = large_bw_calculation_fp;
codec_output->vsp_write_ddr = codec_output->vsp_write_noc;
/* accumulation */
codec_output->noc_bw_rd += codec_output->vsp_read_noc;
codec_output->ddr_bw_rd += codec_output->vsp_read_ddr;
codec_output->noc_bw_wr += codec_output->vsp_write_noc;
codec_output->ddr_bw_wr += codec_output->vsp_write_ddr;
large_bw_calculation_fp = 0;
large_bw_calculation_fp = ((collocated_bytes_per_lcu *
lcu_per_frame * codec_input.frame_rate + 999) / 1000 + 999) / 1000;
codec_output->collocated_rd_noc = large_bw_calculation_fp;
codec_output->collocated_wr_noc = codec_output->collocated_rd_noc;
codec_output->collocated_rd_ddr = codec_output->collocated_rd_noc;
codec_output->collocated_wr_ddr = codec_output->collocated_wr_noc;
codec_output->collocated_rd_wr_total_noc =
(u32)(codec_output->collocated_rd_noc + codec_output->collocated_wr_noc);
codec_output->collocated_rd_wr_total_ddr =
codec_output->collocated_rd_wr_total_noc;
/* accumulation */
codec_output->noc_bw_rd += codec_output->collocated_rd_noc;
codec_output->noc_bw_wr += codec_output->collocated_wr_noc;
codec_output->ddr_bw_rd += codec_output->collocated_rd_ddr;
codec_output->ddr_bw_wr += codec_output->collocated_wr_ddr;
large_bw_calculation_fp = 0;
large_bw_calculation_fp = ((codec_input.bitdepth == CODEC_BITDEPTH_8) ?
frame420_y_bw_linear_8bpp :
frame420_y_bw_no_ubwc_tile_10bpp) * decoder_frame_complexity_factor;
large_bw_calculation_fp =
(large_bw_calculation_fp + dpb_compression_factor_y - 1) /
dpb_compression_factor_y;
codec_output->dpb_rd_y_noc = large_bw_calculation_fp;
large_bw_calculation_fp = ((codec_input.bitdepth == CODEC_BITDEPTH_8) ?
frame420_y_bw_linear_8bpp : frame420_y_bw_no_ubwc_tile_10bpp) *
decoder_frame_complexity_factor;
large_bw_calculation_fp =
(large_bw_calculation_fp + dpb_compression_factor_cbcr - 1) /
dpb_compression_factor_cbcr / 2;
codec_output->dpb_rd_crcb_noc = large_bw_calculation_fp;
codec_output->dpb_rdwr_duetooverlap_noc = 0;
large_bw_calculation_fp = ((codec_input.bitdepth == CODEC_BITDEPTH_8) ?
frame420_y_bw_linear_8bpp : frame420_y_bw_no_ubwc_tile_10bpp) *
reconstructed_write_bw_factor_rd;
large_bw_calculation_fp = ((codec_input.bitdepth == CODEC_BITDEPTH_8) ?
frame420_y_bw_linear_8bpp : frame420_y_bw_no_ubwc_tile_10bpp) *
reconstructed_write_bw_factor_rd;
large_bw_calculation_fp = large_bw_calculation_fp *
(dpb_compression_factor_y / 2 + dpb_compression_factor_cbcr);
large_bw_calculation_fp = (large_bw_calculation_fp + dpb_compression_factor_y - 1) /
dpb_compression_factor_y;
large_bw_calculation_fp =
(large_bw_calculation_fp + dpb_compression_factor_cbcr - 1) /
dpb_compression_factor_cbcr;
codec_output->dpb_wr_noc = large_bw_calculation_fp;
codec_output->dpb_rd_y_ddr = (llc_enabled_ref_y_rd) ?
((codec_output->dpb_rd_y_noc * 100 + reference_y_read_bw_factor - 1) /
reference_y_read_bw_factor) : codec_output->dpb_rd_y_noc;
codec_output->dpb_rd_crcb_ddr = (llc_enable_ref_crcb_rd) ?
((codec_output->dpb_rd_crcb_noc * 100 +
reference_cbcr_read_bw_factor - 1) /
reference_cbcr_read_bw_factor) : codec_output->dpb_rd_crcb_noc;
codec_output->dpb_rdwr_duetooverlap_ddr = 0;
codec_output->dpb_wr_ddr = codec_output->dpb_wr_noc;
/* accumulation */
codec_output->noc_bw_rd += codec_output->dpb_rd_y_noc;
codec_output->noc_bw_rd += codec_output->dpb_rd_crcb_noc;
codec_output->noc_bw_rd += codec_output->dpb_rdwr_duetooverlap_noc;
codec_output->noc_bw_wr += codec_output->dpb_wr_noc;
codec_output->ddr_bw_rd += codec_output->dpb_rd_y_ddr;
codec_output->ddr_bw_rd += codec_output->dpb_rd_crcb_ddr;
codec_output->ddr_bw_rd += codec_output->dpb_rdwr_duetooverlap_ddr;
codec_output->ddr_bw_wr += codec_output->dpb_wr_ddr;
if (codec_input.linear_opb || codec_input.split_opb) {
if (codec_input.linear_opb) {
if (codec_input.bitdepth == CODEC_BITDEPTH_8) {
large_bw_calculation_fp = ((frame420_y_bw_linear_8bpp) *
3 / 2 / dpb_to_opb_ratios_ds);
codec_output->opb_write_total_noc = large_bw_calculation_fp;
} else {
large_bw_calculation_fp = ((frame420_y_bw_linear_10bpp) *
3 / 2 / dpb_to_opb_ratios_ds);
codec_output->opb_write_total_noc = large_bw_calculation_fp;
}
} else { /* (CODEC_INPUT.split_opb) */
if (codec_input.bitdepth == CODEC_BITDEPTH_8) {
large_bw_calculation_fp =
(frame420_y_bw_linear_8bpp * 3 / 2 / dpb_to_opb_ratios_ds *
100 + opb_compression_factor_ycbcr - 1) /
opb_compression_factor_ycbcr;
codec_output->opb_write_total_noc = large_bw_calculation_fp;
} else {
large_bw_calculation_fp =
(frame420_y_bw_no_ubwc_tile_10bpp * 3 / 2 /
dpb_to_opb_ratios_ds * 100 +
opb_compression_factor_ycbcr - 1) /
opb_compression_factor_ycbcr;
codec_output->opb_write_total_noc = large_bw_calculation_fp;
}
}
} else {
codec_output->opb_write_total_noc = 0;
}
codec_output->opb_write_total_ddr = codec_output->opb_write_total_noc;
/* accumulation */
codec_output->noc_bw_wr += codec_output->opb_write_total_noc;
codec_output->ddr_bw_wr += codec_output->opb_write_total_ddr;
large_bw_calculation_fp = ((bse_tlb_byte_per_lcu * lcu_per_frame *
codec_input.frame_rate + 999) / 1000 + 999) / 1000;
codec_output->bse_tlb_rd_noc = large_bw_calculation_fp;
if (llc_enabled_bse_tlb)
codec_output->bse_tlb_rd_ddr = 0;
else
codec_output->bse_tlb_rd_ddr = codec_output->bse_tlb_rd_noc;
codec_output->bse_tlb_wr_noc = codec_output->bse_tlb_rd_noc;
if (llc_enabled_bse_tlb)
codec_output->bse_tlb_wr_ddr = 0;
else
codec_output->bse_tlb_wr_ddr = codec_output->bse_tlb_wr_noc;
/* accumulation */
codec_output->noc_bw_rd += codec_output->bse_tlb_rd_noc;
codec_output->ddr_bw_rd += codec_output->bse_tlb_rd_ddr;
codec_output->noc_bw_wr += codec_output->bse_tlb_wr_noc;
codec_output->ddr_bw_wr += codec_output->bse_tlb_wr_ddr;
if (codec_input.codec == CODEC_AV1) {
codec_output->statistics_rd_noc = (av1_collated_seg_buffer_rd_wr +
av1_probability_table_rdwr_bytesperframe * av1_tile_numbers /
1000 / 1000 + av1_fe_left_line_buffer_rdwr);
codec_output->statistics_wr_noc = (av1_collated_seg_buffer_rd_wr +
av1_probability_table_rdwr_bytesperframe * av1_tile_numbers /
1000 / 1000 + av1_fe_left_line_buffer_rdwr);
if (llc_enable_probtable_av1d_21pipe) {
/* assert(CODEC_INPUT.pipe_num != 4); */
codec_output->statistics_rd_ddr = codec_output->statistics_rd_noc -
av1_probability_table_rdwr_bytesperframe *
av1_tile_numbers / 1000 / 1000;
codec_output->statistics_wr_ddr = codec_output->statistics_wr_noc -
av1_probability_table_rdwr_bytesperframe *
av1_tile_numbers / 1000 / 1000;
} else {
codec_output->statistics_rd_ddr = codec_output->statistics_rd_noc;
codec_output->statistics_wr_ddr = codec_output->statistics_wr_noc;
}
/* accumulation */
codec_output->noc_bw_rd += codec_output->statistics_rd_noc;
codec_output->ddr_bw_rd += codec_output->statistics_rd_ddr;
codec_output->noc_bw_wr += codec_output->statistics_wr_noc;
codec_output->ddr_bw_wr += codec_output->statistics_wr_ddr;
}
codec_output->mmu_rd_ddr = 0;
codec_output->mmu_rd_noc = 0;
/* accumulation */
codec_output->noc_bw_rd += codec_output->mmu_rd_noc;
codec_output->ddr_bw_rd += codec_output->mmu_rd_ddr;
return 0;
}
static int calculate_bandwidth_encoder_iris3(
struct api_calculation_input codec_input,
struct api_calculation_bw_output *codec_output)
{
/* common control parameters */
u32 frame_width;
u32 frame_height;
u32 frame_lcu_size;
u32 lcu_per_frame;
u32 target_bitrate;
u32 collocated_bytes_per_lcu;
u32 frame420_y_bw_linear_8bpp;
u32 frame420_y_bw_no_ubwc_tile_10bpp;
u32 frame420_y_bw_linear_10bpp;
u16 ubwc_tile_w;
u16 ubwc_tile_h;
u32 dpb_compression_factor_y;
u32 dpb_compression_factor_cbcr;
u32 reconstructed_write_bw_factor_rd;
u32 reference_y_read_bw_factor;
u32 reference_crcb_read_bw_factor;
/* encoder control parameters */
u32 en_vertical_tiles_width = 960;
u8 en_rotation_90_270 = 0;
/* TODO Can we use (codec_input.status_llc_onoff) for enc_llc_*? */
u8 en_llc_enable_ref_rd_crcb = 0;
u8 en_llc_enable_rec_wr_uncompleted = 0;
u8 en_llc_enable_ref_rd_y_overlap = 0;
u32 en_bins_to_bits_factor = 4;
u32 en_search_windows_size_horizontal = 96;
u32 en_tile_number;
u32 ipb_compression_factor_y;
u32 ipb_compression_factor;
u32 large_bw_calculation_fp = 0;
/* TODO Are these really needed in Encoder? */
u32 bse_tlb_byte_per_lcu = 0;
u8 llc_enabled_bse_tlb = 1;
/*H265D BSE tlb in LLC will be pored in Kailua */
llc_enabled_bse_tlb = (codec_input.status_llc_onoff) ? 1 : 0;
frame_width = codec_input.frame_width;
frame_height = codec_input.frame_height;
if ((codec_input.codec == CODEC_H264) ||
(codec_input.codec == CODEC_H264_CAVLC)) {
frame_lcu_size = 16;
collocated_bytes_per_lcu = 16;
} else if (codec_input.codec == CODEC_HEVC) {
frame_lcu_size = 32;
collocated_bytes_per_lcu = 64;
} else {
/* TODO What is the value for VP9, AV1? */
frame_lcu_size = 16;
collocated_bytes_per_lcu = 16; /* TODO Fixes Uninitialized compilation error. */
}
lcu_per_frame =
calculate_number_lcus_kalama(frame_width, frame_height, frame_lcu_size);
bse_tlb_byte_per_lcu = 16; /* TODO Should be in common declaration */
target_bitrate = (u32)(codec_input.bitrate_mbps); /* Mbps */
ubwc_tile_w = (codec_input.bitdepth == CODEC_BITDEPTH_8) ? 32 : 48;
ubwc_tile_h = (codec_input.bitdepth == CODEC_BITDEPTH_8) ? 8 : 4;
/* yuv */
if (codec_input.ipb_yuvrgb == 0) {
frame420_y_bw_linear_8bpp =
((calculate_number_ubwctiles_kalama(frame_width, frame_height,
32, 8) * 256 * codec_input.frame_rate + 999) / 1000 + 999) / 1000;
} else { /* RGBA */
frame420_y_bw_linear_8bpp =
((calculate_number_ubwctiles_kalama(frame_width, frame_height,
6, 4) * 256 * codec_input.frame_rate + 999) / 1000 + 999) / 1000;
}
frame420_y_bw_no_ubwc_tile_10bpp =
((calculate_number_ubwctiles_kalama(frame_width, frame_height, 48, 4) *
256 * codec_input.frame_rate + 999) / 1000 + 999) / 1000;
frame420_y_bw_linear_10bpp = ((frame_width * frame_height *
codec_input.frame_rate * 2 + 999) / 1000 + 999) / 1000;
/* TODO Integrate Compression Ratio returned by FW */
get_compression_factors(&compression_factor, codec_input);
dpb_compression_factor_y = compression_factor.dpb_cf_y;
dpb_compression_factor_cbcr = compression_factor.dpb_cf_cbcr;
ipb_compression_factor_y = compression_factor.ipb_cr_y;
ipb_compression_factor = compression_factor.ipb_cr;
en_tile_number = (frame_width % en_vertical_tiles_width) ?
((frame_width / en_vertical_tiles_width) + 1) :
(frame_width / en_vertical_tiles_width);
en_tile_number = en_tile_number * 100;
/* ceil is same as excel roundup (float, 0); */
reconstructed_write_bw_factor_rd = ((en_tile_number - 100) * 2 *
((codec_input.lcu_size + ubwc_tile_w - 1) / ubwc_tile_w) *
ubwc_tile_w + (frame_width - 1)) / (frame_width)+100;
reference_y_read_bw_factor = ((en_tile_number - 100) * 2 *
((en_search_windows_size_horizontal + ubwc_tile_w - 1) / ubwc_tile_w) *
ubwc_tile_w + (frame_width - 1)) / frame_width + 100;
reference_crcb_read_bw_factor = 150;
codec_output->noc_bw_rd = 0;
codec_output->noc_bw_wr = 0;
codec_output->ddr_bw_rd = 0;
codec_output->ddr_bw_wr = 0;
large_bw_calculation_fp = (target_bitrate * en_bins_to_bits_factor + 7) / 8;
codec_output->vsp_read_noc = large_bw_calculation_fp;
codec_output->vsp_read_ddr = codec_output->vsp_read_noc;
large_bw_calculation_fp = (target_bitrate + 7) / 8;
codec_output->vsp_write_noc = codec_output->vsp_read_noc +
large_bw_calculation_fp;
codec_output->vsp_write_ddr = codec_output->vsp_write_noc;
/* accumulation */
codec_output->noc_bw_rd += codec_output->vsp_read_noc;
codec_output->ddr_bw_rd += codec_output->vsp_read_ddr;
codec_output->noc_bw_wr += codec_output->vsp_write_noc;
codec_output->ddr_bw_wr += codec_output->vsp_write_ddr;
large_bw_calculation_fp = ((collocated_bytes_per_lcu * lcu_per_frame *
codec_input.frame_rate + 999) / 1000 + 999) / 1000;
codec_output->collocated_rd_noc = large_bw_calculation_fp;
codec_output->collocated_wr_noc = codec_output->collocated_rd_noc;
codec_output->collocated_rd_ddr = codec_output->collocated_rd_noc;
codec_output->collocated_wr_ddr = codec_output->collocated_wr_noc;
codec_output->collocated_rd_wr_total_noc =
(u32)(codec_output->collocated_rd_noc + codec_output->collocated_wr_noc);
codec_output->collocated_rd_wr_total_ddr =
codec_output->collocated_rd_wr_total_noc;
/* accumulation */
codec_output->noc_bw_rd += codec_output->collocated_rd_noc;
codec_output->noc_bw_wr += codec_output->collocated_wr_noc;
codec_output->ddr_bw_rd += codec_output->collocated_rd_ddr;
codec_output->ddr_bw_wr += codec_output->collocated_wr_ddr;
large_bw_calculation_fp = 0;
large_bw_calculation_fp = ((codec_input.bitdepth == CODEC_BITDEPTH_8) ?
frame420_y_bw_linear_8bpp :
frame420_y_bw_no_ubwc_tile_10bpp) * reference_y_read_bw_factor;
large_bw_calculation_fp = (large_bw_calculation_fp *
kalama_en_readfactor[codec_input.hierachical_layer]);
large_bw_calculation_fp = (large_bw_calculation_fp +
dpb_compression_factor_y - 1) / dpb_compression_factor_y;
large_bw_calculation_fp = (large_bw_calculation_fp + 999) / 1000;
codec_output->dpb_rd_y_noc = large_bw_calculation_fp;
large_bw_calculation_fp = 0;
large_bw_calculation_fp = ((codec_input.bitdepth == CODEC_BITDEPTH_8) ?
frame420_y_bw_linear_8bpp :
frame420_y_bw_no_ubwc_tile_10bpp) * reference_crcb_read_bw_factor / 2;
large_bw_calculation_fp = large_bw_calculation_fp *
kalama_en_readfactor[codec_input.hierachical_layer];
large_bw_calculation_fp = (large_bw_calculation_fp +
dpb_compression_factor_cbcr - 1) / dpb_compression_factor_cbcr;
large_bw_calculation_fp = (large_bw_calculation_fp + 999) / 1000;
codec_output->dpb_rd_crcb_noc = large_bw_calculation_fp;
large_bw_calculation_fp = 0;
large_bw_calculation_fp = ((codec_input.bitdepth == CODEC_BITDEPTH_8) ?
frame420_y_bw_linear_8bpp : frame420_y_bw_no_ubwc_tile_10bpp) *
reconstructed_write_bw_factor_rd *
kalama_en_writefactor[codec_input.hierachical_layer] /
kalama_en_frame_num_parallel;
large_bw_calculation_fp = (large_bw_calculation_fp + 999) / 1000;
large_bw_calculation_fp = large_bw_calculation_fp *
(dpb_compression_factor_cbcr + dpb_compression_factor_y / 2);
large_bw_calculation_fp = (large_bw_calculation_fp +
dpb_compression_factor_y - 1) / dpb_compression_factor_y;
large_bw_calculation_fp = (large_bw_calculation_fp +
dpb_compression_factor_cbcr - 1) / dpb_compression_factor_cbcr;
codec_output->dpb_wr_noc = large_bw_calculation_fp;
/*
* Summary:
* by default (for both HFR and HSR cases) :
* -Any resolution and fps >= 120, enable layering.
* (120 -> 3, 240 -> 4, 480 -> 5)
* - (once we enable layering) : 50 per cent frames are Non - reference
* frames.recon write is disable by Venus firmware
* - Customer has ability to enable / disable layering.
* Hence, recon write savings would not be there if
* customer explicitly disables layer encoding.
*/
/*HFR Cases use alternating rec write if not PWC*/
if ((codec_input.frame_rate >= 120) && (codec_input.complexity_setting != 0))
codec_output->dpb_wr_noc = codec_output->dpb_wr_noc / 2;
/* for power cases with [B1] adaptive non-ref b frame */
/* power caes IbP non reference b */
if ((codec_input.hierachical_layer >= 1) &&
(codec_input.hierachical_layer <= 3) &&
(codec_input.complexity_setting != 0))
codec_output->dpb_wr_noc = codec_output->dpb_wr_noc / 2;
large_bw_calculation_fp = 0;
large_bw_calculation_fp = codec_output->dpb_wr_noc *
(reconstructed_write_bw_factor_rd - 100);
large_bw_calculation_fp = (large_bw_calculation_fp +
reconstructed_write_bw_factor_rd - 1) / reconstructed_write_bw_factor_rd;
codec_output->dpb_rdwr_duetooverlap_noc = large_bw_calculation_fp;
codec_output->dpb_rd_y_ddr = (en_llc_enable_ref_rd_y_overlap) ?
(codec_output->dpb_rd_y_noc * 100 + reference_y_read_bw_factor - 1) /
reference_y_read_bw_factor : codec_output->dpb_rd_y_noc;
codec_output->dpb_rd_crcb_ddr = (en_llc_enable_ref_rd_crcb) ?
(codec_output->dpb_rd_crcb_noc * 100 + reference_crcb_read_bw_factor - 1) /
reference_crcb_read_bw_factor : codec_output->dpb_rd_crcb_noc;
codec_output->dpb_rdwr_duetooverlap_ddr = (en_llc_enable_rec_wr_uncompleted) ?
0 : codec_output->dpb_rdwr_duetooverlap_noc;
codec_output->dpb_wr_ddr = (en_llc_enable_rec_wr_uncompleted) ?
0 : codec_output->dpb_wr_noc;
/* accumulation */
codec_output->noc_bw_rd += codec_output->dpb_rd_y_noc;
codec_output->noc_bw_rd += codec_output->dpb_rd_crcb_noc;
codec_output->noc_bw_rd += codec_output->dpb_rdwr_duetooverlap_noc;
codec_output->noc_bw_wr += codec_output->dpb_wr_noc;
codec_output->ddr_bw_rd += codec_output->dpb_rd_y_ddr;
codec_output->ddr_bw_rd += codec_output->dpb_rd_crcb_ddr;
codec_output->ddr_bw_rd += codec_output->dpb_rdwr_duetooverlap_ddr;
codec_output->ddr_bw_wr += codec_output->dpb_wr_ddr;
if (codec_input.bitdepth == CODEC_BITDEPTH_8) {
if (codec_input.ipb_yuvrgb == 0) { /* yuv */
large_bw_calculation_fp = ((frame420_y_bw_linear_8bpp) * 3 / 2);
codec_output->ipb_rd_total_noc = large_bw_calculation_fp;
if (codec_input.linear_ipb == 0) {
codec_output->ipb_rd_total_noc =
(large_bw_calculation_fp * 100 +
ipb_compression_factor - 1) / ipb_compression_factor;
}
} else { /* rgb */
large_bw_calculation_fp = frame420_y_bw_linear_8bpp;
codec_output->ipb_rd_total_noc = large_bw_calculation_fp;
if (codec_input.linear_ipb == 0) {
if (codec_input.complexity_setting == 0) /* pwc */
codec_output->ipb_rd_total_noc =
(large_bw_calculation_fp * 100 +
en_original_compression_factor_rgba_pwd_kalama
- 1) /
en_original_compression_factor_rgba_pwd_kalama;
else
codec_output->ipb_rd_total_noc =
(large_bw_calculation_fp * 100 +
en_original_compression_factor_rgba_avg_kalama - 1) /
en_original_compression_factor_rgba_avg_kalama;
}
}
} else {
if (codec_input.linear_ipb == 1) {
large_bw_calculation_fp = (frame420_y_bw_linear_10bpp) * 3 / 2;
codec_output->ipb_rd_total_noc = large_bw_calculation_fp;
} else {
large_bw_calculation_fp = (frame420_y_bw_no_ubwc_tile_10bpp *
300 / 2 + ipb_compression_factor - 1) / ipb_compression_factor;
codec_output->ipb_rd_total_noc = large_bw_calculation_fp;
}
}
if (en_rotation_90_270) {
if (codec_input.codec == CODEC_HEVC) {
if ((codec_input.bitdepth == CODEC_BITDEPTH_8) &&
(codec_input.ipb_yuvrgb == 0))
codec_output->ipb_rd_total_noc = codec_output->ipb_rd_total_noc
* 1;
else
codec_output->ipb_rd_total_noc = codec_output->ipb_rd_total_noc
* 3;
} else {
codec_output->ipb_rd_total_noc = codec_output->ipb_rd_total_noc * 2;
}
}
codec_output->ipb_rd_total_ddr = codec_output->ipb_rd_total_noc;
/* accumulation */
codec_output->noc_bw_rd += codec_output->ipb_rd_total_noc;
codec_output->ddr_bw_rd += codec_output->ipb_rd_total_ddr;
codec_output->bse_tlb_rd_noc =
((bse_tlb_byte_per_lcu * lcu_per_frame * codec_input.frame_rate + 999)
/ 1000 + 999) / 1000;
if (llc_enabled_bse_tlb) /* TODO should be common declaration */
codec_output->bse_tlb_rd_ddr = 0;
else
codec_output->bse_tlb_rd_ddr = codec_output->bse_tlb_rd_noc;
codec_output->bse_tlb_wr_noc = codec_output->bse_tlb_rd_noc;
if (llc_enabled_bse_tlb)
codec_output->bse_tlb_wr_ddr = 0;
else
codec_output->bse_tlb_wr_ddr = codec_output->bse_tlb_wr_noc;
/* accumulation */
codec_output->noc_bw_rd += codec_output->bse_tlb_rd_noc;
codec_output->ddr_bw_rd += codec_output->bse_tlb_rd_ddr;
codec_output->noc_bw_wr += codec_output->bse_tlb_wr_noc;
codec_output->ddr_bw_wr += codec_output->bse_tlb_wr_ddr;
codec_output->mmu_rd_ddr = 0;
codec_output->mmu_rd_noc = 0;
/* accumulation */
codec_output->noc_bw_rd += codec_output->mmu_rd_noc;
codec_output->ddr_bw_rd += codec_output->mmu_rd_ddr;
return 0;
}
int msm_vidc_calculate_bandwidth(struct api_calculation_input codec_input,
struct api_calculation_bw_output *codec_output)
{
int rc = 0;
if (codec_input.decoder_or_encoder == CODEC_DECODER) {
rc = calculate_bandwidth_decoder_iris3(codec_input, codec_output);
} else if (codec_input.decoder_or_encoder == CODEC_ENCODER) {
rc = calculate_bandwidth_encoder_iris3(codec_input, codec_output);
} else {
d_vpr_e("%s: invalid codec\n", codec_input.decoder_or_encoder);
return -EINVAL;
}
return rc;
}

557
qcom/opensource/video-driver/driver/variant/iris3/src/msm_vidc_clock_iris3.c ノーマルファイル
ファイルの表示

@@ -0,0 +1,557 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kalama_technology.h"
#include "msm_vidc_debug.h"
static u32 calculate_number_mbs_kalama(u32 width, u32 height, u32 lcu_size)
{
u32 mbs_width = (width % lcu_size) ?
(width / lcu_size + 1) : (width / lcu_size);
u32 mbs_height = (height % lcu_size) ?
(height / lcu_size + 1) : (height / lcu_size);
return mbs_width * mbs_height * (lcu_size / 16) * (lcu_size / 16);
}
static int initialize_encoder_complexity_table(void)
{
/* Beging Calculate Encoder GOP Complexity Table and HW Floor numbers */
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_Bb_ENTRY] = 70000;
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_P_ENTRY] = 10000;
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_Bb_ENTRY] * 150 +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_P_ENTRY] * 100);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] +
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_Bb_ENTRY] +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_P_ENTRY] - 1);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] /
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_Bb_ENTRY] +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_P_ENTRY]);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_Bb_ENTRY] = 30000;
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_P_ENTRY] = 10000;
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_Bb_ENTRY] * 150 +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_P_ENTRY] * 100);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] +
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_Bb_ENTRY] +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_P_ENTRY] - 1);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] /
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_Bb_ENTRY] +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_P_ENTRY]);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_Bb_ENTRY] = 10000;
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_P_ENTRY] = 10000;
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_Bb_ENTRY] * 150 +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_P_ENTRY] * 100);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_FACTORY_ENTRY] +
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_Bb_ENTRY] +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_P_ENTRY] - 1);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_FACTORY_ENTRY] /
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_Bb_ENTRY] +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_P_ENTRY]);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_Bb_ENTRY] = 0;
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_P_ENTRY] = 1;
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_Bb_ENTRY] * 150 +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_P_ENTRY] * 100);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_FACTORY_ENTRY] +
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_Bb_ENTRY] +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_P_ENTRY] - 1);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_FACTORY_ENTRY] /
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_Bb_ENTRY] +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_P_ENTRY]);
return 0;
}
u32 get_bitrate_entry(u32 pixle_count)
{
u32 bitrate_entry = 0;
if (pixle_count >= fp_pixel_count_bar1)
bitrate_entry = 1;
else if (pixle_count >= fp_pixel_count_bar2)
bitrate_entry = 2;
else if (pixle_count >= fp_pixel_count_bar3)
bitrate_entry = 3;
else if (pixle_count >= fp_pixel_count_bar4)
bitrate_entry = 4;
else if (pixle_count >= fp_pixel_count_bar5)
bitrate_entry = 5;
else if (pixle_count >= fp_pixel_count_bar6)
bitrate_entry = 6;
else if (pixle_count >= fp_pixel_count_bar7)
bitrate_entry = 7;
else if (pixle_count >= fp_pixel_count_bar8)
bitrate_entry = 8;
else if (pixle_count >= fp_pixel_count_bar9)
bitrate_entry = 9;
else
bitrate_entry = 9;
return bitrate_entry;
}
static int calculate_vsp_min_freq(struct api_calculation_input codec_input,
struct api_calculation_freq_output *codec_output)
{
/*
* VSP calculation
* different methodology from Lahaina
*/
u32 vsp_hw_min_frequency = 0;
/* UInt32 decoder_vsp_fw_overhead = 100 + 5; // amplified by 100x */
u32 fw_sw_vsp_offset = 1000 + 55; /* amplified by 1000x */
/*
* Ignore fw_sw_vsp_offset, as this is baked into the reference bitrate tables.
* As a consequence remove x1000 multipler as well.
*/
u32 codec = codec_input.codec;
/* UInt32 *bitratetable; */
u32 pixle_count = codec_input.frame_width *
codec_input.frame_height * codec_input.frame_rate;
u8 bitrate_entry = get_bitrate_entry(pixle_count); /* TODO EXTRACT */
input_bitrate_fp = ((u32)(codec_input.bitrate_mbps * 100 + 99)) / 100;
vsp_hw_min_frequency = frequency_table_kalama[0][1] * input_bitrate_fp * 1000;
/* 8KUHD60fps with B frame */
if ((pixle_count >= fp_pixel_count_bar0) &&
(codec_input.hierachical_layer != CODEC_GOP_IPP)) {
/*
* FORMULA: VSPfreq = NOMINAL * (InputBitrate / ReferenceBitrate);
* ReferenceBitrate = 0 for,
* - 1Stage TURBO, all Codecs.
* - 2Stage TURBO, H264 & H265.
*
* 8KUHD60fps with B frame
* - bitrate_entry = 0
* - Clock=NOMINAL for H264 & 2Stage H265. Because bitrate
* table entry for TURBO is 0.
*
* TODO : Reduce these conditions by removing the zero entries from Bitrate table.
*/
vsp_hw_min_frequency = frequency_table_kalama[0][1] *
input_bitrate_fp * 1000;
if (codec_input.codec == CODEC_AV1)
vsp_hw_min_frequency = frequency_table_kalama[0][0] *
input_bitrate_fp * 1000;
if ((codec_input.codec == CODEC_H264) ||
(codec_input.codec == CODEC_H264_CAVLC) ||
((codec_input.codec == CODEC_HEVC) &&
(codec_input.vsp_vpp_mode == CODEC_VSPVPP_MODE_1S))) {
vsp_hw_min_frequency =
DIV_ROUND_UP(frequency_table_kalama[0][1], fw_sw_vsp_offset);
} else if (((codec_input.codec == CODEC_HEVC) &&
(codec_input.vsp_vpp_mode == CODEC_VSPVPP_MODE_2S))
|| (codec_input.codec == CODEC_VP9)
|| (codec_input.codec == CODEC_AV1)) {
if (codec_input.vsp_vpp_mode == CODEC_VSPVPP_MODE_2S) {
vsp_hw_min_frequency = DIV_ROUND_UP(vsp_hw_min_frequency,
(bitrate_table_kalama_2stage_fp[codec][0] *
fw_sw_vsp_offset));
} else {
vsp_hw_min_frequency = DIV_ROUND_UP(vsp_hw_min_frequency,
(bitrate_table_kalama_1stage_fp[codec][0] *
fw_sw_vsp_offset));
}
}
} else {
vsp_hw_min_frequency = frequency_table_kalama[0][1] *
input_bitrate_fp * 1000;
if (codec_input.codec == CODEC_AV1 && bitrate_entry == 1)
vsp_hw_min_frequency = frequency_table_kalama[0][0] *
input_bitrate_fp * 1000;
if ((codec_input.codec == CODEC_H264_CAVLC) &&
(codec_input.entropy_coding_mode == CODEC_ENTROPY_CODING_CAVLC))
codec = CODEC_H264_CAVLC;
else if ((codec_input.codec == CODEC_H264) &&
(codec_input.entropy_coding_mode == CODEC_ENTROPY_CODING_CABAC))
codec = CODEC_H264;
if (codec_input.vsp_vpp_mode == CODEC_VSPVPP_MODE_2S)
vsp_hw_min_frequency = DIV_ROUND_UP(vsp_hw_min_frequency,
(bitrate_table_kalama_2stage_fp[codec][bitrate_entry]) *
fw_sw_vsp_offset);
else
vsp_hw_min_frequency = DIV_ROUND_UP(vsp_hw_min_frequency,
(bitrate_table_kalama_1stage_fp[codec][bitrate_entry]) *
fw_sw_vsp_offset);
}
codec_output->vsp_min_freq = vsp_hw_min_frequency;
return 0;
}
static u32 calculate_pipe_penalty(struct api_calculation_input codec_input)
{
u32 pipe_penalty_codec = 0;
u8 avid_commercial_content = 0;
u32 pixel_count = 0;
/* decoder */
if (codec_input.decoder_or_encoder == CODEC_DECODER) {
pipe_penalty_codec = pipe_penalty_kalama[0][0];
avid_commercial_content = codec_input.av1d_commer_tile_enable;
if (codec_input.codec == CODEC_AV1) {
pixel_count = codec_input.frame_width * codec_input.frame_height;
if (pixel_count <= 1920 * 1080)
pipe_penalty_codec =
pipe_penalty_kalama[avid_commercial_content + 1][0];
else if (pixel_count < 3840 * 2160)
pipe_penalty_codec =
(pipe_penalty_kalama[avid_commercial_content + 1][0] +
pipe_penalty_kalama[avid_commercial_content + 1][1]) / 2;
else if ((pixel_count == 3840 * 2160) ||
(pixel_count == 4096 * 2160) || (pixel_count == 4096 * 2304))
pipe_penalty_codec =
pipe_penalty_kalama[avid_commercial_content + 1][1];
else if (pixel_count < 7680 * 4320)
pipe_penalty_codec =
(pipe_penalty_kalama[avid_commercial_content + 1][1] +
pipe_penalty_kalama[avid_commercial_content + 1][2]) / 2;
else
pipe_penalty_codec =
pipe_penalty_kalama[avid_commercial_content + 1][2];
}
} else {
pipe_penalty_codec = 101;
}
return pipe_penalty_codec;
}
static int calculate_vpp_min_freq(struct api_calculation_input codec_input,
struct api_calculation_freq_output *codec_output)
{
u32 vpp_hw_min_frequency = 0;
u32 fmin = 0;
u32 tensilica_min_frequency = 0;
u32 decoder_vsp_fw_overhead = 100 + 5; /* amplified by 100x */
/* UInt32 fw_sw_vsp_offset = 1000 + 55; amplified by 1000x */
/* TODO from calculate_sw_vsp_min_freq */
u32 vsp_hw_min_frequency = codec_output->vsp_min_freq;
u32 pipe_penalty_codec = 0;
u32 fmin_fwoverhead105 = 0;
u32 fmin_measured_fwoverhead = 0;
u32 lpmode_uhd_cycle_permb = 0;
u32 hqmode1080p_cycle_permb = 0;
u32 encoder_vpp_target_clk_per_mb = 0;
codec_mbspersession_kalama =
calculate_number_mbs_kalama(codec_input.frame_width,
codec_input.frame_height, codec_input.lcu_size) *
codec_input.frame_rate;
/* Section 2. 0 VPP/VSP calculation */
if (codec_input.decoder_or_encoder == CODEC_DECODER) { /* decoder */
vpp_hw_min_frequency = ((decoder_vpp_target_clk_per_mb_kalama) *
(codec_mbspersession_kalama) + codec_input.pipe_num - 1) /
(codec_input.pipe_num);
vpp_hw_min_frequency = (vpp_hw_min_frequency + 99999) / 1000000;
if (codec_input.pipe_num > 1) {
pipe_penalty_codec = calculate_pipe_penalty(codec_input);
vpp_hw_min_frequency = (vpp_hw_min_frequency *
pipe_penalty_codec + 999) / 1000;
}
if (codec_input.vsp_vpp_mode == CODEC_VSPVPP_MODE_2S) {
/* FW overhead, convert FW cycles to impact to one pipe */
u64 decoder_vpp_fw_overhead = 0;
decoder_vpp_fw_overhead =
DIV_ROUND_UP((DECODER_VPP_FW_OVERHEAD_KALAMA * 10 *
codec_input.frame_rate), 15);
decoder_vpp_fw_overhead =
DIV_ROUND_UP((decoder_vpp_fw_overhead * 1000),
(codec_mbspersession_kalama *
decoder_vpp_target_clk_per_mb_kalama / codec_input.pipe_num));
decoder_vpp_fw_overhead += 1000;
decoder_vpp_fw_overhead = (decoder_vpp_fw_overhead < 1050) ?
1050 : decoder_vpp_fw_overhead;
/* VPP HW + FW */
if (codec_input.linear_opb == 1 &&
codec_input.bitdepth == CODEC_BITDEPTH_10)
/* multiply by 1.20 for 10b case */
decoder_vpp_fw_overhead = 1200 + decoder_vpp_fw_overhead - 1000;
vpp_hw_min_frequency = (vpp_hw_min_frequency *
decoder_vpp_fw_overhead + 999) / 1000;
/* VSP HW+FW */
vsp_hw_min_frequency =
(vsp_hw_min_frequency * decoder_vsp_fw_overhead + 99) / 100;
fmin = (vpp_hw_min_frequency > vsp_hw_min_frequency) ?
vpp_hw_min_frequency : vsp_hw_min_frequency;
} else {
/* 1-stage need SW cycles + FW cycles + HW time */
if (codec_input.linear_opb == 1 &&
codec_input.bitdepth == CODEC_BITDEPTH_10)
/* multiply by 1.20 for 10b linear case */
vpp_hw_min_frequency =
(vpp_hw_min_frequency * 1200 + 999) / 1000;
/*
* HW time
* comment: 02/23/2021 SY: the bitrate is measured bitrate,
* the overlapping effect is already considered into bitrate.
* no need to add extra anymore
*/
fmin = (vpp_hw_min_frequency > vsp_hw_min_frequency) ?
vpp_hw_min_frequency : vsp_hw_min_frequency;
/* FW time */
fmin_fwoverhead105 = (fmin * 105 + 99) / 100;
fmin_measured_fwoverhead = fmin +
(((DECODER_VPPVSP1STAGE_FW_OVERHEAD_KALAMA *
codec_input.frame_rate * 10 + 14) / 15 + 999) / 1000 + 999) /
1000;
fmin = (fmin_fwoverhead105 > fmin_measured_fwoverhead) ?
fmin_fwoverhead105 : fmin_measured_fwoverhead;
}
tensilica_min_frequency = (DECODER_SW_OVERHEAD_KALAMA * 10 + 14) / 15;
tensilica_min_frequency = (tensilica_min_frequency + 999) / 1000;
tensilica_min_frequency = tensilica_min_frequency * codec_input.frame_rate;
tensilica_min_frequency = (tensilica_min_frequency + 999) / 1000;
fmin = (tensilica_min_frequency > fmin) ? tensilica_min_frequency : fmin;
} else { /* encoder */
/* Decide LP/HQ */
u8 hq_mode = 0;
if (codec_input.pipe_num > 1)
if (codec_input.frame_width * codec_input.frame_height <=
1920 * 1080)
if (codec_input.frame_width * codec_input.frame_height *
codec_input.frame_rate <= 1920 * 1080 * 60)
hq_mode = 1;
codec_output->enc_hqmode = hq_mode;
/* Section 1. 0 */
/* TODO ONETIME call, should be in another place. */
initialize_encoder_complexity_table();
/* End Calculate Encoder GOP Complexity Table */
/* VPP base cycle */
lpmode_uhd_cycle_permb = (320 *
codec_encoder_gop_complexity_table_fp
[codec_input.hierachical_layer][CODEC_ENCODER_GOP_FACTORY_ENTRY]
+ 99) / 100;
if ((codec_input.frame_width == 1920) &&
((codec_input.frame_height == 1080) ||
(codec_input.frame_height == 1088)) &&
(codec_input.frame_rate >= 480))
lpmode_uhd_cycle_permb = (90 * 4 *
codec_encoder_gop_complexity_table_fp
[codec_input.hierachical_layer][CODEC_ENCODER_GOP_FACTORY_ENTRY]
+ 99) / 100;
if ((codec_input.frame_width == 1280) &&
((codec_input.frame_height == 720) ||
(codec_input.frame_height == 768)) &&
(codec_input.frame_rate >= 960))
lpmode_uhd_cycle_permb = (99 * 4 *
codec_encoder_gop_complexity_table_fp
[codec_input.hierachical_layer][CODEC_ENCODER_GOP_FACTORY_ENTRY]
+ 99) / 100;
hqmode1080p_cycle_permb = (675 *
codec_encoder_gop_complexity_table_fp
[codec_input.hierachical_layer][CODEC_ENCODER_GOP_FACTORY_ENTRY]
+ 99) / 100;
encoder_vpp_target_clk_per_mb = (hq_mode) ?
hqmode1080p_cycle_permb : lpmode_uhd_cycle_permb;
vpp_hw_min_frequency = ((encoder_vpp_target_clk_per_mb) *
(codec_mbspersession_kalama) + codec_input.pipe_num - 1) /
(codec_input.pipe_num);
vpp_hw_min_frequency = (vpp_hw_min_frequency + 99999) / 1000000;
if (codec_input.pipe_num > 1) {
u32 pipe_penalty_codec = 101;
vpp_hw_min_frequency = (vpp_hw_min_frequency *
pipe_penalty_codec + 99) / 100;
}
if (codec_input.vsp_vpp_mode == CODEC_VSPVPP_MODE_2S) {
/* FW overhead, convert FW cycles to impact to one pipe */
u64 encoder_vpp_fw_overhead = 0;
encoder_vpp_fw_overhead =
DIV_ROUND_UP((ENCODER_VPP_FW_OVERHEAD_KALAMA * 10 *
codec_input.frame_rate), 15);
encoder_vpp_fw_overhead =
DIV_ROUND_UP((encoder_vpp_fw_overhead * 1000),
(codec_mbspersession_kalama * encoder_vpp_target_clk_per_mb /
codec_input.pipe_num));
encoder_vpp_fw_overhead += 1000;
encoder_vpp_fw_overhead = (encoder_vpp_fw_overhead < 1050) ?
1050 : encoder_vpp_fw_overhead;
/* VPP HW + FW */
vpp_hw_min_frequency = (vpp_hw_min_frequency *
encoder_vpp_fw_overhead + 999) / 1000;
/* TODO : decoder_vsp_fw_overhead? */
vsp_hw_min_frequency = (vsp_hw_min_frequency *
decoder_vsp_fw_overhead + 99) / 100;
fmin = (vpp_hw_min_frequency > vsp_hw_min_frequency) ?
vpp_hw_min_frequency : vsp_hw_min_frequency;
} else {
/* HW time */
fmin = (vpp_hw_min_frequency > vsp_hw_min_frequency) ?
vpp_hw_min_frequency : vsp_hw_min_frequency;
/* FW time */
fmin_fwoverhead105 = (fmin * 105 + 99) / 100;
fmin_measured_fwoverhead = fmin +
(((DECODER_VPPVSP1STAGE_FW_OVERHEAD_KALAMA *
codec_input.frame_rate * 10 + 14) / 15 + 999) /
1000 + 999) / 1000;
fmin = (fmin_fwoverhead105 > fmin_measured_fwoverhead) ?
fmin_fwoverhead105 : fmin_measured_fwoverhead;
/* SW time */
}
tensilica_min_frequency = (ENCODER_SW_OVERHEAD_KALAMA * 10 + 14) / 15;
tensilica_min_frequency = (tensilica_min_frequency + 999) / 1000;
tensilica_min_frequency = tensilica_min_frequency *
codec_input.frame_rate;
tensilica_min_frequency = (tensilica_min_frequency + 999) / 1000;
fmin = (tensilica_min_frequency > fmin) ?
tensilica_min_frequency : fmin;
}
codec_output->vpp_min_freq = vpp_hw_min_frequency;
codec_output->vsp_min_freq = vsp_hw_min_frequency;
codec_output->tensilica_min_freq = tensilica_min_frequency;
codec_output->hw_min_freq = fmin;
return 0;
}
int msm_vidc_calculate_frequency(struct api_calculation_input codec_input,
struct api_calculation_freq_output *codec_output)
{
int rc = 0;
rc = calculate_vsp_min_freq(codec_input, codec_output);
if (rc)
return rc;
rc = calculate_vpp_min_freq(codec_input, codec_output);
if (rc)
return rc;
return rc;
}

1038
qcom/opensource/video-driver/driver/variant/iris3/src/msm_vidc_iris3.c ノーマルファイル
ファイルの表示

ファイル差分が大きすぎるため省略します 差分を読み込み

1160
qcom/opensource/video-driver/driver/variant/iris3/src/msm_vidc_power_iris3.c ノーマルファイル
ファイルの表示

ファイル差分が大きすぎるため省略します 差分を読み込み

1819
qcom/opensource/video-driver/driver/variant/iris33/inc/hfi_buffer_iris33.h ノーマルファイル
ファイルの表示

ファイル差分が大きすぎるため省略します 差分を読み込み

19
qcom/opensource/video-driver/driver/variant/iris33/inc/msm_vidc_buffer_iris33.h ノーマルファイル
ファイルの表示

@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __H_MSM_VIDC_BUFFER_IRIS3_3_H__
#define __H_MSM_VIDC_BUFFER_IRIS3_3_H__
#include "msm_vidc_inst.h"
int msm_buffer_size_iris33(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type);
int msm_buffer_min_count_iris33(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type);
int msm_buffer_extra_count_iris33(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type);
#endif // __H_MSM_VIDC_BUFFER_IRIS3_3_H__

27
qcom/opensource/video-driver/driver/variant/iris33/inc/msm_vidc_iris33.h ノーマルファイル
ファイルの表示

@@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _MSM_VIDC_IRIS3_3_H_
#define _MSM_VIDC_IRIS3_3_H_
#include "msm_vidc_core.h"
#if defined(CONFIG_MSM_VIDC_PINEAPPLE)
int msm_vidc_init_iris33(struct msm_vidc_core *core);
int msm_vidc_adjust_bitrate_boost_iris33(void *instance, struct v4l2_ctrl *ctrl);
#else
static inline int msm_vidc_init_iris33(struct msm_vidc_core *core)
{
return -EINVAL;
}
static inline int msm_vidc_adjust_bitrate_boost_iris33(void *instance, struct v4l2_ctrl *ctrl)
{
return -EINVAL;
}
#endif
#endif // _MSM_VIDC_IRIS3_3_H_

20
qcom/opensource/video-driver/driver/variant/iris33/inc/msm_vidc_power_iris33.h ノーマルファイル
ファイルの表示

@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __H_MSM_VIDC_POWER_IRIS3_3_H__
#define __H_MSM_VIDC_POWER_IRIS3_3_H__
#include "msm_vidc_inst.h"
#include "msm_vidc_power.h"
#define ENABLE_LEGACY_POWER_CALCULATIONS 0
int msm_vidc_ring_buf_count_iris33(struct msm_vidc_inst *inst, u32 data_size);
u64 msm_vidc_calc_freq_iris33(struct msm_vidc_inst *inst, u32 data_size);
int msm_vidc_calc_bw_iris33(struct msm_vidc_inst *inst,
struct vidc_bus_vote_data *vote_data);
#endif

743
qcom/opensource/video-driver/driver/variant/iris33/src/msm_vidc_buffer_iris33.c ノーマルファイル
ファイルの表示

@@ -0,0 +1,743 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "msm_vidc_buffer_iris33.h"
#include "msm_vidc_buffer.h"
#include "msm_vidc_inst.h"
#include "msm_vidc_core.h"
#include "msm_vidc_driver.h"
#include "msm_vidc_debug.h"
#include "msm_media_info.h"
#include "msm_vidc_platform.h"
#include "hfi_property.h"
#include "hfi_buffer_iris33.h"
static u32 msm_vidc_decoder_bin_size_iris33(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
u32 size = 0;
u32 width, height, num_vpp_pipes;
struct v4l2_format *f;
bool is_interlaced;
u32 vpp_delay;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
if (inst->decode_vpp_delay.enable)
vpp_delay = inst->decode_vpp_delay.size;
else
vpp_delay = DEFAULT_BSE_VPP_DELAY;
if (inst->capabilities[CODED_FRAMES].value ==
CODED_FRAMES_PROGRESSIVE)
is_interlaced = false;
else
is_interlaced = true;
f = &inst->fmts[INPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_BIN_H264D(size, width, height,
is_interlaced, vpp_delay, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_BIN_H265D(size, width, height,
0, vpp_delay, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_VP9)
HFI_BUFFER_BIN_VP9D(size, width, height,
0, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_AV1)
HFI_BUFFER_BIN_AV1D(size, width, height, is_interlaced,
0, num_vpp_pipes);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_comv_size_iris33(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 width, height, num_comv, vpp_delay;
struct v4l2_format *f;
f = &inst->fmts[INPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (inst->codec == MSM_VIDC_AV1) {
/*
* AV1 requires larger COMV buffer size to meet performance
* for certain use cases. Increase the COMV buffer size by
* increasing COMV bufcount. Use lower count for 8k to
* achieve performance but save memory.
*/
if (res_is_greater_than(width, height, 4096, 2176))
num_comv = inst->fw_min_count ?
inst->fw_min_count + 3 : inst->buffers.output.min_count + 3;
else
num_comv = inst->fw_min_count ?
inst->fw_min_count + 7 : inst->buffers.output.min_count + 7;
} else {
num_comv = inst->buffers.output.min_count;
}
msm_vidc_update_cap_value(inst, NUM_COMV, num_comv, __func__);
if (inst->codec == MSM_VIDC_HEIC
&& is_thumbnail_session(inst)) {
vpp_delay = 0;
} else {
if (inst->decode_vpp_delay.enable)
vpp_delay = inst->decode_vpp_delay.size;
else
vpp_delay = DEFAULT_BSE_VPP_DELAY;
}
num_comv = max(vpp_delay + 1, num_comv);
if (inst->codec == MSM_VIDC_H264) {
HFI_BUFFER_COMV_H264D(size, width, height, num_comv);
} else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC) {
HFI_BUFFER_COMV_H265D(size, width, height, num_comv);
} else if (inst->codec == MSM_VIDC_AV1) {
/*
* When DRAP is enabled, COMV buffer is part of PERSIST buffer and
* should not be allocated separately.
* When DRAP is disabled, COMV buffer must be allocated.
*/
if (inst->capabilities[DRAP].value)
size = 0;
else
HFI_BUFFER_COMV_AV1D(size, width, height, num_comv);
}
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_non_comv_size_iris33(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 width, height, num_vpp_pipes;
struct msm_vidc_core *core;
struct v4l2_format *f;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
f = &inst->fmts[INPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_NON_COMV_H264D(size, width, height, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_NON_COMV_H265D(size, width, height, num_vpp_pipes);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_line_size_iris33(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
u32 size = 0;
u32 width, height, out_min_count, num_vpp_pipes, vpp_delay;
struct v4l2_format *f;
bool is_opb;
u32 color_fmt;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
color_fmt = v4l2_colorformat_to_driver(inst,
inst->fmts[OUTPUT_PORT].fmt.pix_mp.pixelformat, __func__);
if (is_linear_colorformat(color_fmt))
is_opb = true;
else
is_opb = false;
/*
* assume worst case, since color format is unknown at this
* time.
*/
is_opb = true;
if (inst->decode_vpp_delay.enable)
vpp_delay = inst->decode_vpp_delay.size;
else
vpp_delay = DEFAULT_BSE_VPP_DELAY;
f = &inst->fmts[INPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
out_min_count = inst->buffers.output.min_count;
out_min_count = max(vpp_delay + 1, out_min_count);
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_LINE_H264D(size, width, height, is_opb,
num_vpp_pipes);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_LINE_H265D(size, width, height, is_opb,
num_vpp_pipes);
else if (inst->codec == MSM_VIDC_VP9)
HFI_BUFFER_LINE_VP9D(size, width, height, out_min_count,
is_opb, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_AV1)
HFI_BUFFER_LINE_AV1D(size, width, height, is_opb,
num_vpp_pipes);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_partial_data_size_iris33(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 width, height;
struct v4l2_format *f;
f = &inst->fmts[INPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (inst->codec == MSM_VIDC_AV1)
HFI_BUFFER_IBC_AV1D(size, width, height);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_persist_size_iris33(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 rpu_enabled = 0;
if (inst->capabilities[META_DOLBY_RPU].value)
rpu_enabled = 1;
if (inst->codec == MSM_VIDC_H264) {
HFI_BUFFER_PERSIST_H264D(size, rpu_enabled);
} else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC) {
HFI_BUFFER_PERSIST_H265D(size, rpu_enabled);
} else if (inst->codec == MSM_VIDC_VP9) {
HFI_BUFFER_PERSIST_VP9D(size);
} else if (inst->codec == MSM_VIDC_AV1) {
/*
* When DRAP is enabled, COMV buffer is part of PERSIST buffer and
* should not be allocated separately. PERSIST buffer should include
* COMV buffer calculated with width, height, refcount.
* When DRAP is disabled, COMV buffer should not be included in PERSIST
* buffer.
*/
if (inst->capabilities[DRAP].value)
HFI_BUFFER_PERSIST_AV1D(size,
inst->capabilities[FRAME_WIDTH].max,
inst->capabilities[FRAME_HEIGHT].max, 16);
else
HFI_BUFFER_PERSIST_AV1D(size, 0, 0, 0);
}
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_decoder_dpb_size_iris33(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 color_fmt;
u32 width, height;
u32 interlace = 0;
struct v4l2_format *f;
/*
* For legacy codecs (non-AV1), DPB is calculated only
* for linear formats. For AV1, DPB is needed for film-grain
* enabled bitstreams (UBWC & linear).
*/
color_fmt = inst->capabilities[PIX_FMTS].value;
if (!is_linear_colorformat(color_fmt)) {
if (inst->codec != MSM_VIDC_AV1)
return size;
if (inst->codec == MSM_VIDC_AV1 &&
!inst->capabilities[FILM_GRAIN].value)
return size;
}
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (inst->codec == MSM_VIDC_H264 &&
res_is_less_than_or_equal_to(width, height, 1920, 1088))
interlace = 1;
if (color_fmt == MSM_VIDC_FMT_NV12 ||
color_fmt == MSM_VIDC_FMT_NV12C) {
color_fmt = MSM_VIDC_FMT_NV12C;
HFI_NV12_UBWC_IL_CALC_BUF_SIZE_V2(size, width, height,
video_y_stride_bytes(color_fmt, width),
video_y_scanlines(color_fmt, height),
video_uv_stride_bytes(color_fmt, width),
video_uv_scanlines(color_fmt, height),
video_y_meta_stride(color_fmt, width),
video_y_meta_scanlines(color_fmt, height),
video_uv_meta_stride(color_fmt, width),
video_uv_meta_scanlines(color_fmt, height),
interlace);
} else if (color_fmt == MSM_VIDC_FMT_P010 ||
color_fmt == MSM_VIDC_FMT_TP10C) {
color_fmt = MSM_VIDC_FMT_TP10C;
HFI_YUV420_TP10_UBWC_CALC_BUF_SIZE(size,
video_y_stride_bytes(color_fmt, width),
video_y_scanlines(color_fmt, height),
video_uv_stride_bytes(color_fmt, width),
video_uv_scanlines(color_fmt, height),
video_y_meta_stride(color_fmt, width),
video_y_meta_scanlines(color_fmt, height),
video_uv_meta_stride(color_fmt, width),
video_uv_meta_scanlines(color_fmt, height));
}
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
/* encoder internal buffers */
static u32 msm_vidc_encoder_bin_size_iris33(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
u32 size = 0;
u32 width, height, num_vpp_pipes, stage, profile, ring_buf_count;
struct v4l2_format *f;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
stage = inst->capabilities[STAGE].value;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
profile = inst->capabilities[PROFILE].value;
ring_buf_count = inst->capabilities[ENC_RING_BUFFER_COUNT].value;
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_BIN_H264E(size, inst->hfi_rc_type, width,
height, stage, num_vpp_pipes, profile, ring_buf_count);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_BIN_H265E(size, inst->hfi_rc_type, width,
height, stage, num_vpp_pipes, profile, ring_buf_count);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_get_recon_buf_count(struct msm_vidc_inst *inst)
{
u32 num_buf_recon = 0;
s32 n_bframe, ltr_count, hp_layers = 0, hb_layers = 0;
bool is_hybrid_hp = false;
u32 hfi_codec = 0;
n_bframe = inst->capabilities[B_FRAME].value;
ltr_count = inst->capabilities[LTR_COUNT].value;
if (inst->hfi_layer_type == HFI_HIER_B) {
hb_layers = inst->capabilities[ENH_LAYER_COUNT].value + 1;
} else {
hp_layers = inst->capabilities[ENH_LAYER_COUNT].value + 1;
if (inst->hfi_layer_type == HFI_HIER_P_HYBRID_LTR)
is_hybrid_hp = true;
}
if (inst->codec == MSM_VIDC_H264)
hfi_codec = HFI_CODEC_ENCODE_AVC;
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
hfi_codec = HFI_CODEC_ENCODE_HEVC;
HFI_IRIS3_ENC_RECON_BUF_COUNT(num_buf_recon, n_bframe, ltr_count,
hp_layers, hb_layers, is_hybrid_hp, hfi_codec);
return num_buf_recon;
}
static u32 msm_vidc_encoder_comv_size_iris33(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 width, height, num_recon = 0;
struct v4l2_format *f;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
num_recon = msm_vidc_get_recon_buf_count(inst);
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_COMV_H264E(size, width, height, num_recon);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_COMV_H265E(size, width, height, num_recon);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_non_comv_size_iris33(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
u32 size = 0;
u32 width, height, num_vpp_pipes;
struct v4l2_format *f;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_NON_COMV_H264E(size, width, height, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_NON_COMV_H265E(size, width, height, num_vpp_pipes);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_line_size_iris33(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
u32 size = 0;
u32 width, height, pixfmt, num_vpp_pipes;
bool is_tenbit = false;
struct v4l2_format *f;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
pixfmt = inst->capabilities[PIX_FMTS].value;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
is_tenbit = (pixfmt == MSM_VIDC_FMT_P010 || pixfmt == MSM_VIDC_FMT_TP10C);
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_LINE_H264E(size, width, height, is_tenbit, num_vpp_pipes);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_LINE_H265E(size, width, height, is_tenbit, num_vpp_pipes);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_dpb_size_iris33(struct msm_vidc_inst *inst)
{
u32 size = 0;
u32 width, height, pixfmt;
struct v4l2_format *f;
bool is_tenbit;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
pixfmt = inst->capabilities[PIX_FMTS].value;
is_tenbit = (pixfmt == MSM_VIDC_FMT_P010 || pixfmt == MSM_VIDC_FMT_TP10C);
if (inst->codec == MSM_VIDC_H264)
HFI_BUFFER_DPB_H264E(size, width, height);
else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
HFI_BUFFER_DPB_H265E(size, width, height, is_tenbit);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_arp_size_iris33(struct msm_vidc_inst *inst)
{
u32 size = 0;
HFI_BUFFER_ARP_ENC(size);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_vpss_size_iris33(struct msm_vidc_inst *inst)
{
u32 size = 0;
bool ds_enable = false, is_tenbit = false, blur = false;
u32 rotation_val = HFI_ROTATION_NONE;
u32 width, height, driver_colorfmt;
struct v4l2_format *f;
ds_enable = is_scaling_enabled(inst);
msm_vidc_v4l2_to_hfi_enum(inst, ROTATION, &rotation_val);
f = &inst->fmts[OUTPUT_PORT];
if (is_rotation_90_or_270(inst)) {
/*
* output width and height are rotated,
* so unrotate them to use as arguments to
* HFI_BUFFER_VPSS_ENC.
*/
width = f->fmt.pix_mp.height;
height = f->fmt.pix_mp.width;
} else {
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
}
f = &inst->fmts[INPUT_PORT];
driver_colorfmt = v4l2_colorformat_to_driver(inst,
f->fmt.pix_mp.pixelformat, __func__);
is_tenbit = is_10bit_colorformat(driver_colorfmt);
if (inst->capabilities[BLUR_TYPES].value != MSM_VIDC_BLUR_NONE)
blur = true;
HFI_BUFFER_VPSS_ENC(size, width, height, ds_enable, blur, is_tenbit);
i_vpr_l(inst, "%s: size %d\n", __func__, size);
return size;
}
static u32 msm_vidc_encoder_output_size_iris33(struct msm_vidc_inst *inst)
{
u32 frame_size;
struct v4l2_format *f;
bool is_ten_bit = false;
int bitrate_mode, frame_rc;
u32 hfi_rc_type = HFI_RC_VBR_CFR;
enum msm_vidc_codec_type codec;
f = &inst->fmts[OUTPUT_PORT];
codec = v4l2_codec_to_driver(inst, f->fmt.pix_mp.pixelformat, __func__);
if (codec == MSM_VIDC_HEVC || codec == MSM_VIDC_HEIC)
is_ten_bit = true;
bitrate_mode = inst->capabilities[BITRATE_MODE].value;
frame_rc = inst->capabilities[FRAME_RC_ENABLE].value;
if (!frame_rc && !is_image_session(inst))
hfi_rc_type = HFI_RC_OFF;
else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ)
hfi_rc_type = HFI_RC_CQ;
HFI_BUFFER_BITSTREAM_ENC(frame_size, f->fmt.pix_mp.width,
f->fmt.pix_mp.height, hfi_rc_type, is_ten_bit);
frame_size = msm_vidc_enc_delivery_mode_based_output_buf_size(inst, frame_size);
return frame_size;
}
struct msm_vidc_buf_type_handle {
enum msm_vidc_buffer_type type;
u32 (*handle)(struct msm_vidc_inst *inst);
};
int msm_buffer_size_iris33(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type)
{
int i;
u32 size = 0, buf_type_handle_size = 0;
const struct msm_vidc_buf_type_handle *buf_type_handle_arr = NULL;
static const struct msm_vidc_buf_type_handle dec_buf_type_handle[] = {
{MSM_VIDC_BUF_INPUT, msm_vidc_decoder_input_size },
{MSM_VIDC_BUF_OUTPUT, msm_vidc_decoder_output_size },
{MSM_VIDC_BUF_INPUT_META, msm_vidc_decoder_input_meta_size },
{MSM_VIDC_BUF_OUTPUT_META, msm_vidc_decoder_output_meta_size },
{MSM_VIDC_BUF_BIN, msm_vidc_decoder_bin_size_iris33 },
{MSM_VIDC_BUF_COMV, msm_vidc_decoder_comv_size_iris33 },
{MSM_VIDC_BUF_NON_COMV, msm_vidc_decoder_non_comv_size_iris33 },
{MSM_VIDC_BUF_LINE, msm_vidc_decoder_line_size_iris33 },
{MSM_VIDC_BUF_PERSIST, msm_vidc_decoder_persist_size_iris33 },
{MSM_VIDC_BUF_DPB, msm_vidc_decoder_dpb_size_iris33 },
{MSM_VIDC_BUF_PARTIAL_DATA, msm_vidc_decoder_partial_data_size_iris33 },
};
static const struct msm_vidc_buf_type_handle enc_buf_type_handle[] = {
{MSM_VIDC_BUF_INPUT, msm_vidc_encoder_input_size },
{MSM_VIDC_BUF_OUTPUT, msm_vidc_encoder_output_size_iris33 },
{MSM_VIDC_BUF_INPUT_META, msm_vidc_encoder_input_meta_size },
{MSM_VIDC_BUF_OUTPUT_META, msm_vidc_encoder_output_meta_size },
{MSM_VIDC_BUF_BIN, msm_vidc_encoder_bin_size_iris33 },
{MSM_VIDC_BUF_COMV, msm_vidc_encoder_comv_size_iris33 },
{MSM_VIDC_BUF_NON_COMV, msm_vidc_encoder_non_comv_size_iris33 },
{MSM_VIDC_BUF_LINE, msm_vidc_encoder_line_size_iris33 },
{MSM_VIDC_BUF_DPB, msm_vidc_encoder_dpb_size_iris33 },
{MSM_VIDC_BUF_ARP, msm_vidc_encoder_arp_size_iris33 },
{MSM_VIDC_BUF_VPSS, msm_vidc_encoder_vpss_size_iris33 },
};
if (is_decode_session(inst)) {
buf_type_handle_size = ARRAY_SIZE(dec_buf_type_handle);
buf_type_handle_arr = dec_buf_type_handle;
} else if (is_encode_session(inst)) {
buf_type_handle_size = ARRAY_SIZE(enc_buf_type_handle);
buf_type_handle_arr = enc_buf_type_handle;
}
/* handle invalid session */
if (!buf_type_handle_arr || !buf_type_handle_size) {
i_vpr_e(inst, "%s: invalid session %d\n", __func__, inst->domain);
return size;
}
/* fetch buffer size */
for (i = 0; i < buf_type_handle_size; i++) {
if (buf_type_handle_arr[i].type == buffer_type) {
size = buf_type_handle_arr[i].handle(inst);
break;
}
}
/* handle unknown buffer type */
if (i == buf_type_handle_size) {
i_vpr_e(inst, "%s: unknown buffer type %#x\n", __func__, buffer_type);
goto exit;
}
i_vpr_l(inst, "buffer_size: type: %11s, size: %9u\n", buf_name(buffer_type), size);
exit:
return size;
}
static int msm_vidc_input_min_count_iris33(struct msm_vidc_inst *inst)
{
u32 input_min_count = 0;
u32 total_hb_layer = 0;
if (is_decode_session(inst)) {
input_min_count = MIN_DEC_INPUT_BUFFERS;
} else if (is_encode_session(inst)) {
total_hb_layer = is_hierb_type_requested(inst) ?
inst->capabilities[ENH_LAYER_COUNT].value + 1 : 0;
if (inst->codec == MSM_VIDC_H264 &&
!inst->capabilities[LAYER_ENABLE].value) {
total_hb_layer = 0;
}
HFI_IRIS3_ENC_MIN_INPUT_BUF_COUNT(input_min_count,
total_hb_layer);
} else {
i_vpr_e(inst, "%s: invalid domain %d\n", __func__, inst->domain);
return 0;
}
if (is_thumbnail_session(inst) || is_image_session(inst))
input_min_count = 1;
return input_min_count;
}
static int msm_buffer_dpb_count(struct msm_vidc_inst *inst)
{
int count = 0;
/* encoder dpb buffer count */
if (is_encode_session(inst))
return msm_vidc_get_recon_buf_count(inst);
/* decoder dpb buffer count */
if (is_split_mode_enabled(inst)) {
count = inst->fw_min_count ?
inst->fw_min_count : inst->buffers.output.min_count;
}
return count;
}
static int msm_buffer_delivery_mode_based_min_count_iris33(struct msm_vidc_inst *inst,
uint32_t count)
{
struct v4l2_format *f;
struct msm_vidc_core *core = NULL;
u32 width, height, total_num_slices = 1;
u32 hfi_codec = 0;
u32 max_mbs_per_slice = 0;
u32 slice_mode = 0;
u32 delivery_mode = 0;
u32 num_vpp_pipes;
slice_mode = inst->capabilities[SLICE_MODE].value;
delivery_mode = inst->capabilities[DELIVERY_MODE].value;
if (slice_mode != V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB ||
(!delivery_mode))
return count;
f = &inst->fmts[OUTPUT_PORT];
width = f->fmt.pix_mp.width;
height = f->fmt.pix_mp.height;
max_mbs_per_slice = inst->capabilities[SLICE_MAX_MB].value;
if (inst->codec == MSM_VIDC_H264)
hfi_codec = HFI_CODEC_ENCODE_AVC;
else if (inst->codec == MSM_VIDC_HEVC)
hfi_codec = HFI_CODEC_ENCODE_HEVC;
core = inst->core;
num_vpp_pipes = core->capabilities[NUM_VPP_PIPE].value;
HFI_IRIS3_ENC_MB_BASED_MULTI_SLICE_COUNT(total_num_slices, width, height,
hfi_codec, max_mbs_per_slice, num_vpp_pipes);
return (total_num_slices * count);
}
int msm_buffer_min_count_iris33(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type)
{
int count = 0;
switch (buffer_type) {
case MSM_VIDC_BUF_INPUT:
case MSM_VIDC_BUF_INPUT_META:
count = msm_vidc_input_min_count_iris33(inst);
break;
case MSM_VIDC_BUF_OUTPUT:
case MSM_VIDC_BUF_OUTPUT_META:
count = msm_vidc_output_min_count(inst);
count = msm_buffer_delivery_mode_based_min_count_iris33(inst, count);
break;
case MSM_VIDC_BUF_BIN:
case MSM_VIDC_BUF_COMV:
case MSM_VIDC_BUF_NON_COMV:
case MSM_VIDC_BUF_LINE:
case MSM_VIDC_BUF_PERSIST:
case MSM_VIDC_BUF_ARP:
case MSM_VIDC_BUF_VPSS:
case MSM_VIDC_BUF_PARTIAL_DATA:
count = msm_vidc_internal_buffer_count(inst, buffer_type);
break;
case MSM_VIDC_BUF_DPB:
count = msm_buffer_dpb_count(inst);
break;
default:
break;
}
i_vpr_l(inst, " min_count: type: %11s, count: %9u\n", buf_name(buffer_type), count);
return count;
}
int msm_buffer_extra_count_iris33(struct msm_vidc_inst *inst,
enum msm_vidc_buffer_type buffer_type)
{
int count = 0;
switch (buffer_type) {
case MSM_VIDC_BUF_INPUT:
case MSM_VIDC_BUF_INPUT_META:
count = msm_vidc_input_extra_count(inst);
break;
case MSM_VIDC_BUF_OUTPUT:
case MSM_VIDC_BUF_OUTPUT_META:
count = msm_vidc_output_extra_count(inst);
break;
default:
break;
}
i_vpr_l(inst, "extra_count: type: %11s, count: %9u\n", buf_name(buffer_type), count);
return count;
}

1051
qcom/opensource/video-driver/driver/variant/iris33/src/msm_vidc_bus_iris33.c ノーマルファイル
ファイルの表示

ファイル差分が大きすぎるため省略します 差分を読み込み

726
qcom/opensource/video-driver/driver/variant/iris33/src/msm_vidc_clock_iris33.c ノーマルファイル
ファイルの表示

@@ -0,0 +1,726 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "perf_static_model.h"
#include "msm_vidc_debug.h"
#include "msm_vidc_platform.h"
#define ENABLE_FINEBITRATE_SUBUHD60 0
static u32 codec_encoder_gop_complexity_table_fp[8][3];
static u32 codec_mbspersession_iris33;
static u32 input_bitrate_fp;
/*
* Chipset Generation Technology: SW/FW overhead profiling
* need update with new numbers
*/
static u32 frequency_table_iris33[2][6] = {
/* //make lowsvs_D1 as invalid; */
{533, 480, 435, 380, 300, 196},
{840, 720, 652, 570, 450, 294},
};
static u32 frequency_table_iris33_2p[2][6] = {
/* //make lowsvs_D1 as invalid; */
{ 533, 444, 366, 338, 240, 192 },
{ 800, 666, 549, 507, 360, 288 },
};
/*
* TODO Move to pineapple.c
* TODO Replace hardcoded values with
* ENCODER_VPP_TARGET_CLK_PER_MB_IRIS33 in CPP file.
*/
/* Tensilica cycles profiled by FW team in lanai device Feb 2022 */
#define DECODER_VPP_FW_OVERHEAD_IRIS33_AV1D ((80000*3)/2)
#define DECODER_VPP_FW_OVERHEAD_IRIS33_NONAV1D ((60000*3)/2)
/* Tensilica cycles */
#define DECODER_VPP_FW_OVERHEAD_IRIS33 (0)
/* Tensilica cycles; this is measured in Lahaina 1stage with FW profiling */
#define DECODER_VPPVSP1STAGE_FW_OVERHEAD_IRIS33 (93000)
#define DECODER_VSP_FW_OVERHEAD_IRIS33 \
(DECODER_VPPVSP1STAGE_FW_OVERHEAD_IRIS33 - DECODER_VPP_FW_OVERHEAD_IRIS33)
/* Tensilica cycles; encoder has ARP register */
#define ENCODER_VPP_FW_OVERHEAD_IRIS33 (69000*3/2)
#define ENCODER_VPPVSP1STAGE_FW_OVERHEAD_IRIS33 \
(ENCODER_VPP_FW_OVERHEAD_IRIS33 + DECODER_VSP_FW_OVERHEAD_IRIS33)
#define DECODER_SW_OVERHEAD_IRIS33 (489583)
#define ENCODER_SW_OVERHEAD_IRIS33 (489583)
/* Video IP Core Technology: pipefloor and pipe penlaty */
// static u32 encoder_vpp_target_clk_per_mb_iris33[2] = {320, 675};
static u32 decoder_vpp_target_clk_per_mb_iris33 = 200;
/*
* These pipe penalty numbers only applies to 4 pipe
* For 2pipe and 1pipe, these numbers need recalibrate
*/
static u32 pipe_penalty_iris33[3][3] = {
/* NON AV1 */
{1059, 1059, 1059},
/* AV1 RECOMMENDED TILE 1080P_V2XH1, UHD_V2X2, 8KUHD_V8X2 */
{1410, 1248, 1226},
/* AV1 YOUTUBE/NETFLIX TILE 1080P_V4XH2_V4X1, UHD_V8X4_V8X1, 8KUHD_V8X8_V8X1 */
{2039, 2464, 1191},
};
static u32 pipe_penalty_iris33_2p[3][3] = {
/* NON AV1 */
{ 1059, 1059, 1059 },
/* AV1 RECOMMENDED TILE 1080P_V2XH1, UHD_V2X2, 8KUHD_V8X2 */
{ 1123, 1079, 1079 },
/* AV1 YOUTUBE/NETFLIX TILE 1080P_V4XH2_V4X1, UHD_V8X4_V8X1, 8KUHD_V8X8_V8X1 */
{ 1197, 1287, 1051 },
};
/*
* Video IP Core Technology: bitrate constraint
* HW limit bitrate table (these values are measured end to end fw/sw impacts are also considered)
* TODO Can we convert to Cycles/MB? This will remove DIVISION.
*/
static u32 bitrate_table_iris33_2stage_fp[5][10] = {
/* h264 cavlc */
{0, 220, 220, 220, 220, 220, 220, 220, 220, 220},
/* h264 cabac */
{0, 140, 150, 160, 175, 190, 190, 190, 190, 190},
/* h265 */
{90, 140, 160, 180, 190, 200, 200, 200, 200, 200},
/* vp9 */
{90, 90, 90, 90, 90, 90, 90, 90, 90, 90},
/* av1 */
{130, 130, 120, 120, 120, 120, 120, 120, 120, 120},
};
static u32 bitrate_table_iris33_2p_2stage_fp[5][10] = {
/* h264 cavlc */
{ 0, 220, 220, 220, 220, 220, 220, 220, 220, 220 },
/* h264 cabac */
{ 0, 140, 150, 160, 160, 160, 160, 160, 160, 160 },
/* h265 */
{ 90, 140, 160, 160, 160, 160, 160, 160, 160, 160 },
/*vp9 */
{ 90, 90, 90, 90, 90, 90, 90, 90, 90, 90 },
{ 130, 130, 120, 120, 120, 120, 120, 120, 120, 120 },
};
/*
* HW limit bitrate table (these values are measured
* end to end fw/sw impacts are also considered)
*/
static u32 bitrate_table_iris33_1stage_fp[5][10] = { /* 1-stage assume IPPP */
/* h264 cavlc */
{0, 220, 220, 220, 220, 220, 220, 220, 220, 220},
/* h264 cabac */
{0, 110, 150, 150, 150, 150, 150, 150, 150, 150},
/* h265 */
{0, 140, 150, 150, 150, 150, 150, 150, 150, 150},
/* vp9 */
{0, 70, 70, 70, 70, 70, 70, 70, 70, 70},
/* av1 */
{0, 100, 100, 100, 100, 100, 100, 100, 100, 100},
};
/* 8KUHD60; UHD240; 1080p960 with B */
static u32 fp_pixel_count_bar0 = 3840 * 2160 * 240;
/* 8KUHD60; UHD240; 1080p960 without B */
static u32 fp_pixel_count_bar1 = 3840 * 2160 * 240;
/* 1080p720 */
static u32 fp_pixel_count_bar2 = 3840 * 2160 * 180;
/* UHD120 */
static u32 fp_pixel_count_bar3 = 3840 * 2160 * 120;
/* UHD90 */
static u32 fp_pixel_count_bar4 = 3840 * 2160 * 90;
/* UHD60 */
static u32 fp_pixel_count_bar5 = 3840 * 2160 * 60;
/* UHD30; FHD120; HD240 */
static u32 fp_pixel_count_bar6 = 3840 * 2160 * 30;
/* FHD60 */
static u32 fp_pixel_count_bar7 = 1920 * 1080 * 60;
/* FHD30 */
static u32 fp_pixel_count_bar8 = 1920 * 1080 * 30;
/* HD30 */
static u32 fp_pixel_count_bar9 = 1280 * 720 * 30;
static u32 calculate_number_mbs_iris33(u32 width, u32 height, u32 lcu_size)
{
u32 mbs_width = (width % lcu_size) ?
(width / lcu_size + 1) : (width / lcu_size);
u32 mbs_height = (height % lcu_size) ?
(height / lcu_size + 1) : (height / lcu_size);
return mbs_width * mbs_height * (lcu_size / 16) * (lcu_size / 16);
}
static int initialize_encoder_complexity_table(void)
{
/* Beging Calculate Encoder GOP Complexity Table and HW Floor numbers */
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_Bb_ENTRY] = 70000;
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_P_ENTRY] = 10000;
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_Bb_ENTRY] * 150 +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_P_ENTRY] * 100);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] +
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_Bb_ENTRY] +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_P_ENTRY] - 1);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] /
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_Bb_ENTRY] +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I3B4b1P][CODEC_ENCODER_GOP_P_ENTRY]);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_Bb_ENTRY] = 30000;
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_P_ENTRY] = 10000;
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_Bb_ENTRY] * 150 +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_P_ENTRY] * 100);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] +
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_Bb_ENTRY] +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_P_ENTRY] - 1);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_FACTORY_ENTRY] /
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_Bb_ENTRY] +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_I1B2b1P][CODEC_ENCODER_GOP_P_ENTRY]);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_Bb_ENTRY] = 10000;
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_P_ENTRY] = 10000;
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_Bb_ENTRY] * 150 +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_P_ENTRY] * 100);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_FACTORY_ENTRY] +
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_Bb_ENTRY] +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_P_ENTRY] - 1);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_FACTORY_ENTRY] /
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_Bb_ENTRY] +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IbP][CODEC_ENCODER_GOP_P_ENTRY]);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_Bb_ENTRY] = 0;
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_P_ENTRY] = 1;
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_Bb_ENTRY] * 150 +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_P_ENTRY] * 100);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_FACTORY_ENTRY] +
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_Bb_ENTRY] +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_P_ENTRY] - 1);
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_FACTORY_ENTRY] =
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_FACTORY_ENTRY] /
(codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_Bb_ENTRY] +
codec_encoder_gop_complexity_table_fp
[CODEC_GOP_IPP][CODEC_ENCODER_GOP_P_ENTRY]);
return 0;
}
u32 get_bitrate_entry(u32 pixle_count)
{
u32 bitrate_entry = 0;
if (pixle_count >= fp_pixel_count_bar1)
bitrate_entry = 1;
else if (pixle_count >= fp_pixel_count_bar2)
bitrate_entry = 2;
else if (pixle_count >= fp_pixel_count_bar3)
bitrate_entry = 3;
else if (pixle_count >= fp_pixel_count_bar4)
bitrate_entry = 4;
else if (pixle_count >= fp_pixel_count_bar5)
bitrate_entry = 5;
else if (pixle_count >= fp_pixel_count_bar6)
bitrate_entry = 6;
else if (pixle_count >= fp_pixel_count_bar7)
bitrate_entry = 7;
else if (pixle_count >= fp_pixel_count_bar8)
bitrate_entry = 8;
else if (pixle_count >= fp_pixel_count_bar9)
bitrate_entry = 9;
else
bitrate_entry = 9;
return bitrate_entry;
}
static int calculate_vsp_min_freq(struct api_calculation_input codec_input,
struct api_calculation_freq_output *codec_output)
{
u32 (*frequency_table_value)[6];
u32 (*bitrate_table_2stage_value)[10];
/*
* VSP calculation
* different methodology from Lahaina
*/
u32 vsp_hw_min_frequency = 0;
/* UInt32 decoder_vsp_fw_overhead = 100 + 5; // amplified by 100x */
u32 fw_sw_vsp_offset = 1000 + 55; /* amplified by 1000x */
/*
* Ignore fw_sw_vsp_offset, as this is baked into the reference bitrate tables.
* As a consequence remove x1000 multipler as well.
*/
u32 codec = codec_input.codec;
/* UInt32 *bitratetable; */
u32 pixle_count = codec_input.frame_width *
codec_input.frame_height * codec_input.frame_rate;
u8 bitrate_entry = get_bitrate_entry(pixle_count); /* TODO EXTRACT */
input_bitrate_fp = ((u32)(codec_input.bitrate_mbps * 100 + 99)) / 100;
if (codec_input.vpu_ver == VPU_VERSION_IRIS33) {
frequency_table_value = frequency_table_iris33;
bitrate_table_2stage_value = bitrate_table_iris33_2stage_fp;
} else if (codec_input.vpu_ver == VPU_VERSION_IRIS33_2P) {
frequency_table_value = frequency_table_iris33_2p;
bitrate_table_2stage_value = bitrate_table_iris33_2p_2stage_fp;
}
/* 8KUHD60fps with B frame */
if ((pixle_count >= fp_pixel_count_bar0) &&
(codec_input.hierachical_layer != CODEC_GOP_IPP)) {
/*
* FORMULA: VSPfreq = NOMINAL * (InputBitrate / ReferenceBitrate);
* ReferenceBitrate = 0 for,
* - 1Stage TURBO, all Codecs.
* - 2Stage TURBO, H264 & H265.
*
* 8KUHD60fps with B frame
* - bitrate_entry = 0
* - Clock=NOMINAL for H264 & 2Stage H265. Because bitrate
* table entry for TURBO is 0.
*
* TODO : Reduce these conditions by removing the zero entries from Bitrate table.
*/
vsp_hw_min_frequency = frequency_table_value[0][2] *
input_bitrate_fp * 1000;
if (codec_input.codec == CODEC_AV1)
vsp_hw_min_frequency = frequency_table_value[0][1] *
input_bitrate_fp * 1000;
if ((codec_input.codec == CODEC_H264) ||
(codec_input.codec == CODEC_H264_CAVLC)) {
vsp_hw_min_frequency = (frequency_table_value[0][2] * 1000 +
(fw_sw_vsp_offset - 1));
vsp_hw_min_frequency =
DIV_ROUND_UP(vsp_hw_min_frequency, fw_sw_vsp_offset);
} else {
if (codec_input.vsp_vpp_mode == CODEC_VSPVPP_MODE_2S) {
vsp_hw_min_frequency = vsp_hw_min_frequency +
(bitrate_table_2stage_value[codec][0] *
fw_sw_vsp_offset - 1);
vsp_hw_min_frequency = DIV_ROUND_UP(vsp_hw_min_frequency,
(bitrate_table_2stage_value[codec][0]) *
fw_sw_vsp_offset);
} else {
vsp_hw_min_frequency = vsp_hw_min_frequency +
(bitrate_table_iris33_1stage_fp[codec][0] *
fw_sw_vsp_offset - 1);
vsp_hw_min_frequency = DIV_ROUND_UP(vsp_hw_min_frequency,
(bitrate_table_iris33_1stage_fp[codec][0]) *
fw_sw_vsp_offset);
}
}
} else {
vsp_hw_min_frequency = frequency_table_value[0][2] *
input_bitrate_fp * 1000;
if (codec_input.codec == CODEC_AV1 && bitrate_entry == 1)
vsp_hw_min_frequency = frequency_table_value[0][1] *
input_bitrate_fp * 1000;
if (codec_input.vsp_vpp_mode == CODEC_VSPVPP_MODE_2S) {
vsp_hw_min_frequency = vsp_hw_min_frequency +
(bitrate_table_2stage_value[codec][bitrate_entry] *
fw_sw_vsp_offset - 1);
vsp_hw_min_frequency = DIV_ROUND_UP(vsp_hw_min_frequency,
(bitrate_table_2stage_value[codec][bitrate_entry]) *
fw_sw_vsp_offset);
} else {
vsp_hw_min_frequency = vsp_hw_min_frequency +
(bitrate_table_iris33_1stage_fp[codec][bitrate_entry] *
fw_sw_vsp_offset - 1);
vsp_hw_min_frequency = DIV_ROUND_UP(vsp_hw_min_frequency,
(bitrate_table_iris33_1stage_fp[codec][bitrate_entry]) *
fw_sw_vsp_offset);
}
}
codec_output->vsp_min_freq = vsp_hw_min_frequency;
return 0;
}
static u32 calculate_pipe_penalty(struct api_calculation_input codec_input)
{
u32 pipe_penalty_codec = 0;
u8 avid_commercial_content = 0;
u32 pixel_count = 0;
u32 (*pipe_penalty_value)[3];
if (codec_input.vpu_ver == VPU_VERSION_IRIS33)
pipe_penalty_value = pipe_penalty_iris33;
else if (codec_input.vpu_ver == VPU_VERSION_IRIS33_2P)
pipe_penalty_value = pipe_penalty_iris33_2p;
/* decoder */
if (codec_input.decoder_or_encoder == CODEC_DECODER) {
pipe_penalty_codec = pipe_penalty_value[0][0];
avid_commercial_content = codec_input.av1d_commer_tile_enable;
if (codec_input.codec == CODEC_AV1) {
pixel_count = codec_input.frame_width * codec_input.frame_height;
if (pixel_count <= 1920 * 1080)
pipe_penalty_codec =
pipe_penalty_value[avid_commercial_content + 1][0];
else if (pixel_count < 3840 * 2160)
pipe_penalty_codec =
(pipe_penalty_value[avid_commercial_content + 1][0] +
pipe_penalty_value[avid_commercial_content + 1][1]) / 2;
else if ((pixel_count == 3840 * 2160) ||
(pixel_count == 4096 * 2160) || (pixel_count == 4096 * 2304))
pipe_penalty_codec =
pipe_penalty_value[avid_commercial_content + 1][1];
else if (pixel_count < 7680 * 4320)
pipe_penalty_codec =
(pipe_penalty_value[avid_commercial_content + 1][1] +
pipe_penalty_value[avid_commercial_content + 1][2]) / 2;
else
pipe_penalty_codec =
pipe_penalty_value[avid_commercial_content + 1][2];
}
} else {
pipe_penalty_codec = 101;
}
return pipe_penalty_codec;
}
static int calculate_vpp_min_freq(struct api_calculation_input codec_input,
struct api_calculation_freq_output *codec_output)
{
u32 vpp_hw_min_frequency = 0;
u32 fmin = 0;
u32 tensilica_min_frequency = 0;
u32 decoder_vsp_fw_overhead = 100 + 5; /* amplified by 100x */
/* UInt32 fw_sw_vsp_offset = 1000 + 55; amplified by 1000x */
/* TODO from calculate_sw_vsp_min_freq */
u32 vsp_hw_min_frequency = codec_output->vsp_min_freq;
u32 pipe_penalty_codec = 0;
u32 fmin_fwoverhead105 = 0;
u32 fmin_measured_fwoverhead = 0;
u32 lpmode_uhd_cycle_permb = 0;
u32 hqmode1080p_cycle_permb = 0;
u32 encoder_vpp_target_clk_per_mb = 0;
u32 decoder_vpp_fw_overhead = DECODER_VPP_FW_OVERHEAD_IRIS33;
codec_mbspersession_iris33 =
calculate_number_mbs_iris33(codec_input.frame_width,
codec_input.frame_height, codec_input.lcu_size) *
codec_input.frame_rate;
/* Section 2. 0 VPP/VSP calculation */
if (codec_input.decoder_or_encoder == CODEC_DECODER) { /* decoder */
vpp_hw_min_frequency = ((decoder_vpp_target_clk_per_mb_iris33) *
(codec_mbspersession_iris33) + codec_input.pipe_num - 1) /
(codec_input.pipe_num);
vpp_hw_min_frequency = (vpp_hw_min_frequency + 99999) / 1000000;
if (codec_input.pipe_num > 1) {
pipe_penalty_codec = calculate_pipe_penalty(codec_input);
vpp_hw_min_frequency = (vpp_hw_min_frequency *
pipe_penalty_codec + 999) / 1000;
}
if (codec_input.codec == CODEC_AV1)
decoder_vpp_fw_overhead = DECODER_VPP_FW_OVERHEAD_IRIS33_AV1D;
else
decoder_vpp_fw_overhead = DECODER_VPP_FW_OVERHEAD_IRIS33_NONAV1D;
if (codec_input.vsp_vpp_mode == CODEC_VSPVPP_MODE_2S) {
/* FW overhead, convert FW cycles to impact to one pipe */
decoder_vpp_fw_overhead =
DIV_ROUND_UP((decoder_vpp_fw_overhead * 10 *
codec_input.frame_rate), 15);
decoder_vpp_fw_overhead =
DIV_ROUND_UP((decoder_vpp_fw_overhead * 1000),
(codec_mbspersession_iris33 *
decoder_vpp_target_clk_per_mb_iris33 / codec_input.pipe_num));
decoder_vpp_fw_overhead += 1000;
decoder_vpp_fw_overhead = (decoder_vpp_fw_overhead < 1050) ?
1050 : decoder_vpp_fw_overhead;
/* VPP HW + FW */
if (codec_input.linear_opb == 1 &&
codec_input.bitdepth == CODEC_BITDEPTH_10)
/* multiply by 1.20 for 10b case */
decoder_vpp_fw_overhead = 1200 + decoder_vpp_fw_overhead - 1000;
vpp_hw_min_frequency = (vpp_hw_min_frequency *
decoder_vpp_fw_overhead + 999) / 1000;
/* VSP HW+FW */
vsp_hw_min_frequency =
(vsp_hw_min_frequency * decoder_vsp_fw_overhead + 99) / 100;
fmin = (vpp_hw_min_frequency > vsp_hw_min_frequency) ?
vpp_hw_min_frequency : vsp_hw_min_frequency;
} else {
/* 1-stage need SW cycles + FW cycles + HW time */
if (codec_input.linear_opb == 1 &&
codec_input.bitdepth == CODEC_BITDEPTH_10)
/* multiply by 1.20 for 10b linear case */
vpp_hw_min_frequency =
(vpp_hw_min_frequency * 1200 + 999) / 1000;
/*
* HW time
* comment: 02/23/2021 SY: the bitrate is measured bitrate,
* the overlapping effect is already considered into bitrate.
* no need to add extra anymore
*/
fmin = (vpp_hw_min_frequency > vsp_hw_min_frequency) ?
vpp_hw_min_frequency : vsp_hw_min_frequency;
/* FW time */
fmin_fwoverhead105 = (fmin * 105 + 99) / 100;
fmin_measured_fwoverhead = fmin +
(((DECODER_VPPVSP1STAGE_FW_OVERHEAD_IRIS33 *
codec_input.frame_rate * 10 + 14) / 15 + 999) / 1000 + 999) /
1000;
fmin = (fmin_fwoverhead105 > fmin_measured_fwoverhead) ?
fmin_fwoverhead105 : fmin_measured_fwoverhead;
}
tensilica_min_frequency = (DECODER_SW_OVERHEAD_IRIS33 * 10 + 14) / 15;
tensilica_min_frequency = (tensilica_min_frequency + 999) / 1000;
tensilica_min_frequency = tensilica_min_frequency * codec_input.frame_rate;
tensilica_min_frequency = (tensilica_min_frequency + 999) / 1000;
fmin = (tensilica_min_frequency > fmin) ? tensilica_min_frequency : fmin;
} else { /* encoder */
/* Decide LP/HQ */
u8 hq_mode = 0;
if (codec_input.pipe_num > 1)
if (codec_input.frame_width * codec_input.frame_height <=
1920 * 1080)
if (codec_input.frame_width * codec_input.frame_height *
codec_input.frame_rate <= 1920 * 1080 * 60)
hq_mode = 1;
codec_output->enc_hqmode = hq_mode;
/* Section 1. 0 */
/* TODO ONETIME call, should be in another place. */
initialize_encoder_complexity_table();
/* End Calculate Encoder GOP Complexity Table */
/* VPP base cycle */
lpmode_uhd_cycle_permb = (320 *
codec_encoder_gop_complexity_table_fp
[codec_input.hierachical_layer][CODEC_ENCODER_GOP_FACTORY_ENTRY]
+ 99) / 100;
if ((codec_input.frame_width == 1920) &&
((codec_input.frame_height == 1080) ||
(codec_input.frame_height == 1088)) &&
(codec_input.frame_rate >= 480))
lpmode_uhd_cycle_permb = (90 * 4 *
codec_encoder_gop_complexity_table_fp
[codec_input.hierachical_layer][CODEC_ENCODER_GOP_FACTORY_ENTRY]
+ 99) / 100;
if ((codec_input.frame_width == 1280) &&
((codec_input.frame_height == 720) ||
(codec_input.frame_height == 768)) &&
(codec_input.frame_rate >= 960))
lpmode_uhd_cycle_permb = (99 * 4 *
codec_encoder_gop_complexity_table_fp
[codec_input.hierachical_layer][CODEC_ENCODER_GOP_FACTORY_ENTRY]
+ 99) / 100;
hqmode1080p_cycle_permb = (675 *
codec_encoder_gop_complexity_table_fp
[codec_input.hierachical_layer][CODEC_ENCODER_GOP_FACTORY_ENTRY]
+ 99) / 100;
encoder_vpp_target_clk_per_mb = (hq_mode) ?
hqmode1080p_cycle_permb : lpmode_uhd_cycle_permb;
vpp_hw_min_frequency = ((encoder_vpp_target_clk_per_mb) *
(codec_mbspersession_iris33) + codec_input.pipe_num - 1) /
(codec_input.pipe_num);
vpp_hw_min_frequency = (vpp_hw_min_frequency + 99999) / 1000000;
if (codec_input.pipe_num > 1) {
u32 pipe_penalty_codec = 101;
vpp_hw_min_frequency = (vpp_hw_min_frequency *
pipe_penalty_codec + 99) / 100;
}
if (codec_input.vsp_vpp_mode == CODEC_VSPVPP_MODE_2S) {
/* FW overhead, convert FW cycles to impact to one pipe */
u64 encoder_vpp_fw_overhead = 0;
encoder_vpp_fw_overhead =
DIV_ROUND_UP((ENCODER_VPP_FW_OVERHEAD_IRIS33 * 10 *
codec_input.frame_rate), 15);
encoder_vpp_fw_overhead =
DIV_ROUND_UP((encoder_vpp_fw_overhead * 1000),
(codec_mbspersession_iris33 * encoder_vpp_target_clk_per_mb /
codec_input.pipe_num));
encoder_vpp_fw_overhead += 1000;
encoder_vpp_fw_overhead = (encoder_vpp_fw_overhead < 1050) ?
1050 : encoder_vpp_fw_overhead;
/* VPP HW + FW */
vpp_hw_min_frequency = (vpp_hw_min_frequency *
encoder_vpp_fw_overhead + 999) / 1000;
/* TODO : decoder_vsp_fw_overhead? */
vsp_hw_min_frequency = (vsp_hw_min_frequency *
decoder_vsp_fw_overhead + 99) / 100;
fmin = (vpp_hw_min_frequency > vsp_hw_min_frequency) ?
vpp_hw_min_frequency : vsp_hw_min_frequency;
} else {
/* HW time */
fmin = (vpp_hw_min_frequency > vsp_hw_min_frequency) ?
vpp_hw_min_frequency : vsp_hw_min_frequency;
/* FW time */
fmin_fwoverhead105 = (fmin * 105 + 99) / 100;
fmin_measured_fwoverhead = fmin +
(((DECODER_VPPVSP1STAGE_FW_OVERHEAD_IRIS33 *
codec_input.frame_rate * 10 + 14) / 15 + 999) /
1000 + 999) / 1000;
fmin = (fmin_fwoverhead105 > fmin_measured_fwoverhead) ?
fmin_fwoverhead105 : fmin_measured_fwoverhead;
/* SW time */
}
tensilica_min_frequency = (ENCODER_SW_OVERHEAD_IRIS33 * 10 + 14) / 15;
tensilica_min_frequency = (tensilica_min_frequency + 999) / 1000;
tensilica_min_frequency = tensilica_min_frequency *
codec_input.frame_rate;
tensilica_min_frequency = (tensilica_min_frequency + 999) / 1000;
fmin = (tensilica_min_frequency > fmin) ?
tensilica_min_frequency : fmin;
}
codec_output->vpp_min_freq = vpp_hw_min_frequency;
codec_output->vsp_min_freq = vsp_hw_min_frequency;
codec_output->tensilica_min_freq = tensilica_min_frequency;
codec_output->hw_min_freq = fmin;
return 0;
}
int msm_vidc_calculate_frequency(struct api_calculation_input codec_input,
struct api_calculation_freq_output *codec_output)
{
int rc = 0;
rc = calculate_vsp_min_freq(codec_input, codec_output);
if (rc)
return rc;
rc = calculate_vpp_min_freq(codec_input, codec_output);
if (rc)
return rc;
return rc;
}

1614
qcom/opensource/video-driver/driver/variant/iris33/src/msm_vidc_iris33.c ノーマルファイル
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1366
qcom/opensource/video-driver/driver/variant/iris33/src/msm_vidc_power_iris33.c ノーマルファイル
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