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disp: msm: dsi: update DSI PHY post divider for slave PLL

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The change ensures that for the slave PLL the PHY post divider
always needs to be configured to 0x1.

Change-Id: I481b4fd206d9f8e05af724687beb2e89fd6c2ea6
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This commit is contained in:
Satya Rama Aditya Pinapala
2021-04-29 12:35:13 -07:00
parent 63f829cf27
commit ef4dd310a4
1 changed files with 3 additions and 2 deletions
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5
msm/dsi/dsi_pll_5nm.c
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@@ -107,10 +107,11 @@ static inline void dsi_pll_set_phy_post_div(struct dsi_pll_resource *pll, u32
reg_val &= ~0x0F; reg_val &= ~0x0F;
reg_val |= phy_post_div; reg_val |= phy_post_div;
DSI_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG0, reg_val); DSI_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG0, reg_val);
/* For slave PLL, this divider always should be set to 1 */
if (pll->slave) { if (pll->slave) {
reg_val = DSI_PLL_REG_R(pll->slave->phy_base, PHY_CMN_CLK_CFG0); reg_val = DSI_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG0);
reg_val &= ~0x0F; reg_val &= ~0x0F;
reg_val |= phy_post_div; reg_val |= 0x1;
DSI_PLL_REG_W(pll->slave->phy_base, PHY_CMN_CLK_CFG0, reg_val); DSI_PLL_REG_W(pll->slave->phy_base, PHY_CMN_CLK_CFG0, reg_val);
} }
} }