From ef4dd310a4819c37aa3acd959638680d3e3b40a1 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 29 Apr 2021 12:35:13 -0700 Subject: [PATCH] disp: msm: dsi: update DSI PHY post divider for slave PLL The change ensures that for the slave PLL the PHY post divider always needs to be configured to 0x1. Change-Id: I481b4fd206d9f8e05af724687beb2e89fd6c2ea6 Signed-off-by: Satya Rama Aditya Pinapala --- msm/dsi/dsi_pll_5nm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/msm/dsi/dsi_pll_5nm.c b/msm/dsi/dsi_pll_5nm.c index f28c4f39c6..b3c884a6b7 100644 --- a/msm/dsi/dsi_pll_5nm.c +++ b/msm/dsi/dsi_pll_5nm.c @@ -107,10 +107,11 @@ static inline void dsi_pll_set_phy_post_div(struct dsi_pll_resource *pll, u32 reg_val &= ~0x0F; reg_val |= phy_post_div; DSI_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG0, reg_val); + /* For slave PLL, this divider always should be set to 1 */ if (pll->slave) { - reg_val = DSI_PLL_REG_R(pll->slave->phy_base, PHY_CMN_CLK_CFG0); + reg_val = DSI_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG0); reg_val &= ~0x0F; - reg_val |= phy_post_div; + reg_val |= 0x1; DSI_PLL_REG_W(pll->slave->phy_base, PHY_CMN_CLK_CFG0, reg_val); } }