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@@ -16,7 +16,6 @@
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#include <linux/suspend.h>
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#include <linux/version.h>
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#include <linux/sched.h>
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-
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#include "main.h"
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#include "bus.h"
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#include "debug.h"
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@@ -427,7 +426,9 @@ static const struct mhi_controller_config cnss_mhi_config_genoa = {
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CNSS_MHI_SATELLITE_EVT_COUNT,
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.event_cfg = cnss_mhi_events,
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.m2_no_db = true,
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+#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0))
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.bhie_offset = 0x0324,
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+#endif
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};
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static const struct mhi_controller_config cnss_mhi_config_no_satellite = {
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@@ -1567,7 +1568,7 @@ void cnss_pci_handle_linkdown(struct cnss_pci_data *pci_priv)
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}
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if (pci_dev->device == QCA6174_DEVICE_ID)
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- disable_irq(pci_dev->irq);
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+ disable_irq_nosync(pci_dev->irq);
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/* Notify bus related event. Now for all supported chips.
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* Here PCIe LINK_DOWN notification taken care.
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@@ -3988,7 +3989,9 @@ static int cnss_pci_resume(struct device *dev)
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goto out;
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if (!pci_priv->disable_pc) {
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+ mutex_lock(&pci_priv->bus_lock);
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ret = cnss_pci_resume_bus(pci_priv);
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+ mutex_unlock(&pci_priv->bus_lock);
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if (ret)
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goto out;
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}
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@@ -5153,8 +5156,8 @@ int cnss_smmu_map(struct device *dev,
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cnss_pr_dbg("IOMMU map: iova %lx, len %zu\n", iova, len);
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- ret = iommu_map(pci_priv->iommu_domain, iova,
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- rounddown(paddr, PAGE_SIZE), len, flag);
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+ ret = cnss_iommu_map(pci_priv->iommu_domain, iova,
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+ rounddown(paddr, PAGE_SIZE), len, flag);
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if (ret) {
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cnss_pr_err("PA to IOVA mapping failed, ret %d\n", ret);
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return ret;
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@@ -6351,7 +6354,8 @@ static char *cnss_mhi_notify_status_to_str(enum mhi_callback status)
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return "FATAL_ERROR";
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case MHI_CB_EE_MISSION_MODE:
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return "MISSION_MODE";
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-#if IS_ENABLED(CONFIG_MHI_BUS_MISC)
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+#if IS_ENABLED(CONFIG_MHI_BUS_MISC) && \
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+(LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0))
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case MHI_CB_FALLBACK_IMG:
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return "FW_FALLBACK";
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#endif
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@@ -6479,7 +6483,8 @@ static void cnss_mhi_notify_status(struct mhi_controller *mhi_ctrl,
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cnss_pci_update_status(pci_priv, CNSS_FW_DOWN);
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cnss_reason = CNSS_REASON_RDDM;
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break;
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-#if IS_ENABLED(CONFIG_MHI_BUS_MISC)
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+#if IS_ENABLED(CONFIG_MHI_BUS_MISC) && \
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+(LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0))
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case MHI_CB_FALLBACK_IMG:
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/* for kiwi_v2 binary fallback is used, skip path fallback here */
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if (!(pci_priv->device_id == KIWI_DEVICE_ID &&
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@@ -6489,6 +6494,7 @@ static void cnss_mhi_notify_status(struct mhi_controller *mhi_ctrl,
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}
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return;
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#endif
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+
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default:
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cnss_pr_err("Unsupported MHI status cb reason: %d\n", reason);
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return;
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@@ -6664,7 +6670,8 @@ static int cnss_pci_register_mhi(struct cnss_pci_data *pci_priv)
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mhi_ctrl->cntrl_dev = &pci_dev->dev;
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mhi_ctrl->fw_image = plat_priv->firmware_name;
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-#if IS_ENABLED(CONFIG_MHI_BUS_MISC)
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+#if IS_ENABLED(CONFIG_MHI_BUS_MISC) && \
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+(LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0))
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mhi_ctrl->fallback_fw_image = plat_priv->fw_fallback_name;
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#endif
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@@ -7046,6 +7053,24 @@ static bool cnss_should_suspend_pwroff(struct pci_dev *pci_dev)
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}
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#endif
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+static int cnss_pci_set_gen2_speed(struct cnss_plat_data *plat_priv, u32 rc_num)
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+{
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+ int ret;
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+
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+ /* Always set initial target PCIe link speed to Gen2 for QCA6490 device
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+ * since there may be link issues if it boots up with Gen3 link speed.
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+ * Device is able to change it later at any time. It will be rejected
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+ * if requested speed is higher than the one specified in PCIe DT.
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+ */
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+ ret = cnss_pci_set_max_link_speed(plat_priv->bus_priv, rc_num,
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+ PCI_EXP_LNKSTA_CLS_5_0GB);
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+ if (ret && ret != -EPROBE_DEFER)
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+ cnss_pr_err("Failed to set max PCIe RC%x link speed to Gen2, err = %d\n",
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+ rc_num, ret);
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+
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+ return ret;
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+}
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+
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#ifdef CONFIG_CNSS2_ENUM_WITH_LOW_SPEED
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static void
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cnss_pci_downgrade_rc_speed(struct cnss_plat_data *plat_priv, u32 rc_num)
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@@ -7066,7 +7091,9 @@ cnss_pci_restore_rc_speed(struct cnss_pci_data *pci_priv)
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struct cnss_plat_data *plat_priv = pci_priv->plat_priv;
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/* if not Genoa, do not restore rc speed */
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- if (pci_priv->device_id != QCN7605_DEVICE_ID) {
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+ if (pci_priv->device_id == QCA6490_DEVICE_ID) {
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+ cnss_pci_set_gen2_speed(plat_priv, plat_priv->rc_num);
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+ } else if (pci_priv->device_id != QCN7605_DEVICE_ID) {
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/* The request 0 will reset maximum GEN speed to default */
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ret = cnss_pci_set_max_link_speed(pci_priv, plat_priv->rc_num, 0);
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if (ret)
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@@ -7362,17 +7389,8 @@ static int cnss_pci_enumerate(struct cnss_plat_data *plat_priv, u32 rc_num)
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{
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int ret, retry = 0;
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- /* Always set initial target PCIe link speed to Gen2 for QCA6490 device
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- * since there may be link issues if it boots up with Gen3 link speed.
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- * Device is able to change it later at any time. It will be rejected
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- * if requested speed is higher than the one specified in PCIe DT.
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- */
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if (plat_priv->device_id == QCA6490_DEVICE_ID) {
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- ret = cnss_pci_set_max_link_speed(plat_priv->bus_priv, rc_num,
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- PCI_EXP_LNKSTA_CLS_5_0GB);
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- if (ret && ret != -EPROBE_DEFER)
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- cnss_pr_err("Failed to set max PCIe RC%x link speed to Gen2, err = %d\n",
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- rc_num, ret);
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+ cnss_pci_set_gen2_speed(plat_priv, rc_num);
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} else {
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cnss_pci_downgrade_rc_speed(plat_priv, rc_num);
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}
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