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asoc: lpass-cdc: add lpass-cdc v2p5 register updates

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Update lpass-cdc version 2p5 registers update and remove old
version tables.

Change-Id: I14e0efe09e3ff5ded49b91e2e226558ae444bc0f
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
This commit is contained in:
Laxminath Kasam
2020-09-10 23:45:11 +05:30
committed by Gerrit - the friendly Code Review server
parent 9e61f25f98
commit eca32d433e
11 changed files with 1748 additions and 3091 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
asoc/codecs/lpass-cdc/internal.h
View File

@@ -102,10 +102,6 @@ int lpass_cdc_get_macro_id(bool va_no_dec_flag, u16 reg);
extern const struct regmap_config lpass_cdc_regmap_config;
extern u8 *lpass_cdc_reg_access[MAX_MACRO];
extern u8 lpass_cdc_va_top_reg_access[LPASS_CDC_VA_MACRO_TOP_MAX];
extern u8 lpass_cdc_va_reg_access_v2[LPASS_CDC_VA_MACRO_MAX];
extern u8 lpass_cdc_va_reg_access_v3[LPASS_CDC_VA_MACRO_MAX];
extern u8 lpass_cdc_tx_reg_access_v2[LPASS_CDC_TX_MACRO_MAX];
extern const u16 macro_id_base_offset[MAX_MACRO];
#endif

752
asoc/codecs/lpass-cdc/lpass-cdc-registers.h
View File

@@ -13,18 +13,11 @@
#define LPASS_CDC_TX_TOP_CSR_TOP_CFG0 (TX_START_OFFSET + 0x0080)
#define LPASS_CDC_TX_TOP_CSR_ANC_CFG (TX_START_OFFSET + 0x0084)
#define LPASS_CDC_TX_TOP_CSR_SWR_CTRL (TX_START_OFFSET + 0x0088)
#define LPASS_CDC_TX_TOP_CSR_FREQ_MCLK (TX_START_OFFSET + 0x0090)
#define LPASS_CDC_TX_TOP_CSR_DEBUG_BUS (TX_START_OFFSET + 0x0094)
#define LPASS_CDC_TX_TOP_CSR_DEBUG_EN (TX_START_OFFSET + 0x0098)
#define LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL (TX_START_OFFSET + 0x00A4)
#define LPASS_CDC_TX_TOP_CSR_I2S_CLK (TX_START_OFFSET + 0x00A8)
#define LPASS_CDC_TX_TOP_CSR_I2S_RESET (TX_START_OFFSET + 0x00AC)
#define LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL (TX_START_OFFSET + 0x00C0)
#define LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL (TX_START_OFFSET + 0x00C4)
#define LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL (TX_START_OFFSET + 0x00C8)
#define LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL (TX_START_OFFSET + 0x00CC)
#define LPASS_CDC_TX_TOP_CSR_SWR_AMIC0_CTL (TX_START_OFFSET + 0x00D0)
#define LPASS_CDC_TX_TOP_CSR_SWR_AMIC1_CTL (TX_START_OFFSET + 0x00D4)
#define LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL (TX_START_OFFSET + 0x00C0)
#define LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL (TX_START_OFFSET + 0x00C4)
#define LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL (TX_START_OFFSET + 0x00C8)
@@ -158,6 +151,7 @@
#define RX_START_OFFSET 0x1000
#define LPASS_CDC_RX_TOP_TOP_CFG0 (RX_START_OFFSET + 0x0000)
#define LPASS_CDC_RX_TOP_TOP_CFG1 (RX_START_OFFSET + 0x0004)
#define LPASS_CDC_RX_TOP_SWR_CTRL (RX_START_OFFSET + 0x0008)
#define LPASS_CDC_RX_TOP_DEBUG (RX_START_OFFSET + 0x000C)
#define LPASS_CDC_RX_TOP_DEBUG_BUS (RX_START_OFFSET + 0x0010)
@@ -260,13 +254,6 @@
#define LPASS_CDC_RX_BCL_VBAT_ATTN1 (RX_START_OFFSET + 0x0300)
#define LPASS_CDC_RX_BCL_VBAT_ATTN2 (RX_START_OFFSET + 0x0304)
#define LPASS_CDC_RX_BCL_VBAT_ATTN3 (RX_START_OFFSET + 0x0308)
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1 (RX_START_OFFSET + 0x030C)
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2 (RX_START_OFFSET + 0x0310)
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1 (RX_START_OFFSET + 0x0314)
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2 (RX_START_OFFSET + 0x0318)
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3 (RX_START_OFFSET + 0x031C)
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4 (RX_START_OFFSET + 0x0320)
#define LPASS_CDC_RX_BCL_VBAT_DECODE_ST (RX_START_OFFSET + 0x0324)
#define LPASS_CDC_RX_INTR_CTRL_CFG (RX_START_OFFSET + 0x0340)
#define LPASS_CDC_RX_INTR_CTRL_CLR_COMMIT (RX_START_OFFSET + 0x0344)
#define LPASS_CDC_RX_INTR_CTRL_PIN1_MASK0 (RX_START_OFFSET + 0x0360)
@@ -301,49 +288,137 @@
#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x0450)
#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x0454)
#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x0458)
#define LPASS_CDC_RX_RX1_RX_PATH_CTL (RX_START_OFFSET + 0x0480)
#define LPASS_CDC_RX_RX1_RX_PATH_CFG0 (RX_START_OFFSET + 0x0484)
#define LPASS_CDC_RX_RX1_RX_PATH_CFG1 (RX_START_OFFSET + 0x0488)
#define LPASS_CDC_RX_RX1_RX_PATH_CFG2 (RX_START_OFFSET + 0x048C)
#define LPASS_CDC_RX_RX1_RX_PATH_CFG3 (RX_START_OFFSET + 0x0490)
#define LPASS_CDC_RX_RX1_RX_VOL_CTL (RX_START_OFFSET + 0x0494)
#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0498)
#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x049C)
#define LPASS_CDC_RX_RX1_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x04A0)
#define LPASS_CDC_RX_RX1_RX_PATH_SEC1 (RX_START_OFFSET + 0x04A4)
#define LPASS_CDC_RX_RX1_RX_PATH_SEC2 (RX_START_OFFSET + 0x04A8)
#define LPASS_CDC_RX_RX1_RX_PATH_SEC3 (RX_START_OFFSET + 0x04AC)
#define LPASS_CDC_RX_RX1_RX_PATH_SEC4 (RX_START_OFFSET + 0x04B0)
#define LPASS_CDC_RX_RX1_RX_PATH_SEC7 (RX_START_OFFSET + 0x04B4)
#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x04B8)
#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x04BC)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x04C0)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA1 (RX_START_OFFSET + 0x04C4)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA2 (RX_START_OFFSET + 0x04C8)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA3 (RX_START_OFFSET + 0x04CC)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x04D0)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x04D4)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x04D8)
#define LPASS_CDC_RX_RX2_RX_PATH_CTL (RX_START_OFFSET + 0x0500)
#define LPASS_CDC_RX_RX2_RX_PATH_CFG0 (RX_START_OFFSET + 0x0504)
#define LPASS_CDC_RX_RX2_RX_PATH_CFG1 (RX_START_OFFSET + 0x0508)
#define LPASS_CDC_RX_RX2_RX_PATH_CFG2 (RX_START_OFFSET + 0x050C)
#define LPASS_CDC_RX_RX2_RX_PATH_CFG3 (RX_START_OFFSET + 0x0510)
#define LPASS_CDC_RX_RX2_RX_VOL_CTL (RX_START_OFFSET + 0x0514)
#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0518)
#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x051C)
#define LPASS_CDC_RX_RX2_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x0520)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC0 (RX_START_OFFSET + 0x0524)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC1 (RX_START_OFFSET + 0x0528)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC2 (RX_START_OFFSET + 0x052C)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC3 (RX_START_OFFSET + 0x0530)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC4 (RX_START_OFFSET + 0x0534)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC5 (RX_START_OFFSET + 0x0538)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC6 (RX_START_OFFSET + 0x053C)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC7 (RX_START_OFFSET + 0x0540)
#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x0544)
#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x0548)
#define LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x054C)
#define LPASS_CDC_RX_RX0_RX_FIR_CTL (RX_START_OFFSET + 0x045C)
#define LPASS_CDC_RX_RX0_RX_FIR_CFG (RX_START_OFFSET + 0x0460)
#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR (RX_START_OFFSET + 0x0464)
#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0 (RX_START_OFFSET + 0x0468)
#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1 (RX_START_OFFSET + 0x046C)
#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2 (RX_START_OFFSET + 0x0470)
#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3 (RX_START_OFFSET + 0x0474)
#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4 (RX_START_OFFSET + 0x0478)
#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5 (RX_START_OFFSET + 0x047C)
#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6 (RX_START_OFFSET + 0x0480)
#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7 (RX_START_OFFSET + 0x0484)
#define LPASS_CDC_RX_RX1_RX_PATH_CTL (RX_START_OFFSET + 0x04C0)
#define LPASS_CDC_RX_RX1_RX_PATH_CFG0 (RX_START_OFFSET + 0x04C4)
#define LPASS_CDC_RX_RX1_RX_PATH_CFG1 (RX_START_OFFSET + 0x04C8)
#define LPASS_CDC_RX_RX1_RX_PATH_CFG2 (RX_START_OFFSET + 0x04CC)
#define LPASS_CDC_RX_RX1_RX_PATH_CFG3 (RX_START_OFFSET + 0x04D0)
#define LPASS_CDC_RX_RX1_RX_VOL_CTL (RX_START_OFFSET + 0x04D4)
#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x04D8)
#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x04DC)
#define LPASS_CDC_RX_RX1_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x04E0)
#define LPASS_CDC_RX_RX1_RX_PATH_SEC1 (RX_START_OFFSET + 0x04E4)
#define LPASS_CDC_RX_RX1_RX_PATH_SEC2 (RX_START_OFFSET + 0x04E8)
#define LPASS_CDC_RX_RX1_RX_PATH_SEC3 (RX_START_OFFSET + 0x04EC)
#define LPASS_CDC_RX_RX1_RX_PATH_SEC4 (RX_START_OFFSET + 0x04F0)
#define LPASS_CDC_RX_RX1_RX_PATH_SEC7 (RX_START_OFFSET + 0x04F4)
#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x04F8)
#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x04FC)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x0500)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA1 (RX_START_OFFSET + 0x0504)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA2 (RX_START_OFFSET + 0x0508)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA3 (RX_START_OFFSET + 0x050C)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x0510)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x0514)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x0518)
#define LPASS_CDC_RX_RX1_RX_FIR_CTL (RX_START_OFFSET + 0x051C)
#define LPASS_CDC_RX_RX1_RX_FIR_CFG (RX_START_OFFSET + 0x0520)
#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR (RX_START_OFFSET + 0x0524)
#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0 (RX_START_OFFSET + 0x0528)
#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1 (RX_START_OFFSET + 0x052C)
#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2 (RX_START_OFFSET + 0x0530)
#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3 (RX_START_OFFSET + 0x0534)
#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4 (RX_START_OFFSET + 0x0538)
#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5 (RX_START_OFFSET + 0x053C)
#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6 (RX_START_OFFSET + 0x0540)
#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7 (RX_START_OFFSET + 0x0544)
#define LPASS_CDC_RX_RX2_RX_PATH_CTL (RX_START_OFFSET + 0x0580)
#define LPASS_CDC_RX_RX2_RX_PATH_CFG0 (RX_START_OFFSET + 0x0584)
#define LPASS_CDC_RX_RX2_RX_PATH_CFG1 (RX_START_OFFSET + 0x0588)
#define LPASS_CDC_RX_RX2_RX_PATH_CFG2 (RX_START_OFFSET + 0x058C)
#define LPASS_CDC_RX_RX2_RX_PATH_CFG3 (RX_START_OFFSET + 0x0590)
#define LPASS_CDC_RX_RX2_RX_VOL_CTL (RX_START_OFFSET + 0x0594)
#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0598)
#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x059C)
#define LPASS_CDC_RX_RX2_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x05A0)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC0 (RX_START_OFFSET + 0x05A4)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC1 (RX_START_OFFSET + 0x05A8)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC2 (RX_START_OFFSET + 0x05AC)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC3 (RX_START_OFFSET + 0x05B0)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC4 (RX_START_OFFSET + 0x05B4)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC5 (RX_START_OFFSET + 0x05B8)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC6 (RX_START_OFFSET + 0x05BC)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC7 (RX_START_OFFSET + 0x05C0)
#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x05C4)
#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x05C8)
#define LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x05CC)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1 (RX_START_OFFSET + 0x0600)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2 (RX_START_OFFSET + 0x0604)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3 (RX_START_OFFSET + 0x0608)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1 (RX_START_OFFSET + 0x060C)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2 (RX_START_OFFSET + 0x0610)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3 (RX_START_OFFSET + 0x0614)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4 (RX_START_OFFSET + 0x0618)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5 (RX_START_OFFSET + 0x061C)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6 (RX_START_OFFSET + 0x0620)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7 (RX_START_OFFSET + 0x0624)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8 (RX_START_OFFSET + 0x0628)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1 (RX_START_OFFSET + 0x062C)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2 (RX_START_OFFSET + 0x0630)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3 (RX_START_OFFSET + 0x0634)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4 (RX_START_OFFSET + 0x0638)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1 (RX_START_OFFSET + 0x063C)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2 (RX_START_OFFSET + 0x0640)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3 (RX_START_OFFSET + 0x0644)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4 (RX_START_OFFSET + 0x0648)
#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5 (RX_START_OFFSET + 0x064C)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL (RX_START_OFFSET + 0x0680)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG (RX_START_OFFSET + 0x0684)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1 (RX_START_OFFSET + 0x0688)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2 (RX_START_OFFSET + 0x068C)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3 (RX_START_OFFSET + 0x0690)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1 (RX_START_OFFSET + 0x0694)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2 (RX_START_OFFSET + 0x0698)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3 (RX_START_OFFSET + 0x069C)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1 (RX_START_OFFSET + 0x06A0)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC2 (RX_START_OFFSET + 0x06A4)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1 (RX_START_OFFSET + 0x06A8)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2 (RX_START_OFFSET + 0x06AC)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3 (RX_START_OFFSET + 0x06B0)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4 (RX_START_OFFSET + 0x06B4)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1 (RX_START_OFFSET + 0x06B8)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2 (RX_START_OFFSET + 0x06BC)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3 (RX_START_OFFSET + 0x06C0)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4 (RX_START_OFFSET + 0x06C4)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5 (RX_START_OFFSET + 0x06C8)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1 (RX_START_OFFSET + 0x06CC)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON \
(RX_START_OFFSET + 0x06D0)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL \
(RX_START_OFFSET + 0x06D4)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN (RX_START_OFFSET + 0x06D8)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1 \
(RX_START_OFFSET + 0x06DC)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2 \
(RX_START_OFFSET + 0x06E0)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3 \
(RX_START_OFFSET + 0x06E4)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4 \
(RX_START_OFFSET + 0x06E8)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5 \
(RX_START_OFFSET + 0x06EC)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6 \
(RX_START_OFFSET + 0x06F0)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7 \
(RX_START_OFFSET + 0x06F4)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8 \
(RX_START_OFFSET + 0x06F8)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9 \
(RX_START_OFFSET + 0x06FC)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1 (RX_START_OFFSET + 0x0700)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2 (RX_START_OFFSET + 0x0704)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3 (RX_START_OFFSET + 0x0708)
#define LPASS_CDC_RX_IDLE_DETECT_PATH_CTL (RX_START_OFFSET + 0x0780)
#define LPASS_CDC_RX_IDLE_DETECT_CFG0 (RX_START_OFFSET + 0x0784)
#define LPASS_CDC_RX_IDLE_DETECT_CFG1 (RX_START_OFFSET + 0x0788)
@@ -357,14 +432,38 @@
#define LPASS_CDC_RX_COMPANDER0_CTL5 (RX_START_OFFSET + 0x0814)
#define LPASS_CDC_RX_COMPANDER0_CTL6 (RX_START_OFFSET + 0x0818)
#define LPASS_CDC_RX_COMPANDER0_CTL7 (RX_START_OFFSET + 0x081C)
#define LPASS_CDC_RX_COMPANDER1_CTL0 (RX_START_OFFSET + 0x0840)
#define LPASS_CDC_RX_COMPANDER1_CTL1 (RX_START_OFFSET + 0x0844)
#define LPASS_CDC_RX_COMPANDER1_CTL2 (RX_START_OFFSET + 0x0848)
#define LPASS_CDC_RX_COMPANDER1_CTL3 (RX_START_OFFSET + 0x084C)
#define LPASS_CDC_RX_COMPANDER1_CTL4 (RX_START_OFFSET + 0x0850)
#define LPASS_CDC_RX_COMPANDER1_CTL5 (RX_START_OFFSET + 0x0854)
#define LPASS_CDC_RX_COMPANDER1_CTL6 (RX_START_OFFSET + 0x0858)
#define LPASS_CDC_RX_COMPANDER1_CTL7 (RX_START_OFFSET + 0x085C)
#define LPASS_CDC_RX_COMPANDER0_CTL8 (RX_START_OFFSET + 0x0820)
#define LPASS_CDC_RX_COMPANDER0_CTL9 (RX_START_OFFSET + 0x0820)
#define LPASS_CDC_RX_COMPANDER0_CTL10 (RX_START_OFFSET + 0x0824)
#define LPASS_CDC_RX_COMPANDER0_CTL11 (RX_START_OFFSET + 0x0828)
#define LPASS_CDC_RX_COMPANDER0_CTL12 (RX_START_OFFSET + 0x082C)
#define LPASS_CDC_RX_COMPANDER0_CTL13 (RX_START_OFFSET + 0x0830)
#define LPASS_CDC_RX_COMPANDER0_CTL14 (RX_START_OFFSET + 0x0834)
#define LPASS_CDC_RX_COMPANDER0_CTL15 (RX_START_OFFSET + 0x0838)
#define LPASS_CDC_RX_COMPANDER0_CTL16 (RX_START_OFFSET + 0x083C)
#define LPASS_CDC_RX_COMPANDER0_CTL17 (RX_START_OFFSET + 0x0840)
#define LPASS_CDC_RX_COMPANDER0_CTL18 (RX_START_OFFSET + 0x0848)
#define LPASS_CDC_RX_COMPANDER0_CTL19 (RX_START_OFFSET + 0x084C)
#define LPASS_CDC_RX_COMPANDER1_CTL0 (RX_START_OFFSET + 0x0860)
#define LPASS_CDC_RX_COMPANDER1_CTL1 (RX_START_OFFSET + 0x0864)
#define LPASS_CDC_RX_COMPANDER1_CTL2 (RX_START_OFFSET + 0x0868)
#define LPASS_CDC_RX_COMPANDER1_CTL3 (RX_START_OFFSET + 0x086C)
#define LPASS_CDC_RX_COMPANDER1_CTL4 (RX_START_OFFSET + 0x0870)
#define LPASS_CDC_RX_COMPANDER1_CTL5 (RX_START_OFFSET + 0x0874)
#define LPASS_CDC_RX_COMPANDER1_CTL6 (RX_START_OFFSET + 0x0878)
#define LPASS_CDC_RX_COMPANDER1_CTL7 (RX_START_OFFSET + 0x087C)
#define LPASS_CDC_RX_COMPANDER1_CTL8 (RX_START_OFFSET + 0x0880)
#define LPASS_CDC_RX_COMPANDER1_CTL9 (RX_START_OFFSET + 0x0884)
#define LPASS_CDC_RX_COMPANDER1_CTL10 (RX_START_OFFSET + 0x0888)
#define LPASS_CDC_RX_COMPANDER1_CTL11 (RX_START_OFFSET + 0x088C)
#define LPASS_CDC_RX_COMPANDER1_CTL12 (RX_START_OFFSET + 0x0890)
#define LPASS_CDC_RX_COMPANDER1_CTL13 (RX_START_OFFSET + 0x0894)
#define LPASS_CDC_RX_COMPANDER1_CTL14 (RX_START_OFFSET + 0x0898)
#define LPASS_CDC_RX_COMPANDER1_CTL15 (RX_START_OFFSET + 0x089C)
#define LPASS_CDC_RX_COMPANDER1_CTL16 (RX_START_OFFSET + 0x08A0)
#define LPASS_CDC_RX_COMPANDER1_CTL17 (RX_START_OFFSET + 0x08A4)
#define LPASS_CDC_RX_COMPANDER1_CTL18 (RX_START_OFFSET + 0x08A8)
#define LPASS_CDC_RX_COMPANDER1_CTL19 (RX_START_OFFSET + 0x08AC)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL \
(RX_START_OFFSET + 0x0A00)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL \
@@ -509,6 +608,19 @@
#define LPASS_CDC_WSA_TOP_TX_I2S_CTL (WSA_START_OFFSET + 0x00A0)
#define LPASS_CDC_WSA_TOP_I2S_CLK (WSA_START_OFFSET + 0x00A4)
#define LPASS_CDC_WSA_TOP_I2S_RESET (WSA_START_OFFSET + 0x00A8)
#define LPASS_CDC_WSA_TOP_FS_UNGATE (WSA_START_OFFSET + 0x00AC)
#define LPASS_CDC_WSA_TOP_GRP_SEL (WSA_START_OFFSET + 0x00B0)
#define LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_LSB (WSA_START_OFFSET + 0x00B4)
#define LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_MSB (WSA_START_OFFSET + 0x00B8)
#define LPASS_CDC_WSA_TOP_SPKR_COMP7_LUT (WSA_START_OFFSET + 0x00BC)
#define LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_LSB (WSA_START_OFFSET + 0x00C0)
#define LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_MSB (WSA_START_OFFSET + 0x00C4)
#define LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_LSB (WSA_START_OFFSET + 0x00C8)
#define LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_MSB (WSA_START_OFFSET + 0x00CC)
#define LPASS_CDC_WSA_TOP_SPKR_COMP8_LUT (WSA_START_OFFSET + 0x00D0)
#define LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_LSB (WSA_START_OFFSET + 0x00D4)
#define LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_MSB (WSA_START_OFFSET + 0x00D8)
#define LPASS_CDC_WSA_TOP_FS_UNGATE2 (WSA_START_OFFSET + 0x00DC)
#define LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 (WSA_START_OFFSET + 0x0100)
#define LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1 (WSA_START_OFFSET + 0x0104)
#define LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0 (WSA_START_OFFSET + 0x0108)
@@ -563,19 +675,6 @@
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1 (WSA_START_OFFSET + 0x0200)
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2 (WSA_START_OFFSET + 0x0204)
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3 (WSA_START_OFFSET + 0x0208)
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1 \
(WSA_START_OFFSET + 0x020C)
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2 \
(WSA_START_OFFSET + 0x0210)
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1 \
(WSA_START_OFFSET + 0x0214)
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2 \
(WSA_START_OFFSET + 0x0218)
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3 \
(WSA_START_OFFSET + 0x021C)
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4 \
(WSA_START_OFFSET + 0x0220)
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST (WSA_START_OFFSET + 0x0224)
#define LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CTL (WSA_START_OFFSET + 0x0244)
#define LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 (WSA_START_OFFSET + 0x0248)
#define LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CTL (WSA_START_OFFSET + 0x0264)
@@ -649,53 +748,126 @@
#define LPASS_CDC_WSA_COMPANDER0_CTL5 (WSA_START_OFFSET + 0x0594)
#define LPASS_CDC_WSA_COMPANDER0_CTL6 (WSA_START_OFFSET + 0x0598)
#define LPASS_CDC_WSA_COMPANDER0_CTL7 (WSA_START_OFFSET + 0x059C)
#define LPASS_CDC_WSA_COMPANDER1_CTL0 (WSA_START_OFFSET + 0x05C0)
#define LPASS_CDC_WSA_COMPANDER1_CTL1 (WSA_START_OFFSET + 0x05C4)
#define LPASS_CDC_WSA_COMPANDER1_CTL2 (WSA_START_OFFSET + 0x05C8)
#define LPASS_CDC_WSA_COMPANDER1_CTL3 (WSA_START_OFFSET + 0x05CC)
#define LPASS_CDC_WSA_COMPANDER1_CTL4 (WSA_START_OFFSET + 0x05D0)
#define LPASS_CDC_WSA_COMPANDER1_CTL5 (WSA_START_OFFSET + 0x05D4)
#define LPASS_CDC_WSA_COMPANDER1_CTL6 (WSA_START_OFFSET + 0x05D8)
#define LPASS_CDC_WSA_COMPANDER1_CTL7 (WSA_START_OFFSET + 0x05DC)
#define LPASS_CDC_WSA_SOFTCLIP0_CRC (WSA_START_OFFSET + 0x0600)
#define LPASS_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL (WSA_START_OFFSET + 0x0604)
#define LPASS_CDC_WSA_SOFTCLIP1_CRC (WSA_START_OFFSET + 0x0640)
#define LPASS_CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL (WSA_START_OFFSET + 0x0644)
#define LPASS_CDC_WSA_COMPANDER0_CTL8 (WSA_START_OFFSET + 0x05A0)
#define LPASS_CDC_WSA_COMPANDER0_CTL9 (WSA_START_OFFSET + 0x05A4)
#define LPASS_CDC_WSA_COMPANDER0_CTL10 (WSA_START_OFFSET + 0x05A8)
#define LPASS_CDC_WSA_COMPANDER0_CTL11 (WSA_START_OFFSET + 0x05AC)
#define LPASS_CDC_WSA_COMPANDER0_CTL12 (WSA_START_OFFSET + 0x05B0)
#define LPASS_CDC_WSA_COMPANDER0_CTL13 (WSA_START_OFFSET + 0x05B4)
#define LPASS_CDC_WSA_COMPANDER0_CTL14 (WSA_START_OFFSET + 0x05B8)
#define LPASS_CDC_WSA_COMPANDER0_CTL15 (WSA_START_OFFSET + 0x05BC)
#define LPASS_CDC_WSA_COMPANDER0_CTL16 (WSA_START_OFFSET + 0x05C0)
#define LPASS_CDC_WSA_COMPANDER0_CTL17 (WSA_START_OFFSET + 0x05C4)
#define LPASS_CDC_WSA_COMPANDER0_CTL18 (WSA_START_OFFSET + 0x05C8)
#define LPASS_CDC_WSA_COMPANDER0_CTL19 (WSA_START_OFFSET + 0x05CC)
#define LPASS_CDC_WSA_COMPANDER1_CTL0 (WSA_START_OFFSET + 0x05E0)
#define LPASS_CDC_WSA_COMPANDER1_CTL1 (WSA_START_OFFSET + 0x05E4)
#define LPASS_CDC_WSA_COMPANDER1_CTL2 (WSA_START_OFFSET + 0x05E8)
#define LPASS_CDC_WSA_COMPANDER1_CTL3 (WSA_START_OFFSET + 0x05EC)
#define LPASS_CDC_WSA_COMPANDER1_CTL4 (WSA_START_OFFSET + 0x05F0)
#define LPASS_CDC_WSA_COMPANDER1_CTL5 (WSA_START_OFFSET + 0x05F4)
#define LPASS_CDC_WSA_COMPANDER1_CTL6 (WSA_START_OFFSET + 0x05F8)
#define LPASS_CDC_WSA_COMPANDER1_CTL7 (WSA_START_OFFSET + 0x05FC)
#define LPASS_CDC_WSA_COMPANDER1_CTL8 (WSA_START_OFFSET + 0x0600)
#define LPASS_CDC_WSA_COMPANDER1_CTL9 (WSA_START_OFFSET + 0x0604)
#define LPASS_CDC_WSA_COMPANDER1_CTL10 (WSA_START_OFFSET + 0x0608)
#define LPASS_CDC_WSA_COMPANDER1_CTL11 (WSA_START_OFFSET + 0x060C)
#define LPASS_CDC_WSA_COMPANDER1_CTL12 (WSA_START_OFFSET + 0x0610)
#define LPASS_CDC_WSA_COMPANDER1_CTL13 (WSA_START_OFFSET + 0x0614)
#define LPASS_CDC_WSA_COMPANDER1_CTL14 (WSA_START_OFFSET + 0x0618)
#define LPASS_CDC_WSA_COMPANDER1_CTL15 (WSA_START_OFFSET + 0x061C)
#define LPASS_CDC_WSA_COMPANDER1_CTL16 (WSA_START_OFFSET + 0x0620)
#define LPASS_CDC_WSA_COMPANDER1_CTL17 (WSA_START_OFFSET + 0x0624)
#define LPASS_CDC_WSA_COMPANDER1_CTL18 (WSA_START_OFFSET + 0x0628)
#define LPASS_CDC_WSA_COMPANDER1_CTL19 (WSA_START_OFFSET + 0x062C)
#define LPASS_CDC_WSA_SOFTCLIP0_CRC (WSA_START_OFFSET + 0x0640)
#define LPASS_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL (WSA_START_OFFSET + 0x0644)
#define LPASS_CDC_WSA_SOFTCLIP1_CRC (WSA_START_OFFSET + 0x0660)
#define LPASS_CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL (WSA_START_OFFSET + 0x0664)
#define LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL \
(WSA_START_OFFSET + 0x0680)
#define LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 (WSA_START_OFFSET + 0x0684)
#define LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL \
(WSA_START_OFFSET + 0x06C0)
#define LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0 (WSA_START_OFFSET + 0x06C4)
#define LPASS_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL (WSA_START_OFFSET + 0x0700)
#define LPASS_CDC_WSA_SPLINE_ASRC0_CTL0 (WSA_START_OFFSET + 0x0704)
#define LPASS_CDC_WSA_SPLINE_ASRC0_CTL1 (WSA_START_OFFSET + 0x0708)
#define LPASS_CDC_WSA_SPLINE_ASRC0_FIFO_CTL (WSA_START_OFFSET + 0x070C)
#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB \
(WSA_START_OFFSET + 0x0710)
#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB \
(WSA_START_OFFSET + 0x0714)
#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB \
(WSA_START_OFFSET + 0x0718)
#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB \
(WSA_START_OFFSET + 0x071C)
#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO (WSA_START_OFFSET + 0x0720)
#define LPASS_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL (WSA_START_OFFSET + 0x0740)
#define LPASS_CDC_WSA_SPLINE_ASRC1_CTL0 (WSA_START_OFFSET + 0x0744)
#define LPASS_CDC_WSA_SPLINE_ASRC1_CTL1 (WSA_START_OFFSET + 0x0748)
#define LPASS_CDC_WSA_SPLINE_ASRC1_FIFO_CTL (WSA_START_OFFSET + 0x074C)
#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB \
(WSA_START_OFFSET + 0x0750)
#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB \
(WSA_START_OFFSET + 0x0754)
#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB \
(WSA_START_OFFSET + 0x0758)
#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB \
(WSA_START_OFFSET + 0x075C)
#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO (WSA_START_OFFSET + 0x0760)
#define WSA_MAX_OFFSET (WSA_START_OFFSET + 0x0760)
#define LPASS_CDC_WSA_IDLE_DETECT_PATH_CTL (WSA_START_OFFSET + 0x0780)
#define LPASS_CDC_WSA_IDLE_DETECT_CFG0 (WSA_START_OFFSET + 0x0784)
#define LPASS_CDC_WSA_IDLE_DETECT_CFG1 (WSA_START_OFFSET + 0x0788)
#define LPASS_CDC_WSA_IDLE_DETECT_CFG2 (WSA_START_OFFSET + 0x078C)
#define LPASS_CDC_WSA_IDLE_DETECT_CFG3 (WSA_START_OFFSET + 0x0790)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL1 (WSA_START_OFFSET + 0x0900)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL2 (WSA_START_OFFSET + 0x0904)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL3 (WSA_START_OFFSET + 0x0908)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG1 (WSA_START_OFFSET + 0x090C)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG2 (WSA_START_OFFSET + 0x0910)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG3 (WSA_START_OFFSET + 0x0914)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG4 (WSA_START_OFFSET + 0x0918)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG5 (WSA_START_OFFSET + 0x091C)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG6 (WSA_START_OFFSET + 0x0920)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG7 (WSA_START_OFFSET + 0x0924)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG8 (WSA_START_OFFSET + 0x0928)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST1 \
(WSA_START_OFFSET + 0x092C)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST2 \
(WSA_START_OFFSET + 0x0930)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST3 \
(WSA_START_OFFSET + 0x0934)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST4 \
(WSA_START_OFFSET + 0x0938)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST1 (WSA_START_OFFSET + 0x093C)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST2 (WSA_START_OFFSET + 0x0940)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST3 (WSA_START_OFFSET + 0x0944)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST4 (WSA_START_OFFSET + 0x0948)
#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST5 (WSA_START_OFFSET + 0x094C)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_PATH_CTL (WSA_START_OFFSET + 0x0980)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_CFG (WSA_START_OFFSET + 0x0984)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL1 (WSA_START_OFFSET + 0x0988)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL2 (WSA_START_OFFSET + 0x098C)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL3 (WSA_START_OFFSET + 0x0990)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST1 (WSA_START_OFFSET + 0x0994)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST2 (WSA_START_OFFSET + 0x0998)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST3 (WSA_START_OFFSET + 0x099C)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC1 (WSA_START_OFFSET + 0x09A0)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC2 (WSA_START_OFFSET + 0x09A4)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC1 (WSA_START_OFFSET + 0x09A8)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC2 (WSA_START_OFFSET + 0x09AC)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC3 (WSA_START_OFFSET + 0x09B0)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC4 (WSA_START_OFFSET + 0x09B4)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD1 (WSA_START_OFFSET + 0x09B8)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD2 (WSA_START_OFFSET + 0x09BC)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD3 (WSA_START_OFFSET + 0x09C0)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD4 (WSA_START_OFFSET + 0x09C4)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD5 (WSA_START_OFFSET + 0x09C8)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_DEBUG1 (WSA_START_OFFSET + 0x09CC)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD_MON \
(WSA_START_OFFSET + 0x09D0)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_MON_VAL \
(WSA_START_OFFSET + 0x09D4)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BAN (WSA_START_OFFSET + 0x09D8)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD1 \
(WSA_START_OFFSET + 0x09DC)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD2 \
(WSA_START_OFFSET + 0x09E0)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD3 \
(WSA_START_OFFSET + 0x09E4)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD4 \
(WSA_START_OFFSET + 0x09E8)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD5 \
(WSA_START_OFFSET + 0x09EC)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD6 \
(WSA_START_OFFSET + 0x09F0)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD7 \
(WSA_START_OFFSET + 0x09F4)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD8 \
(WSA_START_OFFSET + 0x09F8)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD9 \
(WSA_START_OFFSET + 0x09FC)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN1 (WSA_START_OFFSET + 0x0A00)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN2 (WSA_START_OFFSET + 0x0A04)
#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN3 (WSA_START_OFFSET + 0x0A08)
#define WSA_MAX_OFFSET (WSA_START_OFFSET + 0x0A08)
#define LPASS_CDC_WSA_MACRO_MAX 0x1D9 /* 0x760/4 = 0x1D8 + 1 registers */
#define LPASS_CDC_WSA_MACRO_MAX 0x283 /* 0xA08/4 = 0x282 + 1 registers */
/* VA macro registers */
#define VA_START_OFFSET 0x3000
@@ -714,19 +886,15 @@
#define LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL (VA_START_OFFSET + 0x00A4)
#define LPASS_CDC_VA_TOP_CSR_I2S_CLK (VA_START_OFFSET + 0x00A8)
#define LPASS_CDC_VA_TOP_CSR_I2S_RESET (VA_START_OFFSET + 0x00AC)
#define LPASS_CDC_VA_TOP_CSR_DEBUG_CLK (VA_START_OFFSET + 0x00B0)
#define LPASS_CDC_VA_TOP_CSR_CORE_ID_0 (VA_START_OFFSET + 0x00C0)
#define LPASS_CDC_VA_TOP_CSR_CORE_ID_1 (VA_START_OFFSET + 0x00C4)
#define LPASS_CDC_VA_TOP_CSR_CORE_ID_2 (VA_START_OFFSET + 0x00C8)
#define LPASS_CDC_VA_TOP_CSR_CORE_ID_3 (VA_START_OFFSET + 0x00CC)
#define VA_TOP_MAX_OFFSET (VA_START_OFFSET + 0x00CC)
#define LPASS_CDC_VA_MACRO_TOP_MAX 0x34 /* 0x0CC/4 = 0x33 + 1 = 0x34 */
#define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL0 (VA_START_OFFSET + 0x00D0)
#define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1 (VA_START_OFFSET + 0x00D4)
#define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2 (VA_START_OFFSET + 0x00D8)
#define LPASS_CDC_VA_TOP_CSR_SWR_CTRL (VA_START_OFFSET + 0x00DC)
#define LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0 (VA_START_OFFSET + 0x0100)
#define LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1 (VA_START_OFFSET + 0x0104)
#define LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0 (VA_START_OFFSET + 0x0108)
@@ -735,15 +903,6 @@
#define LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG1 (VA_START_OFFSET + 0x0114)
#define LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0 (VA_START_OFFSET + 0x0118)
#define LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG1 (VA_START_OFFSET + 0x011C)
#define LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG0 (VA_START_OFFSET + 0x0120)
#define LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG1 (VA_START_OFFSET + 0x0124)
#define LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG0 (VA_START_OFFSET + 0x0128)
#define LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG1 (VA_START_OFFSET + 0x012C)
#define LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG0 (VA_START_OFFSET + 0x0130)
#define LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG1 (VA_START_OFFSET + 0x0134)
#define LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG0 (VA_START_OFFSET + 0x0138)
#define LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG1 (VA_START_OFFSET + 0x013C)
#define LPASS_CDC_VA_TX0_TX_PATH_CTL (VA_START_OFFSET + 0x0400)
#define LPASS_CDC_VA_TX0_TX_PATH_CFG0 (VA_START_OFFSET + 0x0404)
#define LPASS_CDC_VA_TX0_TX_PATH_CFG1 (VA_START_OFFSET + 0x0408)
@@ -789,55 +948,290 @@
#define LPASS_CDC_VA_TX3_TX_PATH_SEC4 (VA_START_OFFSET + 0x05A0)
#define LPASS_CDC_VA_TX3_TX_PATH_SEC5 (VA_START_OFFSET + 0x05A4)
#define LPASS_CDC_VA_TX3_TX_PATH_SEC6 (VA_START_OFFSET + 0x05A8)
#define LPASS_CDC_VA_TX4_TX_PATH_CTL (VA_START_OFFSET + 0x0600)
#define LPASS_CDC_VA_TX4_TX_PATH_CFG0 (VA_START_OFFSET + 0x0604)
#define LPASS_CDC_VA_TX4_TX_PATH_CFG1 (VA_START_OFFSET + 0x0608)
#define LPASS_CDC_VA_TX4_TX_VOL_CTL (VA_START_OFFSET + 0x060C)
#define LPASS_CDC_VA_TX4_TX_PATH_SEC0 (VA_START_OFFSET + 0x0610)
#define LPASS_CDC_VA_TX4_TX_PATH_SEC1 (VA_START_OFFSET + 0x0614)
#define LPASS_CDC_VA_TX4_TX_PATH_SEC2 (VA_START_OFFSET + 0x0618)
#define LPASS_CDC_VA_TX4_TX_PATH_SEC3 (VA_START_OFFSET + 0x061C)
#define LPASS_CDC_VA_TX4_TX_PATH_SEC4 (VA_START_OFFSET + 0x0620)
#define LPASS_CDC_VA_TX4_TX_PATH_SEC5 (VA_START_OFFSET + 0x0624)
#define LPASS_CDC_VA_TX4_TX_PATH_SEC6 (VA_START_OFFSET + 0x0628)
#define LPASS_CDC_VA_TX5_TX_PATH_CTL (VA_START_OFFSET + 0x0680)
#define LPASS_CDC_VA_TX5_TX_PATH_CFG0 (VA_START_OFFSET + 0x0684)
#define LPASS_CDC_VA_TX5_TX_PATH_CFG1 (VA_START_OFFSET + 0x0688)
#define LPASS_CDC_VA_TX5_TX_VOL_CTL (VA_START_OFFSET + 0x068C)
#define LPASS_CDC_VA_TX5_TX_PATH_SEC0 (VA_START_OFFSET + 0x0690)
#define LPASS_CDC_VA_TX5_TX_PATH_SEC1 (VA_START_OFFSET + 0x0694)
#define LPASS_CDC_VA_TX5_TX_PATH_SEC2 (VA_START_OFFSET + 0x0698)
#define LPASS_CDC_VA_TX5_TX_PATH_SEC3 (VA_START_OFFSET + 0x069C)
#define LPASS_CDC_VA_TX5_TX_PATH_SEC4 (VA_START_OFFSET + 0x06A0)
#define LPASS_CDC_VA_TX5_TX_PATH_SEC5 (VA_START_OFFSET + 0x06A4)
#define LPASS_CDC_VA_TX5_TX_PATH_SEC6 (VA_START_OFFSET + 0x06A8)
#define LPASS_CDC_VA_TX6_TX_PATH_CTL (VA_START_OFFSET + 0x0700)
#define LPASS_CDC_VA_TX6_TX_PATH_CFG0 (VA_START_OFFSET + 0x0704)
#define LPASS_CDC_VA_TX6_TX_PATH_CFG1 (VA_START_OFFSET + 0x0708)
#define LPASS_CDC_VA_TX6_TX_VOL_CTL (VA_START_OFFSET + 0x070C)
#define LPASS_CDC_VA_TX6_TX_PATH_SEC0 (VA_START_OFFSET + 0x0710)
#define LPASS_CDC_VA_TX6_TX_PATH_SEC1 (VA_START_OFFSET + 0x0714)
#define LPASS_CDC_VA_TX6_TX_PATH_SEC2 (VA_START_OFFSET + 0x0718)
#define LPASS_CDC_VA_TX6_TX_PATH_SEC3 (VA_START_OFFSET + 0x071C)
#define LPASS_CDC_VA_TX6_TX_PATH_SEC4 (VA_START_OFFSET + 0x0720)
#define LPASS_CDC_VA_TX6_TX_PATH_SEC5 (VA_START_OFFSET + 0x0724)
#define LPASS_CDC_VA_TX6_TX_PATH_SEC6 (VA_START_OFFSET + 0x0728)
#define LPASS_CDC_VA_TX7_TX_PATH_CTL (VA_START_OFFSET + 0x0780)
#define LPASS_CDC_VA_TX7_TX_PATH_CFG0 (VA_START_OFFSET + 0x0784)
#define LPASS_CDC_VA_TX7_TX_PATH_CFG1 (VA_START_OFFSET + 0x0788)
#define LPASS_CDC_VA_TX7_TX_VOL_CTL (VA_START_OFFSET + 0x078C)
#define LPASS_CDC_VA_TX7_TX_PATH_SEC0 (VA_START_OFFSET + 0x0790)
#define LPASS_CDC_VA_TX7_TX_PATH_SEC1 (VA_START_OFFSET + 0x0794)
#define LPASS_CDC_VA_TX7_TX_PATH_SEC2 (VA_START_OFFSET + 0x0798)
#define LPASS_CDC_VA_TX7_TX_PATH_SEC3 (VA_START_OFFSET + 0x079C)
#define LPASS_CDC_VA_TX7_TX_PATH_SEC4 (VA_START_OFFSET + 0x07A0)
#define LPASS_CDC_VA_TX7_TX_PATH_SEC5 (VA_START_OFFSET + 0x07A4)
#define LPASS_CDC_VA_TX7_TX_PATH_SEC6 (VA_START_OFFSET + 0x07A8)
#define VA_MAX_OFFSET (VA_START_OFFSET + 0x07A8)
#define VA_MAX_OFFSET (VA_START_OFFSET + 0x05A8)
#define LPASS_CDC_VA_MACRO_MAX 0x1EB /* 7A8/4 = 1EA + 1 = 1EB */
#define LPASS_CDC_VA_MACRO_MAX 0x16B /* 5A8/4 = 16A + 1 = 16B */
#define LPASS_CDC_MAX_REGISTER VA_MAX_OFFSET
/* WSA2 - macro#5 */
#define WSA2_START_OFFSET 0x4000
#define LPASS_CDC_WSA2_CLK_RST_CTRL_MCLK_CONTROL \
(WSA2_START_OFFSET + 0x0000)
#define LPASS_CDC_WSA2_CLK_RST_CTRL_FS_CNT_CONTROL \
(WSA2_START_OFFSET + 0x0004)
#define LPASS_CDC_WSA2_CLK_RST_CTRL_SWR_CONTROL (WSA2_START_OFFSET + 0x0008)
#define LPASS_CDC_WSA2_TOP_TOP_CFG0 (WSA2_START_OFFSET + 0x0080)
#define LPASS_CDC_WSA2_TOP_TOP_CFG1 (WSA2_START_OFFSET + 0x0084)
#define LPASS_CDC_WSA2_TOP_FREQ_MCLK (WSA2_START_OFFSET + 0x0088)
#define LPASS_CDC_WSA2_TOP_DEBUG_BUS_SEL (WSA2_START_OFFSET + 0x008C)
#define LPASS_CDC_WSA2_TOP_DEBUG_EN0 (WSA2_START_OFFSET + 0x0090)
#define LPASS_CDC_WSA2_TOP_DEBUG_EN1 (WSA2_START_OFFSET + 0x0094)
#define LPASS_CDC_WSA2_TOP_DEBUG_DSM_LB (WSA2_START_OFFSET + 0x0098)
#define LPASS_CDC_WSA2_TOP_RX_I2S_CTL (WSA2_START_OFFSET + 0x009C)
#define LPASS_CDC_WSA2_TOP_TX_I2S_CTL (WSA2_START_OFFSET + 0x00A0)
#define LPASS_CDC_WSA2_TOP_I2S_CLK (WSA2_START_OFFSET + 0x00A4)
#define LPASS_CDC_WSA2_TOP_I2S_RESET (WSA2_START_OFFSET + 0x00A8)
#define LPASS_CDC_WSA2_TOP_FS_UNGATE (WSA2_START_OFFSET + 0x00AC)
#define LPASS_CDC_WSA2_TOP_GRP_SEL (WSA2_START_OFFSET + 0x00B0)
#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_LSB (WSA2_START_OFFSET + 0x00B4)
#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_MSB (WSA2_START_OFFSET + 0x00B8)
#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_LUT (WSA2_START_OFFSET + 0x00BC)
#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_LSB (WSA2_START_OFFSET + 0x00C0)
#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_MSB (WSA2_START_OFFSET + 0x00C4)
#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_LSB (WSA2_START_OFFSET + 0x00C8)
#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_MSB (WSA2_START_OFFSET + 0x00CC)
#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_LUT (WSA2_START_OFFSET + 0x00D0)
#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_LSB (WSA2_START_OFFSET + 0x00D4)
#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_MSB (WSA2_START_OFFSET + 0x00D8)
#define LPASS_CDC_WSA2_TOP_FS_UNGATE2 (WSA2_START_OFFSET + 0x00DC)
#define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0 (WSA2_START_OFFSET + 0x0100)
#define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG1 (WSA2_START_OFFSET + 0x0104)
#define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG0 (WSA2_START_OFFSET + 0x0108)
#define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG1 (WSA2_START_OFFSET + 0x010C)
#define LPASS_CDC_WSA2_RX_INP_MUX_RX_MIX_CFG0 (WSA2_START_OFFSET + 0x0110)
#define LPASS_CDC_WSA2_RX_INP_MUX_RX_EC_CFG0 (WSA2_START_OFFSET + 0x0114)
#define LPASS_CDC_WSA2_RX_INP_MUX_SOFTCLIP_CFG0 (WSA2_START_OFFSET + 0x0118)
/* VBAT registers */
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_PATH_CTL (WSA2_START_OFFSET + 0x0180)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG (WSA2_START_OFFSET + 0x0184)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL1 (WSA2_START_OFFSET + 0x0188)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL2 (WSA2_START_OFFSET + 0x018C)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL3 (WSA2_START_OFFSET + 0x0190)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST1 (WSA2_START_OFFSET + 0x0194)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST2 (WSA2_START_OFFSET + 0x0198)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST3 (WSA2_START_OFFSET + 0x019C)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC1 (WSA2_START_OFFSET + 0x01A0)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC2 (WSA2_START_OFFSET + 0x01A4)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC1 (WSA2_START_OFFSET + 0x01A8)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC2 (WSA2_START_OFFSET + 0x01AC)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC3 (WSA2_START_OFFSET + 0x01B0)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC4 (WSA2_START_OFFSET + 0x01B4)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD1 (WSA2_START_OFFSET + 0x01B8)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD2 (WSA2_START_OFFSET + 0x01BC)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD3 (WSA2_START_OFFSET + 0x01C0)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD4 (WSA2_START_OFFSET + 0x01C4)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD5 (WSA2_START_OFFSET + 0x01C8)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_DEBUG1 (WSA2_START_OFFSET + 0x01CC)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD_MON \
(WSA2_START_OFFSET + 0x01D0)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_MON_VAL \
(WSA2_START_OFFSET + 0x01D4)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BAN (WSA2_START_OFFSET + 0x01D8)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD1 \
(WSA2_START_OFFSET + 0x01DC)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD2 \
(WSA2_START_OFFSET + 0x01E0)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD3 \
(WSA2_START_OFFSET + 0x01E4)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD4 \
(WSA2_START_OFFSET + 0x01E8)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD5 \
(WSA2_START_OFFSET + 0x01EC)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD6 \
(WSA2_START_OFFSET + 0x01F0)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD7 \
(WSA2_START_OFFSET + 0x01F4)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD8 \
(WSA2_START_OFFSET + 0x01F8)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD9 \
(WSA2_START_OFFSET + 0x01FC)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN1 (WSA2_START_OFFSET + 0x0200)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN2 (WSA2_START_OFFSET + 0x0204)
#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN3 (WSA2_START_OFFSET + 0x0208)
#define LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL (WSA2_START_OFFSET + 0x0244)
#define LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CFG0 (WSA2_START_OFFSET + 0x0248)
#define LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL (WSA2_START_OFFSET + 0x0264)
#define LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CFG0 (WSA2_START_OFFSET + 0x0268)
#define LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL (WSA2_START_OFFSET + 0x0284)
#define LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CFG0 (WSA2_START_OFFSET + 0x0288)
#define LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL (WSA2_START_OFFSET + 0x02A4)
#define LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CFG0 (WSA2_START_OFFSET + 0x02A8)
#define LPASS_CDC_WSA2_INTR_CTRL_CFG (WSA2_START_OFFSET + 0x0340)
#define LPASS_CDC_WSA2_INTR_CTRL_CLR_COMMIT (WSA2_START_OFFSET + 0x0344)
#define LPASS_CDC_WSA2_INTR_CTRL_PIN1_MASK0 (WSA2_START_OFFSET + 0x0360)
#define LPASS_CDC_WSA2_INTR_CTRL_PIN1_STATUS0 (WSA2_START_OFFSET + 0x0368)
#define LPASS_CDC_WSA2_INTR_CTRL_PIN1_CLEAR0 (WSA2_START_OFFSET + 0x0370)
#define LPASS_CDC_WSA2_INTR_CTRL_PIN2_MASK0 (WSA2_START_OFFSET + 0x0380)
#define LPASS_CDC_WSA2_INTR_CTRL_PIN2_STATUS0 (WSA2_START_OFFSET + 0x0388)
#define LPASS_CDC_WSA2_INTR_CTRL_PIN2_CLEAR0 (WSA2_START_OFFSET + 0x0390)
#define LPASS_CDC_WSA2_INTR_CTRL_LEVEL0 (WSA2_START_OFFSET + 0x03C0)
#define LPASS_CDC_WSA2_INTR_CTRL_BYPASS0 (WSA2_START_OFFSET + 0x03C8)
#define LPASS_CDC_WSA2_INTR_CTRL_SET0 (WSA2_START_OFFSET + 0x03D0)
#define LPASS_CDC_WSA2_RX0_RX_PATH_CTL (WSA2_START_OFFSET + 0x0400)
#define LPASS_CDC_WSA2_RX0_RX_PATH_CFG0 (WSA2_START_OFFSET + 0x0404)
#define LPASS_CDC_WSA2_RX0_RX_PATH_CFG1 (WSA2_START_OFFSET + 0x0408)
#define LPASS_CDC_WSA2_RX0_RX_PATH_CFG2 (WSA2_START_OFFSET + 0x040C)
#define LPASS_CDC_WSA2_RX0_RX_PATH_CFG3 (WSA2_START_OFFSET + 0x0410)
#define LPASS_CDC_WSA2_RX0_RX_VOL_CTL (WSA2_START_OFFSET + 0x0414)
#define LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CTL (WSA2_START_OFFSET + 0x0418)
#define LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CFG (WSA2_START_OFFSET + 0x041C)
#define LPASS_CDC_WSA2_RX0_RX_VOL_MIX_CTL (WSA2_START_OFFSET + 0x0420)
#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC0 (WSA2_START_OFFSET + 0x0424)
#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC1 (WSA2_START_OFFSET + 0x0428)
#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC2 (WSA2_START_OFFSET + 0x042C)
#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC3 (WSA2_START_OFFSET + 0x0430)
#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC5 (WSA2_START_OFFSET + 0x0438)
#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC6 (WSA2_START_OFFSET + 0x043C)
#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC7 (WSA2_START_OFFSET + 0x0440)
#define LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC0 (WSA2_START_OFFSET + 0x0444)
#define LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC1 (WSA2_START_OFFSET + 0x0448)
#define LPASS_CDC_WSA2_RX0_RX_PATH_DSMDEM_CTL (WSA2_START_OFFSET + 0x044C)
#define LPASS_CDC_WSA2_RX1_RX_PATH_CTL (WSA2_START_OFFSET + 0x0480)
#define LPASS_CDC_WSA2_RX1_RX_PATH_CFG0 (WSA2_START_OFFSET + 0x0484)
#define LPASS_CDC_WSA2_RX1_RX_PATH_CFG1 (WSA2_START_OFFSET + 0x0488)
#define LPASS_CDC_WSA2_RX1_RX_PATH_CFG2 (WSA2_START_OFFSET + 0x048C)
#define LPASS_CDC_WSA2_RX1_RX_PATH_CFG3 (WSA2_START_OFFSET + 0x0490)
#define LPASS_CDC_WSA2_RX1_RX_VOL_CTL (WSA2_START_OFFSET + 0x0494)
#define LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CTL (WSA2_START_OFFSET + 0x0498)
#define LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CFG (WSA2_START_OFFSET + 0x049C)
#define LPASS_CDC_WSA2_RX1_RX_VOL_MIX_CTL (WSA2_START_OFFSET + 0x04A0)
#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC0 (WSA2_START_OFFSET + 0x04A4)
#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC1 (WSA2_START_OFFSET + 0x04A8)
#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC2 (WSA2_START_OFFSET + 0x04AC)
#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC3 (WSA2_START_OFFSET + 0x04B0)
#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC5 (WSA2_START_OFFSET + 0x04B8)
#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC6 (WSA2_START_OFFSET + 0x04BC)
#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC7 (WSA2_START_OFFSET + 0x04C0)
#define LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC0 (WSA2_START_OFFSET + 0x04C4)
#define LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC1 (WSA2_START_OFFSET + 0x04C8)
#define LPASS_CDC_WSA2_RX1_RX_PATH_DSMDEM_CTL (WSA2_START_OFFSET + 0x04CC)
#define LPASS_CDC_WSA2_BOOST0_BOOST_PATH_CTL (WSA2_START_OFFSET + 0x0500)
#define LPASS_CDC_WSA2_BOOST0_BOOST_CTL (WSA2_START_OFFSET + 0x0504)
#define LPASS_CDC_WSA2_BOOST0_BOOST_CFG1 (WSA2_START_OFFSET + 0x0508)
#define LPASS_CDC_WSA2_BOOST0_BOOST_CFG2 (WSA2_START_OFFSET + 0x050C)
#define LPASS_CDC_WSA2_BOOST1_BOOST_PATH_CTL (WSA2_START_OFFSET + 0x0540)
#define LPASS_CDC_WSA2_BOOST1_BOOST_CTL (WSA2_START_OFFSET + 0x0544)
#define LPASS_CDC_WSA2_BOOST1_BOOST_CFG1 (WSA2_START_OFFSET + 0x0548)
#define LPASS_CDC_WSA2_BOOST1_BOOST_CFG2 (WSA2_START_OFFSET + 0x054C)
#define LPASS_CDC_WSA2_COMPANDER0_CTL0 (WSA2_START_OFFSET + 0x0580)
#define LPASS_CDC_WSA2_COMPANDER0_CTL1 (WSA2_START_OFFSET + 0x0584)
#define LPASS_CDC_WSA2_COMPANDER0_CTL2 (WSA2_START_OFFSET + 0x0588)
#define LPASS_CDC_WSA2_COMPANDER0_CTL3 (WSA2_START_OFFSET + 0x058C)
#define LPASS_CDC_WSA2_COMPANDER0_CTL4 (WSA2_START_OFFSET + 0x0590)
#define LPASS_CDC_WSA2_COMPANDER0_CTL5 (WSA2_START_OFFSET + 0x0594)
#define LPASS_CDC_WSA2_COMPANDER0_CTL6 (WSA2_START_OFFSET + 0x0598)
#define LPASS_CDC_WSA2_COMPANDER0_CTL7 (WSA2_START_OFFSET + 0x059C)
#define LPASS_CDC_WSA2_COMPANDER0_CTL8 (WSA2_START_OFFSET + 0x05A0)
#define LPASS_CDC_WSA2_COMPANDER0_CTL9 (WSA2_START_OFFSET + 0x05A4)
#define LPASS_CDC_WSA2_COMPANDER0_CTL10 (WSA2_START_OFFSET + 0x05A8)
#define LPASS_CDC_WSA2_COMPANDER0_CTL11 (WSA2_START_OFFSET + 0x05AC)
#define LPASS_CDC_WSA2_COMPANDER0_CTL12 (WSA2_START_OFFSET + 0x05B0)
#define LPASS_CDC_WSA2_COMPANDER0_CTL13 (WSA2_START_OFFSET + 0x05B4)
#define LPASS_CDC_WSA2_COMPANDER0_CTL14 (WSA2_START_OFFSET + 0x05B8)
#define LPASS_CDC_WSA2_COMPANDER0_CTL15 (WSA2_START_OFFSET + 0x05BC)
#define LPASS_CDC_WSA2_COMPANDER0_CTL16 (WSA2_START_OFFSET + 0x05C0)
#define LPASS_CDC_WSA2_COMPANDER0_CTL17 (WSA2_START_OFFSET + 0x05C4)
#define LPASS_CDC_WSA2_COMPANDER0_CTL18 (WSA2_START_OFFSET + 0x05C8)
#define LPASS_CDC_WSA2_COMPANDER0_CTL19 (WSA2_START_OFFSET + 0x05CC)
#define LPASS_CDC_WSA2_COMPANDER1_CTL0 (WSA2_START_OFFSET + 0x05E0)
#define LPASS_CDC_WSA2_COMPANDER1_CTL1 (WSA2_START_OFFSET + 0x05E4)
#define LPASS_CDC_WSA2_COMPANDER1_CTL2 (WSA2_START_OFFSET + 0x05E8)
#define LPASS_CDC_WSA2_COMPANDER1_CTL3 (WSA2_START_OFFSET + 0x05EC)
#define LPASS_CDC_WSA2_COMPANDER1_CTL4 (WSA2_START_OFFSET + 0x05F0)
#define LPASS_CDC_WSA2_COMPANDER1_CTL5 (WSA2_START_OFFSET + 0x05F4)
#define LPASS_CDC_WSA2_COMPANDER1_CTL6 (WSA2_START_OFFSET + 0x05F8)
#define LPASS_CDC_WSA2_COMPANDER1_CTL7 (WSA2_START_OFFSET + 0x05FC)
#define LPASS_CDC_WSA2_COMPANDER1_CTL8 (WSA2_START_OFFSET + 0x0600)
#define LPASS_CDC_WSA2_COMPANDER1_CTL9 (WSA2_START_OFFSET + 0x0604)
#define LPASS_CDC_WSA2_COMPANDER1_CTL10 (WSA2_START_OFFSET + 0x0608)
#define LPASS_CDC_WSA2_COMPANDER1_CTL11 (WSA2_START_OFFSET + 0x060C)
#define LPASS_CDC_WSA2_COMPANDER1_CTL12 (WSA2_START_OFFSET + 0x0610)
#define LPASS_CDC_WSA2_COMPANDER1_CTL13 (WSA2_START_OFFSET + 0x0614)
#define LPASS_CDC_WSA2_COMPANDER1_CTL14 (WSA2_START_OFFSET + 0x0618)
#define LPASS_CDC_WSA2_COMPANDER1_CTL15 (WSA2_START_OFFSET + 0x061C)
#define LPASS_CDC_WSA2_COMPANDER1_CTL16 (WSA2_START_OFFSET + 0x0620)
#define LPASS_CDC_WSA2_COMPANDER1_CTL17 (WSA2_START_OFFSET + 0x0624)
#define LPASS_CDC_WSA2_COMPANDER1_CTL18 (WSA2_START_OFFSET + 0x0628)
#define LPASS_CDC_WSA2_COMPANDER1_CTL19 (WSA2_START_OFFSET + 0x062C)
#define LPASS_CDC_WSA2_SOFTCLIP0_CRC (WSA2_START_OFFSET + 0x0640)
#define LPASS_CDC_WSA2_SOFTCLIP0_SOFTCLIP_CTRL (WSA2_START_OFFSET + 0x0644)
#define LPASS_CDC_WSA2_SOFTCLIP1_CRC (WSA2_START_OFFSET + 0x0660)
#define LPASS_CDC_WSA2_SOFTCLIP1_SOFTCLIP_CTRL (WSA2_START_OFFSET + 0x0664)
#define LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_PATH_CTL \
(WSA2_START_OFFSET + 0x0680)
#define LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_CFG0 (WSA2_START_OFFSET + 0x0684)
#define LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_PATH_CTL \
(WSA2_START_OFFSET + 0x06C0)
#define LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_CFG0 (WSA2_START_OFFSET + 0x06C4)
#define LPASS_CDC_WSA2_IDLE_DETECT_PATH_CTL (WSA2_START_OFFSET + 0x0780)
#define LPASS_CDC_WSA2_IDLE_DETECT_CFG0 (WSA2_START_OFFSET + 0x0784)
#define LPASS_CDC_WSA2_IDLE_DETECT_CFG1 (WSA2_START_OFFSET + 0x0788)
#define LPASS_CDC_WSA2_IDLE_DETECT_CFG2 (WSA2_START_OFFSET + 0x078C)
#define LPASS_CDC_WSA2_IDLE_DETECT_CFG3 (WSA2_START_OFFSET + 0x0790)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL1 (WSA2_START_OFFSET + 0x0900)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL2 (WSA2_START_OFFSET + 0x0904)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL3 (WSA2_START_OFFSET + 0x0908)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG1 (WSA2_START_OFFSET + 0x090C)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG2 (WSA2_START_OFFSET + 0x0910)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG3 (WSA2_START_OFFSET + 0x0914)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG4 (WSA2_START_OFFSET + 0x0918)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG5 (WSA2_START_OFFSET + 0x091C)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG6 (WSA2_START_OFFSET + 0x0920)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG7 (WSA2_START_OFFSET + 0x0924)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG8 (WSA2_START_OFFSET + 0x0928)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST1 \
(WSA2_START_OFFSET + 0x092C)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST2 \
(WSA2_START_OFFSET + 0x0930)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST3 \
(WSA2_START_OFFSET + 0x0934)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST4 \
(WSA2_START_OFFSET + 0x0938)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST1 (WSA2_START_OFFSET + 0x093C)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST2 (WSA2_START_OFFSET + 0x0940)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST3 (WSA2_START_OFFSET + 0x0944)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST4 (WSA2_START_OFFSET + 0x0948)
#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST5 (WSA2_START_OFFSET + 0x094C)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PATH_CTL (WSA2_START_OFFSET + 0x0980)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_CFG (WSA2_START_OFFSET + 0x0984)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL1 (WSA2_START_OFFSET + 0x0988)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL2 (WSA2_START_OFFSET + 0x098C)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL3 (WSA2_START_OFFSET + 0x0990)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST1 (WSA2_START_OFFSET + 0x0994)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST2 (WSA2_START_OFFSET + 0x0998)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST3 (WSA2_START_OFFSET + 0x099C)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC1 (WSA2_START_OFFSET + 0x09A0)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC2 (WSA2_START_OFFSET + 0x09A4)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC1 (WSA2_START_OFFSET + 0x09A8)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC2 (WSA2_START_OFFSET + 0x09AC)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC3 (WSA2_START_OFFSET + 0x09B0)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC4 (WSA2_START_OFFSET + 0x09B4)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD1 (WSA2_START_OFFSET + 0x09B8)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD2 (WSA2_START_OFFSET + 0x09BC)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD3 (WSA2_START_OFFSET + 0x09C0)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD4 (WSA2_START_OFFSET + 0x09C4)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD5 (WSA2_START_OFFSET + 0x09C8)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_DEBUG1 (WSA2_START_OFFSET + 0x09CC)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD_MON \
(WSA2_START_OFFSET + 0x09D0)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_MON_VAL \
(WSA2_START_OFFSET + 0x09D4)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BAN (WSA2_START_OFFSET + 0x09D8)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD1 \
(WSA2_START_OFFSET + 0x09DC)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD2 \
(WSA2_START_OFFSET + 0x09E0)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD3 \
(WSA2_START_OFFSET + 0x09E4)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD4 \
(WSA2_START_OFFSET + 0x09E8)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD5 \
(WSA2_START_OFFSET + 0x09EC)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD6 \
(WSA2_START_OFFSET + 0x09F0)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD7 \
(WSA2_START_OFFSET + 0x09F4)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD8 \
(WSA2_START_OFFSET + 0x09F8)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD9 \
(WSA2_START_OFFSET + 0x09FC)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN1 (WSA2_START_OFFSET + 0x0A00)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN2 (WSA2_START_OFFSET + 0x0A04)
#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN3 (WSA2_START_OFFSET + 0x0A08)
#define WSA2_MAX_OFFSET (WSA2_START_OFFSET + 0x0A08)
#define LPASS_CDC_WSA2_MACRO_MAX 0x283 /* 0xA08/4 = 0x282 + 1 registers */
#define LPASS_CDC_MAX_REGISTER WSA2_MAX_OFFSET
#define LPASS_CDC_REG(reg) (((reg) & 0x0FFF)/4)

576
asoc/codecs/lpass-cdc/lpass-cdc-regmap.c
View File

@@ -13,19 +13,18 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
{ LPASS_CDC_TX_TOP_CSR_ANC_CFG, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0x60},
{ LPASS_CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
{ LPASS_CDC_TX_TOP_CSR_DEBUG_EN, 0x00},
{ LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C},
{ LPASS_CDC_TX_TOP_CSR_I2S_CLK, 0x00},
{ LPASS_CDC_TX_TOP_CSR_I2S_RESET, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL, 0x0E},
{ LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
{ LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
{ LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},
@@ -150,6 +149,7 @@ static const struct reg_default lpass_cdc_defaults[] = {
/* RX Macro */
{ LPASS_CDC_RX_TOP_TOP_CFG0, 0x00},
{ LPASS_CDC_RX_TOP_TOP_CFG1, 0x00},
{ LPASS_CDC_RX_TOP_SWR_CTRL, 0x00},
{ LPASS_CDC_RX_TOP_DEBUG, 0x00},
{ LPASS_CDC_RX_TOP_DEBUG_BUS, 0x00},
@@ -169,11 +169,11 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11},
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20},
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00},
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00},
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x08},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x08},
{ LPASS_CDC_RX_TOP_RX_I2S_CTL, 0x0C},
{ LPASS_CDC_RX_TOP_TX_I2S2_CTL, 0x0C},
{ LPASS_CDC_RX_TOP_I2S_CLK, 0x0C},
@@ -250,13 +250,6 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_BCL_VBAT_ATTN1, 0x04},
{ LPASS_CDC_RX_BCL_VBAT_ATTN2, 0x08},
{ LPASS_CDC_RX_BCL_VBAT_ATTN3, 0x0C},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_ST, 0x00},
{ LPASS_CDC_RX_INTR_CTRL_CFG, 0x00},
{ LPASS_CDC_RX_INTR_CTRL_CLR_COMMIT, 0x00},
{ LPASS_CDC_RX_INTR_CTRL_PIN1_MASK0, 0xFF},
@@ -272,7 +265,7 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_RX0_RX_PATH_CFG0, 0x00},
{ LPASS_CDC_RX_RX0_RX_PATH_CFG1, 0x64},
{ LPASS_CDC_RX_RX0_RX_PATH_CFG2, 0x8F},
{ LPASS_CDC_RX_RX0_RX_PATH_CFG3, 0x00},
{ LPASS_CDC_RX_RX0_RX_PATH_CFG3, 0x03},
{ LPASS_CDC_RX_RX0_RX_VOL_CTL, 0x00},
{ LPASS_CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04},
{ LPASS_CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E},
@@ -291,11 +284,22 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55},
{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55},
{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55},
{ LPASS_CDC_RX_RX0_RX_FIR_CTL, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_CFG, 0x64},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7, 0x00},
{ LPASS_CDC_RX_RX1_RX_PATH_CTL, 0x04},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG0, 0x00},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG1, 0x64},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG2, 0x8F},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG3, 0x00},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG3, 0x03},
{ LPASS_CDC_RX_RX1_RX_VOL_CTL, 0x00},
{ LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04},
{ LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E},
@@ -314,11 +318,22 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55},
{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55},
{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55},
{ LPASS_CDC_RX_RX1_RX_FIR_CTL, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_CFG, 0x64},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_CTL, 0x04},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG0, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG1, 0x64},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG2, 0x8F},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG3, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG3, 0x03},
{ LPASS_CDC_RX_RX2_RX_VOL_CTL, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04},
{ LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E},
@@ -334,6 +349,61 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08},
{ LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1, 0x85},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2, 0xDC},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3, 0x85},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4, 0xDC},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5, 0x85},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6, 0xDC},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7, 0x32},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG, 0x10},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3, 0x04},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1, 0xE0},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3, 0x40},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1, 0x2A},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2, 0x18},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3, 0x18},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4, 0x03},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4, 0x64},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN, 0x0C},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2, 0x77},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5, 0x4B},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1, 0x04},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2, 0x08},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3, 0x0C},
{ LPASS_CDC_RX_IDLE_DETECT_PATH_CTL, 0x00},
{ LPASS_CDC_RX_IDLE_DETECT_CFG0, 0x07},
{ LPASS_CDC_RX_IDLE_DETECT_CFG1, 0x3C},
@@ -347,6 +417,18 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_COMPANDER0_CTL5, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL6, 0x01},
{ LPASS_CDC_RX_COMPANDER0_CTL7, 0x28},
{ LPASS_CDC_RX_COMPANDER0_CTL8, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL9, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL10, 0x06},
{ LPASS_CDC_RX_COMPANDER0_CTL11, 0x12},
{ LPASS_CDC_RX_COMPANDER0_CTL12, 0x1E},
{ LPASS_CDC_RX_COMPANDER0_CTL13, 0x2A},
{ LPASS_CDC_RX_COMPANDER0_CTL14, 0x36},
{ LPASS_CDC_RX_COMPANDER0_CTL15, 0x3C},
{ LPASS_CDC_RX_COMPANDER0_CTL16, 0xC4},
{ LPASS_CDC_RX_COMPANDER0_CTL17, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL18, 0x0C},
{ LPASS_CDC_RX_COMPANDER0_CTL19, 0x16},
{ LPASS_CDC_RX_COMPANDER1_CTL0, 0x60},
{ LPASS_CDC_RX_COMPANDER1_CTL1, 0xDB},
{ LPASS_CDC_RX_COMPANDER1_CTL2, 0xFF},
@@ -355,6 +437,18 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_COMPANDER1_CTL5, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL6, 0x01},
{ LPASS_CDC_RX_COMPANDER1_CTL7, 0x28},
{ LPASS_CDC_RX_COMPANDER1_CTL8, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL9, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL10, 0x06},
{ LPASS_CDC_RX_COMPANDER1_CTL11, 0x12},
{ LPASS_CDC_RX_COMPANDER1_CTL12, 0x1E},
{ LPASS_CDC_RX_COMPANDER1_CTL13, 0x2A},
{ LPASS_CDC_RX_COMPANDER1_CTL14, 0x36},
{ LPASS_CDC_RX_COMPANDER1_CTL15, 0x3C},
{ LPASS_CDC_RX_COMPANDER1_CTL16, 0xC4},
{ LPASS_CDC_RX_COMPANDER1_CTL17, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL18, 0x0C},
{ LPASS_CDC_RX_COMPANDER1_CTL19, 0x16},
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00},
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00},
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00},
@@ -450,6 +544,19 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_WSA_TOP_TX_I2S_CTL, 0x0C},
{ LPASS_CDC_WSA_TOP_I2S_CLK, 0x02},
{ LPASS_CDC_WSA_TOP_I2S_RESET, 0x00},
{ LPASS_CDC_WSA_TOP_FS_UNGATE, 0xFF},
{ LPASS_CDC_WSA_TOP_GRP_SEL, 0x08},
{ LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_LSB, 0x00},
{ LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_MSB, 0x00},
{ LPASS_CDC_WSA_TOP_SPKR_COMP7_LUT, 0x00},
{ LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_LSB, 0x00},
{ LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_MSB, 0x00},
{ LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_LSB, 0x00},
{ LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_MSB, 0x00},
{ LPASS_CDC_WSA_TOP_SPKR_COMP8_LUT, 0x00},
{ LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_LSB, 0x00},
{ LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_MSB, 0x00},
{ LPASS_CDC_WSA_TOP_FS_UNGATE2, 0x03},
{ LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00},
{ LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00},
{ LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00},
@@ -492,13 +599,6 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1, 0x04},
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2, 0x08},
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3, 0x0C},
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1, 0xE0},
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2, 0x00},
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1, 0x00},
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2, 0x00},
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3, 0x00},
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4, 0x00},
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST, 0x00},
{ LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02},
{ LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00},
{ LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02},
@@ -571,6 +671,18 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_WSA_COMPANDER0_CTL5, 0x00},
{ LPASS_CDC_WSA_COMPANDER0_CTL6, 0x01},
{ LPASS_CDC_WSA_COMPANDER0_CTL7, 0x28},
{ LPASS_CDC_WSA_COMPANDER0_CTL8, 0x00},
{ LPASS_CDC_WSA_COMPANDER0_CTL9, 0x00},
{ LPASS_CDC_WSA_COMPANDER0_CTL10, 0x06},
{ LPASS_CDC_WSA_COMPANDER0_CTL11, 0x12},
{ LPASS_CDC_WSA_COMPANDER0_CTL12, 0x1E},
{ LPASS_CDC_WSA_COMPANDER0_CTL13, 0x24},
{ LPASS_CDC_WSA_COMPANDER0_CTL14, 0x24},
{ LPASS_CDC_WSA_COMPANDER0_CTL15, 0x24},
{ LPASS_CDC_WSA_COMPANDER0_CTL16, 0x00},
{ LPASS_CDC_WSA_COMPANDER0_CTL17, 0x24},
{ LPASS_CDC_WSA_COMPANDER0_CTL18, 0x2A},
{ LPASS_CDC_WSA_COMPANDER0_CTL19, 0x16},
{ LPASS_CDC_WSA_COMPANDER1_CTL0, 0x60},
{ LPASS_CDC_WSA_COMPANDER1_CTL1, 0xDB},
{ LPASS_CDC_WSA_COMPANDER1_CTL2, 0xFF},
@@ -579,6 +691,18 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_WSA_COMPANDER1_CTL5, 0x00},
{ LPASS_CDC_WSA_COMPANDER1_CTL6, 0x01},
{ LPASS_CDC_WSA_COMPANDER1_CTL7, 0x28},
{ LPASS_CDC_WSA_COMPANDER1_CTL8, 0x00},
{ LPASS_CDC_WSA_COMPANDER1_CTL9, 0x00},
{ LPASS_CDC_WSA_COMPANDER1_CTL10, 0x06},
{ LPASS_CDC_WSA_COMPANDER1_CTL11, 0x12},
{ LPASS_CDC_WSA_COMPANDER1_CTL12, 0x1E},
{ LPASS_CDC_WSA_COMPANDER1_CTL13, 0x24},
{ LPASS_CDC_WSA_COMPANDER1_CTL14, 0x24},
{ LPASS_CDC_WSA_COMPANDER1_CTL15, 0x24},
{ LPASS_CDC_WSA_COMPANDER1_CTL16, 0x00},
{ LPASS_CDC_WSA_COMPANDER1_CTL17, 0x24},
{ LPASS_CDC_WSA_COMPANDER1_CTL18, 0x2A},
{ LPASS_CDC_WSA_COMPANDER1_CTL19, 0x16},
{ LPASS_CDC_WSA_SOFTCLIP0_CRC, 0x00},
{ LPASS_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38},
{ LPASS_CDC_WSA_SOFTCLIP1_CRC, 0x00},
@@ -587,24 +711,66 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01},
{ LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00},
{ LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01},
{ LPASS_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00},
{ LPASS_CDC_WSA_SPLINE_ASRC0_CTL0, 0x00},
{ LPASS_CDC_WSA_SPLINE_ASRC0_CTL1, 0x00},
{ LPASS_CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8},
{ LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00},
{ LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00},
{ LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00},
{ LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00},
{ LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00},
{ LPASS_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00},
{ LPASS_CDC_WSA_SPLINE_ASRC1_CTL0, 0x00},
{ LPASS_CDC_WSA_SPLINE_ASRC1_CTL1, 0x00},
{ LPASS_CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8},
{ LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00},
{ LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00},
{ LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00},
{ LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00},
{ LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00},
{ LPASS_CDC_WSA_IDLE_DETECT_PATH_CTL, 0x00},
{ LPASS_CDC_WSA_IDLE_DETECT_CFG0, 0x07},
{ LPASS_CDC_WSA_IDLE_DETECT_CFG1, 0x3C},
{ LPASS_CDC_WSA_IDLE_DETECT_CFG2, 0x00},
{ LPASS_CDC_WSA_IDLE_DETECT_CFG3, 0x00},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL1, 0x00},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL2, 0x00},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL3, 0x00},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG1, 0x85},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG2, 0xDC},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG3, 0x85},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG4, 0xDC},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG5, 0x85},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG6, 0xDC},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG7, 0x32},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG8, 0x00},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST1, 0x00},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST2, 0x00},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST3, 0x00},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST4, 0x00},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST1, 0x00},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST2, 0x00},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST3, 0x00},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST4, 0x00},
{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST5, 0x00},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_PATH_CTL, 0x00},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_CFG, 0x10},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL1, 0x00},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL2, 0x00},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL3, 0x04},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST1, 0xE0},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST2, 0x01},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST3, 0x40},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC1, 0x2A},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC1, 0x00},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC1, 0x00},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC2, 0x18},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC3, 0x18},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC4, 0x03},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD1, 0x01},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD2, 0x00},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD3, 0x00},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD4, 0x64},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD5, 0x01},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_DEBUG1, 0x00},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD_MON, 0x00},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_MON_VAL, 0x00},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BAN, 0x0C},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD1, 0x00},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD2, 0x77},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD3, 0x01},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD4, 0x00},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD5, 0x4B},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD6, 0x00},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD7, 0x01},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD8, 0x00},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD9, 0x00},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN1, 0x04},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN2, 0x08},
{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN3, 0x0C},
/* VA macro */
{ LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
@@ -639,14 +805,6 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00},
{ LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00},
{ LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00},
{ LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG0, 0x00},
{ LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG1, 0x00},
{ LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG0, 0x00},
{ LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG1, 0x00},
{ LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG0, 0x00},
{ LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG1, 0x00},
{ LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG0, 0x00},
{ LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG1, 0x00},
{ LPASS_CDC_VA_TX0_TX_PATH_CTL, 0x04},
{ LPASS_CDC_VA_TX0_TX_PATH_CFG0, 0x10},
{ LPASS_CDC_VA_TX0_TX_PATH_CFG1, 0x0B},
@@ -692,50 +850,249 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_VA_TX3_TX_PATH_SEC4, 0x20},
{ LPASS_CDC_VA_TX3_TX_PATH_SEC5, 0x00},
{ LPASS_CDC_VA_TX3_TX_PATH_SEC6, 0x00},
{ LPASS_CDC_VA_TX4_TX_PATH_CTL, 0x04},
{ LPASS_CDC_VA_TX4_TX_PATH_CFG0, 0x10},
{ LPASS_CDC_VA_TX4_TX_PATH_CFG1, 0x0B},
{ LPASS_CDC_VA_TX4_TX_VOL_CTL, 0x00},
{ LPASS_CDC_VA_TX4_TX_PATH_SEC0, 0x00},
{ LPASS_CDC_VA_TX4_TX_PATH_SEC1, 0x00},
{ LPASS_CDC_VA_TX4_TX_PATH_SEC2, 0x01},
{ LPASS_CDC_VA_TX4_TX_PATH_SEC3, 0x3C},
{ LPASS_CDC_VA_TX4_TX_PATH_SEC4, 0x20},
{ LPASS_CDC_VA_TX4_TX_PATH_SEC5, 0x00},
{ LPASS_CDC_VA_TX4_TX_PATH_SEC6, 0x00},
{ LPASS_CDC_VA_TX5_TX_PATH_CTL, 0x04},
{ LPASS_CDC_VA_TX5_TX_PATH_CFG0, 0x10},
{ LPASS_CDC_VA_TX5_TX_PATH_CFG1, 0x0B},
{ LPASS_CDC_VA_TX5_TX_VOL_CTL, 0x00},
{ LPASS_CDC_VA_TX5_TX_PATH_SEC0, 0x00},
{ LPASS_CDC_VA_TX5_TX_PATH_SEC1, 0x00},
{ LPASS_CDC_VA_TX5_TX_PATH_SEC2, 0x01},
{ LPASS_CDC_VA_TX5_TX_PATH_SEC3, 0x3C},
{ LPASS_CDC_VA_TX5_TX_PATH_SEC4, 0x20},
{ LPASS_CDC_VA_TX5_TX_PATH_SEC5, 0x00},
{ LPASS_CDC_VA_TX5_TX_PATH_SEC6, 0x00},
{ LPASS_CDC_VA_TX6_TX_PATH_CTL, 0x04},
{ LPASS_CDC_VA_TX6_TX_PATH_CFG0, 0x10},
{ LPASS_CDC_VA_TX6_TX_PATH_CFG1, 0x0B},
{ LPASS_CDC_VA_TX6_TX_VOL_CTL, 0x00},
{ LPASS_CDC_VA_TX6_TX_PATH_SEC0, 0x00},
{ LPASS_CDC_VA_TX6_TX_PATH_SEC1, 0x00},
{ LPASS_CDC_VA_TX6_TX_PATH_SEC2, 0x01},
{ LPASS_CDC_VA_TX6_TX_PATH_SEC3, 0x3C},
{ LPASS_CDC_VA_TX6_TX_PATH_SEC4, 0x20},
{ LPASS_CDC_VA_TX6_TX_PATH_SEC5, 0x00},
{ LPASS_CDC_VA_TX6_TX_PATH_SEC6, 0x00},
{ LPASS_CDC_VA_TX7_TX_PATH_CTL, 0x04},
{ LPASS_CDC_VA_TX7_TX_PATH_CFG0, 0x10},
{ LPASS_CDC_VA_TX7_TX_PATH_CFG1, 0x0B},
{ LPASS_CDC_VA_TX7_TX_VOL_CTL, 0x00},
{ LPASS_CDC_VA_TX7_TX_PATH_SEC0, 0x00},
{ LPASS_CDC_VA_TX7_TX_PATH_SEC1, 0x00},
{ LPASS_CDC_VA_TX7_TX_PATH_SEC2, 0x01},
{ LPASS_CDC_VA_TX7_TX_PATH_SEC3, 0x3C},
{ LPASS_CDC_VA_TX7_TX_PATH_SEC4, 0x20},
{ LPASS_CDC_VA_TX7_TX_PATH_SEC5, 0x00},
{ LPASS_CDC_VA_TX7_TX_PATH_SEC6, 0x00},
/* WSA2 Macro */
{ LPASS_CDC_WSA2_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
{ LPASS_CDC_WSA2_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
{ LPASS_CDC_WSA2_CLK_RST_CTRL_SWR_CONTROL, 0x00},
{ LPASS_CDC_WSA2_TOP_TOP_CFG0, 0x00},
{ LPASS_CDC_WSA2_TOP_TOP_CFG1, 0x00},
{ LPASS_CDC_WSA2_TOP_FREQ_MCLK, 0x00},
{ LPASS_CDC_WSA2_TOP_DEBUG_BUS_SEL, 0x00},
{ LPASS_CDC_WSA2_TOP_DEBUG_EN0, 0x00},
{ LPASS_CDC_WSA2_TOP_DEBUG_EN1, 0x00},
{ LPASS_CDC_WSA2_TOP_DEBUG_DSM_LB, 0x88},
{ LPASS_CDC_WSA2_TOP_RX_I2S_CTL, 0x0C},
{ LPASS_CDC_WSA2_TOP_TX_I2S_CTL, 0x0C},
{ LPASS_CDC_WSA2_TOP_I2S_CLK, 0x02},
{ LPASS_CDC_WSA2_TOP_I2S_RESET, 0x00},
{ LPASS_CDC_WSA2_TOP_FS_UNGATE, 0xFF},
{ LPASS_CDC_WSA2_TOP_GRP_SEL, 0x08},
{ LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_LSB, 0x00},
{ LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_MSB, 0x00},
{ LPASS_CDC_WSA2_TOP_SPKR_COMP7_LUT, 0x00},
{ LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_LSB, 0x00},
{ LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_MSB, 0x00},
{ LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_LSB, 0x00},
{ LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_MSB, 0x00},
{ LPASS_CDC_WSA2_TOP_SPKR_COMP8_LUT, 0x00},
{ LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_LSB, 0x00},
{ LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_MSB, 0x00},
{ LPASS_CDC_WSA2_TOP_FS_UNGATE2, 0x03},
{ LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0, 0x00},
{ LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG1, 0x00},
{ LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG0, 0x00},
{ LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG1, 0x00},
{ LPASS_CDC_WSA2_RX_INP_MUX_RX_MIX_CFG0, 0x00},
{ LPASS_CDC_WSA2_RX_INP_MUX_RX_EC_CFG0, 0x00},
{ LPASS_CDC_WSA2_RX_INP_MUX_SOFTCLIP_CFG0, 0x00},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_PATH_CTL, 0x00},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG, 0x10},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL1, 0x00},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL2, 0x00},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL3, 0x04},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST1, 0xE0},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST2, 0x01},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST3, 0x40},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC1, 0x2A},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC2, 0x00},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC1, 0x00},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC2, 0x18},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC3, 0x18},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC4, 0x03},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD1, 0x01},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD2, 0x00},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD3, 0x00},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD4, 0x64},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD5, 0x01},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_DEBUG1, 0x00},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD_MON, 0x00},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_MON_VAL, 0x00},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BAN, 0x0C},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD1, 0x00},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD2, 0x77},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD3, 0x01},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD4, 0x00},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD5, 0x4B},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD6, 0x00},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD7, 0x01},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD8, 0x00},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD9, 0x00},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN1, 0x04},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN2, 0x08},
{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN3, 0x0C},
{ LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL, 0x02},
{ LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CFG0, 0x00},
{ LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL, 0x02},
{ LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CFG0, 0x00},
{ LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL, 0x02},
{ LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CFG0, 0x00},
{ LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL, 0x02},
{ LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CFG0, 0x00},
{ LPASS_CDC_WSA2_INTR_CTRL_CFG, 0x00},
{ LPASS_CDC_WSA2_INTR_CTRL_CLR_COMMIT, 0x00},
{ LPASS_CDC_WSA2_INTR_CTRL_PIN1_MASK0, 0xFF},
{ LPASS_CDC_WSA2_INTR_CTRL_PIN1_STATUS0, 0x00},
{ LPASS_CDC_WSA2_INTR_CTRL_PIN1_CLEAR0, 0x00},
{ LPASS_CDC_WSA2_INTR_CTRL_PIN2_MASK0, 0xFF},
{ LPASS_CDC_WSA2_INTR_CTRL_PIN2_STATUS0, 0x00},
{ LPASS_CDC_WSA2_INTR_CTRL_PIN2_CLEAR0, 0x00},
{ LPASS_CDC_WSA2_INTR_CTRL_LEVEL0, 0x00},
{ LPASS_CDC_WSA2_INTR_CTRL_BYPASS0, 0x00},
{ LPASS_CDC_WSA2_INTR_CTRL_SET0, 0x00},
{ LPASS_CDC_WSA2_RX0_RX_PATH_CTL, 0x04},
{ LPASS_CDC_WSA2_RX0_RX_PATH_CFG0, 0x00},
{ LPASS_CDC_WSA2_RX0_RX_PATH_CFG1, 0x64},
{ LPASS_CDC_WSA2_RX0_RX_PATH_CFG2, 0x8F},
{ LPASS_CDC_WSA2_RX0_RX_PATH_CFG3, 0x00},
{ LPASS_CDC_WSA2_RX0_RX_VOL_CTL, 0x00},
{ LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CTL, 0x04},
{ LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CFG, 0x7E},
{ LPASS_CDC_WSA2_RX0_RX_VOL_MIX_CTL, 0x00},
{ LPASS_CDC_WSA2_RX0_RX_PATH_SEC0, 0x04},
{ LPASS_CDC_WSA2_RX0_RX_PATH_SEC1, 0x08},
{ LPASS_CDC_WSA2_RX0_RX_PATH_SEC2, 0x00},
{ LPASS_CDC_WSA2_RX0_RX_PATH_SEC3, 0x00},
{ LPASS_CDC_WSA2_RX0_RX_PATH_SEC5, 0x00},
{ LPASS_CDC_WSA2_RX0_RX_PATH_SEC6, 0x00},
{ LPASS_CDC_WSA2_RX0_RX_PATH_SEC7, 0x00},
{ LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC0, 0x08},
{ LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC1, 0x00},
{ LPASS_CDC_WSA2_RX0_RX_PATH_DSMDEM_CTL, 0x00},
{ LPASS_CDC_WSA2_RX1_RX_PATH_CFG0, 0x00},
{ LPASS_CDC_WSA2_RX1_RX_PATH_CFG1, 0x64},
{ LPASS_CDC_WSA2_RX1_RX_PATH_CFG2, 0x8F},
{ LPASS_CDC_WSA2_RX1_RX_PATH_CFG3, 0x00},
{ LPASS_CDC_WSA2_RX1_RX_VOL_CTL, 0x00},
{ LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CTL, 0x04},
{ LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CFG, 0x7E},
{ LPASS_CDC_WSA2_RX1_RX_VOL_MIX_CTL, 0x00},
{ LPASS_CDC_WSA2_RX1_RX_PATH_SEC0, 0x04},
{ LPASS_CDC_WSA2_RX1_RX_PATH_SEC1, 0x08},
{ LPASS_CDC_WSA2_RX1_RX_PATH_SEC2, 0x00},
{ LPASS_CDC_WSA2_RX1_RX_PATH_SEC3, 0x00},
{ LPASS_CDC_WSA2_RX1_RX_PATH_SEC5, 0x00},
{ LPASS_CDC_WSA2_RX1_RX_PATH_SEC6, 0x00},
{ LPASS_CDC_WSA2_RX1_RX_PATH_SEC7, 0x00},
{ LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC0, 0x08},
{ LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC1, 0x00},
{ LPASS_CDC_WSA2_RX1_RX_PATH_DSMDEM_CTL, 0x00},
{ LPASS_CDC_WSA2_BOOST0_BOOST_PATH_CTL, 0x00},
{ LPASS_CDC_WSA2_BOOST0_BOOST_CTL, 0xD0},
{ LPASS_CDC_WSA2_BOOST0_BOOST_CFG1, 0x89},
{ LPASS_CDC_WSA2_BOOST0_BOOST_CFG2, 0x04},
{ LPASS_CDC_WSA2_BOOST1_BOOST_PATH_CTL, 0x00},
{ LPASS_CDC_WSA2_BOOST1_BOOST_CTL, 0xD0},
{ LPASS_CDC_WSA2_BOOST1_BOOST_CFG1, 0x89},
{ LPASS_CDC_WSA2_BOOST1_BOOST_CFG2, 0x04},
{ LPASS_CDC_WSA2_COMPANDER0_CTL0, 0x60},
{ LPASS_CDC_WSA2_COMPANDER0_CTL1, 0xDB},
{ LPASS_CDC_WSA2_COMPANDER0_CTL2, 0xFF},
{ LPASS_CDC_WSA2_COMPANDER0_CTL3, 0x35},
{ LPASS_CDC_WSA2_COMPANDER0_CTL4, 0xFF},
{ LPASS_CDC_WSA2_COMPANDER0_CTL5, 0x00},
{ LPASS_CDC_WSA2_COMPANDER0_CTL6, 0x01},
{ LPASS_CDC_WSA2_COMPANDER0_CTL7, 0x28},
{ LPASS_CDC_WSA2_COMPANDER0_CTL8, 0x00},
{ LPASS_CDC_WSA2_COMPANDER0_CTL9, 0x00},
{ LPASS_CDC_WSA2_COMPANDER0_CTL10, 0x06},
{ LPASS_CDC_WSA2_COMPANDER0_CTL11, 0x12},
{ LPASS_CDC_WSA2_COMPANDER0_CTL12, 0x1E},
{ LPASS_CDC_WSA2_COMPANDER0_CTL13, 0x24},
{ LPASS_CDC_WSA2_COMPANDER0_CTL14, 0x24},
{ LPASS_CDC_WSA2_COMPANDER0_CTL15, 0x24},
{ LPASS_CDC_WSA2_COMPANDER0_CTL16, 0x00},
{ LPASS_CDC_WSA2_COMPANDER0_CTL17, 0x24},
{ LPASS_CDC_WSA2_COMPANDER0_CTL18, 0x2A},
{ LPASS_CDC_WSA2_COMPANDER0_CTL19, 0x16},
{ LPASS_CDC_WSA2_COMPANDER1_CTL0, 0x60},
{ LPASS_CDC_WSA2_COMPANDER1_CTL1, 0xDB},
{ LPASS_CDC_WSA2_COMPANDER1_CTL2, 0xFF},
{ LPASS_CDC_WSA2_COMPANDER1_CTL3, 0x35},
{ LPASS_CDC_WSA2_COMPANDER1_CTL4, 0xFF},
{ LPASS_CDC_WSA2_COMPANDER1_CTL5, 0x00},
{ LPASS_CDC_WSA2_COMPANDER1_CTL6, 0x01},
{ LPASS_CDC_WSA2_COMPANDER1_CTL7, 0x28},
{ LPASS_CDC_WSA2_COMPANDER1_CTL8, 0x00},
{ LPASS_CDC_WSA2_COMPANDER1_CTL9, 0x00},
{ LPASS_CDC_WSA2_COMPANDER1_CTL10, 0x06},
{ LPASS_CDC_WSA2_COMPANDER1_CTL11, 0x12},
{ LPASS_CDC_WSA2_COMPANDER1_CTL12, 0x1E},
{ LPASS_CDC_WSA2_COMPANDER1_CTL13, 0x24},
{ LPASS_CDC_WSA2_COMPANDER1_CTL14, 0x24},
{ LPASS_CDC_WSA2_COMPANDER1_CTL15, 0x24},
{ LPASS_CDC_WSA2_COMPANDER1_CTL16, 0x00},
{ LPASS_CDC_WSA2_COMPANDER1_CTL17, 0x24},
{ LPASS_CDC_WSA2_COMPANDER1_CTL18, 0x2A},
{ LPASS_CDC_WSA2_COMPANDER1_CTL19, 0x16},
{ LPASS_CDC_WSA2_SOFTCLIP0_CRC, 0x00},
{ LPASS_CDC_WSA2_SOFTCLIP0_SOFTCLIP_CTRL, 0x38},
{ LPASS_CDC_WSA2_SOFTCLIP1_CRC, 0x00},
{ LPASS_CDC_WSA2_SOFTCLIP1_SOFTCLIP_CTRL, 0x38},
{ LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00},
{ LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_CFG0, 0x01},
{ LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00},
{ LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_CFG0, 0x01},
{ LPASS_CDC_WSA2_IDLE_DETECT_PATH_CTL, 0x00},
{ LPASS_CDC_WSA2_IDLE_DETECT_CFG0, 0x07},
{ LPASS_CDC_WSA2_IDLE_DETECT_CFG1, 0x3C},
{ LPASS_CDC_WSA2_IDLE_DETECT_CFG2, 0x00},
{ LPASS_CDC_WSA2_IDLE_DETECT_CFG3, 0x00},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL1, 0x00},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL2, 0x00},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL3, 0x00},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG1, 0x85},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG2, 0xDC},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG3, 0x85},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG4, 0xDC},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG5, 0x85},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG6, 0xDC},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG7, 0x32},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG8, 0x00},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST1, 0x00},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST2, 0x00},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST3, 0x00},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST4, 0x00},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST1, 0x00},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST2, 0x00},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST3, 0x00},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST4, 0x00},
{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST5, 0x00},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PATH_CTL, 0x00},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_CFG, 0x10},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL1, 0x00},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL2, 0x00},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL3, 0x04},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST1, 0xE0},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST2, 0x01},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST3, 0x40},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC1, 0x2A},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC1, 0x00},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC1, 0x00},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC2, 0x18},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC3, 0x18},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC4, 0x03},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD1, 0x01},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD2, 0x00},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD3, 0x00},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD4, 0x64},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD5, 0x01},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_DEBUG1, 0x00},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD_MON, 0x00},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_MON_VAL, 0x00},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BAN, 0x0C},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD1, 0x00},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD2, 0x77},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD3, 0x01},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD4, 0x00},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD5, 0x4B},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD6, 0x00},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD7, 0x01},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD8, 0x00},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD9, 0x00},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN1, 0x04},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN2, 0x08},
{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN3, 0x0C},
};
static bool lpass_cdc_is_readable_register(struct device *dev,
@@ -801,28 +1158,22 @@ static bool lpass_cdc_is_volatile_register(struct device *dev,
case LPASS_CDC_VA_TOP_CSR_DMIC1_CTL:
case LPASS_CDC_VA_TOP_CSR_DMIC2_CTL:
case LPASS_CDC_VA_TOP_CSR_DMIC3_CTL:
case LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
case LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
case LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
case LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
case LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL:
case LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL:
case LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL:
case LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL:
case LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL:
case LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL:
case LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_MON_VAL:
case LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST:
case LPASS_CDC_WSA_INTR_CTRL_PIN1_STATUS0:
case LPASS_CDC_WSA_INTR_CTRL_PIN2_STATUS0:
case LPASS_CDC_WSA_COMPANDER0_CTL6:
case LPASS_CDC_WSA_COMPANDER1_CTL6:
case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:
case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:
case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:
case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:
case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:
case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:
case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:
case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:
case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:
case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:
case LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_MON_VAL:
case LPASS_CDC_WSA2_INTR_CTRL_PIN1_STATUS0:
case LPASS_CDC_WSA2_INTR_CTRL_PIN2_STATUS0:
case LPASS_CDC_WSA2_COMPANDER0_CTL6:
case LPASS_CDC_WSA2_COMPANDER1_CTL6:
case LPASS_CDC_RX_TOP_HPHL_COMP_RD_LSB:
case LPASS_CDC_RX_TOP_HPHL_COMP_WR_LSB:
case LPASS_CDC_RX_TOP_HPHL_COMP_RD_MSB:
@@ -834,7 +1185,6 @@ static bool lpass_cdc_is_volatile_register(struct device *dev,
case LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG2:
case LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG2:
case LPASS_CDC_RX_BCL_VBAT_GAIN_MON_VAL:
case LPASS_CDC_RX_BCL_VBAT_DECODE_ST:
case LPASS_CDC_RX_INTR_CTRL_PIN1_STATUS0:
case LPASS_CDC_RX_INTR_CTRL_PIN2_STATUS0:
case LPASS_CDC_RX_COMPANDER0_CTL6:

22
asoc/codecs/lpass-cdc/lpass-cdc-rx-macro.c
View File

@@ -3863,30 +3863,8 @@ static void lpass_cdc_rx_macro_init_bcl_pmic_reg(struct snd_soc_component *compo
switch (rx_priv->bcl_pmic_params.id) {
case 0:
/* Enable ID0 to listen to respective PMIC group interrupts */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1, 0x02, 0x02);
/* Update MC_SID0 */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1, 0x0F,
rx_priv->bcl_pmic_params.sid);
/* Update MC_PPID0 */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2, 0xFF,
rx_priv->bcl_pmic_params.ppid);
break;
case 1:
/* Enable ID1 to listen to respective PMIC group interrupts */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1, 0x01, 0x01);
/* Update MC_SID1 */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3, 0x0F,
rx_priv->bcl_pmic_params.sid);
/* Update MC_PPID1 */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1, 0xFF,
rx_priv->bcl_pmic_params.ppid);
break;
default:
dev_err(rx_dev, "%s: PMIC ID is invalid %d\n",

806
asoc/codecs/lpass-cdc/lpass-cdc-tables.c
View File

@@ -14,34 +14,17 @@ u8 lpass_cdc_tx_reg_access[LPASS_CDC_TX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_ANC_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_FREQ_MCLK)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_I2S_CLK)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_I2S_RESET)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_AMIC0_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_AMIC1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_CLK_RESET_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_2_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_SHIFT)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_SHIFT)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_A_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_B_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FB_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_SMLPF_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_DCFLT_SHIFT_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_2_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_GAIN_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
@@ -58,6 +41,22 @@ u8 lpass_cdc_tx_reg_access[LPASS_CDC_TX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_CLK_RESET_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_2_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_SHIFT)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_SHIFT)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_A_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_B_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FB_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_SMLPF_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_DCFLT_SHIFT_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_2_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_GAIN_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CFG1)] = RD_WR_REG,
@@ -149,98 +148,9 @@ u8 lpass_cdc_tx_reg_access[LPASS_CDC_TX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_TX7_TX_PATH_SEC6)] = RD_WR_REG,
};
u8 lpass_cdc_tx_reg_access_v2[LPASS_CDC_TX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_ANC_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_FREQ_MCLK)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_I2S_CLK)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_I2S_RESET)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_AMIC0_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_AMIC1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_CLK_RESET_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_2_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_SHIFT)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_SHIFT)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_A_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_B_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FB_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_SMLPF_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_DCFLT_SHIFT_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_2_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_GAIN_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_VOL_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_VOL_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_VOL_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_VOL_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC6)] = RD_WR_REG,
};
u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_TOP_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_TOP_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_SWR_CTRL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DEBUG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DEBUG_BUS)] = RD_WR_REG,
@@ -341,13 +251,6 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_ATTN1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_ATTN2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_ATTN3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_ST)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_CLR_COMMIT)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_PIN1_MASK0)] = RD_WR_REG,
@@ -382,6 +285,17 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CFG1)] = RD_WR_REG,
@@ -405,6 +319,17 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CFG1)] = RD_WR_REG,
@@ -425,6 +350,61 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_CFG1)] = RD_WR_REG,
@@ -438,6 +418,18 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL6)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL10)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL11)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL12)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL13)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL14)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL15)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL16)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL17)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL18)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL19)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL2)] = RD_WR_REG,
@@ -446,6 +438,18 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL6)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL10)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL11)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL12)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL13)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL14)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL15)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL16)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL17)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL18)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL19)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL)] = RD_WR_REG,
@@ -530,200 +534,6 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
};
u8 lpass_cdc_va_reg_access[LPASS_CDC_VA_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC2_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC3_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_CLK)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_RESET)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_VOL_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_VOL_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_VOL_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_VOL_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_VOL_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_VOL_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_VOL_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_VOL_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC6)] = RD_WR_REG,
};
u8 lpass_cdc_va_top_reg_access[LPASS_CDC_VA_MACRO_TOP_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG,
};
u8 lpass_cdc_va_reg_access_v2[LPASS_CDC_VA_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC2_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC3_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_CLK)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_RESET)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_VOL_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_VOL_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC6)] = RD_WR_REG,
};
u8 lpass_cdc_va_reg_access_v3[LPASS_CDC_VA_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
@@ -816,6 +626,19 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_TX_I2S_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_I2S_CLK)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_I2S_RESET)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_FS_UNGATE)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_GRP_SEL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_LSB)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_MSB)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP7_LUT)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_LSB)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_MSB)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_LSB)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_MSB)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_LUT)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_LSB)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_MSB)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_FS_UNGATE2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0)] = RD_WR_REG,
@@ -858,13 +681,6 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
@@ -938,6 +754,18 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL6)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL10)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL11)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL12)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL13)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL14)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL15)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL16)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL17)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL18)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL19)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL2)] = RD_WR_REG,
@@ -946,6 +774,18 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL6)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL10)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL11)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL12)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL13)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL14)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL15)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL16)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL17)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL18)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL19)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SOFTCLIP0_CRC)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SOFTCLIP1_CRC)] = RD_WR_REG,
@@ -954,24 +794,311 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_CTL0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_FIFO_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_CTL0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_FIFO_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_IDLE_DETECT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_IDLE_DETECT_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_IDLE_DETECT_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_IDLE_DETECT_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_IDLE_DETECT_CFG3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL3)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST1)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST2)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST3)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST4)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST5)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_DEBUG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD_MON)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_MON_VAL)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BAN)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN3)] = RD_WR_REG,
};
u8 lpass_cdc_wsa2_reg_access[LPASS_CDC_WSA2_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_WSA2_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_TOP_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_TOP_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_FREQ_MCLK)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_DEBUG_BUS_SEL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_DEBUG_EN0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_DEBUG_EN1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_DEBUG_DSM_LB)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_RX_I2S_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_TX_I2S_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_I2S_CLK)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_I2S_RESET)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_FS_UNGATE)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_GRP_SEL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_LSB)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_MSB)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP7_LUT)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_LSB)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_MSB)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_LSB)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_MSB)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_LUT)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_LSB)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_MSB)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_FS_UNGATE2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_MIX_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_EC_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_SOFTCLIP_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_DEBUG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD_MON)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_MON_VAL)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BAN)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_CLR_COMMIT)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN1_MASK0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN1_STATUS0)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN1_CLEAR0)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN2_MASK0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN2_STATUS0)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN2_CLEAR0)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_LEVEL0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_BYPASS0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_SET0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_CFG3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_VOL_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_VOL_MIX_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_DSMDEM_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_CFG3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_VOL_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_VOL_MIX_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_DSMDEM_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST0_BOOST_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST0_BOOST_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST0_BOOST_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST0_BOOST_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST1_BOOST_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST1_BOOST_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST1_BOOST_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST1_BOOST_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL6)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL10)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL11)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL12)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL13)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL14)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL15)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL16)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL17)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL18)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL19)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL6)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL10)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL11)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL12)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL13)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL14)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL15)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL16)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL17)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL18)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL19)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_SOFTCLIP0_CRC)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_SOFTCLIP0_SOFTCLIP_CTRL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_SOFTCLIP1_CRC)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_SOFTCLIP1_SOFTCLIP_CTRL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_IDLE_DETECT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_IDLE_DETECT_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_IDLE_DETECT_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_IDLE_DETECT_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_IDLE_DETECT_CFG3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL3)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST1)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST2)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST3)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST4)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST5)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_DEBUG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD_MON)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_MON_VAL)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BAN)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN3)] = RD_WR_REG,
};
u8 *lpass_cdc_reg_access[MAX_MACRO] = {
@@ -979,4 +1106,5 @@ u8 *lpass_cdc_reg_access[MAX_MACRO] = {
[RX_MACRO] = lpass_cdc_rx_reg_access,
[WSA_MACRO] = lpass_cdc_wsa_reg_access,
[VA_MACRO] = lpass_cdc_va_reg_access,
[WSA2_MACRO] = lpass_cdc_wsa2_reg_access,
};

1499
asoc/codecs/lpass-cdc/lpass-cdc-tx-macro.c
View File

File diff suppressed because it is too large Load Diff

13
asoc/codecs/lpass-cdc/lpass-cdc-utils.c
View File

@@ -15,6 +15,7 @@ const u16 macro_id_base_offset[MAX_MACRO] = {
RX_START_OFFSET,
WSA_START_OFFSET,
VA_START_OFFSET,
WSA2_START_OFFSET,
};
int lpass_cdc_get_macro_id(bool va_no_dec_flag, u16 reg)
@@ -28,13 +29,11 @@ int lpass_cdc_get_macro_id(bool va_no_dec_flag, u16 reg)
if (reg >= WSA_START_OFFSET
&& reg <= WSA_MAX_OFFSET)
return WSA_MACRO;
if (!va_no_dec_flag &&
(reg >= VA_START_OFFSET &&
reg <= VA_MAX_OFFSET))
return VA_MACRO;
if (va_no_dec_flag &&
(reg >= VA_START_OFFSET &&
reg <= VA_TOP_MAX_OFFSET))
if (reg >= WSA2_START_OFFSET
&& reg <= WSA2_MAX_OFFSET)
return WSA2_MACRO;
if (reg >= VA_START_OFFSET &&
reg <= VA_MAX_OFFSET)
return VA_MACRO;
return -EINVAL;

946
asoc/codecs/lpass-cdc/lpass-cdc-va-macro.c
View File

File diff suppressed because it is too large Load Diff

22
asoc/codecs/lpass-cdc/lpass-cdc-wsa-macro.c
View File

@@ -2791,30 +2791,8 @@ static void lpass_cdc_wsa_macro_init_bcl_pmic_reg(struct snd_soc_component *comp
switch (wsa_priv->bcl_pmic_params.id) {
case 0:
/* Enable ID0 to listen to respective PMIC group interrupts */
snd_soc_component_update_bits(component,
LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1, 0x02, 0x02);
/* Update MC_SID0 */
snd_soc_component_update_bits(component,
LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1, 0x0F,
wsa_priv->bcl_pmic_params.sid);
/* Update MC_PPID0 */
snd_soc_component_update_bits(component,
LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2, 0xFF,
wsa_priv->bcl_pmic_params.ppid);
break;
case 1:
/* Enable ID1 to listen to respective PMIC group interrupts */
snd_soc_component_update_bits(component,
LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1, 0x01, 0x01);
/* Update MC_SID1 */
snd_soc_component_update_bits(component,
LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3, 0x0F,
wsa_priv->bcl_pmic_params.sid);
/* Update MC_PPID1 */
snd_soc_component_update_bits(component,
LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4, 0xFF,
wsa_priv->bcl_pmic_params.ppid);
break;
default:
dev_err(wsa_dev, "%s: PMIC ID is invalid %d\n",

60
asoc/codecs/lpass-cdc/lpass-cdc.c
View File

@@ -108,30 +108,9 @@ static int __lpass_cdc_reg_read(struct lpass_cdc_priv *priv,
goto ssr_err;
}
if (priv->version < LPASS_CDC_VERSION_2_0) {
/* Request Clk before register access */
ret = lpass_cdc_clk_rsc_request_clock(priv->macro_params[macro_id].dev,
priv->macro_params[macro_id].default_clk_id,
priv->macro_params[macro_id].clk_id_req,
true);
if (ret < 0) {
dev_err_ratelimited(priv->dev,
"%s: Failed to enable clock, ret:%d\n",
__func__, ret);
goto err;
}
}
lpass_cdc_ahb_read_device(
priv->macro_params[macro_id].io_base, reg, val);
if (priv->version < LPASS_CDC_VERSION_2_0)
lpass_cdc_clk_rsc_request_clock(priv->macro_params[macro_id].dev,
priv->macro_params[macro_id].default_clk_id,
priv->macro_params[macro_id].clk_id_req,
false);
err:
if (priv->macro_params[VA_MACRO].dev) {
pm_runtime_mark_last_busy(priv->macro_params[VA_MACRO].dev);
pm_runtime_put_autosuspend(priv->macro_params[VA_MACRO].dev);
@@ -159,30 +138,9 @@ static int __lpass_cdc_reg_write(struct lpass_cdc_priv *priv,
goto ssr_err;
}
if (priv->version < LPASS_CDC_VERSION_2_0) {
/* Request Clk before register access */
ret = lpass_cdc_clk_rsc_request_clock(priv->macro_params[macro_id].dev,
priv->macro_params[macro_id].default_clk_id,
priv->macro_params[macro_id].clk_id_req,
true);
if (ret < 0) {
dev_err_ratelimited(priv->dev,
"%s: Failed to enable clock, ret:%d\n",
__func__, ret);
goto err;
}
}
lpass_cdc_ahb_write_device(
priv->macro_params[macro_id].io_base, reg, val);
if (priv->version < LPASS_CDC_VERSION_2_0)
lpass_cdc_clk_rsc_request_clock(priv->macro_params[macro_id].dev,
priv->macro_params[macro_id].default_clk_id,
priv->macro_params[macro_id].clk_id_req,
false);
err:
if (priv->macro_params[VA_MACRO].dev) {
pm_runtime_mark_last_busy(priv->macro_params[VA_MACRO].dev);
pm_runtime_put_autosuspend(priv->macro_params[VA_MACRO].dev);
@@ -694,11 +652,9 @@ int lpass_cdc_register_macro(struct device *dev, u16 macro_id,
if (macro_id == TX_MACRO || macro_id == VA_MACRO)
priv->macro_params[macro_id].clk_div_get = ops->clk_div_get;
if (priv->version == LPASS_CDC_VERSION_2_1) {
if (macro_id == VA_MACRO)
priv->macro_params[macro_id].reg_wake_irq =
ops->reg_wake_irq;
}
priv->num_dais += ops->num_dais;
priv->num_macros_registered++;
priv->macros_supported[macro_id] = true;
@@ -1047,15 +1003,9 @@ int lpass_cdc_register_wake_irq(struct snd_soc_component *component,
return -EINVAL;
}
if (priv->version == LPASS_CDC_VERSION_2_1) {
if (priv->macro_params[VA_MACRO].reg_wake_irq)
priv->macro_params[VA_MACRO].reg_wake_irq(
component, ipc_wakeup);
} else {
if (priv->macro_params[TX_MACRO].reg_wake_irq)
priv->macro_params[TX_MACRO].reg_wake_irq(
component, ipc_wakeup);
}
return 0;
}
@@ -1314,10 +1264,6 @@ static int lpass_cdc_probe(struct platform_device *pdev)
__func__, priv->num_macros, MAX_MACRO);
return -EINVAL;
}
priv->va_without_decimation = of_property_read_bool(pdev->dev.of_node,
"qcom,va-without-decimation");
if (priv->va_without_decimation)
lpass_cdc_reg_access[VA_MACRO] = lpass_cdc_va_top_reg_access;
ret = of_property_read_u32(pdev->dev.of_node,
"qcom,lpass-cdc-version", &priv->version);
@@ -1326,12 +1272,6 @@ static int lpass_cdc_probe(struct platform_device *pdev)
__func__);
ret = 0;
}
if (priv->version == LPASS_CDC_VERSION_2_1) {
lpass_cdc_reg_access[TX_MACRO] = lpass_cdc_tx_reg_access_v2;
lpass_cdc_reg_access[VA_MACRO] = lpass_cdc_va_reg_access_v2;
} else if (priv->version == LPASS_CDC_VERSION_2_0) {
lpass_cdc_reg_access[VA_MACRO] = lpass_cdc_va_reg_access_v3;
}
priv->dev = &pdev->dev;
priv->dev_up = true;

1
asoc/codecs/lpass-cdc/lpass-cdc.h
View File

@@ -20,6 +20,7 @@ enum {
RX_MACRO,
WSA_MACRO,
VA_MACRO,
WSA2_MACRO,
MAX_MACRO
};