diff --git a/asoc/codecs/lpass-cdc/internal.h b/asoc/codecs/lpass-cdc/internal.h index 7f08ab24a9..79a0c3455d 100644 --- a/asoc/codecs/lpass-cdc/internal.h +++ b/asoc/codecs/lpass-cdc/internal.h @@ -102,10 +102,6 @@ int lpass_cdc_get_macro_id(bool va_no_dec_flag, u16 reg); extern const struct regmap_config lpass_cdc_regmap_config; extern u8 *lpass_cdc_reg_access[MAX_MACRO]; -extern u8 lpass_cdc_va_top_reg_access[LPASS_CDC_VA_MACRO_TOP_MAX]; -extern u8 lpass_cdc_va_reg_access_v2[LPASS_CDC_VA_MACRO_MAX]; -extern u8 lpass_cdc_va_reg_access_v3[LPASS_CDC_VA_MACRO_MAX]; -extern u8 lpass_cdc_tx_reg_access_v2[LPASS_CDC_TX_MACRO_MAX]; extern const u16 macro_id_base_offset[MAX_MACRO]; #endif diff --git a/asoc/codecs/lpass-cdc/lpass-cdc-registers.h b/asoc/codecs/lpass-cdc/lpass-cdc-registers.h index 78eb9872a4..b766949926 100644 --- a/asoc/codecs/lpass-cdc/lpass-cdc-registers.h +++ b/asoc/codecs/lpass-cdc/lpass-cdc-registers.h @@ -13,18 +13,11 @@ #define LPASS_CDC_TX_TOP_CSR_TOP_CFG0 (TX_START_OFFSET + 0x0080) #define LPASS_CDC_TX_TOP_CSR_ANC_CFG (TX_START_OFFSET + 0x0084) #define LPASS_CDC_TX_TOP_CSR_SWR_CTRL (TX_START_OFFSET + 0x0088) -#define LPASS_CDC_TX_TOP_CSR_FREQ_MCLK (TX_START_OFFSET + 0x0090) #define LPASS_CDC_TX_TOP_CSR_DEBUG_BUS (TX_START_OFFSET + 0x0094) #define LPASS_CDC_TX_TOP_CSR_DEBUG_EN (TX_START_OFFSET + 0x0098) -#define LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL (TX_START_OFFSET + 0x00A4) +#define LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL (TX_START_OFFSET + 0x00A4) #define LPASS_CDC_TX_TOP_CSR_I2S_CLK (TX_START_OFFSET + 0x00A8) #define LPASS_CDC_TX_TOP_CSR_I2S_RESET (TX_START_OFFSET + 0x00AC) -#define LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL (TX_START_OFFSET + 0x00C0) -#define LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL (TX_START_OFFSET + 0x00C4) -#define LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL (TX_START_OFFSET + 0x00C8) -#define LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL (TX_START_OFFSET + 0x00CC) -#define LPASS_CDC_TX_TOP_CSR_SWR_AMIC0_CTL (TX_START_OFFSET + 0x00D0) -#define LPASS_CDC_TX_TOP_CSR_SWR_AMIC1_CTL (TX_START_OFFSET + 0x00D4) #define LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL (TX_START_OFFSET + 0x00C0) #define LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL (TX_START_OFFSET + 0x00C4) #define LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL (TX_START_OFFSET + 0x00C8) @@ -47,22 +40,22 @@ #define LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG1 (TX_START_OFFSET + 0x0134) #define LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0 (TX_START_OFFSET + 0x0138) #define LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG1 (TX_START_OFFSET + 0x013C) -#define LPASS_CDC_TX_ANC0_CLK_RESET_CTL (TX_START_OFFSET + 0x0200) +#define LPASS_CDC_TX_ANC0_CLK_RESET_CTL (TX_START_OFFSET + 0x0200) #define LPASS_CDC_TX_ANC0_MODE_1_CTL (TX_START_OFFSET + 0x0204) #define LPASS_CDC_TX_ANC0_MODE_2_CTL (TX_START_OFFSET + 0x0208) #define LPASS_CDC_TX_ANC0_FF_SHIFT (TX_START_OFFSET + 0x020C) #define LPASS_CDC_TX_ANC0_FB_SHIFT (TX_START_OFFSET + 0x0210) -#define LPASS_CDC_TX_ANC0_LPF_FF_A_CTL (TX_START_OFFSET + 0x0214) -#define LPASS_CDC_TX_ANC0_LPF_FF_B_CTL (TX_START_OFFSET + 0x0218) -#define LPASS_CDC_TX_ANC0_LPF_FB_CTL (TX_START_OFFSET + 0x021C) -#define LPASS_CDC_TX_ANC0_SMLPF_CTL (TX_START_OFFSET + 0x0220) +#define LPASS_CDC_TX_ANC0_LPF_FF_A_CTL (TX_START_OFFSET + 0x0214) +#define LPASS_CDC_TX_ANC0_LPF_FF_B_CTL (TX_START_OFFSET + 0x0218) +#define LPASS_CDC_TX_ANC0_LPF_FB_CTL (TX_START_OFFSET + 0x021C) +#define LPASS_CDC_TX_ANC0_SMLPF_CTL (TX_START_OFFSET + 0x0220) #define LPASS_CDC_TX_ANC0_DCFLT_SHIFT_CTL (TX_START_OFFSET + 0x0224) -#define LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL (TX_START_OFFSET + 0x0228) +#define LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL (TX_START_OFFSET + 0x0228) #define LPASS_CDC_TX_ANC0_IIR_COEFF_1_CTL (TX_START_OFFSET + 0x022C) #define LPASS_CDC_TX_ANC0_IIR_COEFF_2_CTL (TX_START_OFFSET + 0x0230) -#define LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL (TX_START_OFFSET + 0x0234) -#define LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL (TX_START_OFFSET + 0x0238) -#define LPASS_CDC_TX_ANC0_FB_GAIN_CTL (TX_START_OFFSET + 0x023C) +#define LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL (TX_START_OFFSET + 0x0234) +#define LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL (TX_START_OFFSET + 0x0238) +#define LPASS_CDC_TX_ANC0_FB_GAIN_CTL (TX_START_OFFSET + 0x023C) #define LPASS_CDC_TX0_TX_PATH_CTL (TX_START_OFFSET + 0x0400) #define LPASS_CDC_TX0_TX_PATH_CFG0 (TX_START_OFFSET + 0x0404) #define LPASS_CDC_TX0_TX_PATH_CFG1 (TX_START_OFFSET + 0x0408) @@ -158,6 +151,7 @@ #define RX_START_OFFSET 0x1000 #define LPASS_CDC_RX_TOP_TOP_CFG0 (RX_START_OFFSET + 0x0000) +#define LPASS_CDC_RX_TOP_TOP_CFG1 (RX_START_OFFSET + 0x0004) #define LPASS_CDC_RX_TOP_SWR_CTRL (RX_START_OFFSET + 0x0008) #define LPASS_CDC_RX_TOP_DEBUG (RX_START_OFFSET + 0x000C) #define LPASS_CDC_RX_TOP_DEBUG_BUS (RX_START_OFFSET + 0x0010) @@ -260,13 +254,6 @@ #define LPASS_CDC_RX_BCL_VBAT_ATTN1 (RX_START_OFFSET + 0x0300) #define LPASS_CDC_RX_BCL_VBAT_ATTN2 (RX_START_OFFSET + 0x0304) #define LPASS_CDC_RX_BCL_VBAT_ATTN3 (RX_START_OFFSET + 0x0308) -#define LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1 (RX_START_OFFSET + 0x030C) -#define LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2 (RX_START_OFFSET + 0x0310) -#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1 (RX_START_OFFSET + 0x0314) -#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2 (RX_START_OFFSET + 0x0318) -#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3 (RX_START_OFFSET + 0x031C) -#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4 (RX_START_OFFSET + 0x0320) -#define LPASS_CDC_RX_BCL_VBAT_DECODE_ST (RX_START_OFFSET + 0x0324) #define LPASS_CDC_RX_INTR_CTRL_CFG (RX_START_OFFSET + 0x0340) #define LPASS_CDC_RX_INTR_CTRL_CLR_COMMIT (RX_START_OFFSET + 0x0344) #define LPASS_CDC_RX_INTR_CTRL_PIN1_MASK0 (RX_START_OFFSET + 0x0360) @@ -301,49 +288,137 @@ #define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x0450) #define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x0454) #define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x0458) -#define LPASS_CDC_RX_RX1_RX_PATH_CTL (RX_START_OFFSET + 0x0480) -#define LPASS_CDC_RX_RX1_RX_PATH_CFG0 (RX_START_OFFSET + 0x0484) -#define LPASS_CDC_RX_RX1_RX_PATH_CFG1 (RX_START_OFFSET + 0x0488) -#define LPASS_CDC_RX_RX1_RX_PATH_CFG2 (RX_START_OFFSET + 0x048C) -#define LPASS_CDC_RX_RX1_RX_PATH_CFG3 (RX_START_OFFSET + 0x0490) -#define LPASS_CDC_RX_RX1_RX_VOL_CTL (RX_START_OFFSET + 0x0494) -#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0498) -#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x049C) -#define LPASS_CDC_RX_RX1_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x04A0) -#define LPASS_CDC_RX_RX1_RX_PATH_SEC1 (RX_START_OFFSET + 0x04A4) -#define LPASS_CDC_RX_RX1_RX_PATH_SEC2 (RX_START_OFFSET + 0x04A8) -#define LPASS_CDC_RX_RX1_RX_PATH_SEC3 (RX_START_OFFSET + 0x04AC) -#define LPASS_CDC_RX_RX1_RX_PATH_SEC4 (RX_START_OFFSET + 0x04B0) -#define LPASS_CDC_RX_RX1_RX_PATH_SEC7 (RX_START_OFFSET + 0x04B4) -#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x04B8) -#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x04BC) -#define LPASS_CDC_RX_RX1_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x04C0) -#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA1 (RX_START_OFFSET + 0x04C4) -#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA2 (RX_START_OFFSET + 0x04C8) -#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA3 (RX_START_OFFSET + 0x04CC) -#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x04D0) -#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x04D4) -#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x04D8) -#define LPASS_CDC_RX_RX2_RX_PATH_CTL (RX_START_OFFSET + 0x0500) -#define LPASS_CDC_RX_RX2_RX_PATH_CFG0 (RX_START_OFFSET + 0x0504) -#define LPASS_CDC_RX_RX2_RX_PATH_CFG1 (RX_START_OFFSET + 0x0508) -#define LPASS_CDC_RX_RX2_RX_PATH_CFG2 (RX_START_OFFSET + 0x050C) -#define LPASS_CDC_RX_RX2_RX_PATH_CFG3 (RX_START_OFFSET + 0x0510) -#define LPASS_CDC_RX_RX2_RX_VOL_CTL (RX_START_OFFSET + 0x0514) -#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0518) -#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x051C) -#define LPASS_CDC_RX_RX2_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x0520) -#define LPASS_CDC_RX_RX2_RX_PATH_SEC0 (RX_START_OFFSET + 0x0524) -#define LPASS_CDC_RX_RX2_RX_PATH_SEC1 (RX_START_OFFSET + 0x0528) -#define LPASS_CDC_RX_RX2_RX_PATH_SEC2 (RX_START_OFFSET + 0x052C) -#define LPASS_CDC_RX_RX2_RX_PATH_SEC3 (RX_START_OFFSET + 0x0530) -#define LPASS_CDC_RX_RX2_RX_PATH_SEC4 (RX_START_OFFSET + 0x0534) -#define LPASS_CDC_RX_RX2_RX_PATH_SEC5 (RX_START_OFFSET + 0x0538) -#define LPASS_CDC_RX_RX2_RX_PATH_SEC6 (RX_START_OFFSET + 0x053C) -#define LPASS_CDC_RX_RX2_RX_PATH_SEC7 (RX_START_OFFSET + 0x0540) -#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x0544) -#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x0548) -#define LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x054C) +#define LPASS_CDC_RX_RX0_RX_FIR_CTL (RX_START_OFFSET + 0x045C) +#define LPASS_CDC_RX_RX0_RX_FIR_CFG (RX_START_OFFSET + 0x0460) +#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR (RX_START_OFFSET + 0x0464) +#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0 (RX_START_OFFSET + 0x0468) +#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1 (RX_START_OFFSET + 0x046C) +#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2 (RX_START_OFFSET + 0x0470) +#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3 (RX_START_OFFSET + 0x0474) +#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4 (RX_START_OFFSET + 0x0478) +#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5 (RX_START_OFFSET + 0x047C) +#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6 (RX_START_OFFSET + 0x0480) +#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7 (RX_START_OFFSET + 0x0484) +#define LPASS_CDC_RX_RX1_RX_PATH_CTL (RX_START_OFFSET + 0x04C0) +#define LPASS_CDC_RX_RX1_RX_PATH_CFG0 (RX_START_OFFSET + 0x04C4) +#define LPASS_CDC_RX_RX1_RX_PATH_CFG1 (RX_START_OFFSET + 0x04C8) +#define LPASS_CDC_RX_RX1_RX_PATH_CFG2 (RX_START_OFFSET + 0x04CC) +#define LPASS_CDC_RX_RX1_RX_PATH_CFG3 (RX_START_OFFSET + 0x04D0) +#define LPASS_CDC_RX_RX1_RX_VOL_CTL (RX_START_OFFSET + 0x04D4) +#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x04D8) +#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x04DC) +#define LPASS_CDC_RX_RX1_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x04E0) +#define LPASS_CDC_RX_RX1_RX_PATH_SEC1 (RX_START_OFFSET + 0x04E4) +#define LPASS_CDC_RX_RX1_RX_PATH_SEC2 (RX_START_OFFSET + 0x04E8) +#define LPASS_CDC_RX_RX1_RX_PATH_SEC3 (RX_START_OFFSET + 0x04EC) +#define LPASS_CDC_RX_RX1_RX_PATH_SEC4 (RX_START_OFFSET + 0x04F0) +#define LPASS_CDC_RX_RX1_RX_PATH_SEC7 (RX_START_OFFSET + 0x04F4) +#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x04F8) +#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x04FC) +#define LPASS_CDC_RX_RX1_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x0500) +#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA1 (RX_START_OFFSET + 0x0504) +#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA2 (RX_START_OFFSET + 0x0508) +#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA3 (RX_START_OFFSET + 0x050C) +#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x0510) +#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x0514) +#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x0518) +#define LPASS_CDC_RX_RX1_RX_FIR_CTL (RX_START_OFFSET + 0x051C) +#define LPASS_CDC_RX_RX1_RX_FIR_CFG (RX_START_OFFSET + 0x0520) +#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR (RX_START_OFFSET + 0x0524) +#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0 (RX_START_OFFSET + 0x0528) +#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1 (RX_START_OFFSET + 0x052C) +#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2 (RX_START_OFFSET + 0x0530) +#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3 (RX_START_OFFSET + 0x0534) +#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4 (RX_START_OFFSET + 0x0538) +#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5 (RX_START_OFFSET + 0x053C) +#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6 (RX_START_OFFSET + 0x0540) +#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7 (RX_START_OFFSET + 0x0544) +#define LPASS_CDC_RX_RX2_RX_PATH_CTL (RX_START_OFFSET + 0x0580) +#define LPASS_CDC_RX_RX2_RX_PATH_CFG0 (RX_START_OFFSET + 0x0584) +#define LPASS_CDC_RX_RX2_RX_PATH_CFG1 (RX_START_OFFSET + 0x0588) +#define LPASS_CDC_RX_RX2_RX_PATH_CFG2 (RX_START_OFFSET + 0x058C) +#define LPASS_CDC_RX_RX2_RX_PATH_CFG3 (RX_START_OFFSET + 0x0590) +#define LPASS_CDC_RX_RX2_RX_VOL_CTL (RX_START_OFFSET + 0x0594) +#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0598) +#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x059C) +#define LPASS_CDC_RX_RX2_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x05A0) +#define LPASS_CDC_RX_RX2_RX_PATH_SEC0 (RX_START_OFFSET + 0x05A4) +#define LPASS_CDC_RX_RX2_RX_PATH_SEC1 (RX_START_OFFSET + 0x05A8) +#define LPASS_CDC_RX_RX2_RX_PATH_SEC2 (RX_START_OFFSET + 0x05AC) +#define LPASS_CDC_RX_RX2_RX_PATH_SEC3 (RX_START_OFFSET + 0x05B0) +#define LPASS_CDC_RX_RX2_RX_PATH_SEC4 (RX_START_OFFSET + 0x05B4) +#define LPASS_CDC_RX_RX2_RX_PATH_SEC5 (RX_START_OFFSET + 0x05B8) +#define LPASS_CDC_RX_RX2_RX_PATH_SEC6 (RX_START_OFFSET + 0x05BC) +#define LPASS_CDC_RX_RX2_RX_PATH_SEC7 (RX_START_OFFSET + 0x05C0) +#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x05C4) +#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x05C8) +#define LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x05CC) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1 (RX_START_OFFSET + 0x0600) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2 (RX_START_OFFSET + 0x0604) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3 (RX_START_OFFSET + 0x0608) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1 (RX_START_OFFSET + 0x060C) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2 (RX_START_OFFSET + 0x0610) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3 (RX_START_OFFSET + 0x0614) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4 (RX_START_OFFSET + 0x0618) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5 (RX_START_OFFSET + 0x061C) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6 (RX_START_OFFSET + 0x0620) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7 (RX_START_OFFSET + 0x0624) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8 (RX_START_OFFSET + 0x0628) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1 (RX_START_OFFSET + 0x062C) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2 (RX_START_OFFSET + 0x0630) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3 (RX_START_OFFSET + 0x0634) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4 (RX_START_OFFSET + 0x0638) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1 (RX_START_OFFSET + 0x063C) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2 (RX_START_OFFSET + 0x0640) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3 (RX_START_OFFSET + 0x0644) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4 (RX_START_OFFSET + 0x0648) +#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5 (RX_START_OFFSET + 0x064C) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL (RX_START_OFFSET + 0x0680) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG (RX_START_OFFSET + 0x0684) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1 (RX_START_OFFSET + 0x0688) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2 (RX_START_OFFSET + 0x068C) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3 (RX_START_OFFSET + 0x0690) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1 (RX_START_OFFSET + 0x0694) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2 (RX_START_OFFSET + 0x0698) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3 (RX_START_OFFSET + 0x069C) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1 (RX_START_OFFSET + 0x06A0) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC2 (RX_START_OFFSET + 0x06A4) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1 (RX_START_OFFSET + 0x06A8) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2 (RX_START_OFFSET + 0x06AC) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3 (RX_START_OFFSET + 0x06B0) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4 (RX_START_OFFSET + 0x06B4) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1 (RX_START_OFFSET + 0x06B8) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2 (RX_START_OFFSET + 0x06BC) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3 (RX_START_OFFSET + 0x06C0) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4 (RX_START_OFFSET + 0x06C4) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5 (RX_START_OFFSET + 0x06C8) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1 (RX_START_OFFSET + 0x06CC) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON \ + (RX_START_OFFSET + 0x06D0) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL \ + (RX_START_OFFSET + 0x06D4) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN (RX_START_OFFSET + 0x06D8) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1 \ + (RX_START_OFFSET + 0x06DC) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2 \ + (RX_START_OFFSET + 0x06E0) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3 \ + (RX_START_OFFSET + 0x06E4) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4 \ + (RX_START_OFFSET + 0x06E8) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5 \ + (RX_START_OFFSET + 0x06EC) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6 \ + (RX_START_OFFSET + 0x06F0) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7 \ + (RX_START_OFFSET + 0x06F4) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8 \ + (RX_START_OFFSET + 0x06F8) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9 \ + (RX_START_OFFSET + 0x06FC) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1 (RX_START_OFFSET + 0x0700) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2 (RX_START_OFFSET + 0x0704) +#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3 (RX_START_OFFSET + 0x0708) #define LPASS_CDC_RX_IDLE_DETECT_PATH_CTL (RX_START_OFFSET + 0x0780) #define LPASS_CDC_RX_IDLE_DETECT_CFG0 (RX_START_OFFSET + 0x0784) #define LPASS_CDC_RX_IDLE_DETECT_CFG1 (RX_START_OFFSET + 0x0788) @@ -357,14 +432,38 @@ #define LPASS_CDC_RX_COMPANDER0_CTL5 (RX_START_OFFSET + 0x0814) #define LPASS_CDC_RX_COMPANDER0_CTL6 (RX_START_OFFSET + 0x0818) #define LPASS_CDC_RX_COMPANDER0_CTL7 (RX_START_OFFSET + 0x081C) -#define LPASS_CDC_RX_COMPANDER1_CTL0 (RX_START_OFFSET + 0x0840) -#define LPASS_CDC_RX_COMPANDER1_CTL1 (RX_START_OFFSET + 0x0844) -#define LPASS_CDC_RX_COMPANDER1_CTL2 (RX_START_OFFSET + 0x0848) -#define LPASS_CDC_RX_COMPANDER1_CTL3 (RX_START_OFFSET + 0x084C) -#define LPASS_CDC_RX_COMPANDER1_CTL4 (RX_START_OFFSET + 0x0850) -#define LPASS_CDC_RX_COMPANDER1_CTL5 (RX_START_OFFSET + 0x0854) -#define LPASS_CDC_RX_COMPANDER1_CTL6 (RX_START_OFFSET + 0x0858) -#define LPASS_CDC_RX_COMPANDER1_CTL7 (RX_START_OFFSET + 0x085C) +#define LPASS_CDC_RX_COMPANDER0_CTL8 (RX_START_OFFSET + 0x0820) +#define LPASS_CDC_RX_COMPANDER0_CTL9 (RX_START_OFFSET + 0x0820) +#define LPASS_CDC_RX_COMPANDER0_CTL10 (RX_START_OFFSET + 0x0824) +#define LPASS_CDC_RX_COMPANDER0_CTL11 (RX_START_OFFSET + 0x0828) +#define LPASS_CDC_RX_COMPANDER0_CTL12 (RX_START_OFFSET + 0x082C) +#define LPASS_CDC_RX_COMPANDER0_CTL13 (RX_START_OFFSET + 0x0830) +#define LPASS_CDC_RX_COMPANDER0_CTL14 (RX_START_OFFSET + 0x0834) +#define LPASS_CDC_RX_COMPANDER0_CTL15 (RX_START_OFFSET + 0x0838) +#define LPASS_CDC_RX_COMPANDER0_CTL16 (RX_START_OFFSET + 0x083C) +#define LPASS_CDC_RX_COMPANDER0_CTL17 (RX_START_OFFSET + 0x0840) +#define LPASS_CDC_RX_COMPANDER0_CTL18 (RX_START_OFFSET + 0x0848) +#define LPASS_CDC_RX_COMPANDER0_CTL19 (RX_START_OFFSET + 0x084C) +#define LPASS_CDC_RX_COMPANDER1_CTL0 (RX_START_OFFSET + 0x0860) +#define LPASS_CDC_RX_COMPANDER1_CTL1 (RX_START_OFFSET + 0x0864) +#define LPASS_CDC_RX_COMPANDER1_CTL2 (RX_START_OFFSET + 0x0868) +#define LPASS_CDC_RX_COMPANDER1_CTL3 (RX_START_OFFSET + 0x086C) +#define LPASS_CDC_RX_COMPANDER1_CTL4 (RX_START_OFFSET + 0x0870) +#define LPASS_CDC_RX_COMPANDER1_CTL5 (RX_START_OFFSET + 0x0874) +#define LPASS_CDC_RX_COMPANDER1_CTL6 (RX_START_OFFSET + 0x0878) +#define LPASS_CDC_RX_COMPANDER1_CTL7 (RX_START_OFFSET + 0x087C) +#define LPASS_CDC_RX_COMPANDER1_CTL8 (RX_START_OFFSET + 0x0880) +#define LPASS_CDC_RX_COMPANDER1_CTL9 (RX_START_OFFSET + 0x0884) +#define LPASS_CDC_RX_COMPANDER1_CTL10 (RX_START_OFFSET + 0x0888) +#define LPASS_CDC_RX_COMPANDER1_CTL11 (RX_START_OFFSET + 0x088C) +#define LPASS_CDC_RX_COMPANDER1_CTL12 (RX_START_OFFSET + 0x0890) +#define LPASS_CDC_RX_COMPANDER1_CTL13 (RX_START_OFFSET + 0x0894) +#define LPASS_CDC_RX_COMPANDER1_CTL14 (RX_START_OFFSET + 0x0898) +#define LPASS_CDC_RX_COMPANDER1_CTL15 (RX_START_OFFSET + 0x089C) +#define LPASS_CDC_RX_COMPANDER1_CTL16 (RX_START_OFFSET + 0x08A0) +#define LPASS_CDC_RX_COMPANDER1_CTL17 (RX_START_OFFSET + 0x08A4) +#define LPASS_CDC_RX_COMPANDER1_CTL18 (RX_START_OFFSET + 0x08A8) +#define LPASS_CDC_RX_COMPANDER1_CTL19 (RX_START_OFFSET + 0x08AC) #define LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL \ (RX_START_OFFSET + 0x0A00) #define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL \ @@ -509,6 +608,19 @@ #define LPASS_CDC_WSA_TOP_TX_I2S_CTL (WSA_START_OFFSET + 0x00A0) #define LPASS_CDC_WSA_TOP_I2S_CLK (WSA_START_OFFSET + 0x00A4) #define LPASS_CDC_WSA_TOP_I2S_RESET (WSA_START_OFFSET + 0x00A8) +#define LPASS_CDC_WSA_TOP_FS_UNGATE (WSA_START_OFFSET + 0x00AC) +#define LPASS_CDC_WSA_TOP_GRP_SEL (WSA_START_OFFSET + 0x00B0) +#define LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_LSB (WSA_START_OFFSET + 0x00B4) +#define LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_MSB (WSA_START_OFFSET + 0x00B8) +#define LPASS_CDC_WSA_TOP_SPKR_COMP7_LUT (WSA_START_OFFSET + 0x00BC) +#define LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_LSB (WSA_START_OFFSET + 0x00C0) +#define LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_MSB (WSA_START_OFFSET + 0x00C4) +#define LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_LSB (WSA_START_OFFSET + 0x00C8) +#define LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_MSB (WSA_START_OFFSET + 0x00CC) +#define LPASS_CDC_WSA_TOP_SPKR_COMP8_LUT (WSA_START_OFFSET + 0x00D0) +#define LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_LSB (WSA_START_OFFSET + 0x00D4) +#define LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_MSB (WSA_START_OFFSET + 0x00D8) +#define LPASS_CDC_WSA_TOP_FS_UNGATE2 (WSA_START_OFFSET + 0x00DC) #define LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 (WSA_START_OFFSET + 0x0100) #define LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1 (WSA_START_OFFSET + 0x0104) #define LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0 (WSA_START_OFFSET + 0x0108) @@ -563,19 +675,6 @@ #define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1 (WSA_START_OFFSET + 0x0200) #define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2 (WSA_START_OFFSET + 0x0204) #define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3 (WSA_START_OFFSET + 0x0208) -#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1 \ - (WSA_START_OFFSET + 0x020C) -#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2 \ - (WSA_START_OFFSET + 0x0210) -#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1 \ - (WSA_START_OFFSET + 0x0214) -#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2 \ - (WSA_START_OFFSET + 0x0218) -#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3 \ - (WSA_START_OFFSET + 0x021C) -#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4 \ - (WSA_START_OFFSET + 0x0220) -#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST (WSA_START_OFFSET + 0x0224) #define LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CTL (WSA_START_OFFSET + 0x0244) #define LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 (WSA_START_OFFSET + 0x0248) #define LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CTL (WSA_START_OFFSET + 0x0264) @@ -649,53 +748,126 @@ #define LPASS_CDC_WSA_COMPANDER0_CTL5 (WSA_START_OFFSET + 0x0594) #define LPASS_CDC_WSA_COMPANDER0_CTL6 (WSA_START_OFFSET + 0x0598) #define LPASS_CDC_WSA_COMPANDER0_CTL7 (WSA_START_OFFSET + 0x059C) -#define LPASS_CDC_WSA_COMPANDER1_CTL0 (WSA_START_OFFSET + 0x05C0) -#define LPASS_CDC_WSA_COMPANDER1_CTL1 (WSA_START_OFFSET + 0x05C4) -#define LPASS_CDC_WSA_COMPANDER1_CTL2 (WSA_START_OFFSET + 0x05C8) -#define LPASS_CDC_WSA_COMPANDER1_CTL3 (WSA_START_OFFSET + 0x05CC) -#define LPASS_CDC_WSA_COMPANDER1_CTL4 (WSA_START_OFFSET + 0x05D0) -#define LPASS_CDC_WSA_COMPANDER1_CTL5 (WSA_START_OFFSET + 0x05D4) -#define LPASS_CDC_WSA_COMPANDER1_CTL6 (WSA_START_OFFSET + 0x05D8) -#define LPASS_CDC_WSA_COMPANDER1_CTL7 (WSA_START_OFFSET + 0x05DC) -#define LPASS_CDC_WSA_SOFTCLIP0_CRC (WSA_START_OFFSET + 0x0600) -#define LPASS_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL (WSA_START_OFFSET + 0x0604) -#define LPASS_CDC_WSA_SOFTCLIP1_CRC (WSA_START_OFFSET + 0x0640) -#define LPASS_CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL (WSA_START_OFFSET + 0x0644) +#define LPASS_CDC_WSA_COMPANDER0_CTL8 (WSA_START_OFFSET + 0x05A0) +#define LPASS_CDC_WSA_COMPANDER0_CTL9 (WSA_START_OFFSET + 0x05A4) +#define LPASS_CDC_WSA_COMPANDER0_CTL10 (WSA_START_OFFSET + 0x05A8) +#define LPASS_CDC_WSA_COMPANDER0_CTL11 (WSA_START_OFFSET + 0x05AC) +#define LPASS_CDC_WSA_COMPANDER0_CTL12 (WSA_START_OFFSET + 0x05B0) +#define LPASS_CDC_WSA_COMPANDER0_CTL13 (WSA_START_OFFSET + 0x05B4) +#define LPASS_CDC_WSA_COMPANDER0_CTL14 (WSA_START_OFFSET + 0x05B8) +#define LPASS_CDC_WSA_COMPANDER0_CTL15 (WSA_START_OFFSET + 0x05BC) +#define LPASS_CDC_WSA_COMPANDER0_CTL16 (WSA_START_OFFSET + 0x05C0) +#define LPASS_CDC_WSA_COMPANDER0_CTL17 (WSA_START_OFFSET + 0x05C4) +#define LPASS_CDC_WSA_COMPANDER0_CTL18 (WSA_START_OFFSET + 0x05C8) +#define LPASS_CDC_WSA_COMPANDER0_CTL19 (WSA_START_OFFSET + 0x05CC) +#define LPASS_CDC_WSA_COMPANDER1_CTL0 (WSA_START_OFFSET + 0x05E0) +#define LPASS_CDC_WSA_COMPANDER1_CTL1 (WSA_START_OFFSET + 0x05E4) +#define LPASS_CDC_WSA_COMPANDER1_CTL2 (WSA_START_OFFSET + 0x05E8) +#define LPASS_CDC_WSA_COMPANDER1_CTL3 (WSA_START_OFFSET + 0x05EC) +#define LPASS_CDC_WSA_COMPANDER1_CTL4 (WSA_START_OFFSET + 0x05F0) +#define LPASS_CDC_WSA_COMPANDER1_CTL5 (WSA_START_OFFSET + 0x05F4) +#define LPASS_CDC_WSA_COMPANDER1_CTL6 (WSA_START_OFFSET + 0x05F8) +#define LPASS_CDC_WSA_COMPANDER1_CTL7 (WSA_START_OFFSET + 0x05FC) +#define LPASS_CDC_WSA_COMPANDER1_CTL8 (WSA_START_OFFSET + 0x0600) +#define LPASS_CDC_WSA_COMPANDER1_CTL9 (WSA_START_OFFSET + 0x0604) +#define LPASS_CDC_WSA_COMPANDER1_CTL10 (WSA_START_OFFSET + 0x0608) +#define LPASS_CDC_WSA_COMPANDER1_CTL11 (WSA_START_OFFSET + 0x060C) +#define LPASS_CDC_WSA_COMPANDER1_CTL12 (WSA_START_OFFSET + 0x0610) +#define LPASS_CDC_WSA_COMPANDER1_CTL13 (WSA_START_OFFSET + 0x0614) +#define LPASS_CDC_WSA_COMPANDER1_CTL14 (WSA_START_OFFSET + 0x0618) +#define LPASS_CDC_WSA_COMPANDER1_CTL15 (WSA_START_OFFSET + 0x061C) +#define LPASS_CDC_WSA_COMPANDER1_CTL16 (WSA_START_OFFSET + 0x0620) +#define LPASS_CDC_WSA_COMPANDER1_CTL17 (WSA_START_OFFSET + 0x0624) +#define LPASS_CDC_WSA_COMPANDER1_CTL18 (WSA_START_OFFSET + 0x0628) +#define LPASS_CDC_WSA_COMPANDER1_CTL19 (WSA_START_OFFSET + 0x062C) +#define LPASS_CDC_WSA_SOFTCLIP0_CRC (WSA_START_OFFSET + 0x0640) +#define LPASS_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL (WSA_START_OFFSET + 0x0644) +#define LPASS_CDC_WSA_SOFTCLIP1_CRC (WSA_START_OFFSET + 0x0660) +#define LPASS_CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL (WSA_START_OFFSET + 0x0664) #define LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL \ (WSA_START_OFFSET + 0x0680) #define LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 (WSA_START_OFFSET + 0x0684) #define LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL \ (WSA_START_OFFSET + 0x06C0) #define LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0 (WSA_START_OFFSET + 0x06C4) -#define LPASS_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL (WSA_START_OFFSET + 0x0700) -#define LPASS_CDC_WSA_SPLINE_ASRC0_CTL0 (WSA_START_OFFSET + 0x0704) -#define LPASS_CDC_WSA_SPLINE_ASRC0_CTL1 (WSA_START_OFFSET + 0x0708) -#define LPASS_CDC_WSA_SPLINE_ASRC0_FIFO_CTL (WSA_START_OFFSET + 0x070C) -#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB \ - (WSA_START_OFFSET + 0x0710) -#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB \ - (WSA_START_OFFSET + 0x0714) -#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB \ - (WSA_START_OFFSET + 0x0718) -#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB \ - (WSA_START_OFFSET + 0x071C) -#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO (WSA_START_OFFSET + 0x0720) -#define LPASS_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL (WSA_START_OFFSET + 0x0740) -#define LPASS_CDC_WSA_SPLINE_ASRC1_CTL0 (WSA_START_OFFSET + 0x0744) -#define LPASS_CDC_WSA_SPLINE_ASRC1_CTL1 (WSA_START_OFFSET + 0x0748) -#define LPASS_CDC_WSA_SPLINE_ASRC1_FIFO_CTL (WSA_START_OFFSET + 0x074C) -#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB \ - (WSA_START_OFFSET + 0x0750) -#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB \ - (WSA_START_OFFSET + 0x0754) -#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB \ - (WSA_START_OFFSET + 0x0758) -#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB \ - (WSA_START_OFFSET + 0x075C) -#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO (WSA_START_OFFSET + 0x0760) -#define WSA_MAX_OFFSET (WSA_START_OFFSET + 0x0760) +#define LPASS_CDC_WSA_IDLE_DETECT_PATH_CTL (WSA_START_OFFSET + 0x0780) +#define LPASS_CDC_WSA_IDLE_DETECT_CFG0 (WSA_START_OFFSET + 0x0784) +#define LPASS_CDC_WSA_IDLE_DETECT_CFG1 (WSA_START_OFFSET + 0x0788) +#define LPASS_CDC_WSA_IDLE_DETECT_CFG2 (WSA_START_OFFSET + 0x078C) +#define LPASS_CDC_WSA_IDLE_DETECT_CFG3 (WSA_START_OFFSET + 0x0790) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL1 (WSA_START_OFFSET + 0x0900) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL2 (WSA_START_OFFSET + 0x0904) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL3 (WSA_START_OFFSET + 0x0908) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG1 (WSA_START_OFFSET + 0x090C) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG2 (WSA_START_OFFSET + 0x0910) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG3 (WSA_START_OFFSET + 0x0914) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG4 (WSA_START_OFFSET + 0x0918) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG5 (WSA_START_OFFSET + 0x091C) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG6 (WSA_START_OFFSET + 0x0920) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG7 (WSA_START_OFFSET + 0x0924) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG8 (WSA_START_OFFSET + 0x0928) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST1 \ + (WSA_START_OFFSET + 0x092C) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST2 \ + (WSA_START_OFFSET + 0x0930) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST3 \ + (WSA_START_OFFSET + 0x0934) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST4 \ + (WSA_START_OFFSET + 0x0938) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST1 (WSA_START_OFFSET + 0x093C) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST2 (WSA_START_OFFSET + 0x0940) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST3 (WSA_START_OFFSET + 0x0944) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST4 (WSA_START_OFFSET + 0x0948) +#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST5 (WSA_START_OFFSET + 0x094C) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_PATH_CTL (WSA_START_OFFSET + 0x0980) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_CFG (WSA_START_OFFSET + 0x0984) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL1 (WSA_START_OFFSET + 0x0988) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL2 (WSA_START_OFFSET + 0x098C) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL3 (WSA_START_OFFSET + 0x0990) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST1 (WSA_START_OFFSET + 0x0994) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST2 (WSA_START_OFFSET + 0x0998) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST3 (WSA_START_OFFSET + 0x099C) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC1 (WSA_START_OFFSET + 0x09A0) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC2 (WSA_START_OFFSET + 0x09A4) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC1 (WSA_START_OFFSET + 0x09A8) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC2 (WSA_START_OFFSET + 0x09AC) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC3 (WSA_START_OFFSET + 0x09B0) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC4 (WSA_START_OFFSET + 0x09B4) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD1 (WSA_START_OFFSET + 0x09B8) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD2 (WSA_START_OFFSET + 0x09BC) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD3 (WSA_START_OFFSET + 0x09C0) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD4 (WSA_START_OFFSET + 0x09C4) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD5 (WSA_START_OFFSET + 0x09C8) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_DEBUG1 (WSA_START_OFFSET + 0x09CC) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD_MON \ + (WSA_START_OFFSET + 0x09D0) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_MON_VAL \ + (WSA_START_OFFSET + 0x09D4) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BAN (WSA_START_OFFSET + 0x09D8) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD1 \ + (WSA_START_OFFSET + 0x09DC) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD2 \ + (WSA_START_OFFSET + 0x09E0) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD3 \ + (WSA_START_OFFSET + 0x09E4) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD4 \ + (WSA_START_OFFSET + 0x09E8) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD5 \ + (WSA_START_OFFSET + 0x09EC) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD6 \ + (WSA_START_OFFSET + 0x09F0) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD7 \ + (WSA_START_OFFSET + 0x09F4) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD8 \ + (WSA_START_OFFSET + 0x09F8) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD9 \ + (WSA_START_OFFSET + 0x09FC) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN1 (WSA_START_OFFSET + 0x0A00) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN2 (WSA_START_OFFSET + 0x0A04) +#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN3 (WSA_START_OFFSET + 0x0A08) +#define WSA_MAX_OFFSET (WSA_START_OFFSET + 0x0A08) -#define LPASS_CDC_WSA_MACRO_MAX 0x1D9 /* 0x760/4 = 0x1D8 + 1 registers */ +#define LPASS_CDC_WSA_MACRO_MAX 0x283 /* 0xA08/4 = 0x282 + 1 registers */ /* VA macro registers */ #define VA_START_OFFSET 0x3000 @@ -711,22 +883,18 @@ #define LPASS_CDC_VA_TOP_CSR_DMIC_CFG (VA_START_OFFSET + 0x0094) #define LPASS_CDC_VA_TOP_CSR_DEBUG_BUS (VA_START_OFFSET + 0x009C) #define LPASS_CDC_VA_TOP_CSR_DEBUG_EN (VA_START_OFFSET + 0x00A0) -#define LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL (VA_START_OFFSET + 0x00A4) +#define LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL (VA_START_OFFSET + 0x00A4) #define LPASS_CDC_VA_TOP_CSR_I2S_CLK (VA_START_OFFSET + 0x00A8) #define LPASS_CDC_VA_TOP_CSR_I2S_RESET (VA_START_OFFSET + 0x00AC) +#define LPASS_CDC_VA_TOP_CSR_DEBUG_CLK (VA_START_OFFSET + 0x00B0) #define LPASS_CDC_VA_TOP_CSR_CORE_ID_0 (VA_START_OFFSET + 0x00C0) #define LPASS_CDC_VA_TOP_CSR_CORE_ID_1 (VA_START_OFFSET + 0x00C4) #define LPASS_CDC_VA_TOP_CSR_CORE_ID_2 (VA_START_OFFSET + 0x00C8) #define LPASS_CDC_VA_TOP_CSR_CORE_ID_3 (VA_START_OFFSET + 0x00CC) -#define VA_TOP_MAX_OFFSET (VA_START_OFFSET + 0x00CC) - -#define LPASS_CDC_VA_MACRO_TOP_MAX 0x34 /* 0x0CC/4 = 0x33 + 1 = 0x34 */ - #define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL0 (VA_START_OFFSET + 0x00D0) #define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1 (VA_START_OFFSET + 0x00D4) #define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2 (VA_START_OFFSET + 0x00D8) #define LPASS_CDC_VA_TOP_CSR_SWR_CTRL (VA_START_OFFSET + 0x00DC) - #define LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0 (VA_START_OFFSET + 0x0100) #define LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1 (VA_START_OFFSET + 0x0104) #define LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0 (VA_START_OFFSET + 0x0108) @@ -735,15 +903,6 @@ #define LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG1 (VA_START_OFFSET + 0x0114) #define LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0 (VA_START_OFFSET + 0x0118) #define LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG1 (VA_START_OFFSET + 0x011C) -#define LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG0 (VA_START_OFFSET + 0x0120) -#define LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG1 (VA_START_OFFSET + 0x0124) -#define LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG0 (VA_START_OFFSET + 0x0128) -#define LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG1 (VA_START_OFFSET + 0x012C) -#define LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG0 (VA_START_OFFSET + 0x0130) -#define LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG1 (VA_START_OFFSET + 0x0134) -#define LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG0 (VA_START_OFFSET + 0x0138) -#define LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG1 (VA_START_OFFSET + 0x013C) - #define LPASS_CDC_VA_TX0_TX_PATH_CTL (VA_START_OFFSET + 0x0400) #define LPASS_CDC_VA_TX0_TX_PATH_CFG0 (VA_START_OFFSET + 0x0404) #define LPASS_CDC_VA_TX0_TX_PATH_CFG1 (VA_START_OFFSET + 0x0408) @@ -789,55 +948,290 @@ #define LPASS_CDC_VA_TX3_TX_PATH_SEC4 (VA_START_OFFSET + 0x05A0) #define LPASS_CDC_VA_TX3_TX_PATH_SEC5 (VA_START_OFFSET + 0x05A4) #define LPASS_CDC_VA_TX3_TX_PATH_SEC6 (VA_START_OFFSET + 0x05A8) -#define LPASS_CDC_VA_TX4_TX_PATH_CTL (VA_START_OFFSET + 0x0600) -#define LPASS_CDC_VA_TX4_TX_PATH_CFG0 (VA_START_OFFSET + 0x0604) -#define LPASS_CDC_VA_TX4_TX_PATH_CFG1 (VA_START_OFFSET + 0x0608) -#define LPASS_CDC_VA_TX4_TX_VOL_CTL (VA_START_OFFSET + 0x060C) -#define LPASS_CDC_VA_TX4_TX_PATH_SEC0 (VA_START_OFFSET + 0x0610) -#define LPASS_CDC_VA_TX4_TX_PATH_SEC1 (VA_START_OFFSET + 0x0614) -#define LPASS_CDC_VA_TX4_TX_PATH_SEC2 (VA_START_OFFSET + 0x0618) -#define LPASS_CDC_VA_TX4_TX_PATH_SEC3 (VA_START_OFFSET + 0x061C) -#define LPASS_CDC_VA_TX4_TX_PATH_SEC4 (VA_START_OFFSET + 0x0620) -#define LPASS_CDC_VA_TX4_TX_PATH_SEC5 (VA_START_OFFSET + 0x0624) -#define LPASS_CDC_VA_TX4_TX_PATH_SEC6 (VA_START_OFFSET + 0x0628) -#define LPASS_CDC_VA_TX5_TX_PATH_CTL (VA_START_OFFSET + 0x0680) -#define LPASS_CDC_VA_TX5_TX_PATH_CFG0 (VA_START_OFFSET + 0x0684) -#define LPASS_CDC_VA_TX5_TX_PATH_CFG1 (VA_START_OFFSET + 0x0688) -#define LPASS_CDC_VA_TX5_TX_VOL_CTL (VA_START_OFFSET + 0x068C) -#define LPASS_CDC_VA_TX5_TX_PATH_SEC0 (VA_START_OFFSET + 0x0690) -#define LPASS_CDC_VA_TX5_TX_PATH_SEC1 (VA_START_OFFSET + 0x0694) -#define LPASS_CDC_VA_TX5_TX_PATH_SEC2 (VA_START_OFFSET + 0x0698) -#define LPASS_CDC_VA_TX5_TX_PATH_SEC3 (VA_START_OFFSET + 0x069C) -#define LPASS_CDC_VA_TX5_TX_PATH_SEC4 (VA_START_OFFSET + 0x06A0) -#define LPASS_CDC_VA_TX5_TX_PATH_SEC5 (VA_START_OFFSET + 0x06A4) -#define LPASS_CDC_VA_TX5_TX_PATH_SEC6 (VA_START_OFFSET + 0x06A8) -#define LPASS_CDC_VA_TX6_TX_PATH_CTL (VA_START_OFFSET + 0x0700) -#define LPASS_CDC_VA_TX6_TX_PATH_CFG0 (VA_START_OFFSET + 0x0704) -#define LPASS_CDC_VA_TX6_TX_PATH_CFG1 (VA_START_OFFSET + 0x0708) -#define LPASS_CDC_VA_TX6_TX_VOL_CTL (VA_START_OFFSET + 0x070C) -#define LPASS_CDC_VA_TX6_TX_PATH_SEC0 (VA_START_OFFSET + 0x0710) -#define LPASS_CDC_VA_TX6_TX_PATH_SEC1 (VA_START_OFFSET + 0x0714) -#define LPASS_CDC_VA_TX6_TX_PATH_SEC2 (VA_START_OFFSET + 0x0718) -#define LPASS_CDC_VA_TX6_TX_PATH_SEC3 (VA_START_OFFSET + 0x071C) -#define LPASS_CDC_VA_TX6_TX_PATH_SEC4 (VA_START_OFFSET + 0x0720) -#define LPASS_CDC_VA_TX6_TX_PATH_SEC5 (VA_START_OFFSET + 0x0724) -#define LPASS_CDC_VA_TX6_TX_PATH_SEC6 (VA_START_OFFSET + 0x0728) -#define LPASS_CDC_VA_TX7_TX_PATH_CTL (VA_START_OFFSET + 0x0780) -#define LPASS_CDC_VA_TX7_TX_PATH_CFG0 (VA_START_OFFSET + 0x0784) -#define LPASS_CDC_VA_TX7_TX_PATH_CFG1 (VA_START_OFFSET + 0x0788) -#define LPASS_CDC_VA_TX7_TX_VOL_CTL (VA_START_OFFSET + 0x078C) -#define LPASS_CDC_VA_TX7_TX_PATH_SEC0 (VA_START_OFFSET + 0x0790) -#define LPASS_CDC_VA_TX7_TX_PATH_SEC1 (VA_START_OFFSET + 0x0794) -#define LPASS_CDC_VA_TX7_TX_PATH_SEC2 (VA_START_OFFSET + 0x0798) -#define LPASS_CDC_VA_TX7_TX_PATH_SEC3 (VA_START_OFFSET + 0x079C) -#define LPASS_CDC_VA_TX7_TX_PATH_SEC4 (VA_START_OFFSET + 0x07A0) -#define LPASS_CDC_VA_TX7_TX_PATH_SEC5 (VA_START_OFFSET + 0x07A4) -#define LPASS_CDC_VA_TX7_TX_PATH_SEC6 (VA_START_OFFSET + 0x07A8) -#define VA_MAX_OFFSET (VA_START_OFFSET + 0x07A8) +#define VA_MAX_OFFSET (VA_START_OFFSET + 0x05A8) -#define LPASS_CDC_VA_MACRO_MAX 0x1EB /* 7A8/4 = 1EA + 1 = 1EB */ +#define LPASS_CDC_VA_MACRO_MAX 0x16B /* 5A8/4 = 16A + 1 = 16B */ -#define LPASS_CDC_MAX_REGISTER VA_MAX_OFFSET +/* WSA2 - macro#5 */ +#define WSA2_START_OFFSET 0x4000 +#define LPASS_CDC_WSA2_CLK_RST_CTRL_MCLK_CONTROL \ + (WSA2_START_OFFSET + 0x0000) +#define LPASS_CDC_WSA2_CLK_RST_CTRL_FS_CNT_CONTROL \ + (WSA2_START_OFFSET + 0x0004) +#define LPASS_CDC_WSA2_CLK_RST_CTRL_SWR_CONTROL (WSA2_START_OFFSET + 0x0008) +#define LPASS_CDC_WSA2_TOP_TOP_CFG0 (WSA2_START_OFFSET + 0x0080) +#define LPASS_CDC_WSA2_TOP_TOP_CFG1 (WSA2_START_OFFSET + 0x0084) +#define LPASS_CDC_WSA2_TOP_FREQ_MCLK (WSA2_START_OFFSET + 0x0088) +#define LPASS_CDC_WSA2_TOP_DEBUG_BUS_SEL (WSA2_START_OFFSET + 0x008C) +#define LPASS_CDC_WSA2_TOP_DEBUG_EN0 (WSA2_START_OFFSET + 0x0090) +#define LPASS_CDC_WSA2_TOP_DEBUG_EN1 (WSA2_START_OFFSET + 0x0094) +#define LPASS_CDC_WSA2_TOP_DEBUG_DSM_LB (WSA2_START_OFFSET + 0x0098) +#define LPASS_CDC_WSA2_TOP_RX_I2S_CTL (WSA2_START_OFFSET + 0x009C) +#define LPASS_CDC_WSA2_TOP_TX_I2S_CTL (WSA2_START_OFFSET + 0x00A0) +#define LPASS_CDC_WSA2_TOP_I2S_CLK (WSA2_START_OFFSET + 0x00A4) +#define LPASS_CDC_WSA2_TOP_I2S_RESET (WSA2_START_OFFSET + 0x00A8) +#define LPASS_CDC_WSA2_TOP_FS_UNGATE (WSA2_START_OFFSET + 0x00AC) +#define LPASS_CDC_WSA2_TOP_GRP_SEL (WSA2_START_OFFSET + 0x00B0) +#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_LSB (WSA2_START_OFFSET + 0x00B4) +#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_MSB (WSA2_START_OFFSET + 0x00B8) +#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_LUT (WSA2_START_OFFSET + 0x00BC) +#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_LSB (WSA2_START_OFFSET + 0x00C0) +#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_MSB (WSA2_START_OFFSET + 0x00C4) +#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_LSB (WSA2_START_OFFSET + 0x00C8) +#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_MSB (WSA2_START_OFFSET + 0x00CC) +#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_LUT (WSA2_START_OFFSET + 0x00D0) +#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_LSB (WSA2_START_OFFSET + 0x00D4) +#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_MSB (WSA2_START_OFFSET + 0x00D8) +#define LPASS_CDC_WSA2_TOP_FS_UNGATE2 (WSA2_START_OFFSET + 0x00DC) +#define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0 (WSA2_START_OFFSET + 0x0100) +#define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG1 (WSA2_START_OFFSET + 0x0104) +#define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG0 (WSA2_START_OFFSET + 0x0108) +#define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG1 (WSA2_START_OFFSET + 0x010C) +#define LPASS_CDC_WSA2_RX_INP_MUX_RX_MIX_CFG0 (WSA2_START_OFFSET + 0x0110) +#define LPASS_CDC_WSA2_RX_INP_MUX_RX_EC_CFG0 (WSA2_START_OFFSET + 0x0114) +#define LPASS_CDC_WSA2_RX_INP_MUX_SOFTCLIP_CFG0 (WSA2_START_OFFSET + 0x0118) +/* VBAT registers */ +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_PATH_CTL (WSA2_START_OFFSET + 0x0180) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG (WSA2_START_OFFSET + 0x0184) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL1 (WSA2_START_OFFSET + 0x0188) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL2 (WSA2_START_OFFSET + 0x018C) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL3 (WSA2_START_OFFSET + 0x0190) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST1 (WSA2_START_OFFSET + 0x0194) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST2 (WSA2_START_OFFSET + 0x0198) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST3 (WSA2_START_OFFSET + 0x019C) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC1 (WSA2_START_OFFSET + 0x01A0) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC2 (WSA2_START_OFFSET + 0x01A4) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC1 (WSA2_START_OFFSET + 0x01A8) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC2 (WSA2_START_OFFSET + 0x01AC) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC3 (WSA2_START_OFFSET + 0x01B0) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC4 (WSA2_START_OFFSET + 0x01B4) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD1 (WSA2_START_OFFSET + 0x01B8) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD2 (WSA2_START_OFFSET + 0x01BC) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD3 (WSA2_START_OFFSET + 0x01C0) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD4 (WSA2_START_OFFSET + 0x01C4) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD5 (WSA2_START_OFFSET + 0x01C8) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_DEBUG1 (WSA2_START_OFFSET + 0x01CC) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD_MON \ + (WSA2_START_OFFSET + 0x01D0) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_MON_VAL \ + (WSA2_START_OFFSET + 0x01D4) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BAN (WSA2_START_OFFSET + 0x01D8) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD1 \ + (WSA2_START_OFFSET + 0x01DC) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD2 \ + (WSA2_START_OFFSET + 0x01E0) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD3 \ + (WSA2_START_OFFSET + 0x01E4) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD4 \ + (WSA2_START_OFFSET + 0x01E8) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD5 \ + (WSA2_START_OFFSET + 0x01EC) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD6 \ + (WSA2_START_OFFSET + 0x01F0) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD7 \ + (WSA2_START_OFFSET + 0x01F4) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD8 \ + (WSA2_START_OFFSET + 0x01F8) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD9 \ + (WSA2_START_OFFSET + 0x01FC) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN1 (WSA2_START_OFFSET + 0x0200) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN2 (WSA2_START_OFFSET + 0x0204) +#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN3 (WSA2_START_OFFSET + 0x0208) +#define LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL (WSA2_START_OFFSET + 0x0244) +#define LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CFG0 (WSA2_START_OFFSET + 0x0248) +#define LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL (WSA2_START_OFFSET + 0x0264) +#define LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CFG0 (WSA2_START_OFFSET + 0x0268) +#define LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL (WSA2_START_OFFSET + 0x0284) +#define LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CFG0 (WSA2_START_OFFSET + 0x0288) +#define LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL (WSA2_START_OFFSET + 0x02A4) +#define LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CFG0 (WSA2_START_OFFSET + 0x02A8) +#define LPASS_CDC_WSA2_INTR_CTRL_CFG (WSA2_START_OFFSET + 0x0340) +#define LPASS_CDC_WSA2_INTR_CTRL_CLR_COMMIT (WSA2_START_OFFSET + 0x0344) +#define LPASS_CDC_WSA2_INTR_CTRL_PIN1_MASK0 (WSA2_START_OFFSET + 0x0360) +#define LPASS_CDC_WSA2_INTR_CTRL_PIN1_STATUS0 (WSA2_START_OFFSET + 0x0368) +#define LPASS_CDC_WSA2_INTR_CTRL_PIN1_CLEAR0 (WSA2_START_OFFSET + 0x0370) +#define LPASS_CDC_WSA2_INTR_CTRL_PIN2_MASK0 (WSA2_START_OFFSET + 0x0380) +#define LPASS_CDC_WSA2_INTR_CTRL_PIN2_STATUS0 (WSA2_START_OFFSET + 0x0388) +#define LPASS_CDC_WSA2_INTR_CTRL_PIN2_CLEAR0 (WSA2_START_OFFSET + 0x0390) +#define LPASS_CDC_WSA2_INTR_CTRL_LEVEL0 (WSA2_START_OFFSET + 0x03C0) +#define LPASS_CDC_WSA2_INTR_CTRL_BYPASS0 (WSA2_START_OFFSET + 0x03C8) +#define LPASS_CDC_WSA2_INTR_CTRL_SET0 (WSA2_START_OFFSET + 0x03D0) +#define LPASS_CDC_WSA2_RX0_RX_PATH_CTL (WSA2_START_OFFSET + 0x0400) +#define LPASS_CDC_WSA2_RX0_RX_PATH_CFG0 (WSA2_START_OFFSET + 0x0404) +#define LPASS_CDC_WSA2_RX0_RX_PATH_CFG1 (WSA2_START_OFFSET + 0x0408) +#define LPASS_CDC_WSA2_RX0_RX_PATH_CFG2 (WSA2_START_OFFSET + 0x040C) +#define LPASS_CDC_WSA2_RX0_RX_PATH_CFG3 (WSA2_START_OFFSET + 0x0410) +#define LPASS_CDC_WSA2_RX0_RX_VOL_CTL (WSA2_START_OFFSET + 0x0414) +#define LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CTL (WSA2_START_OFFSET + 0x0418) +#define LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CFG (WSA2_START_OFFSET + 0x041C) +#define LPASS_CDC_WSA2_RX0_RX_VOL_MIX_CTL (WSA2_START_OFFSET + 0x0420) +#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC0 (WSA2_START_OFFSET + 0x0424) +#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC1 (WSA2_START_OFFSET + 0x0428) +#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC2 (WSA2_START_OFFSET + 0x042C) +#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC3 (WSA2_START_OFFSET + 0x0430) +#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC5 (WSA2_START_OFFSET + 0x0438) +#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC6 (WSA2_START_OFFSET + 0x043C) +#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC7 (WSA2_START_OFFSET + 0x0440) +#define LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC0 (WSA2_START_OFFSET + 0x0444) +#define LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC1 (WSA2_START_OFFSET + 0x0448) +#define LPASS_CDC_WSA2_RX0_RX_PATH_DSMDEM_CTL (WSA2_START_OFFSET + 0x044C) +#define LPASS_CDC_WSA2_RX1_RX_PATH_CTL (WSA2_START_OFFSET + 0x0480) +#define LPASS_CDC_WSA2_RX1_RX_PATH_CFG0 (WSA2_START_OFFSET + 0x0484) +#define LPASS_CDC_WSA2_RX1_RX_PATH_CFG1 (WSA2_START_OFFSET + 0x0488) +#define LPASS_CDC_WSA2_RX1_RX_PATH_CFG2 (WSA2_START_OFFSET + 0x048C) +#define LPASS_CDC_WSA2_RX1_RX_PATH_CFG3 (WSA2_START_OFFSET + 0x0490) +#define LPASS_CDC_WSA2_RX1_RX_VOL_CTL (WSA2_START_OFFSET + 0x0494) +#define LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CTL (WSA2_START_OFFSET + 0x0498) +#define LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CFG (WSA2_START_OFFSET + 0x049C) +#define LPASS_CDC_WSA2_RX1_RX_VOL_MIX_CTL (WSA2_START_OFFSET + 0x04A0) +#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC0 (WSA2_START_OFFSET + 0x04A4) +#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC1 (WSA2_START_OFFSET + 0x04A8) +#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC2 (WSA2_START_OFFSET + 0x04AC) +#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC3 (WSA2_START_OFFSET + 0x04B0) +#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC5 (WSA2_START_OFFSET + 0x04B8) +#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC6 (WSA2_START_OFFSET + 0x04BC) +#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC7 (WSA2_START_OFFSET + 0x04C0) +#define LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC0 (WSA2_START_OFFSET + 0x04C4) +#define LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC1 (WSA2_START_OFFSET + 0x04C8) +#define LPASS_CDC_WSA2_RX1_RX_PATH_DSMDEM_CTL (WSA2_START_OFFSET + 0x04CC) +#define LPASS_CDC_WSA2_BOOST0_BOOST_PATH_CTL (WSA2_START_OFFSET + 0x0500) +#define LPASS_CDC_WSA2_BOOST0_BOOST_CTL (WSA2_START_OFFSET + 0x0504) +#define LPASS_CDC_WSA2_BOOST0_BOOST_CFG1 (WSA2_START_OFFSET + 0x0508) +#define LPASS_CDC_WSA2_BOOST0_BOOST_CFG2 (WSA2_START_OFFSET + 0x050C) +#define LPASS_CDC_WSA2_BOOST1_BOOST_PATH_CTL (WSA2_START_OFFSET + 0x0540) +#define LPASS_CDC_WSA2_BOOST1_BOOST_CTL (WSA2_START_OFFSET + 0x0544) +#define LPASS_CDC_WSA2_BOOST1_BOOST_CFG1 (WSA2_START_OFFSET + 0x0548) +#define LPASS_CDC_WSA2_BOOST1_BOOST_CFG2 (WSA2_START_OFFSET + 0x054C) +#define LPASS_CDC_WSA2_COMPANDER0_CTL0 (WSA2_START_OFFSET + 0x0580) +#define LPASS_CDC_WSA2_COMPANDER0_CTL1 (WSA2_START_OFFSET + 0x0584) +#define LPASS_CDC_WSA2_COMPANDER0_CTL2 (WSA2_START_OFFSET + 0x0588) +#define LPASS_CDC_WSA2_COMPANDER0_CTL3 (WSA2_START_OFFSET + 0x058C) +#define LPASS_CDC_WSA2_COMPANDER0_CTL4 (WSA2_START_OFFSET + 0x0590) +#define LPASS_CDC_WSA2_COMPANDER0_CTL5 (WSA2_START_OFFSET + 0x0594) +#define LPASS_CDC_WSA2_COMPANDER0_CTL6 (WSA2_START_OFFSET + 0x0598) +#define LPASS_CDC_WSA2_COMPANDER0_CTL7 (WSA2_START_OFFSET + 0x059C) +#define LPASS_CDC_WSA2_COMPANDER0_CTL8 (WSA2_START_OFFSET + 0x05A0) +#define LPASS_CDC_WSA2_COMPANDER0_CTL9 (WSA2_START_OFFSET + 0x05A4) +#define LPASS_CDC_WSA2_COMPANDER0_CTL10 (WSA2_START_OFFSET + 0x05A8) +#define LPASS_CDC_WSA2_COMPANDER0_CTL11 (WSA2_START_OFFSET + 0x05AC) +#define LPASS_CDC_WSA2_COMPANDER0_CTL12 (WSA2_START_OFFSET + 0x05B0) +#define LPASS_CDC_WSA2_COMPANDER0_CTL13 (WSA2_START_OFFSET + 0x05B4) +#define LPASS_CDC_WSA2_COMPANDER0_CTL14 (WSA2_START_OFFSET + 0x05B8) +#define LPASS_CDC_WSA2_COMPANDER0_CTL15 (WSA2_START_OFFSET + 0x05BC) +#define LPASS_CDC_WSA2_COMPANDER0_CTL16 (WSA2_START_OFFSET + 0x05C0) +#define LPASS_CDC_WSA2_COMPANDER0_CTL17 (WSA2_START_OFFSET + 0x05C4) +#define LPASS_CDC_WSA2_COMPANDER0_CTL18 (WSA2_START_OFFSET + 0x05C8) +#define LPASS_CDC_WSA2_COMPANDER0_CTL19 (WSA2_START_OFFSET + 0x05CC) +#define LPASS_CDC_WSA2_COMPANDER1_CTL0 (WSA2_START_OFFSET + 0x05E0) +#define LPASS_CDC_WSA2_COMPANDER1_CTL1 (WSA2_START_OFFSET + 0x05E4) +#define LPASS_CDC_WSA2_COMPANDER1_CTL2 (WSA2_START_OFFSET + 0x05E8) +#define LPASS_CDC_WSA2_COMPANDER1_CTL3 (WSA2_START_OFFSET + 0x05EC) +#define LPASS_CDC_WSA2_COMPANDER1_CTL4 (WSA2_START_OFFSET + 0x05F0) +#define LPASS_CDC_WSA2_COMPANDER1_CTL5 (WSA2_START_OFFSET + 0x05F4) +#define LPASS_CDC_WSA2_COMPANDER1_CTL6 (WSA2_START_OFFSET + 0x05F8) +#define LPASS_CDC_WSA2_COMPANDER1_CTL7 (WSA2_START_OFFSET + 0x05FC) +#define LPASS_CDC_WSA2_COMPANDER1_CTL8 (WSA2_START_OFFSET + 0x0600) +#define LPASS_CDC_WSA2_COMPANDER1_CTL9 (WSA2_START_OFFSET + 0x0604) +#define LPASS_CDC_WSA2_COMPANDER1_CTL10 (WSA2_START_OFFSET + 0x0608) +#define LPASS_CDC_WSA2_COMPANDER1_CTL11 (WSA2_START_OFFSET + 0x060C) +#define LPASS_CDC_WSA2_COMPANDER1_CTL12 (WSA2_START_OFFSET + 0x0610) +#define LPASS_CDC_WSA2_COMPANDER1_CTL13 (WSA2_START_OFFSET + 0x0614) +#define LPASS_CDC_WSA2_COMPANDER1_CTL14 (WSA2_START_OFFSET + 0x0618) +#define LPASS_CDC_WSA2_COMPANDER1_CTL15 (WSA2_START_OFFSET + 0x061C) +#define LPASS_CDC_WSA2_COMPANDER1_CTL16 (WSA2_START_OFFSET + 0x0620) +#define LPASS_CDC_WSA2_COMPANDER1_CTL17 (WSA2_START_OFFSET + 0x0624) +#define LPASS_CDC_WSA2_COMPANDER1_CTL18 (WSA2_START_OFFSET + 0x0628) +#define LPASS_CDC_WSA2_COMPANDER1_CTL19 (WSA2_START_OFFSET + 0x062C) +#define LPASS_CDC_WSA2_SOFTCLIP0_CRC (WSA2_START_OFFSET + 0x0640) +#define LPASS_CDC_WSA2_SOFTCLIP0_SOFTCLIP_CTRL (WSA2_START_OFFSET + 0x0644) +#define LPASS_CDC_WSA2_SOFTCLIP1_CRC (WSA2_START_OFFSET + 0x0660) +#define LPASS_CDC_WSA2_SOFTCLIP1_SOFTCLIP_CTRL (WSA2_START_OFFSET + 0x0664) +#define LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_PATH_CTL \ + (WSA2_START_OFFSET + 0x0680) +#define LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_CFG0 (WSA2_START_OFFSET + 0x0684) +#define LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_PATH_CTL \ + (WSA2_START_OFFSET + 0x06C0) +#define LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_CFG0 (WSA2_START_OFFSET + 0x06C4) +#define LPASS_CDC_WSA2_IDLE_DETECT_PATH_CTL (WSA2_START_OFFSET + 0x0780) +#define LPASS_CDC_WSA2_IDLE_DETECT_CFG0 (WSA2_START_OFFSET + 0x0784) +#define LPASS_CDC_WSA2_IDLE_DETECT_CFG1 (WSA2_START_OFFSET + 0x0788) +#define LPASS_CDC_WSA2_IDLE_DETECT_CFG2 (WSA2_START_OFFSET + 0x078C) +#define LPASS_CDC_WSA2_IDLE_DETECT_CFG3 (WSA2_START_OFFSET + 0x0790) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL1 (WSA2_START_OFFSET + 0x0900) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL2 (WSA2_START_OFFSET + 0x0904) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL3 (WSA2_START_OFFSET + 0x0908) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG1 (WSA2_START_OFFSET + 0x090C) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG2 (WSA2_START_OFFSET + 0x0910) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG3 (WSA2_START_OFFSET + 0x0914) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG4 (WSA2_START_OFFSET + 0x0918) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG5 (WSA2_START_OFFSET + 0x091C) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG6 (WSA2_START_OFFSET + 0x0920) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG7 (WSA2_START_OFFSET + 0x0924) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG8 (WSA2_START_OFFSET + 0x0928) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST1 \ + (WSA2_START_OFFSET + 0x092C) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST2 \ + (WSA2_START_OFFSET + 0x0930) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST3 \ + (WSA2_START_OFFSET + 0x0934) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST4 \ + (WSA2_START_OFFSET + 0x0938) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST1 (WSA2_START_OFFSET + 0x093C) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST2 (WSA2_START_OFFSET + 0x0940) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST3 (WSA2_START_OFFSET + 0x0944) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST4 (WSA2_START_OFFSET + 0x0948) +#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST5 (WSA2_START_OFFSET + 0x094C) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PATH_CTL (WSA2_START_OFFSET + 0x0980) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_CFG (WSA2_START_OFFSET + 0x0984) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL1 (WSA2_START_OFFSET + 0x0988) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL2 (WSA2_START_OFFSET + 0x098C) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL3 (WSA2_START_OFFSET + 0x0990) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST1 (WSA2_START_OFFSET + 0x0994) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST2 (WSA2_START_OFFSET + 0x0998) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST3 (WSA2_START_OFFSET + 0x099C) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC1 (WSA2_START_OFFSET + 0x09A0) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC2 (WSA2_START_OFFSET + 0x09A4) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC1 (WSA2_START_OFFSET + 0x09A8) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC2 (WSA2_START_OFFSET + 0x09AC) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC3 (WSA2_START_OFFSET + 0x09B0) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC4 (WSA2_START_OFFSET + 0x09B4) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD1 (WSA2_START_OFFSET + 0x09B8) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD2 (WSA2_START_OFFSET + 0x09BC) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD3 (WSA2_START_OFFSET + 0x09C0) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD4 (WSA2_START_OFFSET + 0x09C4) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD5 (WSA2_START_OFFSET + 0x09C8) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_DEBUG1 (WSA2_START_OFFSET + 0x09CC) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD_MON \ + (WSA2_START_OFFSET + 0x09D0) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_MON_VAL \ + (WSA2_START_OFFSET + 0x09D4) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BAN (WSA2_START_OFFSET + 0x09D8) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD1 \ + (WSA2_START_OFFSET + 0x09DC) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD2 \ + (WSA2_START_OFFSET + 0x09E0) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD3 \ + (WSA2_START_OFFSET + 0x09E4) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD4 \ + (WSA2_START_OFFSET + 0x09E8) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD5 \ + (WSA2_START_OFFSET + 0x09EC) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD6 \ + (WSA2_START_OFFSET + 0x09F0) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD7 \ + (WSA2_START_OFFSET + 0x09F4) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD8 \ + (WSA2_START_OFFSET + 0x09F8) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD9 \ + (WSA2_START_OFFSET + 0x09FC) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN1 (WSA2_START_OFFSET + 0x0A00) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN2 (WSA2_START_OFFSET + 0x0A04) +#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN3 (WSA2_START_OFFSET + 0x0A08) +#define WSA2_MAX_OFFSET (WSA2_START_OFFSET + 0x0A08) + +#define LPASS_CDC_WSA2_MACRO_MAX 0x283 /* 0xA08/4 = 0x282 + 1 registers */ + +#define LPASS_CDC_MAX_REGISTER WSA2_MAX_OFFSET #define LPASS_CDC_REG(reg) (((reg) & 0x0FFF)/4) diff --git a/asoc/codecs/lpass-cdc/lpass-cdc-regmap.c b/asoc/codecs/lpass-cdc/lpass-cdc-regmap.c index b7c2f38aa3..2185926244 100644 --- a/asoc/codecs/lpass-cdc/lpass-cdc-regmap.c +++ b/asoc/codecs/lpass-cdc/lpass-cdc-regmap.c @@ -13,19 +13,18 @@ static const struct reg_default lpass_cdc_defaults[] = { { LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00}, { LPASS_CDC_TX_TOP_CSR_TOP_CFG0, 0x00}, { LPASS_CDC_TX_TOP_CSR_ANC_CFG, 0x00}, - { LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0x00}, - { LPASS_CDC_TX_TOP_CSR_FREQ_MCLK, 0x00}, + { LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0x60}, { LPASS_CDC_TX_TOP_CSR_DEBUG_BUS, 0x00}, { LPASS_CDC_TX_TOP_CSR_DEBUG_EN, 0x00}, { LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C}, { LPASS_CDC_TX_TOP_CSR_I2S_CLK, 0x00}, { LPASS_CDC_TX_TOP_CSR_I2S_RESET, 0x00}, - { LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00}, - { LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00}, - { LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00}, - { LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00}, - { LPASS_CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00}, - { LPASS_CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00}, + { LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL, 0x0E}, + { LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL, 0x0E}, + { LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL, 0x0E}, + { LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL, 0x0E}, + { LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL, 0x0E}, + { LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL, 0x0E}, { LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00}, { LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00}, { LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00}, @@ -150,6 +149,7 @@ static const struct reg_default lpass_cdc_defaults[] = { /* RX Macro */ { LPASS_CDC_RX_TOP_TOP_CFG0, 0x00}, + { LPASS_CDC_RX_TOP_TOP_CFG1, 0x00}, { LPASS_CDC_RX_TOP_SWR_CTRL, 0x00}, { LPASS_CDC_RX_TOP_DEBUG, 0x00}, { LPASS_CDC_RX_TOP_DEBUG_BUS, 0x00}, @@ -169,11 +169,11 @@ static const struct reg_default lpass_cdc_defaults[] = { { LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11}, { LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20}, { LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00}, - { LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00}, + { LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x08}, { LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11}, { LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20}, { LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00}, - { LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00}, + { LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x08}, { LPASS_CDC_RX_TOP_RX_I2S_CTL, 0x0C}, { LPASS_CDC_RX_TOP_TX_I2S2_CTL, 0x0C}, { LPASS_CDC_RX_TOP_I2S_CLK, 0x0C}, @@ -250,13 +250,6 @@ static const struct reg_default lpass_cdc_defaults[] = { { LPASS_CDC_RX_BCL_VBAT_ATTN1, 0x04}, { LPASS_CDC_RX_BCL_VBAT_ATTN2, 0x08}, { LPASS_CDC_RX_BCL_VBAT_ATTN3, 0x0C}, - { LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0}, - { LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00}, - { LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00}, - { LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00}, - { LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00}, - { LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00}, - { LPASS_CDC_RX_BCL_VBAT_DECODE_ST, 0x00}, { LPASS_CDC_RX_INTR_CTRL_CFG, 0x00}, { LPASS_CDC_RX_INTR_CTRL_CLR_COMMIT, 0x00}, { LPASS_CDC_RX_INTR_CTRL_PIN1_MASK0, 0xFF}, @@ -272,7 +265,7 @@ static const struct reg_default lpass_cdc_defaults[] = { { LPASS_CDC_RX_RX0_RX_PATH_CFG0, 0x00}, { LPASS_CDC_RX_RX0_RX_PATH_CFG1, 0x64}, { LPASS_CDC_RX_RX0_RX_PATH_CFG2, 0x8F}, - { LPASS_CDC_RX_RX0_RX_PATH_CFG3, 0x00}, + { LPASS_CDC_RX_RX0_RX_PATH_CFG3, 0x03}, { LPASS_CDC_RX_RX0_RX_VOL_CTL, 0x00}, { LPASS_CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04}, { LPASS_CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E}, @@ -291,11 +284,22 @@ static const struct reg_default lpass_cdc_defaults[] = { { LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55}, { LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55}, { LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55}, + { LPASS_CDC_RX_RX0_RX_FIR_CTL, 0x00}, + { LPASS_CDC_RX_RX0_RX_FIR_CFG, 0x64}, + { LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR, 0x00}, + { LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0, 0x00}, + { LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1, 0x00}, + { LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2, 0x00}, + { LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3, 0x00}, + { LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4, 0x00}, + { LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5, 0x00}, + { LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6, 0x00}, + { LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7, 0x00}, { LPASS_CDC_RX_RX1_RX_PATH_CTL, 0x04}, { LPASS_CDC_RX_RX1_RX_PATH_CFG0, 0x00}, { LPASS_CDC_RX_RX1_RX_PATH_CFG1, 0x64}, { LPASS_CDC_RX_RX1_RX_PATH_CFG2, 0x8F}, - { LPASS_CDC_RX_RX1_RX_PATH_CFG3, 0x00}, + { LPASS_CDC_RX_RX1_RX_PATH_CFG3, 0x03}, { LPASS_CDC_RX_RX1_RX_VOL_CTL, 0x00}, { LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04}, { LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E}, @@ -314,11 +318,22 @@ static const struct reg_default lpass_cdc_defaults[] = { { LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55}, { LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55}, { LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55}, + { LPASS_CDC_RX_RX1_RX_FIR_CTL, 0x00}, + { LPASS_CDC_RX_RX1_RX_FIR_CFG, 0x64}, + { LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR, 0x00}, + { LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0, 0x00}, + { LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1, 0x00}, + { LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2, 0x00}, + { LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3, 0x00}, + { LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4, 0x00}, + { LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5, 0x00}, + { LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6, 0x00}, + { LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7, 0x00}, { LPASS_CDC_RX_RX2_RX_PATH_CTL, 0x04}, { LPASS_CDC_RX_RX2_RX_PATH_CFG0, 0x00}, { LPASS_CDC_RX_RX2_RX_PATH_CFG1, 0x64}, { LPASS_CDC_RX_RX2_RX_PATH_CFG2, 0x8F}, - { LPASS_CDC_RX_RX2_RX_PATH_CFG3, 0x00}, + { LPASS_CDC_RX_RX2_RX_PATH_CFG3, 0x03}, { LPASS_CDC_RX_RX2_RX_VOL_CTL, 0x00}, { LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04}, { LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E}, @@ -334,6 +349,61 @@ static const struct reg_default lpass_cdc_defaults[] = { { LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08}, { LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00}, { LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1, 0x00}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2, 0x00}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3, 0x00}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1, 0x85}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2, 0xDC}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3, 0x85}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4, 0xDC}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5, 0x85}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6, 0xDC}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7, 0x32}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8, 0x00}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1, 0x00}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2, 0x00}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3, 0x00}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4, 0x00}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1, 0x00}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2, 0x00}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3, 0x00}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4, 0x00}, + { LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5, 0x00}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL, 0x00}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG, 0x10}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1, 0x00}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2, 0x00}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3, 0x04}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1, 0xE0}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2, 0x01}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3, 0x40}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1, 0x2A}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1, 0x00}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1, 0x00}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2, 0x18}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3, 0x18}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4, 0x03}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1, 0x01}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2, 0x00}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3, 0x00}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4, 0x64}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5, 0x01}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1, 0x00}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON, 0x00}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL, 0x00}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN, 0x0C}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1, 0x00}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2, 0x77}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3, 0x01}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4, 0x00}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5, 0x4B}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6, 0x00}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7, 0x01}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8, 0x00}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9, 0x00}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1, 0x04}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2, 0x08}, + { LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3, 0x0C}, { LPASS_CDC_RX_IDLE_DETECT_PATH_CTL, 0x00}, { LPASS_CDC_RX_IDLE_DETECT_CFG0, 0x07}, { LPASS_CDC_RX_IDLE_DETECT_CFG1, 0x3C}, @@ -347,6 +417,18 @@ static const struct reg_default lpass_cdc_defaults[] = { { LPASS_CDC_RX_COMPANDER0_CTL5, 0x00}, { LPASS_CDC_RX_COMPANDER0_CTL6, 0x01}, { LPASS_CDC_RX_COMPANDER0_CTL7, 0x28}, + { LPASS_CDC_RX_COMPANDER0_CTL8, 0x00}, + { LPASS_CDC_RX_COMPANDER0_CTL9, 0x00}, + { LPASS_CDC_RX_COMPANDER0_CTL10, 0x06}, + { LPASS_CDC_RX_COMPANDER0_CTL11, 0x12}, + { LPASS_CDC_RX_COMPANDER0_CTL12, 0x1E}, + { LPASS_CDC_RX_COMPANDER0_CTL13, 0x2A}, + { LPASS_CDC_RX_COMPANDER0_CTL14, 0x36}, + { LPASS_CDC_RX_COMPANDER0_CTL15, 0x3C}, + { LPASS_CDC_RX_COMPANDER0_CTL16, 0xC4}, + { LPASS_CDC_RX_COMPANDER0_CTL17, 0x00}, + { LPASS_CDC_RX_COMPANDER0_CTL18, 0x0C}, + { LPASS_CDC_RX_COMPANDER0_CTL19, 0x16}, { LPASS_CDC_RX_COMPANDER1_CTL0, 0x60}, { LPASS_CDC_RX_COMPANDER1_CTL1, 0xDB}, { LPASS_CDC_RX_COMPANDER1_CTL2, 0xFF}, @@ -355,6 +437,18 @@ static const struct reg_default lpass_cdc_defaults[] = { { LPASS_CDC_RX_COMPANDER1_CTL5, 0x00}, { LPASS_CDC_RX_COMPANDER1_CTL6, 0x01}, { LPASS_CDC_RX_COMPANDER1_CTL7, 0x28}, + { LPASS_CDC_RX_COMPANDER1_CTL8, 0x00}, + { LPASS_CDC_RX_COMPANDER1_CTL9, 0x00}, + { LPASS_CDC_RX_COMPANDER1_CTL10, 0x06}, + { LPASS_CDC_RX_COMPANDER1_CTL11, 0x12}, + { LPASS_CDC_RX_COMPANDER1_CTL12, 0x1E}, + { LPASS_CDC_RX_COMPANDER1_CTL13, 0x2A}, + { LPASS_CDC_RX_COMPANDER1_CTL14, 0x36}, + { LPASS_CDC_RX_COMPANDER1_CTL15, 0x3C}, + { LPASS_CDC_RX_COMPANDER1_CTL16, 0xC4}, + { LPASS_CDC_RX_COMPANDER1_CTL17, 0x00}, + { LPASS_CDC_RX_COMPANDER1_CTL18, 0x0C}, + { LPASS_CDC_RX_COMPANDER1_CTL19, 0x16}, { LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00}, { LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00}, { LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00}, @@ -450,6 +544,19 @@ static const struct reg_default lpass_cdc_defaults[] = { { LPASS_CDC_WSA_TOP_TX_I2S_CTL, 0x0C}, { LPASS_CDC_WSA_TOP_I2S_CLK, 0x02}, { LPASS_CDC_WSA_TOP_I2S_RESET, 0x00}, + { LPASS_CDC_WSA_TOP_FS_UNGATE, 0xFF}, + { LPASS_CDC_WSA_TOP_GRP_SEL, 0x08}, + { LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_LSB, 0x00}, + { LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_MSB, 0x00}, + { LPASS_CDC_WSA_TOP_SPKR_COMP7_LUT, 0x00}, + { LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_LSB, 0x00}, + { LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_MSB, 0x00}, + { LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_LSB, 0x00}, + { LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_MSB, 0x00}, + { LPASS_CDC_WSA_TOP_SPKR_COMP8_LUT, 0x00}, + { LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_LSB, 0x00}, + { LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_MSB, 0x00}, + { LPASS_CDC_WSA_TOP_FS_UNGATE2, 0x03}, { LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00}, { LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00}, { LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00}, @@ -492,13 +599,6 @@ static const struct reg_default lpass_cdc_defaults[] = { { LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1, 0x04}, { LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2, 0x08}, { LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3, 0x0C}, - { LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1, 0xE0}, - { LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2, 0x00}, - { LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1, 0x00}, - { LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2, 0x00}, - { LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3, 0x00}, - { LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4, 0x00}, - { LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST, 0x00}, { LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02}, { LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00}, { LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02}, @@ -571,6 +671,18 @@ static const struct reg_default lpass_cdc_defaults[] = { { LPASS_CDC_WSA_COMPANDER0_CTL5, 0x00}, { LPASS_CDC_WSA_COMPANDER0_CTL6, 0x01}, { LPASS_CDC_WSA_COMPANDER0_CTL7, 0x28}, + { LPASS_CDC_WSA_COMPANDER0_CTL8, 0x00}, + { LPASS_CDC_WSA_COMPANDER0_CTL9, 0x00}, + { LPASS_CDC_WSA_COMPANDER0_CTL10, 0x06}, + { LPASS_CDC_WSA_COMPANDER0_CTL11, 0x12}, + { LPASS_CDC_WSA_COMPANDER0_CTL12, 0x1E}, + { LPASS_CDC_WSA_COMPANDER0_CTL13, 0x24}, + { LPASS_CDC_WSA_COMPANDER0_CTL14, 0x24}, + { LPASS_CDC_WSA_COMPANDER0_CTL15, 0x24}, + { LPASS_CDC_WSA_COMPANDER0_CTL16, 0x00}, + { LPASS_CDC_WSA_COMPANDER0_CTL17, 0x24}, + { LPASS_CDC_WSA_COMPANDER0_CTL18, 0x2A}, + { LPASS_CDC_WSA_COMPANDER0_CTL19, 0x16}, { LPASS_CDC_WSA_COMPANDER1_CTL0, 0x60}, { LPASS_CDC_WSA_COMPANDER1_CTL1, 0xDB}, { LPASS_CDC_WSA_COMPANDER1_CTL2, 0xFF}, @@ -579,6 +691,18 @@ static const struct reg_default lpass_cdc_defaults[] = { { LPASS_CDC_WSA_COMPANDER1_CTL5, 0x00}, { LPASS_CDC_WSA_COMPANDER1_CTL6, 0x01}, { LPASS_CDC_WSA_COMPANDER1_CTL7, 0x28}, + { LPASS_CDC_WSA_COMPANDER1_CTL8, 0x00}, + { LPASS_CDC_WSA_COMPANDER1_CTL9, 0x00}, + { LPASS_CDC_WSA_COMPANDER1_CTL10, 0x06}, + { LPASS_CDC_WSA_COMPANDER1_CTL11, 0x12}, + { LPASS_CDC_WSA_COMPANDER1_CTL12, 0x1E}, + { LPASS_CDC_WSA_COMPANDER1_CTL13, 0x24}, + { LPASS_CDC_WSA_COMPANDER1_CTL14, 0x24}, + { LPASS_CDC_WSA_COMPANDER1_CTL15, 0x24}, + { LPASS_CDC_WSA_COMPANDER1_CTL16, 0x00}, + { LPASS_CDC_WSA_COMPANDER1_CTL17, 0x24}, + { LPASS_CDC_WSA_COMPANDER1_CTL18, 0x2A}, + { LPASS_CDC_WSA_COMPANDER1_CTL19, 0x16}, { LPASS_CDC_WSA_SOFTCLIP0_CRC, 0x00}, { LPASS_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38}, { LPASS_CDC_WSA_SOFTCLIP1_CRC, 0x00}, @@ -587,24 +711,66 @@ static const struct reg_default lpass_cdc_defaults[] = { { LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01}, { LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00}, { LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01}, - { LPASS_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00}, - { LPASS_CDC_WSA_SPLINE_ASRC0_CTL0, 0x00}, - { LPASS_CDC_WSA_SPLINE_ASRC0_CTL1, 0x00}, - { LPASS_CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8}, - { LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00}, - { LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00}, - { LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00}, - { LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00}, - { LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00}, - { LPASS_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00}, - { LPASS_CDC_WSA_SPLINE_ASRC1_CTL0, 0x00}, - { LPASS_CDC_WSA_SPLINE_ASRC1_CTL1, 0x00}, - { LPASS_CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8}, - { LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00}, - { LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00}, - { LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00}, - { LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00}, - { LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00}, + { LPASS_CDC_WSA_IDLE_DETECT_PATH_CTL, 0x00}, + { LPASS_CDC_WSA_IDLE_DETECT_CFG0, 0x07}, + { LPASS_CDC_WSA_IDLE_DETECT_CFG1, 0x3C}, + { LPASS_CDC_WSA_IDLE_DETECT_CFG2, 0x00}, + { LPASS_CDC_WSA_IDLE_DETECT_CFG3, 0x00}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL1, 0x00}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL2, 0x00}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL3, 0x00}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG1, 0x85}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG2, 0xDC}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG3, 0x85}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG4, 0xDC}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG5, 0x85}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG6, 0xDC}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG7, 0x32}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG8, 0x00}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST1, 0x00}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST2, 0x00}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST3, 0x00}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST4, 0x00}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST1, 0x00}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST2, 0x00}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST3, 0x00}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST4, 0x00}, + { LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST5, 0x00}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_PATH_CTL, 0x00}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_CFG, 0x10}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL1, 0x00}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL2, 0x00}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL3, 0x04}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST1, 0xE0}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST2, 0x01}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST3, 0x40}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC1, 0x2A}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC1, 0x00}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC1, 0x00}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC2, 0x18}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC3, 0x18}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC4, 0x03}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD1, 0x01}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD2, 0x00}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD3, 0x00}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD4, 0x64}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD5, 0x01}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_DEBUG1, 0x00}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD_MON, 0x00}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_MON_VAL, 0x00}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_BAN, 0x0C}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD1, 0x00}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD2, 0x77}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD3, 0x01}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD4, 0x00}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD5, 0x4B}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD6, 0x00}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD7, 0x01}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD8, 0x00}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD9, 0x00}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN1, 0x04}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN2, 0x08}, + { LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN3, 0x0C}, /* VA macro */ { LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, @@ -639,14 +805,6 @@ static const struct reg_default lpass_cdc_defaults[] = { { LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00}, { LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00}, { LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00}, - { LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG0, 0x00}, - { LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG1, 0x00}, - { LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG0, 0x00}, - { LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG1, 0x00}, - { LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG0, 0x00}, - { LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG1, 0x00}, - { LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG0, 0x00}, - { LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG1, 0x00}, { LPASS_CDC_VA_TX0_TX_PATH_CTL, 0x04}, { LPASS_CDC_VA_TX0_TX_PATH_CFG0, 0x10}, { LPASS_CDC_VA_TX0_TX_PATH_CFG1, 0x0B}, @@ -692,50 +850,249 @@ static const struct reg_default lpass_cdc_defaults[] = { { LPASS_CDC_VA_TX3_TX_PATH_SEC4, 0x20}, { LPASS_CDC_VA_TX3_TX_PATH_SEC5, 0x00}, { LPASS_CDC_VA_TX3_TX_PATH_SEC6, 0x00}, - { LPASS_CDC_VA_TX4_TX_PATH_CTL, 0x04}, - { LPASS_CDC_VA_TX4_TX_PATH_CFG0, 0x10}, - { LPASS_CDC_VA_TX4_TX_PATH_CFG1, 0x0B}, - { LPASS_CDC_VA_TX4_TX_VOL_CTL, 0x00}, - { LPASS_CDC_VA_TX4_TX_PATH_SEC0, 0x00}, - { LPASS_CDC_VA_TX4_TX_PATH_SEC1, 0x00}, - { LPASS_CDC_VA_TX4_TX_PATH_SEC2, 0x01}, - { LPASS_CDC_VA_TX4_TX_PATH_SEC3, 0x3C}, - { LPASS_CDC_VA_TX4_TX_PATH_SEC4, 0x20}, - { LPASS_CDC_VA_TX4_TX_PATH_SEC5, 0x00}, - { LPASS_CDC_VA_TX4_TX_PATH_SEC6, 0x00}, - { LPASS_CDC_VA_TX5_TX_PATH_CTL, 0x04}, - { LPASS_CDC_VA_TX5_TX_PATH_CFG0, 0x10}, - { LPASS_CDC_VA_TX5_TX_PATH_CFG1, 0x0B}, - { LPASS_CDC_VA_TX5_TX_VOL_CTL, 0x00}, - { LPASS_CDC_VA_TX5_TX_PATH_SEC0, 0x00}, - { LPASS_CDC_VA_TX5_TX_PATH_SEC1, 0x00}, - { LPASS_CDC_VA_TX5_TX_PATH_SEC2, 0x01}, - { LPASS_CDC_VA_TX5_TX_PATH_SEC3, 0x3C}, - { LPASS_CDC_VA_TX5_TX_PATH_SEC4, 0x20}, - { LPASS_CDC_VA_TX5_TX_PATH_SEC5, 0x00}, - { LPASS_CDC_VA_TX5_TX_PATH_SEC6, 0x00}, - { LPASS_CDC_VA_TX6_TX_PATH_CTL, 0x04}, - { LPASS_CDC_VA_TX6_TX_PATH_CFG0, 0x10}, - { LPASS_CDC_VA_TX6_TX_PATH_CFG1, 0x0B}, - { LPASS_CDC_VA_TX6_TX_VOL_CTL, 0x00}, - { LPASS_CDC_VA_TX6_TX_PATH_SEC0, 0x00}, - { LPASS_CDC_VA_TX6_TX_PATH_SEC1, 0x00}, - { LPASS_CDC_VA_TX6_TX_PATH_SEC2, 0x01}, - { LPASS_CDC_VA_TX6_TX_PATH_SEC3, 0x3C}, - { LPASS_CDC_VA_TX6_TX_PATH_SEC4, 0x20}, - { LPASS_CDC_VA_TX6_TX_PATH_SEC5, 0x00}, - { LPASS_CDC_VA_TX6_TX_PATH_SEC6, 0x00}, - { LPASS_CDC_VA_TX7_TX_PATH_CTL, 0x04}, - { LPASS_CDC_VA_TX7_TX_PATH_CFG0, 0x10}, - { LPASS_CDC_VA_TX7_TX_PATH_CFG1, 0x0B}, - { LPASS_CDC_VA_TX7_TX_VOL_CTL, 0x00}, - { LPASS_CDC_VA_TX7_TX_PATH_SEC0, 0x00}, - { LPASS_CDC_VA_TX7_TX_PATH_SEC1, 0x00}, - { LPASS_CDC_VA_TX7_TX_PATH_SEC2, 0x01}, - { LPASS_CDC_VA_TX7_TX_PATH_SEC3, 0x3C}, - { LPASS_CDC_VA_TX7_TX_PATH_SEC4, 0x20}, - { LPASS_CDC_VA_TX7_TX_PATH_SEC5, 0x00}, - { LPASS_CDC_VA_TX7_TX_PATH_SEC6, 0x00}, + + /* WSA2 Macro */ + { LPASS_CDC_WSA2_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, + { LPASS_CDC_WSA2_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, + { LPASS_CDC_WSA2_CLK_RST_CTRL_SWR_CONTROL, 0x00}, + { LPASS_CDC_WSA2_TOP_TOP_CFG0, 0x00}, + { LPASS_CDC_WSA2_TOP_TOP_CFG1, 0x00}, + { LPASS_CDC_WSA2_TOP_FREQ_MCLK, 0x00}, + { LPASS_CDC_WSA2_TOP_DEBUG_BUS_SEL, 0x00}, + { LPASS_CDC_WSA2_TOP_DEBUG_EN0, 0x00}, + { LPASS_CDC_WSA2_TOP_DEBUG_EN1, 0x00}, + { LPASS_CDC_WSA2_TOP_DEBUG_DSM_LB, 0x88}, + { LPASS_CDC_WSA2_TOP_RX_I2S_CTL, 0x0C}, + { LPASS_CDC_WSA2_TOP_TX_I2S_CTL, 0x0C}, + { LPASS_CDC_WSA2_TOP_I2S_CLK, 0x02}, + { LPASS_CDC_WSA2_TOP_I2S_RESET, 0x00}, + { LPASS_CDC_WSA2_TOP_FS_UNGATE, 0xFF}, + { LPASS_CDC_WSA2_TOP_GRP_SEL, 0x08}, + { LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_LSB, 0x00}, + { LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_MSB, 0x00}, + { LPASS_CDC_WSA2_TOP_SPKR_COMP7_LUT, 0x00}, + { LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_LSB, 0x00}, + { LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_MSB, 0x00}, + { LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_LSB, 0x00}, + { LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_MSB, 0x00}, + { LPASS_CDC_WSA2_TOP_SPKR_COMP8_LUT, 0x00}, + { LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_LSB, 0x00}, + { LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_MSB, 0x00}, + { LPASS_CDC_WSA2_TOP_FS_UNGATE2, 0x03}, + { LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0, 0x00}, + { LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG1, 0x00}, + { LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG0, 0x00}, + { LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG1, 0x00}, + { LPASS_CDC_WSA2_RX_INP_MUX_RX_MIX_CFG0, 0x00}, + { LPASS_CDC_WSA2_RX_INP_MUX_RX_EC_CFG0, 0x00}, + { LPASS_CDC_WSA2_RX_INP_MUX_SOFTCLIP_CFG0, 0x00}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_PATH_CTL, 0x00}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG, 0x10}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL1, 0x00}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL2, 0x00}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL3, 0x04}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST1, 0xE0}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST2, 0x01}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST3, 0x40}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC1, 0x2A}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC2, 0x00}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC1, 0x00}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC2, 0x18}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC3, 0x18}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC4, 0x03}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD1, 0x01}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD2, 0x00}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD3, 0x00}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD4, 0x64}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD5, 0x01}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_DEBUG1, 0x00}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD_MON, 0x00}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_MON_VAL, 0x00}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_BAN, 0x0C}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD1, 0x00}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD2, 0x77}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD3, 0x01}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD4, 0x00}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD5, 0x4B}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD6, 0x00}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD7, 0x01}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD8, 0x00}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD9, 0x00}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN1, 0x04}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN2, 0x08}, + { LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN3, 0x0C}, + { LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL, 0x02}, + { LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CFG0, 0x00}, + { LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL, 0x02}, + { LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CFG0, 0x00}, + { LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL, 0x02}, + { LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CFG0, 0x00}, + { LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL, 0x02}, + { LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CFG0, 0x00}, + { LPASS_CDC_WSA2_INTR_CTRL_CFG, 0x00}, + { LPASS_CDC_WSA2_INTR_CTRL_CLR_COMMIT, 0x00}, + { LPASS_CDC_WSA2_INTR_CTRL_PIN1_MASK0, 0xFF}, + { LPASS_CDC_WSA2_INTR_CTRL_PIN1_STATUS0, 0x00}, + { LPASS_CDC_WSA2_INTR_CTRL_PIN1_CLEAR0, 0x00}, + { LPASS_CDC_WSA2_INTR_CTRL_PIN2_MASK0, 0xFF}, + { LPASS_CDC_WSA2_INTR_CTRL_PIN2_STATUS0, 0x00}, + { LPASS_CDC_WSA2_INTR_CTRL_PIN2_CLEAR0, 0x00}, + { LPASS_CDC_WSA2_INTR_CTRL_LEVEL0, 0x00}, + { LPASS_CDC_WSA2_INTR_CTRL_BYPASS0, 0x00}, + { LPASS_CDC_WSA2_INTR_CTRL_SET0, 0x00}, + { LPASS_CDC_WSA2_RX0_RX_PATH_CTL, 0x04}, + { LPASS_CDC_WSA2_RX0_RX_PATH_CFG0, 0x00}, + { LPASS_CDC_WSA2_RX0_RX_PATH_CFG1, 0x64}, + { LPASS_CDC_WSA2_RX0_RX_PATH_CFG2, 0x8F}, + { LPASS_CDC_WSA2_RX0_RX_PATH_CFG3, 0x00}, + { LPASS_CDC_WSA2_RX0_RX_VOL_CTL, 0x00}, + { LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CTL, 0x04}, + { LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CFG, 0x7E}, + { LPASS_CDC_WSA2_RX0_RX_VOL_MIX_CTL, 0x00}, + { LPASS_CDC_WSA2_RX0_RX_PATH_SEC0, 0x04}, + { LPASS_CDC_WSA2_RX0_RX_PATH_SEC1, 0x08}, + { LPASS_CDC_WSA2_RX0_RX_PATH_SEC2, 0x00}, + { LPASS_CDC_WSA2_RX0_RX_PATH_SEC3, 0x00}, + { LPASS_CDC_WSA2_RX0_RX_PATH_SEC5, 0x00}, + { LPASS_CDC_WSA2_RX0_RX_PATH_SEC6, 0x00}, + { LPASS_CDC_WSA2_RX0_RX_PATH_SEC7, 0x00}, + { LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC0, 0x08}, + { LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC1, 0x00}, + { LPASS_CDC_WSA2_RX0_RX_PATH_DSMDEM_CTL, 0x00}, + { LPASS_CDC_WSA2_RX1_RX_PATH_CFG0, 0x00}, + { LPASS_CDC_WSA2_RX1_RX_PATH_CFG1, 0x64}, + { LPASS_CDC_WSA2_RX1_RX_PATH_CFG2, 0x8F}, + { LPASS_CDC_WSA2_RX1_RX_PATH_CFG3, 0x00}, + { LPASS_CDC_WSA2_RX1_RX_VOL_CTL, 0x00}, + { LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CTL, 0x04}, + { LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CFG, 0x7E}, + { LPASS_CDC_WSA2_RX1_RX_VOL_MIX_CTL, 0x00}, + { LPASS_CDC_WSA2_RX1_RX_PATH_SEC0, 0x04}, + { LPASS_CDC_WSA2_RX1_RX_PATH_SEC1, 0x08}, + { LPASS_CDC_WSA2_RX1_RX_PATH_SEC2, 0x00}, + { LPASS_CDC_WSA2_RX1_RX_PATH_SEC3, 0x00}, + { LPASS_CDC_WSA2_RX1_RX_PATH_SEC5, 0x00}, + { LPASS_CDC_WSA2_RX1_RX_PATH_SEC6, 0x00}, + { LPASS_CDC_WSA2_RX1_RX_PATH_SEC7, 0x00}, + { LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC0, 0x08}, + { LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC1, 0x00}, + { LPASS_CDC_WSA2_RX1_RX_PATH_DSMDEM_CTL, 0x00}, + { LPASS_CDC_WSA2_BOOST0_BOOST_PATH_CTL, 0x00}, + { LPASS_CDC_WSA2_BOOST0_BOOST_CTL, 0xD0}, + { LPASS_CDC_WSA2_BOOST0_BOOST_CFG1, 0x89}, + { LPASS_CDC_WSA2_BOOST0_BOOST_CFG2, 0x04}, + { LPASS_CDC_WSA2_BOOST1_BOOST_PATH_CTL, 0x00}, + { LPASS_CDC_WSA2_BOOST1_BOOST_CTL, 0xD0}, + { LPASS_CDC_WSA2_BOOST1_BOOST_CFG1, 0x89}, + { LPASS_CDC_WSA2_BOOST1_BOOST_CFG2, 0x04}, + { LPASS_CDC_WSA2_COMPANDER0_CTL0, 0x60}, + { LPASS_CDC_WSA2_COMPANDER0_CTL1, 0xDB}, + { LPASS_CDC_WSA2_COMPANDER0_CTL2, 0xFF}, + { LPASS_CDC_WSA2_COMPANDER0_CTL3, 0x35}, + { LPASS_CDC_WSA2_COMPANDER0_CTL4, 0xFF}, + { LPASS_CDC_WSA2_COMPANDER0_CTL5, 0x00}, + { LPASS_CDC_WSA2_COMPANDER0_CTL6, 0x01}, + { LPASS_CDC_WSA2_COMPANDER0_CTL7, 0x28}, + { LPASS_CDC_WSA2_COMPANDER0_CTL8, 0x00}, + { LPASS_CDC_WSA2_COMPANDER0_CTL9, 0x00}, + { LPASS_CDC_WSA2_COMPANDER0_CTL10, 0x06}, + { LPASS_CDC_WSA2_COMPANDER0_CTL11, 0x12}, + { LPASS_CDC_WSA2_COMPANDER0_CTL12, 0x1E}, + { LPASS_CDC_WSA2_COMPANDER0_CTL13, 0x24}, + { LPASS_CDC_WSA2_COMPANDER0_CTL14, 0x24}, + { LPASS_CDC_WSA2_COMPANDER0_CTL15, 0x24}, + { LPASS_CDC_WSA2_COMPANDER0_CTL16, 0x00}, + { LPASS_CDC_WSA2_COMPANDER0_CTL17, 0x24}, + { LPASS_CDC_WSA2_COMPANDER0_CTL18, 0x2A}, + { LPASS_CDC_WSA2_COMPANDER0_CTL19, 0x16}, + { LPASS_CDC_WSA2_COMPANDER1_CTL0, 0x60}, + { LPASS_CDC_WSA2_COMPANDER1_CTL1, 0xDB}, + { LPASS_CDC_WSA2_COMPANDER1_CTL2, 0xFF}, + { LPASS_CDC_WSA2_COMPANDER1_CTL3, 0x35}, + { LPASS_CDC_WSA2_COMPANDER1_CTL4, 0xFF}, + { LPASS_CDC_WSA2_COMPANDER1_CTL5, 0x00}, + { LPASS_CDC_WSA2_COMPANDER1_CTL6, 0x01}, + { LPASS_CDC_WSA2_COMPANDER1_CTL7, 0x28}, + { LPASS_CDC_WSA2_COMPANDER1_CTL8, 0x00}, + { LPASS_CDC_WSA2_COMPANDER1_CTL9, 0x00}, + { LPASS_CDC_WSA2_COMPANDER1_CTL10, 0x06}, + { LPASS_CDC_WSA2_COMPANDER1_CTL11, 0x12}, + { LPASS_CDC_WSA2_COMPANDER1_CTL12, 0x1E}, + { LPASS_CDC_WSA2_COMPANDER1_CTL13, 0x24}, + { LPASS_CDC_WSA2_COMPANDER1_CTL14, 0x24}, + { LPASS_CDC_WSA2_COMPANDER1_CTL15, 0x24}, + { LPASS_CDC_WSA2_COMPANDER1_CTL16, 0x00}, + { LPASS_CDC_WSA2_COMPANDER1_CTL17, 0x24}, + { LPASS_CDC_WSA2_COMPANDER1_CTL18, 0x2A}, + { LPASS_CDC_WSA2_COMPANDER1_CTL19, 0x16}, + { LPASS_CDC_WSA2_SOFTCLIP0_CRC, 0x00}, + { LPASS_CDC_WSA2_SOFTCLIP0_SOFTCLIP_CTRL, 0x38}, + { LPASS_CDC_WSA2_SOFTCLIP1_CRC, 0x00}, + { LPASS_CDC_WSA2_SOFTCLIP1_SOFTCLIP_CTRL, 0x38}, + { LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00}, + { LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_CFG0, 0x01}, + { LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00}, + { LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_CFG0, 0x01}, + { LPASS_CDC_WSA2_IDLE_DETECT_PATH_CTL, 0x00}, + { LPASS_CDC_WSA2_IDLE_DETECT_CFG0, 0x07}, + { LPASS_CDC_WSA2_IDLE_DETECT_CFG1, 0x3C}, + { LPASS_CDC_WSA2_IDLE_DETECT_CFG2, 0x00}, + { LPASS_CDC_WSA2_IDLE_DETECT_CFG3, 0x00}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL1, 0x00}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL2, 0x00}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL3, 0x00}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG1, 0x85}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG2, 0xDC}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG3, 0x85}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG4, 0xDC}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG5, 0x85}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG6, 0xDC}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG7, 0x32}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG8, 0x00}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST1, 0x00}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST2, 0x00}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST3, 0x00}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST4, 0x00}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST1, 0x00}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST2, 0x00}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST3, 0x00}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST4, 0x00}, + { LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST5, 0x00}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PATH_CTL, 0x00}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_CFG, 0x10}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL1, 0x00}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL2, 0x00}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL3, 0x04}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST1, 0xE0}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST2, 0x01}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST3, 0x40}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC1, 0x2A}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC1, 0x00}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC1, 0x00}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC2, 0x18}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC3, 0x18}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC4, 0x03}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD1, 0x01}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD2, 0x00}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD3, 0x00}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD4, 0x64}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD5, 0x01}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_DEBUG1, 0x00}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD_MON, 0x00}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_MON_VAL, 0x00}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BAN, 0x0C}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD1, 0x00}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD2, 0x77}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD3, 0x01}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD4, 0x00}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD5, 0x4B}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD6, 0x00}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD7, 0x01}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD8, 0x00}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD9, 0x00}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN1, 0x04}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN2, 0x08}, + { LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN3, 0x0C}, }; static bool lpass_cdc_is_readable_register(struct device *dev, @@ -801,28 +1158,22 @@ static bool lpass_cdc_is_volatile_register(struct device *dev, case LPASS_CDC_VA_TOP_CSR_DMIC1_CTL: case LPASS_CDC_VA_TOP_CSR_DMIC2_CTL: case LPASS_CDC_VA_TOP_CSR_DMIC3_CTL: - case LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL: - case LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL: - case LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL: - case LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL: + case LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL: + case LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL: + case LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL: + case LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL: case LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL: case LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL: case LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_MON_VAL: - case LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST: case LPASS_CDC_WSA_INTR_CTRL_PIN1_STATUS0: case LPASS_CDC_WSA_INTR_CTRL_PIN2_STATUS0: case LPASS_CDC_WSA_COMPANDER0_CTL6: case LPASS_CDC_WSA_COMPANDER1_CTL6: - case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB: - case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB: - case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB: - case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB: - case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO: - case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB: - case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB: - case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB: - case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB: - case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO: + case LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_MON_VAL: + case LPASS_CDC_WSA2_INTR_CTRL_PIN1_STATUS0: + case LPASS_CDC_WSA2_INTR_CTRL_PIN2_STATUS0: + case LPASS_CDC_WSA2_COMPANDER0_CTL6: + case LPASS_CDC_WSA2_COMPANDER1_CTL6: case LPASS_CDC_RX_TOP_HPHL_COMP_RD_LSB: case LPASS_CDC_RX_TOP_HPHL_COMP_WR_LSB: case LPASS_CDC_RX_TOP_HPHL_COMP_RD_MSB: @@ -834,7 +1185,6 @@ static bool lpass_cdc_is_volatile_register(struct device *dev, case LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG2: case LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG2: case LPASS_CDC_RX_BCL_VBAT_GAIN_MON_VAL: - case LPASS_CDC_RX_BCL_VBAT_DECODE_ST: case LPASS_CDC_RX_INTR_CTRL_PIN1_STATUS0: case LPASS_CDC_RX_INTR_CTRL_PIN2_STATUS0: case LPASS_CDC_RX_COMPANDER0_CTL6: diff --git a/asoc/codecs/lpass-cdc/lpass-cdc-rx-macro.c b/asoc/codecs/lpass-cdc/lpass-cdc-rx-macro.c index f5f4781449..cc59dfcf9a 100644 --- a/asoc/codecs/lpass-cdc/lpass-cdc-rx-macro.c +++ b/asoc/codecs/lpass-cdc/lpass-cdc-rx-macro.c @@ -3863,30 +3863,8 @@ static void lpass_cdc_rx_macro_init_bcl_pmic_reg(struct snd_soc_component *compo switch (rx_priv->bcl_pmic_params.id) { case 0: - /* Enable ID0 to listen to respective PMIC group interrupts */ - snd_soc_component_update_bits(component, - LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1, 0x02, 0x02); - /* Update MC_SID0 */ - snd_soc_component_update_bits(component, - LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1, 0x0F, - rx_priv->bcl_pmic_params.sid); - /* Update MC_PPID0 */ - snd_soc_component_update_bits(component, - LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2, 0xFF, - rx_priv->bcl_pmic_params.ppid); break; case 1: - /* Enable ID1 to listen to respective PMIC group interrupts */ - snd_soc_component_update_bits(component, - LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1, 0x01, 0x01); - /* Update MC_SID1 */ - snd_soc_component_update_bits(component, - LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3, 0x0F, - rx_priv->bcl_pmic_params.sid); - /* Update MC_PPID1 */ - snd_soc_component_update_bits(component, - LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1, 0xFF, - rx_priv->bcl_pmic_params.ppid); break; default: dev_err(rx_dev, "%s: PMIC ID is invalid %d\n", diff --git a/asoc/codecs/lpass-cdc/lpass-cdc-tables.c b/asoc/codecs/lpass-cdc/lpass-cdc-tables.c index fd79ff5a27..60b8846114 100644 --- a/asoc/codecs/lpass-cdc/lpass-cdc-tables.c +++ b/asoc/codecs/lpass-cdc/lpass-cdc-tables.c @@ -14,34 +14,17 @@ u8 lpass_cdc_tx_reg_access[LPASS_CDC_TX_MACRO_MAX] = { [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TOP_CFG0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_ANC_CFG)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_CTRL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_FREQ_MCLK)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_BUS)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_EN)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_I2S_CLK)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_I2S_RESET)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_AMIC0_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_AMIC1_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_CLK_RESET_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_1_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_2_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_SHIFT)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_SHIFT)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_A_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_B_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FB_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_SMLPF_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_DCFLT_SHIFT_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_1_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_2_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_GAIN_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG, @@ -58,6 +41,22 @@ u8 lpass_cdc_tx_reg_access[LPASS_CDC_TX_MACRO_MAX] = { [LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG1)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_CLK_RESET_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_1_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_2_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_SHIFT)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_SHIFT)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_A_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_B_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FB_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_SMLPF_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_DCFLT_SHIFT_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_1_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_2_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_GAIN_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CFG0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CFG1)] = RD_WR_REG, @@ -149,98 +148,9 @@ u8 lpass_cdc_tx_reg_access[LPASS_CDC_TX_MACRO_MAX] = { [LPASS_CDC_REG(LPASS_CDC_TX7_TX_PATH_SEC6)] = RD_WR_REG, }; -u8 lpass_cdc_tx_reg_access_v2[LPASS_CDC_TX_MACRO_MAX] = { - [LPASS_CDC_REG(LPASS_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TOP_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_ANC_CFG)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_CTRL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_FREQ_MCLK)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_BUS)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_EN)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_I2S_CLK)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_I2S_RESET)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_AMIC0_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_AMIC1_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_CLK_RESET_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_1_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_2_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_SHIFT)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_SHIFT)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_A_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_B_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FB_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_SMLPF_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_DCFLT_SHIFT_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_1_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_2_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_GAIN_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX0_TX_VOL_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC4)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC5)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC6)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC7)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX1_TX_VOL_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC4)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC5)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC6)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX2_TX_VOL_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC4)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC5)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC6)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX3_TX_VOL_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC4)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC5)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC6)] = RD_WR_REG, -}; - u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = { [LPASS_CDC_REG(LPASS_CDC_RX_TOP_TOP_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_TOP_TOP_CFG1)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_TOP_SWR_CTRL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_TOP_DEBUG)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_TOP_DEBUG_BUS)] = RD_WR_REG, @@ -341,13 +251,6 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = { [LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_ATTN1)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_ATTN2)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_ATTN3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_ST)] = RD_REG, [LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_CFG)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_CLR_COMMIT)] = WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_PIN1_MASK0)] = RD_WR_REG, @@ -382,6 +285,17 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = { [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_CFG)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CFG0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CFG1)] = RD_WR_REG, @@ -405,6 +319,17 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = { [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_CFG)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CFG0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CFG1)] = RD_WR_REG, @@ -425,6 +350,61 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = { [LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3)] = WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON)] = WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_PATH_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_CFG0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_CFG1)] = RD_WR_REG, @@ -438,6 +418,18 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = { [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL5)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL6)] = RD_REG, [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL7)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL8)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL9)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL10)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL11)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL12)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL13)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL14)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL15)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL16)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL17)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL18)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL19)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL1)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL2)] = RD_WR_REG, @@ -446,6 +438,18 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = { [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL5)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL6)] = RD_REG, [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL7)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL8)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL9)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL10)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL11)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL12)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL13)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL14)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL15)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL16)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL17)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL18)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL19)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL)] = RD_WR_REG, @@ -530,200 +534,6 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = { }; u8 lpass_cdc_va_reg_access[LPASS_CDC_VA_MACRO_MAX] = { - [LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC2_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC3_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_CLK)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_RESET)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_VOL_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC4)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC5)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC6)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC7)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_VOL_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC4)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC5)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC6)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_VOL_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC4)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC5)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC6)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_VOL_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC4)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC5)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC6)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_VOL_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC4)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC5)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC6)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_VOL_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC4)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC5)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC6)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_VOL_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC4)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC5)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC6)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_VOL_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC4)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC5)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC6)] = RD_WR_REG, -}; - -u8 lpass_cdc_va_top_reg_access[LPASS_CDC_VA_MACRO_TOP_MAX] = { - [LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG, -}; - -u8 lpass_cdc_va_reg_access_v2[LPASS_CDC_VA_MACRO_MAX] = { - [LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC2_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC3_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_CLK)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_RESET)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_CTRL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_VOL_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC4)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC5)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC6)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC7)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_VOL_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC4)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC5)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC6)] = RD_WR_REG, -}; - -u8 lpass_cdc_va_reg_access_v3[LPASS_CDC_VA_MACRO_MAX] = { [LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG, @@ -816,6 +626,19 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = { [LPASS_CDC_REG(LPASS_CDC_WSA_TOP_TX_I2S_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_TOP_I2S_CLK)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_TOP_I2S_RESET)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_TOP_FS_UNGATE)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_TOP_GRP_SEL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_LSB)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_MSB)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP7_LUT)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_LSB)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_MSB)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_LSB)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_MSB)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_LUT)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_LSB)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_MSB)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_TOP_FS_UNGATE2)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0)] = RD_WR_REG, @@ -858,13 +681,6 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = { [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST)] = RD_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CTL)] = RD_WR_REG, @@ -938,6 +754,18 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = { [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL5)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL6)] = RD_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL7)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL8)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL9)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL10)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL11)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL12)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL13)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL14)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL15)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL16)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL17)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL18)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL19)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL1)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL2)] = RD_WR_REG, @@ -946,6 +774,18 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = { [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL5)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL6)] = RD_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL7)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL8)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL9)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL10)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL11)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL12)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL13)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL14)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL15)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL16)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL17)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL18)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL19)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_SOFTCLIP0_CRC)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_SOFTCLIP1_CRC)] = RD_WR_REG, @@ -954,24 +794,311 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = { [LPASS_CDC_REG(LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_CTL0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_CTL1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_FIFO_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_CTL0)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_CTL1)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_FIFO_CTL)] = RD_WR_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB)] = RD_REG, - [LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_IDLE_DETECT_PATH_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_IDLE_DETECT_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_IDLE_DETECT_CFG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_IDLE_DETECT_CFG2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_IDLE_DETECT_CFG3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL3)] = WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG6)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG7)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG8)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST1)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST2)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST3)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST4)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST5)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_PATH_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_CFG)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_DEBUG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD_MON)] = WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_MON_VAL)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BAN)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN3)] = RD_WR_REG, +}; + +u8 lpass_cdc_wsa2_reg_access[LPASS_CDC_WSA2_MACRO_MAX] = { + [LPASS_CDC_REG(LPASS_CDC_WSA2_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_TOP_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_TOP_CFG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_FREQ_MCLK)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_DEBUG_BUS_SEL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_DEBUG_EN0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_DEBUG_EN1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_DEBUG_DSM_LB)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_RX_I2S_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_TX_I2S_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_I2S_CLK)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_I2S_RESET)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_FS_UNGATE)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_GRP_SEL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_LSB)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_MSB)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP7_LUT)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_LSB)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_MSB)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_LSB)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_MSB)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_LUT)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_LSB)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_MSB)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_FS_UNGATE2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_MIX_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_EC_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_SOFTCLIP_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_PATH_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_DEBUG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD_MON)] = WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_MON_VAL)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BAN)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_CFG)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_CLR_COMMIT)] = WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN1_MASK0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN1_STATUS0)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN1_CLEAR0)] = WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN2_MASK0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN2_STATUS0)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN2_CLEAR0)] = WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_LEVEL0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_BYPASS0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_SET0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_CFG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_CFG2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_CFG3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_VOL_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CFG)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_VOL_MIX_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC6)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC7)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_DSMDEM_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_CFG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_CFG2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_CFG3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_VOL_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CFG)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_VOL_MIX_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC6)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC7)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_DSMDEM_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST0_BOOST_PATH_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST0_BOOST_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST0_BOOST_CFG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST0_BOOST_CFG2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST1_BOOST_PATH_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST1_BOOST_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST1_BOOST_CFG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST1_BOOST_CFG2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL6)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL7)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL8)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL9)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL10)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL11)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL12)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL13)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL14)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL15)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL16)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL17)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL18)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL19)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL6)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL7)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL8)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL9)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL10)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL11)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL12)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL13)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL14)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL15)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL16)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL17)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL18)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL19)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_SOFTCLIP0_CRC)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_SOFTCLIP0_SOFTCLIP_CTRL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_SOFTCLIP1_CRC)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_SOFTCLIP1_SOFTCLIP_CTRL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_PATH_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_PATH_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_IDLE_DETECT_PATH_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_IDLE_DETECT_CFG0)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_IDLE_DETECT_CFG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_IDLE_DETECT_CFG2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_IDLE_DETECT_CFG3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL3)] = WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG6)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG7)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG8)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST1)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST2)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST3)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST4)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST5)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PATH_CTL)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_CFG)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_DEBUG1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD_MON)] = WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_MON_VAL)] = RD_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BAN)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN1)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN2)] = RD_WR_REG, + [LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN3)] = RD_WR_REG, }; u8 *lpass_cdc_reg_access[MAX_MACRO] = { @@ -979,4 +1106,5 @@ u8 *lpass_cdc_reg_access[MAX_MACRO] = { [RX_MACRO] = lpass_cdc_rx_reg_access, [WSA_MACRO] = lpass_cdc_wsa_reg_access, [VA_MACRO] = lpass_cdc_va_reg_access, + [WSA2_MACRO] = lpass_cdc_wsa2_reg_access, }; diff --git a/asoc/codecs/lpass-cdc/lpass-cdc-tx-macro.c b/asoc/codecs/lpass-cdc/lpass-cdc-tx-macro.c index 2dc874db5e..ff8b037e28 100644 --- a/asoc/codecs/lpass-cdc/lpass-cdc-tx-macro.c +++ b/asoc/codecs/lpass-cdc/lpass-cdc-tx-macro.c @@ -12,8 +12,6 @@ #include #include #include -#include -#include #include #include "lpass-cdc.h" #include "lpass-cdc-registers.h" @@ -64,25 +62,6 @@ static int lpass_cdc_tx_macro_get_channel_map(struct snd_soc_dai *dai, #define LPASS_CDC_TX_MACRO_SWR_STRING_LEN 80 #define LPASS_CDC_TX_MACRO_CHILD_DEVICES_MAX 3 -/* Hold instance to soundwire platform device */ -struct lpass_cdc_tx_macro_swr_ctrl_data { - struct platform_device *tx_swr_pdev; -}; - -struct lpass_cdc_tx_macro_swr_ctrl_platform_data { - void *handle; /* holds codec private data */ - int (*read)(void *handle, int reg); - int (*write)(void *handle, int reg, int val); - int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len); - int (*clk)(void *handle, bool enable); - int (*core_vote)(void *handle, bool enable); - int (*handle_irq)(void *handle, - irqreturn_t (*swrm_irq_handler)(int irq, - void *data), - void *swrm_handle, - int action); -}; - enum { LPASS_CDC_TX_MACRO_AIF_INVALID = 0, LPASS_CDC_TX_MACRO_AIF1_CAP, @@ -146,39 +125,25 @@ struct lpass_cdc_tx_macro_priv { struct device *dev; bool dec_active[NUM_DECIMATORS]; int tx_mclk_users; - int swr_clk_users; bool dapm_mclk_enable; - bool reset_swr; struct mutex mclk_lock; - struct mutex swr_clk_lock; struct snd_soc_component *component; - struct device_node *tx_swr_gpio_p; - struct lpass_cdc_tx_macro_swr_ctrl_data *swr_ctrl_data; - struct lpass_cdc_tx_macro_swr_ctrl_platform_data swr_plat_data; - struct work_struct lpass_cdc_tx_macro_add_child_devices_work; struct hpf_work tx_hpf_work[NUM_DECIMATORS]; struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS]; u16 dmic_clk_div; u32 version; - u32 is_used_tx_swr_gpio; unsigned long active_ch_mask[LPASS_CDC_TX_MACRO_MAX_DAIS]; unsigned long active_ch_cnt[LPASS_CDC_TX_MACRO_MAX_DAIS]; char __iomem *tx_io_base; struct platform_device *pdev_child_devices [LPASS_CDC_TX_MACRO_CHILD_DEVICES_MAX]; int child_count; - int tx_swr_clk_cnt; - int va_swr_clk_cnt; - int va_clk_status; - int tx_clk_status; bool bcs_enable; int dec_mode[NUM_DECIMATORS]; int bcs_ch; bool bcs_clk_en; bool hs_slow_insert_complete; int amic_sample_rate; - bool lpi_enable; - bool register_event_listener; }; static bool lpass_cdc_tx_macro_get_data(struct snd_soc_component *component, @@ -243,9 +208,6 @@ static int lpass_cdc_tx_macro_mclk_enable( TX_START_OFFSET, TX_MAX_OFFSET); if (tx_priv->tx_mclk_users == 0) { - /* 9.6MHz MCLK, set value 0x00 if other frequency */ - regmap_update_bits(regmap, - LPASS_CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01); regmap_update_bits(regmap, LPASS_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x01, 0x01); @@ -295,83 +257,6 @@ static int __lpass_cdc_tx_macro_mclk_enable(struct snd_soc_component *component, return lpass_cdc_tx_macro_mclk_enable(tx_priv, enable); } -static int lpass_cdc_tx_macro_va_swr_clk_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - struct device *tx_dev = NULL; - struct lpass_cdc_tx_macro_priv *tx_priv = NULL; - struct snd_soc_component *component = - snd_soc_dapm_to_component(w->dapm); - - if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) - return -EINVAL; - - if (SND_SOC_DAPM_EVENT_ON(event)) - ++tx_priv->va_swr_clk_cnt; - if (SND_SOC_DAPM_EVENT_OFF(event)) - --tx_priv->va_swr_clk_cnt; - - return 0; -} - -static int lpass_cdc_tx_macro_tx_swr_clk_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - struct device *tx_dev = NULL; - struct lpass_cdc_tx_macro_priv *tx_priv = NULL; - struct snd_soc_component *component = - snd_soc_dapm_to_component(w->dapm); - - if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) - return -EINVAL; - - if (SND_SOC_DAPM_EVENT_ON(event)) - ++tx_priv->tx_swr_clk_cnt; - if (SND_SOC_DAPM_EVENT_OFF(event)) - --tx_priv->tx_swr_clk_cnt; - - return 0; -} - -static int lpass_cdc_tx_macro_swr_pwr_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - struct snd_soc_component *component = - snd_soc_dapm_to_component(w->dapm); - int ret = 0; - struct device *tx_dev = NULL; - struct lpass_cdc_tx_macro_priv *tx_priv = NULL; - - if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) - return -EINVAL; - - dev_dbg(tx_dev, "%s: event = %d, lpi_enable = %d\n", - __func__, event, tx_priv->lpi_enable); - - if (!tx_priv->lpi_enable) - return ret; - - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - if (tx_priv->lpi_enable) { - lpass_cdc_register_event_listener(component, true); - tx_priv->register_event_listener = true; - } - break; - case SND_SOC_DAPM_POST_PMD: - if (tx_priv->register_event_listener) { - tx_priv->register_event_listener = false; - lpass_cdc_register_event_listener(component, false); - } - break; - default: - dev_err(tx_priv->dev, - "%s: invalid DAPM event %d\n", __func__, event); - ret = -EINVAL; - } - return ret; -} - static int lpass_cdc_tx_macro_mclk_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { @@ -418,11 +303,6 @@ static int lpass_cdc_tx_macro_event_handler(struct snd_soc_component *component, switch (event) { case LPASS_CDC_MACRO_EVT_SSR_DOWN: trace_printk("%s, enter SSR down\n", __func__); - if (tx_priv->swr_ctrl_data) { - swrm_wcd_notify( - tx_priv->swr_ctrl_data[0].tx_swr_pdev, - SWR_DEVICE_SSR_DOWN, NULL); - } if ((!pm_runtime_enabled(tx_dev) || !pm_runtime_suspended(tx_dev))) { ret = lpass_cdc_runtime_suspend(tx_dev); @@ -435,12 +315,6 @@ static int lpass_cdc_tx_macro_event_handler(struct snd_soc_component *component, break; case LPASS_CDC_MACRO_EVT_SSR_UP: trace_printk("%s, enter SSR up\n", __func__); - /* reset swr after ssr/pdr */ - tx_priv->reset_swr = true; - if (tx_priv->swr_ctrl_data) - swrm_wcd_notify( - tx_priv->swr_ctrl_data[0].tx_swr_pdev, - SWR_DEVICE_SSR_UP, NULL); break; case LPASS_CDC_MACRO_EVT_CLK_RESET: lpass_cdc_rsc_clk_reset(tx_dev, TX_CORE_CLK); @@ -461,25 +335,6 @@ static int lpass_cdc_tx_macro_event_handler(struct snd_soc_component *component, return 0; } -static int lpass_cdc_tx_macro_reg_wake_irq(struct snd_soc_component *component, - u32 data) -{ - struct device *tx_dev = NULL; - struct lpass_cdc_tx_macro_priv *tx_priv = NULL; - u32 ipc_wakeup = data; - int ret = 0; - - if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) - return -EINVAL; - - if (tx_priv->swr_ctrl_data) - ret = swrm_wcd_notify( - tx_priv->swr_ctrl_data[0].tx_swr_pdev, - SWR_REGISTER_WAKE_IRQ, &ipc_wakeup); - - return ret; -} - static bool is_amic_enabled(struct snd_soc_component *component, int decimator) { u16 adc_mux_reg = 0, adc_reg = 0; @@ -493,9 +348,8 @@ static bool is_amic_enabled(struct snd_soc_component *component, int decimator) adc_mux_reg = LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + LPASS_CDC_TX_MACRO_ADC_MUX_CFG_OFFSET * decimator; + if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) { - if (tx_priv->version == LPASS_CDC_VERSION_2_1) - return true; adc_reg = LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + LPASS_CDC_TX_MACRO_ADC_MUX_CFG_OFFSET * decimator; adc_n = snd_soc_component_read(component, adc_reg) & @@ -672,7 +526,7 @@ static int lpass_cdc_tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol, LPASS_CDC_VA_TOP_CSR_DMIC_CFG, 0x80, 0x00); dmic_clk_reg = - LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL + + LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL + ((val - 5)/2) * 4; snd_soc_component_update_bits(component, dmic_clk_reg, @@ -828,38 +682,6 @@ static int lpass_cdc_tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol, return 0; } -static int lpass_cdc_tx_macro_lpi_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_component *component = - snd_soc_kcontrol_component(kcontrol); - struct device *tx_dev = NULL; - struct lpass_cdc_tx_macro_priv *tx_priv = NULL; - - if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) - return -EINVAL; - - ucontrol->value.integer.value[0] = tx_priv->lpi_enable; - - return 0; -} - -static int lpass_cdc_tx_macro_lpi_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_component *component = - snd_soc_kcontrol_component(kcontrol); - struct device *tx_dev = NULL; - struct lpass_cdc_tx_macro_priv *tx_priv = NULL; - - if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) - return -EINVAL; - - tx_priv->lpi_enable = ucontrol->value.integer.value[0]; - - return 0; -} - static int lpass_cdc_tx_macro_bcs_ch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { @@ -948,12 +770,12 @@ static int lpass_cdc_tx_macro_get_bcs_ch_sel(struct snd_kcontrol *kcontrol, if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) return -EINVAL; - if (tx_priv->version == LPASS_CDC_VERSION_2_1) - value = (snd_soc_component_read(component, + //if (tx_priv->version == LPASS_CDC_VERSION_2_1) + value = (snd_soc_component_read(component, LPASS_CDC_VA_TOP_CSR_SWR_CTRL)) & 0x0F; - else if (tx_priv->version == LPASS_CDC_VERSION_2_0) - value = (snd_soc_component_read(component, - LPASS_CDC_TX_TOP_CSR_SWR_CTRL)) & 0x0F; + //else if (tx_priv->version == LPASS_CDC_VERSION_2_0) + // value = (snd_soc_component_read32(component, + // LPASS_CDC_TX_TOP_CSR_SWR_CTRL)) & 0x0F; ucontrol->value.integer.value[0] = value; return 0; @@ -976,12 +798,12 @@ static int lpass_cdc_tx_macro_put_bcs_ch_sel(struct snd_kcontrol *kcontrol, return -EINVAL; value = ucontrol->value.integer.value[0]; - if (tx_priv->version == LPASS_CDC_VERSION_2_1) - snd_soc_component_update_bits(component, + //if (tx_priv->version == LPASS_CDC_VERSION_2_1) + snd_soc_component_update_bits(component, LPASS_CDC_VA_TOP_CSR_SWR_CTRL, 0x0F, value); - else if (tx_priv->version == LPASS_CDC_VERSION_2_0) - snd_soc_component_update_bits(component, - LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0x0F, value); + //else if (tx_priv->version == LPASS_CDC_VERSION_2_0) + // snd_soc_component_update_bits(component, + // LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0x0F, value); return 0; } @@ -1146,7 +968,7 @@ static int lpass_cdc_tx_macro_enable_dec(struct snd_soc_dapm_widget *w, LPASS_CDC_TX0_TX_PATH_SEC7, 0x40, 0x40); } - if (tx_priv->version == LPASS_CDC_VERSION_2_0) { + //if (tx_priv->version == LPASS_CDC_VERSION_2_0) { if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) { snd_soc_component_update_bits(component, @@ -1171,7 +993,7 @@ static int lpass_cdc_tx_macro_enable_dec(struct snd_soc_dapm_widget *w, LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL, 0x0E, 0x00); } - } + //} break; case SND_SOC_DAPM_PRE_PMD: hpf_cut_off_freq = @@ -1207,13 +1029,13 @@ static int lpass_cdc_tx_macro_enable_dec(struct snd_soc_dapm_widget *w, cancel_delayed_work_sync( &tx_priv->tx_mute_dwork[decimator].dwork); - if (tx_priv->version == LPASS_CDC_VERSION_2_0) { + //if (tx_priv->version == LPASS_CDC_VERSION_2_0) { if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) snd_soc_component_update_bits(component, LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0x01, 0x00); - } + //} break; case SND_SOC_DAPM_POST_PMD: snd_soc_component_update_bits(component, tx_vol_ctl_reg, @@ -1228,14 +1050,14 @@ static int lpass_cdc_tx_macro_enable_dec(struct snd_soc_dapm_widget *w, snd_soc_component_update_bits(component, LPASS_CDC_TX0_TX_PATH_SEC7, 0x40, 0x00); tx_priv->bcs_clk_en = false; - if (tx_priv->version == LPASS_CDC_VERSION_2_1) - snd_soc_component_update_bits(component, + //if (tx_priv->version == LPASS_CDC_VERSION_2_1) + snd_soc_component_update_bits(component, LPASS_CDC_VA_TOP_CSR_SWR_CTRL, 0x0F, 0x00); - else if (tx_priv->version == LPASS_CDC_VERSION_2_0) - snd_soc_component_update_bits(component, - LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0xF0, - 0x00); + //else if (tx_priv->version == LPASS_CDC_VERSION_2_0) + // snd_soc_component_update_bits(component, + // LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0xF0, + // 0x00); } break; } @@ -1485,9 +1307,9 @@ LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_dmic7, LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0, lpass_cdc_tx_macro_put_dec_enum); static const char * const smic_mux_text[] = { - "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", "SWR_DMIC0", - "SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", "SWR_DMIC4", - "SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7" + "ZERO", "SWR_MIC0", "SWR_MIC1", "SWR_MIC2", "SWR_MIC3", + "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7", + "SWR_MIC8", "SWR_MIC9", "SWR_MIC10", "SWR_MIC11" }; LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic0, LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0, @@ -1522,44 +1344,6 @@ LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic7, LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, smic_mux_text, snd_soc_dapm_get_enum_double, lpass_cdc_tx_macro_put_dec_enum); -static const char * const smic_mux_text_v2[] = { - "ZERO", "SWR_MIC0", "SWR_MIC1", "SWR_MIC2", "SWR_MIC3", - "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7", - "SWR_MIC8", "SWR_MIC9", "SWR_MIC10", "SWR_MIC11" -}; - -LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic0_v2, LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0, - 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, - lpass_cdc_tx_macro_put_dec_enum); - -LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic1_v2, LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0, - 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, - lpass_cdc_tx_macro_put_dec_enum); - -LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic2_v2, LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG0, - 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, - lpass_cdc_tx_macro_put_dec_enum); - -LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic3_v2, LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG0, - 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, - lpass_cdc_tx_macro_put_dec_enum); - -LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic4_v3, LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG0, - 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, - lpass_cdc_tx_macro_put_dec_enum); - -LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic5_v3, LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG0, - 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, - lpass_cdc_tx_macro_put_dec_enum); - -LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic6_v3, LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG0, - 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, - lpass_cdc_tx_macro_put_dec_enum); - -LPASS_CDC_TX_MACRO_DAPM_ENUM_EXT(tx_smic7_v3, LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0, - 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, - lpass_cdc_tx_macro_put_dec_enum); - static const char * const dec_mode_mux_text[] = { "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF", }; @@ -1634,40 +1418,7 @@ static const struct snd_kcontrol_new tx_aif3_cap_mixer[] = { lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put), }; -static const struct snd_kcontrol_new tx_aif1_cap_mixer_v2[] = { - SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC0, 1, 0, - lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC1, 1, 0, - lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC2, 1, 0, - lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC3, 1, 0, - lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put), -}; - -static const struct snd_kcontrol_new tx_aif2_cap_mixer_v2[] = { - SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC0, 1, 0, - lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC1, 1, 0, - lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC2, 1, 0, - lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC3, 1, 0, - lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put), -}; - -static const struct snd_kcontrol_new tx_aif3_cap_mixer_v2[] = { - SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC0, 1, 0, - lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC1, 1, 0, - lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC2, 1, 0, - lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC3, 1, 0, - lpass_cdc_tx_macro_tx_mixer_get, lpass_cdc_tx_macro_tx_mixer_put), -}; - -static const struct snd_soc_dapm_widget lpass_cdc_tx_macro_dapm_widgets_common[] = { +static const struct snd_soc_dapm_widget lpass_cdc_tx_macro_dapm_widgets[] = { SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0, SND_SOC_NOPM, LPASS_CDC_TX_MACRO_AIF1_CAP, 0), @@ -1677,15 +1428,35 @@ static const struct snd_soc_dapm_widget lpass_cdc_tx_macro_dapm_widgets_common[] SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0, SND_SOC_NOPM, LPASS_CDC_TX_MACRO_AIF3_CAP, 0), + SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, + LPASS_CDC_TX_MACRO_AIF1_CAP, 0, + tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)), + + SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, + LPASS_CDC_TX_MACRO_AIF2_CAP, 0, + tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)), + + SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, + LPASS_CDC_TX_MACRO_AIF3_CAP, 0, + tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)), + LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX0", 0, tx_dmic0), LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX1", 0, tx_dmic1), LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX2", 0, tx_dmic2), LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX3", 0, tx_dmic3), + LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX4", 0, tx_dmic4), + LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX5", 0, tx_dmic5), + LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX6", 0, tx_dmic6), + LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX7", 0, tx_dmic7), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX0", 0, tx_smic0_v2), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX1", 0, tx_smic1_v2), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX2", 0, tx_smic2_v2), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX3", 0, tx_smic3_v2), + LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX0", 0, tx_smic0), + LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX1", 0, tx_smic1), + LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX2", 0, tx_smic2), + LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX3", 0, tx_smic3), + LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX4", 0, tx_smic4), + LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX5", 0, tx_smic5), + LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX6", 0, tx_smic6), + LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX7", 0, tx_smic7), SND_SOC_DAPM_SUPPLY("TX MIC BIAS1", SND_SOC_NOPM, 0, 0, lpass_cdc_tx_macro_enable_micbias, @@ -1725,194 +1496,6 @@ static const struct snd_soc_dapm_widget lpass_cdc_tx_macro_dapm_widgets_common[] SND_SOC_DAPM_INPUT("TX SWR_INPUT"), - SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM, - LPASS_CDC_TX_MACRO_DEC0, 0, - &tx_dec0_mux, lpass_cdc_tx_macro_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM, - LPASS_CDC_TX_MACRO_DEC1, 0, - &tx_dec1_mux, lpass_cdc_tx_macro_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM, - LPASS_CDC_TX_MACRO_DEC2, 0, - &tx_dec2_mux, lpass_cdc_tx_macro_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM, - LPASS_CDC_TX_MACRO_DEC3, 0, - &tx_dec3_mux, lpass_cdc_tx_macro_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0, - lpass_cdc_tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_SUPPLY_S("TX_SWR_PWR", -1, SND_SOC_NOPM, 0, 0, - lpass_cdc_tx_macro_swr_pwr_event, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), -}; - -static const struct snd_soc_dapm_widget lpass_cdc_tx_macro_dapm_widgets_v2[] = { - SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, - LPASS_CDC_TX_MACRO_AIF1_CAP, 0, - tx_aif1_cap_mixer_v2, ARRAY_SIZE(tx_aif1_cap_mixer_v2)), - - SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, - LPASS_CDC_TX_MACRO_AIF2_CAP, 0, - tx_aif2_cap_mixer_v2, ARRAY_SIZE(tx_aif2_cap_mixer_v2)), - - SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, - LPASS_CDC_TX_MACRO_AIF3_CAP, 0, - tx_aif3_cap_mixer_v2, ARRAY_SIZE(tx_aif3_cap_mixer_v2)), -}; - -static const struct snd_soc_dapm_widget lpass_cdc_tx_macro_dapm_widgets_v3[] = { - SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, - LPASS_CDC_TX_MACRO_AIF1_CAP, 0, - tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)), - - SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, - LPASS_CDC_TX_MACRO_AIF2_CAP, 0, - tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)), - - SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, - LPASS_CDC_TX_MACRO_AIF3_CAP, 0, - tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)), - - LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX4", 0, tx_dmic4), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX5", 0, tx_dmic5), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX6", 0, tx_dmic6), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX7", 0, tx_dmic7), - - LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX4", 0, tx_smic4_v3), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX5", 0, tx_smic5_v3), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX6", 0, tx_smic6_v3), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX7", 0, tx_smic7_v3), - - SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM, - LPASS_CDC_TX_MACRO_DEC4, 0, - &tx_dec4_mux, lpass_cdc_tx_macro_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM, - LPASS_CDC_TX_MACRO_DEC5, 0, - &tx_dec5_mux, lpass_cdc_tx_macro_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM, - LPASS_CDC_TX_MACRO_DEC6, 0, - &tx_dec6_mux, lpass_cdc_tx_macro_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM, - LPASS_CDC_TX_MACRO_DEC7, 0, - &tx_dec7_mux, lpass_cdc_tx_macro_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, - lpass_cdc_tx_macro_tx_swr_clk_event, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, - lpass_cdc_tx_macro_va_swr_clk_event, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), -}; - -static const struct snd_soc_dapm_widget lpass_cdc_tx_macro_dapm_widgets[] = { - SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0, - SND_SOC_NOPM, LPASS_CDC_TX_MACRO_AIF1_CAP, 0), - - SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0, - SND_SOC_NOPM, LPASS_CDC_TX_MACRO_AIF2_CAP, 0), - - SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0, - SND_SOC_NOPM, LPASS_CDC_TX_MACRO_AIF3_CAP, 0), - - SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_AIF1_CAP, 0, - tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)), - - SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_AIF2_CAP, 0, - tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)), - - SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_AIF3_CAP, 0, - tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)), - - - LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX0", 0, tx_dmic0), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX1", 0, tx_dmic1), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX2", 0, tx_dmic2), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX3", 0, tx_dmic3), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX4", 0, tx_dmic4), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX5", 0, tx_dmic5), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX6", 0, tx_dmic6), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX DMIC MUX7", 0, tx_dmic7), - - LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX0", 0, tx_smic0), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX1", 0, tx_smic1), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX2", 0, tx_smic2), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX3", 0, tx_smic3), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX4", 0, tx_smic4), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX5", 0, tx_smic5), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX6", 0, tx_smic6), - LPASS_CDC_TX_MACRO_DAPM_MUX("TX SMIC MUX7", 0, tx_smic7), - - SND_SOC_DAPM_SUPPLY("TX MIC BIAS1", SND_SOC_NOPM, 0, 0, - lpass_cdc_tx_macro_enable_micbias, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_ADC_E("TX DMIC0", NULL, SND_SOC_NOPM, 0, 0, - lpass_cdc_tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("TX DMIC1", NULL, SND_SOC_NOPM, 0, 0, - lpass_cdc_tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("TX DMIC2", NULL, SND_SOC_NOPM, 0, 0, - lpass_cdc_tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("TX DMIC3", NULL, SND_SOC_NOPM, 0, 0, - lpass_cdc_tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("TX DMIC4", NULL, SND_SOC_NOPM, 0, 0, - lpass_cdc_tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("TX DMIC5", NULL, SND_SOC_NOPM, 0, 0, - lpass_cdc_tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("TX DMIC6", NULL, SND_SOC_NOPM, 0, 0, - lpass_cdc_tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("TX DMIC7", NULL, SND_SOC_NOPM, 0, 0, - lpass_cdc_tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_INPUT("TX SWR_ADC0"), - SND_SOC_DAPM_INPUT("TX SWR_ADC1"), - SND_SOC_DAPM_INPUT("TX SWR_ADC2"), - SND_SOC_DAPM_INPUT("TX SWR_ADC3"), - SND_SOC_DAPM_INPUT("TX SWR_DMIC0"), - SND_SOC_DAPM_INPUT("TX SWR_DMIC1"), - SND_SOC_DAPM_INPUT("TX SWR_DMIC2"), - SND_SOC_DAPM_INPUT("TX SWR_DMIC3"), - SND_SOC_DAPM_INPUT("TX SWR_DMIC4"), - SND_SOC_DAPM_INPUT("TX SWR_DMIC5"), - SND_SOC_DAPM_INPUT("TX SWR_DMIC6"), - SND_SOC_DAPM_INPUT("TX SWR_DMIC7"), - SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM, LPASS_CDC_TX_MACRO_DEC0, 0, &tx_dec0_mux, lpass_cdc_tx_macro_enable_dec, @@ -1963,17 +1546,9 @@ static const struct snd_soc_dapm_widget lpass_cdc_tx_macro_dapm_widgets[] = { SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0, lpass_cdc_tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, - lpass_cdc_tx_macro_tx_swr_clk_event, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, - lpass_cdc_tx_macro_va_swr_clk_event, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), }; -static const struct snd_soc_dapm_route tx_audio_map_common[] = { +static const struct snd_soc_dapm_route tx_audio_map[] = { {"TX_AIF1 CAP", NULL, "TX_MCLK"}, {"TX_AIF2 CAP", NULL, "TX_MCLK"}, {"TX_AIF3 CAP", NULL, "TX_MCLK"}, @@ -1986,21 +1561,37 @@ static const struct snd_soc_dapm_route tx_audio_map_common[] = { {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"}, {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"}, {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"}, + {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"}, + {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"}, + {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"}, + {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"}, {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"}, {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"}, {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"}, {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"}, + {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"}, + {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"}, + {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"}, + {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"}, {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"}, {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"}, {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"}, {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"}, + {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"}, + {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"}, + {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"}, + {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"}, {"TX DEC0 MUX", NULL, "TX_MCLK"}, {"TX DEC1 MUX", NULL, "TX_MCLK"}, {"TX DEC2 MUX", NULL, "TX_MCLK"}, {"TX DEC3 MUX", NULL, "TX_MCLK"}, + {"TX DEC4 MUX", NULL, "TX_MCLK"}, + {"TX DEC5 MUX", NULL, "TX_MCLK"}, + {"TX DEC6 MUX", NULL, "TX_MCLK"}, + {"TX DEC7 MUX", NULL, "TX_MCLK"}, {"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"}, {"TX DMIC MUX0", "DMIC0", "TX DMIC0"}, @@ -2097,28 +1688,6 @@ static const struct snd_soc_dapm_route tx_audio_map_common[] = { {"TX SMIC MUX3", "SWR_MIC9", "TX SWR_INPUT"}, {"TX SMIC MUX3", "SWR_MIC10", "TX SWR_INPUT"}, {"TX SMIC MUX3", "SWR_MIC11", "TX SWR_INPUT"}, -}; - -static const struct snd_soc_dapm_route tx_audio_map_v3[] = { - {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"}, - {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"}, - {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"}, - {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"}, - - {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"}, - {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"}, - {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"}, - {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"}, - - {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"}, - {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"}, - {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"}, - {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"}, - - {"TX DEC4 MUX", NULL, "TX_MCLK"}, - {"TX DEC5 MUX", NULL, "TX_MCLK"}, - {"TX DEC6 MUX", NULL, "TX_MCLK"}, - {"TX DEC7 MUX", NULL, "TX_MCLK"}, {"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"}, {"TX DMIC MUX4", "DMIC0", "TX DMIC0"}, @@ -2215,340 +1784,6 @@ static const struct snd_soc_dapm_route tx_audio_map_v3[] = { {"TX SMIC MUX7", "SWR_MIC9", "TX SWR_INPUT"}, {"TX SMIC MUX7", "SWR_MIC10", "TX SWR_INPUT"}, {"TX SMIC MUX7", "SWR_MIC11", "TX SWR_INPUT"}, - - {"TX SMIC MUX0", NULL, "TX_SWR_CLK"}, - {"TX SMIC MUX1", NULL, "TX_SWR_CLK"}, - {"TX SMIC MUX2", NULL, "TX_SWR_CLK"}, - {"TX SMIC MUX3", NULL, "TX_SWR_CLK"}, - {"TX SMIC MUX4", NULL, "TX_SWR_CLK"}, - {"TX SMIC MUX5", NULL, "TX_SWR_CLK"}, - {"TX SMIC MUX6", NULL, "TX_SWR_CLK"}, - {"TX SMIC MUX7", NULL, "TX_SWR_CLK"}, - - {"TX SWR_INPUT", NULL, "TX_SWR_PWR"}, - {"TX SWR_INPUT", NULL, "TX_SWR_PWR"}, - {"TX SWR_INPUT", NULL, "TX_SWR_PWR"}, - {"TX SWR_INPUT", NULL, "TX_SWR_PWR"}, - {"TX SWR_INPUT", NULL, "TX_SWR_PWR"}, - {"TX SWR_INPUT", NULL, "TX_SWR_PWR"}, - {"TX SWR_INPUT", NULL, "TX_SWR_PWR"}, - {"TX SWR_INPUT", NULL, "TX_SWR_PWR"}, - {"TX SWR_INPUT", NULL, "TX_SWR_PWR"}, - {"TX SWR_INPUT", NULL, "TX_SWR_PWR"}, - {"TX SWR_INPUT", NULL, "TX_SWR_PWR"}, - {"TX SWR_INPUT", NULL, "TX_SWR_PWR"}, -}; - -static const struct snd_soc_dapm_route tx_audio_map[] = { - {"TX_AIF1 CAP", NULL, "TX_MCLK"}, - {"TX_AIF2 CAP", NULL, "TX_MCLK"}, - {"TX_AIF3 CAP", NULL, "TX_MCLK"}, - - {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"}, - {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"}, - {"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"}, - - {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"}, - {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"}, - {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"}, - {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"}, - {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"}, - {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"}, - {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"}, - {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"}, - - {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"}, - {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"}, - {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"}, - {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"}, - {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"}, - {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"}, - {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"}, - {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"}, - - {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"}, - {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"}, - {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"}, - {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"}, - {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"}, - {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"}, - {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"}, - {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"}, - - {"TX DEC0 MUX", NULL, "TX_MCLK"}, - {"TX DEC1 MUX", NULL, "TX_MCLK"}, - {"TX DEC2 MUX", NULL, "TX_MCLK"}, - {"TX DEC3 MUX", NULL, "TX_MCLK"}, - {"TX DEC4 MUX", NULL, "TX_MCLK"}, - {"TX DEC5 MUX", NULL, "TX_MCLK"}, - {"TX DEC6 MUX", NULL, "TX_MCLK"}, - {"TX DEC7 MUX", NULL, "TX_MCLK"}, - - {"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"}, - {"TX DMIC MUX0", "DMIC0", "TX DMIC0"}, - {"TX DMIC MUX0", "DMIC1", "TX DMIC1"}, - {"TX DMIC MUX0", "DMIC2", "TX DMIC2"}, - {"TX DMIC MUX0", "DMIC3", "TX DMIC3"}, - {"TX DMIC MUX0", "DMIC4", "TX DMIC4"}, - {"TX DMIC MUX0", "DMIC5", "TX DMIC5"}, - {"TX DMIC MUX0", "DMIC6", "TX DMIC6"}, - {"TX DMIC MUX0", "DMIC7", "TX DMIC7"}, - - {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"}, - {"TX SMIC MUX0", NULL, "TX_SWR_CLK"}, - {"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"}, - {"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"}, - {"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"}, - {"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"}, - {"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"}, - {"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"}, - {"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"}, - {"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"}, - {"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"}, - {"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"}, - {"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"}, - {"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"}, - - {"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"}, - {"TX DMIC MUX1", "DMIC0", "TX DMIC0"}, - {"TX DMIC MUX1", "DMIC1", "TX DMIC1"}, - {"TX DMIC MUX1", "DMIC2", "TX DMIC2"}, - {"TX DMIC MUX1", "DMIC3", "TX DMIC3"}, - {"TX DMIC MUX1", "DMIC4", "TX DMIC4"}, - {"TX DMIC MUX1", "DMIC5", "TX DMIC5"}, - {"TX DMIC MUX1", "DMIC6", "TX DMIC6"}, - {"TX DMIC MUX1", "DMIC7", "TX DMIC7"}, - - {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"}, - {"TX SMIC MUX1", NULL, "TX_SWR_CLK"}, - {"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"}, - {"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"}, - {"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"}, - {"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"}, - {"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"}, - {"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"}, - {"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"}, - {"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"}, - {"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"}, - {"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"}, - {"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"}, - {"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"}, - - {"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"}, - {"TX DMIC MUX2", "DMIC0", "TX DMIC0"}, - {"TX DMIC MUX2", "DMIC1", "TX DMIC1"}, - {"TX DMIC MUX2", "DMIC2", "TX DMIC2"}, - {"TX DMIC MUX2", "DMIC3", "TX DMIC3"}, - {"TX DMIC MUX2", "DMIC4", "TX DMIC4"}, - {"TX DMIC MUX2", "DMIC5", "TX DMIC5"}, - {"TX DMIC MUX2", "DMIC6", "TX DMIC6"}, - {"TX DMIC MUX2", "DMIC7", "TX DMIC7"}, - - {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"}, - {"TX SMIC MUX2", NULL, "TX_SWR_CLK"}, - {"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"}, - {"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"}, - {"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"}, - {"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"}, - {"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"}, - {"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"}, - {"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"}, - {"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"}, - {"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"}, - {"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"}, - {"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"}, - {"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"}, - - {"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"}, - {"TX DMIC MUX3", "DMIC0", "TX DMIC0"}, - {"TX DMIC MUX3", "DMIC1", "TX DMIC1"}, - {"TX DMIC MUX3", "DMIC2", "TX DMIC2"}, - {"TX DMIC MUX3", "DMIC3", "TX DMIC3"}, - {"TX DMIC MUX3", "DMIC4", "TX DMIC4"}, - {"TX DMIC MUX3", "DMIC5", "TX DMIC5"}, - {"TX DMIC MUX3", "DMIC6", "TX DMIC6"}, - {"TX DMIC MUX3", "DMIC7", "TX DMIC7"}, - - {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"}, - {"TX SMIC MUX3", NULL, "TX_SWR_CLK"}, - {"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"}, - {"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"}, - {"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"}, - {"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"}, - {"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"}, - {"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"}, - {"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"}, - {"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"}, - {"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"}, - {"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"}, - {"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"}, - {"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"}, - - {"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"}, - {"TX DMIC MUX4", "DMIC0", "TX DMIC0"}, - {"TX DMIC MUX4", "DMIC1", "TX DMIC1"}, - {"TX DMIC MUX4", "DMIC2", "TX DMIC2"}, - {"TX DMIC MUX4", "DMIC3", "TX DMIC3"}, - {"TX DMIC MUX4", "DMIC4", "TX DMIC4"}, - {"TX DMIC MUX4", "DMIC5", "TX DMIC5"}, - {"TX DMIC MUX4", "DMIC6", "TX DMIC6"}, - {"TX DMIC MUX4", "DMIC7", "TX DMIC7"}, - - {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"}, - {"TX SMIC MUX4", NULL, "TX_SWR_CLK"}, - {"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"}, - {"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"}, - {"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"}, - {"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"}, - {"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"}, - {"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"}, - {"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"}, - {"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"}, - {"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"}, - {"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"}, - {"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"}, - {"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"}, - - {"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"}, - {"TX DMIC MUX5", "DMIC0", "TX DMIC0"}, - {"TX DMIC MUX5", "DMIC1", "TX DMIC1"}, - {"TX DMIC MUX5", "DMIC2", "TX DMIC2"}, - {"TX DMIC MUX5", "DMIC3", "TX DMIC3"}, - {"TX DMIC MUX5", "DMIC4", "TX DMIC4"}, - {"TX DMIC MUX5", "DMIC5", "TX DMIC5"}, - {"TX DMIC MUX5", "DMIC6", "TX DMIC6"}, - {"TX DMIC MUX5", "DMIC7", "TX DMIC7"}, - - {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"}, - {"TX SMIC MUX5", NULL, "TX_SWR_CLK"}, - {"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"}, - {"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"}, - {"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"}, - {"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"}, - {"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"}, - {"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"}, - {"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"}, - {"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"}, - {"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"}, - {"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"}, - {"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"}, - {"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"}, - - {"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"}, - {"TX DMIC MUX6", "DMIC0", "TX DMIC0"}, - {"TX DMIC MUX6", "DMIC1", "TX DMIC1"}, - {"TX DMIC MUX6", "DMIC2", "TX DMIC2"}, - {"TX DMIC MUX6", "DMIC3", "TX DMIC3"}, - {"TX DMIC MUX6", "DMIC4", "TX DMIC4"}, - {"TX DMIC MUX6", "DMIC5", "TX DMIC5"}, - {"TX DMIC MUX6", "DMIC6", "TX DMIC6"}, - {"TX DMIC MUX6", "DMIC7", "TX DMIC7"}, - - {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"}, - {"TX SMIC MUX6", NULL, "TX_SWR_CLK"}, - {"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"}, - {"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"}, - {"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"}, - {"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"}, - {"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"}, - {"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"}, - {"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"}, - {"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"}, - {"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"}, - {"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"}, - {"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"}, - {"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"}, - - {"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"}, - {"TX DMIC MUX7", "DMIC0", "TX DMIC0"}, - {"TX DMIC MUX7", "DMIC1", "TX DMIC1"}, - {"TX DMIC MUX7", "DMIC2", "TX DMIC2"}, - {"TX DMIC MUX7", "DMIC3", "TX DMIC3"}, - {"TX DMIC MUX7", "DMIC4", "TX DMIC4"}, - {"TX DMIC MUX7", "DMIC5", "TX DMIC5"}, - {"TX DMIC MUX7", "DMIC6", "TX DMIC6"}, - {"TX DMIC MUX7", "DMIC7", "TX DMIC7"}, - - {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"}, - {"TX SMIC MUX7", NULL, "TX_SWR_CLK"}, - {"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"}, - {"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"}, - {"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"}, - {"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"}, - {"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"}, - {"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"}, - {"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"}, - {"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"}, - {"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"}, - {"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"}, - {"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"}, - {"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"}, -}; - -static const struct snd_kcontrol_new lpass_cdc_tx_macro_snd_controls_common[] = { - SOC_SINGLE_S8_TLV("TX_DEC0 Volume", - LPASS_CDC_TX0_TX_VOL_CTL, - -84, 40, digital_gain), - SOC_SINGLE_S8_TLV("TX_DEC1 Volume", - LPASS_CDC_TX1_TX_VOL_CTL, - -84, 40, digital_gain), - SOC_SINGLE_S8_TLV("TX_DEC2 Volume", - LPASS_CDC_TX2_TX_VOL_CTL, - -84, 40, digital_gain), - SOC_SINGLE_S8_TLV("TX_DEC3 Volume", - LPASS_CDC_TX3_TX_VOL_CTL, - -84, 40, digital_gain), - - SOC_SINGLE_EXT("TX LPI Enable", 0, 0, 1, 0, - lpass_cdc_tx_macro_lpi_get, lpass_cdc_tx_macro_lpi_put), - - SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum, - lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put), - - SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum, - lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put), - - SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum, - lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put), - - SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum, - lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put), - - SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0, - lpass_cdc_tx_macro_get_bcs, lpass_cdc_tx_macro_set_bcs), - - SOC_ENUM_EXT("BCS Channel", bcs_ch_enum, - lpass_cdc_tx_macro_bcs_ch_get, lpass_cdc_tx_macro_bcs_ch_put), - - SOC_ENUM_EXT("BCS CH_SEL", bcs_ch_sel_mux_enum, - lpass_cdc_tx_macro_get_bcs_ch_sel, lpass_cdc_tx_macro_put_bcs_ch_sel), -}; - -static const struct snd_kcontrol_new lpass_cdc_tx_macro_snd_controls_v3[] = { - SOC_SINGLE_S8_TLV("TX_DEC4 Volume", - LPASS_CDC_TX4_TX_VOL_CTL, - -84, 40, digital_gain), - SOC_SINGLE_S8_TLV("TX_DEC5 Volume", - LPASS_CDC_TX5_TX_VOL_CTL, - -84, 40, digital_gain), - SOC_SINGLE_S8_TLV("TX_DEC6 Volume", - LPASS_CDC_TX6_TX_VOL_CTL, - -84, 40, digital_gain), - SOC_SINGLE_S8_TLV("TX_DEC7 Volume", - LPASS_CDC_TX7_TX_VOL_CTL, - -84, 40, digital_gain), - - SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum, - lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put), - - SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum, - lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put), - - SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum, - lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put), - - SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum, - lpass_cdc_tx_macro_dec_mode_get, lpass_cdc_tx_macro_dec_mode_put), }; static const struct snd_kcontrol_new lpass_cdc_tx_macro_snd_controls[] = { @@ -2618,227 +1853,14 @@ static const struct snd_kcontrol_new lpass_cdc_tx_macro_snd_controls[] = { SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0, lpass_cdc_tx_macro_get_bcs, lpass_cdc_tx_macro_set_bcs), + + SOC_ENUM_EXT("BCS Channel", bcs_ch_enum, + lpass_cdc_tx_macro_bcs_ch_get, lpass_cdc_tx_macro_bcs_ch_put), + + SOC_ENUM_EXT("BCS CH_SEL", bcs_ch_sel_mux_enum, + lpass_cdc_tx_macro_get_bcs_ch_sel, lpass_cdc_tx_macro_put_bcs_ch_sel), }; -static int lpass_cdc_tx_macro_register_event_listener(struct snd_soc_component *component, - bool enable) -{ - struct device *tx_dev = NULL; - struct lpass_cdc_tx_macro_priv *tx_priv = NULL; - int ret = 0; - - if (!component) - return -EINVAL; - - tx_dev = lpass_cdc_get_device_ptr(component->dev, TX_MACRO); - if (!tx_dev) { - dev_err(component->dev, - "%s: null device for macro!\n", __func__); - return -EINVAL; - } - tx_priv = dev_get_drvdata(tx_dev); - if (!tx_priv) { - dev_err(component->dev, - "%s: priv is null for macro!\n", __func__); - return -EINVAL; - } - if (tx_priv->swr_ctrl_data && - (!tx_priv->tx_swr_clk_cnt || !tx_priv->va_swr_clk_cnt)) { - if (enable) { - ret = swrm_wcd_notify( - tx_priv->swr_ctrl_data[0].tx_swr_pdev, - SWR_REGISTER_WAKEUP, NULL); - msm_cdc_pinctrl_set_wakeup_capable( - tx_priv->tx_swr_gpio_p, false); - } else { - msm_cdc_pinctrl_set_wakeup_capable( - tx_priv->tx_swr_gpio_p, true); - ret = swrm_wcd_notify( - tx_priv->swr_ctrl_data[0].tx_swr_pdev, - SWR_DEREGISTER_WAKEUP, NULL); - } - } - - return ret; -} - -static int lpass_cdc_tx_macro_tx_va_mclk_enable( - struct lpass_cdc_tx_macro_priv *tx_priv, - struct regmap *regmap, int clk_type, - bool enable) -{ - int ret = 0, clk_tx_ret = 0; - - trace_printk("%s: clock type %s, enable: %s tx_mclk_users: %d\n", - __func__, (clk_type ? "VA_MCLK" : "TX_MCLK"), - (enable ? "enable" : "disable"), tx_priv->tx_mclk_users); - dev_dbg(tx_priv->dev, - "%s: clock type %s, enable: %s tx_mclk_users: %d\n", - __func__, (clk_type ? "VA_MCLK" : "TX_MCLK"), - (enable ? "enable" : "disable"), tx_priv->tx_mclk_users); - - if (enable) { - if (tx_priv->swr_clk_users == 0) { - trace_printk("%s: tx swr clk users 0\n", __func__); - ret = msm_cdc_pinctrl_select_active_state( - tx_priv->tx_swr_gpio_p); - if (ret < 0) { - dev_err_ratelimited(tx_priv->dev, - "%s: tx swr pinctrl enable failed\n", - __func__); - goto exit; - } - } - - clk_tx_ret = lpass_cdc_clk_rsc_request_clock(tx_priv->dev, - TX_CORE_CLK, - TX_CORE_CLK, - true); - if (clk_type == TX_MCLK) { - trace_printk("%s: requesting TX_MCLK\n", __func__); - ret = lpass_cdc_tx_macro_mclk_enable(tx_priv, 1); - if (ret < 0) { - if (tx_priv->swr_clk_users == 0) - msm_cdc_pinctrl_select_sleep_state( - tx_priv->tx_swr_gpio_p); - dev_err_ratelimited(tx_priv->dev, - "%s: request clock enable failed\n", - __func__); - goto done; - } - } - if (clk_type == VA_MCLK) { - trace_printk("%s: requesting VA_MCLK\n", __func__); - ret = lpass_cdc_clk_rsc_request_clock(tx_priv->dev, - TX_CORE_CLK, - VA_CORE_CLK, - true); - if (ret < 0) { - if (tx_priv->swr_clk_users == 0) - msm_cdc_pinctrl_select_sleep_state( - tx_priv->tx_swr_gpio_p); - dev_err_ratelimited(tx_priv->dev, - "%s: swr request clk failed\n", - __func__); - goto done; - } - lpass_cdc_clk_rsc_fs_gen_request(tx_priv->dev, - true); - if (tx_priv->tx_mclk_users == 0) { - regmap_update_bits(regmap, - LPASS_CDC_TX_TOP_CSR_FREQ_MCLK, - 0x01, 0x01); - regmap_update_bits(regmap, - LPASS_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, - 0x01, 0x01); - regmap_update_bits(regmap, - LPASS_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, - 0x01, 0x01); - } - tx_priv->tx_mclk_users++; - } - if (tx_priv->swr_clk_users == 0) { - dev_dbg(tx_priv->dev, "%s: reset_swr: %d\n", - __func__, tx_priv->reset_swr); - trace_printk("%s: reset_swr: %d\n", - __func__, tx_priv->reset_swr); - if (tx_priv->reset_swr) - regmap_update_bits(regmap, - LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, - 0x02, 0x02); - regmap_update_bits(regmap, - LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, - 0x01, 0x01); - if (tx_priv->reset_swr) - regmap_update_bits(regmap, - LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, - 0x02, 0x00); - tx_priv->reset_swr = false; - } - if (!clk_tx_ret) - ret = lpass_cdc_clk_rsc_request_clock(tx_priv->dev, - TX_CORE_CLK, - TX_CORE_CLK, - false); - tx_priv->swr_clk_users++; - } else { - if (tx_priv->swr_clk_users <= 0) { - dev_err_ratelimited(tx_priv->dev, - "tx swrm clock users already 0\n"); - tx_priv->swr_clk_users = 0; - return 0; - } - clk_tx_ret = lpass_cdc_clk_rsc_request_clock(tx_priv->dev, - TX_CORE_CLK, - TX_CORE_CLK, - true); - tx_priv->swr_clk_users--; - if (tx_priv->swr_clk_users == 0) - regmap_update_bits(regmap, - LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, - 0x01, 0x00); - if (clk_type == TX_MCLK) - lpass_cdc_tx_macro_mclk_enable(tx_priv, 0); - if (clk_type == VA_MCLK) { - if (tx_priv->tx_mclk_users <= 0) { - dev_err(tx_priv->dev, "%s: clock already disabled\n", - __func__); - tx_priv->tx_mclk_users = 0; - goto tx_clk; - } - tx_priv->tx_mclk_users--; - if (tx_priv->tx_mclk_users == 0) { - regmap_update_bits(regmap, - LPASS_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, - 0x01, 0x00); - regmap_update_bits(regmap, - LPASS_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, - 0x01, 0x00); - } - - lpass_cdc_clk_rsc_fs_gen_request(tx_priv->dev, - false); - ret = lpass_cdc_clk_rsc_request_clock(tx_priv->dev, - TX_CORE_CLK, - VA_CORE_CLK, - false); - if (ret < 0) { - dev_err_ratelimited(tx_priv->dev, - "%s: swr request clk failed\n", - __func__); - goto done; - } - } -tx_clk: - if (!clk_tx_ret) - ret = lpass_cdc_clk_rsc_request_clock(tx_priv->dev, - TX_CORE_CLK, - TX_CORE_CLK, - false); - if (tx_priv->swr_clk_users == 0) { - ret = msm_cdc_pinctrl_select_sleep_state( - tx_priv->tx_swr_gpio_p); - if (ret < 0) { - dev_err_ratelimited(tx_priv->dev, - "%s: tx swr pinctrl disable failed\n", - __func__); - goto exit; - } - } - } - return 0; - -done: - if (!clk_tx_ret) - lpass_cdc_clk_rsc_request_clock(tx_priv->dev, - TX_CORE_CLK, - TX_CORE_CLK, - false); -exit: - trace_printk("%s: exit\n", __func__); - return ret; -} - static int lpass_cdc_tx_macro_clk_div_get(struct snd_soc_component *component) { struct device *tx_dev = NULL; @@ -2850,116 +1872,6 @@ static int lpass_cdc_tx_macro_clk_div_get(struct snd_soc_component *component) return tx_priv->dmic_clk_div; } -static int lpass_cdc_tx_macro_core_vote(void *handle, bool enable) -{ - struct lpass_cdc_tx_macro_priv *tx_priv = (struct lpass_cdc_tx_macro_priv *) handle; - - if (tx_priv == NULL) { - pr_err("%s: tx priv data is NULL\n", __func__); - return -EINVAL; - } - if (enable) { - pm_runtime_get_sync(tx_priv->dev); - pm_runtime_put_autosuspend(tx_priv->dev); - pm_runtime_mark_last_busy(tx_priv->dev); - } - - if (lpass_cdc_check_core_votes(tx_priv->dev)) - return 0; - else - return -EINVAL; -} - -static int lpass_cdc_tx_macro_swrm_clock(void *handle, bool enable) -{ - struct lpass_cdc_tx_macro_priv *tx_priv = (struct lpass_cdc_tx_macro_priv *) handle; - struct regmap *regmap = dev_get_regmap(tx_priv->dev->parent, NULL); - int ret = 0; - - if (regmap == NULL) { - dev_err(tx_priv->dev, "%s: regmap is NULL\n", __func__); - return -EINVAL; - } - - mutex_lock(&tx_priv->swr_clk_lock); - trace_printk("%s: swrm clock %s tx_swr_clk_cnt: %d va_swr_clk_cnt: %d\n", - __func__, - (enable ? "enable" : "disable"), - tx_priv->tx_swr_clk_cnt, tx_priv->va_swr_clk_cnt); - dev_dbg(tx_priv->dev, - "%s: swrm clock %s tx_swr_clk_cnt: %d va_swr_clk_cnt: %d\n", - __func__, (enable ? "enable" : "disable"), - tx_priv->tx_swr_clk_cnt, tx_priv->va_swr_clk_cnt); - - if (enable) { - pm_runtime_get_sync(tx_priv->dev); - if (tx_priv->va_swr_clk_cnt && !tx_priv->tx_swr_clk_cnt) { - ret = lpass_cdc_tx_macro_tx_va_mclk_enable(tx_priv, regmap, - VA_MCLK, enable); - if (ret) { - pm_runtime_mark_last_busy(tx_priv->dev); - pm_runtime_put_autosuspend(tx_priv->dev); - goto done; - } - tx_priv->va_clk_status++; - } else { - ret = lpass_cdc_tx_macro_tx_va_mclk_enable(tx_priv, regmap, - TX_MCLK, enable); - if (ret) { - pm_runtime_mark_last_busy(tx_priv->dev); - pm_runtime_put_autosuspend(tx_priv->dev); - goto done; - } - tx_priv->tx_clk_status++; - } - pm_runtime_mark_last_busy(tx_priv->dev); - pm_runtime_put_autosuspend(tx_priv->dev); - } else { - if (tx_priv->va_clk_status && !tx_priv->tx_clk_status) { - ret = lpass_cdc_tx_macro_tx_va_mclk_enable(tx_priv, regmap, - VA_MCLK, enable); - if (ret) - goto done; - --tx_priv->va_clk_status; - } else if (!tx_priv->va_clk_status && tx_priv->tx_clk_status) { - ret = lpass_cdc_tx_macro_tx_va_mclk_enable(tx_priv, regmap, - TX_MCLK, enable); - if (ret) - goto done; - --tx_priv->tx_clk_status; - } else if (tx_priv->va_clk_status && tx_priv->tx_clk_status) { - if (!tx_priv->va_swr_clk_cnt && tx_priv->tx_swr_clk_cnt) { - ret = lpass_cdc_tx_macro_tx_va_mclk_enable(tx_priv, regmap, - VA_MCLK, enable); - if (ret) - goto done; - --tx_priv->va_clk_status; - } else { - ret = lpass_cdc_tx_macro_tx_va_mclk_enable(tx_priv, regmap, - TX_MCLK, enable); - if (ret) - goto done; - --tx_priv->tx_clk_status; - } - - } else { - dev_dbg(tx_priv->dev, - "%s: Both clocks are disabled\n", __func__); - } - } - - trace_printk("%s: swrm clock users %d tx_clk_sts_cnt: %d va_clk_sts_cnt: %d\n", - __func__, tx_priv->swr_clk_users, tx_priv->tx_clk_status, - tx_priv->va_clk_status); - dev_dbg(tx_priv->dev, - "%s: swrm clock users %d tx_clk_sts_cnt: %d va_clk_sts_cnt: %d\n", - __func__, tx_priv->swr_clk_users, tx_priv->tx_clk_status, - tx_priv->va_clk_status); -done: - mutex_unlock(&tx_priv->swr_clk_lock); - return ret; -} - static int lpass_cdc_tx_macro_validate_dmic_sample_rate(u32 dmic_sample_rate, struct lpass_cdc_tx_macro_priv *tx_priv) { @@ -3035,67 +1947,21 @@ static int lpass_cdc_tx_macro_init(struct snd_soc_component *component) "%s: priv is null for macro!\n", __func__); return -EINVAL; } - tx_priv->lpi_enable = false; - tx_priv->register_event_listener = false; tx_priv->version = lpass_cdc_get_version(tx_dev); - if (tx_priv->version >= LPASS_CDC_VERSION_2_0) { - ret = snd_soc_dapm_new_controls(dapm, - lpass_cdc_tx_macro_dapm_widgets_common, - ARRAY_SIZE(lpass_cdc_tx_macro_dapm_widgets_common)); - if (ret < 0) { - dev_err(tx_dev, "%s: Failed to add controls\n", - __func__); - return ret; - } - if (tx_priv->version == LPASS_CDC_VERSION_2_1) - ret = snd_soc_dapm_new_controls(dapm, - lpass_cdc_tx_macro_dapm_widgets_v2, - ARRAY_SIZE(lpass_cdc_tx_macro_dapm_widgets_v2)); - else if (tx_priv->version == LPASS_CDC_VERSION_2_0) - ret = snd_soc_dapm_new_controls(dapm, - lpass_cdc_tx_macro_dapm_widgets_v3, - ARRAY_SIZE(lpass_cdc_tx_macro_dapm_widgets_v3)); - if (ret < 0) { - dev_err(tx_dev, "%s: Failed to add controls\n", - __func__); - return ret; - } - } else { - ret = snd_soc_dapm_new_controls(dapm, lpass_cdc_tx_macro_dapm_widgets, - ARRAY_SIZE(lpass_cdc_tx_macro_dapm_widgets)); - if (ret < 0) { - dev_err(tx_dev, "%s: Failed to add controls\n", - __func__); - return ret; - } + ret = snd_soc_dapm_new_controls(dapm, lpass_cdc_tx_macro_dapm_widgets, + ARRAY_SIZE(lpass_cdc_tx_macro_dapm_widgets)); + if (ret < 0) { + dev_err(tx_dev, "%s: Failed to add controls\n", + __func__); + return ret; } - if (tx_priv->version >= LPASS_CDC_VERSION_2_0) { - ret = snd_soc_dapm_add_routes(dapm, - tx_audio_map_common, - ARRAY_SIZE(tx_audio_map_common)); - if (ret < 0) { - dev_err(tx_dev, "%s: Failed to add routes\n", - __func__); - return ret; - } - if (tx_priv->version == LPASS_CDC_VERSION_2_0) - ret = snd_soc_dapm_add_routes(dapm, - tx_audio_map_v3, - ARRAY_SIZE(tx_audio_map_v3)); - if (ret < 0) { - dev_err(tx_dev, "%s: Failed to add routes\n", - __func__); - return ret; - } - } else { - ret = snd_soc_dapm_add_routes(dapm, tx_audio_map, - ARRAY_SIZE(tx_audio_map)); - if (ret < 0) { - dev_err(tx_dev, "%s: Failed to add routes\n", - __func__); - return ret; - } + ret = snd_soc_dapm_add_routes(dapm, tx_audio_map, + ARRAY_SIZE(tx_audio_map)); + if (ret < 0) { + dev_err(tx_dev, "%s: Failed to add routes\n", + __func__); + return ret; } ret = snd_soc_dapm_new_widgets(dapm->card); @@ -3104,54 +1970,19 @@ static int lpass_cdc_tx_macro_init(struct snd_soc_component *component) return ret; } - if (tx_priv->version >= LPASS_CDC_VERSION_2_0) { - ret = snd_soc_add_component_controls(component, - lpass_cdc_tx_macro_snd_controls_common, - ARRAY_SIZE(lpass_cdc_tx_macro_snd_controls_common)); - if (ret < 0) { - dev_err(tx_dev, "%s: Failed to add snd_ctls\n", - __func__); - return ret; - } - if (tx_priv->version == LPASS_CDC_VERSION_2_0) - ret = snd_soc_add_component_controls(component, - lpass_cdc_tx_macro_snd_controls_v3, - ARRAY_SIZE(lpass_cdc_tx_macro_snd_controls_v3)); - if (ret < 0) { - dev_err(tx_dev, "%s: Failed to add snd_ctls\n", - __func__); - return ret; - } - } else { - ret = snd_soc_add_component_controls(component, - lpass_cdc_tx_macro_snd_controls, - ARRAY_SIZE(lpass_cdc_tx_macro_snd_controls)); - if (ret < 0) { - dev_err(tx_dev, "%s: Failed to add snd_ctls\n", - __func__); - return ret; - } + ret = snd_soc_add_component_controls(component, + lpass_cdc_tx_macro_snd_controls, + ARRAY_SIZE(lpass_cdc_tx_macro_snd_controls)); + if (ret < 0) { + dev_err(tx_dev, "%s: Failed to add snd_ctls\n", + __func__); + return ret; } snd_soc_dapm_ignore_suspend(dapm, "TX_AIF1 Capture"); snd_soc_dapm_ignore_suspend(dapm, "TX_AIF2 Capture"); snd_soc_dapm_ignore_suspend(dapm, "TX_AIF3 Capture"); - if (tx_priv->version >= LPASS_CDC_VERSION_2_0) { - snd_soc_dapm_ignore_suspend(dapm, "TX SWR_INPUT"); - } else { - snd_soc_dapm_ignore_suspend(dapm, "TX SWR_ADC0"); - snd_soc_dapm_ignore_suspend(dapm, "TX SWR_ADC1"); - snd_soc_dapm_ignore_suspend(dapm, "TX SWR_ADC2"); - snd_soc_dapm_ignore_suspend(dapm, "TX SWR_ADC3"); - snd_soc_dapm_ignore_suspend(dapm, "TX SWR_DMIC0"); - snd_soc_dapm_ignore_suspend(dapm, "TX SWR_DMIC1"); - snd_soc_dapm_ignore_suspend(dapm, "TX SWR_DMIC2"); - snd_soc_dapm_ignore_suspend(dapm, "TX SWR_DMIC3"); - snd_soc_dapm_ignore_suspend(dapm, "TX SWR_DMIC4"); - snd_soc_dapm_ignore_suspend(dapm, "TX SWR_DMIC5"); - snd_soc_dapm_ignore_suspend(dapm, "TX SWR_DMIC6"); - snd_soc_dapm_ignore_suspend(dapm, "TX SWR_DMIC7"); - } + snd_soc_dapm_ignore_suspend(dapm, "TX SWR_INPUT"); snd_soc_dapm_sync(dapm); for (i = 0; i < NUM_DECIMATORS; i++) { @@ -3190,137 +2021,6 @@ static int lpass_cdc_tx_macro_deinit(struct snd_soc_component *component) return 0; } -static void lpass_cdc_tx_macro_add_child_devices(struct work_struct *work) -{ - struct lpass_cdc_tx_macro_priv *tx_priv = NULL; - struct platform_device *pdev = NULL; - struct device_node *node = NULL; - struct lpass_cdc_tx_macro_swr_ctrl_data *swr_ctrl_data = NULL, *temp = NULL; - int ret = 0; - u16 count = 0, ctrl_num = 0; - struct lpass_cdc_tx_macro_swr_ctrl_platform_data *platdata = NULL; - char plat_dev_name[LPASS_CDC_TX_MACRO_SWR_STRING_LEN] = ""; - bool tx_swr_master_node = false; - - tx_priv = container_of(work, struct lpass_cdc_tx_macro_priv, - lpass_cdc_tx_macro_add_child_devices_work); - if (!tx_priv) { - pr_err("%s: Memory for tx_priv does not exist\n", - __func__); - return; - } - - if (!tx_priv->dev) { - pr_err("%s: tx dev does not exist\n", __func__); - return; - } - - if (!tx_priv->dev->of_node) { - dev_err(tx_priv->dev, - "%s: DT node for tx_priv does not exist\n", __func__); - return; - } - - platdata = &tx_priv->swr_plat_data; - tx_priv->child_count = 0; - - for_each_available_child_of_node(tx_priv->dev->of_node, node) { - tx_swr_master_node = false; - if (strnstr(node->name, "tx_swr_master", - strlen("tx_swr_master")) != NULL) - tx_swr_master_node = true; - - if (tx_swr_master_node) - strlcpy(plat_dev_name, "tx_swr_ctrl", - (LPASS_CDC_TX_MACRO_SWR_STRING_LEN - 1)); - else - strlcpy(plat_dev_name, node->name, - (LPASS_CDC_TX_MACRO_SWR_STRING_LEN - 1)); - - pdev = platform_device_alloc(plat_dev_name, -1); - if (!pdev) { - dev_err(tx_priv->dev, "%s: pdev memory alloc failed\n", - __func__); - ret = -ENOMEM; - goto err; - } - pdev->dev.parent = tx_priv->dev; - pdev->dev.of_node = node; - - if (tx_swr_master_node) { - ret = platform_device_add_data(pdev, platdata, - sizeof(*platdata)); - if (ret) { - dev_err(&pdev->dev, - "%s: cannot add plat data ctrl:%d\n", - __func__, ctrl_num); - goto fail_pdev_add; - } - } - - ret = platform_device_add(pdev); - if (ret) { - dev_err(&pdev->dev, - "%s: Cannot add platform device\n", - __func__); - goto fail_pdev_add; - } - - if (tx_swr_master_node) { - temp = krealloc(swr_ctrl_data, - (ctrl_num + 1) * sizeof( - struct lpass_cdc_tx_macro_swr_ctrl_data), - GFP_KERNEL); - if (!temp) { - ret = -ENOMEM; - goto fail_pdev_add; - } - swr_ctrl_data = temp; - swr_ctrl_data[ctrl_num].tx_swr_pdev = pdev; - ctrl_num++; - dev_dbg(&pdev->dev, - "%s: Added soundwire ctrl device(s)\n", - __func__); - tx_priv->swr_ctrl_data = swr_ctrl_data; - } - if (tx_priv->child_count < LPASS_CDC_TX_MACRO_CHILD_DEVICES_MAX) - tx_priv->pdev_child_devices[ - tx_priv->child_count++] = pdev; - else - goto err; - } - return; -fail_pdev_add: - for (count = 0; count < tx_priv->child_count; count++) - platform_device_put(tx_priv->pdev_child_devices[count]); -err: - return; -} - -static int lpass_cdc_tx_macro_set_port_map(struct snd_soc_component *component, - u32 usecase, u32 size, void *data) -{ - struct device *tx_dev = NULL; - struct lpass_cdc_tx_macro_priv *tx_priv = NULL; - struct swrm_port_config port_cfg; - int ret = 0; - - if (!lpass_cdc_tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) - return -EINVAL; - - memset(&port_cfg, 0, sizeof(port_cfg)); - port_cfg.uc = usecase; - port_cfg.size = size; - port_cfg.params = data; - - if (tx_priv->swr_ctrl_data) - ret = swrm_wcd_notify( - tx_priv->swr_ctrl_data[0].tx_swr_pdev, - SWR_SET_PORT_MAP, &port_cfg); - - return ret; -} - static void lpass_cdc_tx_macro_init_ops(struct macro_ops *ops, char __iomem *tx_io_base) { @@ -3331,10 +2031,7 @@ static void lpass_cdc_tx_macro_init_ops(struct macro_ops *ops, ops->dai_ptr = lpass_cdc_tx_macro_dai; ops->num_dais = ARRAY_SIZE(lpass_cdc_tx_macro_dai); ops->event_handler = lpass_cdc_tx_macro_event_handler; - ops->reg_wake_irq = lpass_cdc_tx_macro_reg_wake_irq; - ops->set_port_map = lpass_cdc_tx_macro_set_port_map; ops->clk_div_get = lpass_cdc_tx_macro_clk_div_get; - ops->reg_evt_listener = lpass_cdc_tx_macro_register_event_listener; ops->clk_enable = __lpass_cdc_tx_macro_mclk_enable; } @@ -3346,8 +2043,6 @@ static int lpass_cdc_tx_macro_probe(struct platform_device *pdev) char __iomem *tx_io_base = NULL; int ret = 0; const char *dmic_sample_rate = "qcom,tx-dmic-sample-rate"; - u32 is_used_tx_swr_gpio = 1; - const char *is_used_tx_swr_gpio_dt = "qcom,is-used-swr-gpio"; if (!lpass_cdc_is_va_macro_registered(&pdev->dev)) { dev_err(&pdev->dev, @@ -3370,30 +2065,6 @@ static int lpass_cdc_tx_macro_probe(struct platform_device *pdev) return ret; } dev_set_drvdata(&pdev->dev, tx_priv); - if (of_find_property(pdev->dev.of_node, is_used_tx_swr_gpio_dt, - NULL)) { - ret = of_property_read_u32(pdev->dev.of_node, - is_used_tx_swr_gpio_dt, - &is_used_tx_swr_gpio); - if (ret) { - dev_err(&pdev->dev, "%s: error reading %s in dt\n", - __func__, is_used_tx_swr_gpio_dt); - is_used_tx_swr_gpio = 1; - } - } - tx_priv->tx_swr_gpio_p = of_parse_phandle(pdev->dev.of_node, - "qcom,tx-swr-gpios", 0); - if (!tx_priv->tx_swr_gpio_p && is_used_tx_swr_gpio) { - dev_err(&pdev->dev, "%s: swr_gpios handle not provided!\n", - __func__); - return -EINVAL; - } - if (msm_cdc_pinctrl_get_state(tx_priv->tx_swr_gpio_p) < 0 && - is_used_tx_swr_gpio) { - dev_err(&pdev->dev, "%s: failed to get swr pin state\n", - __func__); - return -EPROBE_DEFER; - } tx_io_base = devm_ioremap(&pdev->dev, tx_base_addr, LPASS_CDC_TX_MACRO_MAX_OFFSET); @@ -3414,20 +2085,6 @@ static int lpass_cdc_tx_macro_probe(struct platform_device *pdev) sample_rate, tx_priv) == LPASS_CDC_TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED) return -EINVAL; } - if (is_used_tx_swr_gpio) { - tx_priv->reset_swr = true; - INIT_WORK(&tx_priv->lpass_cdc_tx_macro_add_child_devices_work, - lpass_cdc_tx_macro_add_child_devices); - tx_priv->swr_plat_data.handle = (void *) tx_priv; - tx_priv->swr_plat_data.read = NULL; - tx_priv->swr_plat_data.write = NULL; - tx_priv->swr_plat_data.bulk_write = NULL; - tx_priv->swr_plat_data.clk = lpass_cdc_tx_macro_swrm_clock; - tx_priv->swr_plat_data.core_vote = lpass_cdc_tx_macro_core_vote; - tx_priv->swr_plat_data.handle_irq = NULL; - mutex_init(&tx_priv->swr_clk_lock); - } - tx_priv->is_used_tx_swr_gpio = is_used_tx_swr_gpio; mutex_init(&tx_priv->mclk_lock); lpass_cdc_tx_macro_init_ops(&ops, tx_io_base); ops.clk_id_req = TX_CORE_CLK; @@ -3438,8 +2095,6 @@ static int lpass_cdc_tx_macro_probe(struct platform_device *pdev) "%s: register macro failed\n", __func__); goto err_reg_macro; } - if (is_used_tx_swr_gpio) - schedule_work(&tx_priv->lpass_cdc_tx_macro_add_child_devices_work); pm_runtime_set_autosuspend_delay(&pdev->dev, AUTO_SUSPEND_DELAY); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); @@ -3449,35 +2104,21 @@ static int lpass_cdc_tx_macro_probe(struct platform_device *pdev) return 0; err_reg_macro: mutex_destroy(&tx_priv->mclk_lock); - if (is_used_tx_swr_gpio) - mutex_destroy(&tx_priv->swr_clk_lock); return ret; } static int lpass_cdc_tx_macro_remove(struct platform_device *pdev) { struct lpass_cdc_tx_macro_priv *tx_priv = NULL; - u16 count = 0; tx_priv = platform_get_drvdata(pdev); if (!tx_priv) return -EINVAL; - if (tx_priv->is_used_tx_swr_gpio) { - if (tx_priv->swr_ctrl_data) - kfree(tx_priv->swr_ctrl_data); - for (count = 0; count < tx_priv->child_count && - count < LPASS_CDC_TX_MACRO_CHILD_DEVICES_MAX; count++) - platform_device_unregister( - tx_priv->pdev_child_devices[count]); - } - pm_runtime_disable(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); mutex_destroy(&tx_priv->mclk_lock); - if (tx_priv->is_used_tx_swr_gpio) - mutex_destroy(&tx_priv->swr_clk_lock); lpass_cdc_unregister_macro(&pdev->dev, TX_MACRO); return 0; } diff --git a/asoc/codecs/lpass-cdc/lpass-cdc-utils.c b/asoc/codecs/lpass-cdc/lpass-cdc-utils.c index 95615c24f0..a586816b6d 100644 --- a/asoc/codecs/lpass-cdc/lpass-cdc-utils.c +++ b/asoc/codecs/lpass-cdc/lpass-cdc-utils.c @@ -15,6 +15,7 @@ const u16 macro_id_base_offset[MAX_MACRO] = { RX_START_OFFSET, WSA_START_OFFSET, VA_START_OFFSET, + WSA2_START_OFFSET, }; int lpass_cdc_get_macro_id(bool va_no_dec_flag, u16 reg) @@ -28,13 +29,11 @@ int lpass_cdc_get_macro_id(bool va_no_dec_flag, u16 reg) if (reg >= WSA_START_OFFSET && reg <= WSA_MAX_OFFSET) return WSA_MACRO; - if (!va_no_dec_flag && - (reg >= VA_START_OFFSET && - reg <= VA_MAX_OFFSET)) - return VA_MACRO; - if (va_no_dec_flag && - (reg >= VA_START_OFFSET && - reg <= VA_TOP_MAX_OFFSET)) + if (reg >= WSA2_START_OFFSET + && reg <= WSA2_MAX_OFFSET) + return WSA2_MACRO; + if (reg >= VA_START_OFFSET && + reg <= VA_MAX_OFFSET) return VA_MACRO; return -EINVAL; diff --git a/asoc/codecs/lpass-cdc/lpass-cdc-va-macro.c b/asoc/codecs/lpass-cdc/lpass-cdc-va-macro.c index 1792a23871..6a28065280 100644 --- a/asoc/codecs/lpass-cdc/lpass-cdc-va-macro.c +++ b/asoc/codecs/lpass-cdc/lpass-cdc-va-macro.c @@ -25,7 +25,7 @@ #define VA_AUTO_SUSPEND_DELAY 100 /* delay in msec */ #define LPASS_CDC_VA_MACRO_MAX_OFFSET 0x1000 -#define LPASS_CDC_VA_MACRO_NUM_DECIMATORS 8 +#define LPASS_CDC_VA_MACRO_NUM_DECIMATORS 4 #define LPASS_CDC_VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ @@ -74,10 +74,6 @@ enum { LPASS_CDC_VA_MACRO_DEC1, LPASS_CDC_VA_MACRO_DEC2, LPASS_CDC_VA_MACRO_DEC3, - LPASS_CDC_VA_MACRO_DEC4, - LPASS_CDC_VA_MACRO_DEC5, - LPASS_CDC_VA_MACRO_DEC6, - LPASS_CDC_VA_MACRO_DEC7, LPASS_CDC_VA_MACRO_DEC_MAX, }; @@ -171,9 +167,8 @@ struct lpass_cdc_va_macro_priv { int va_clk_status; int tx_clk_status; bool lpi_enable; - bool register_event_listener; + bool clk_div_switch; int dec_mode[LPASS_CDC_VA_MACRO_NUM_DECIMATORS]; - int disable_afe_wakeup_event_listener; }; static bool lpass_cdc_va_macro_get_data(struct snd_soc_component *component, @@ -205,10 +200,10 @@ static int lpass_cdc_va_macro_clk_div_get(struct snd_soc_component *component) &va_priv, __func__)) return -EINVAL; - if ((va_priv->version >= LPASS_CDC_VERSION_2_0) - && !va_priv->lpi_enable - && (va_priv->dmic_clk_div == LPASS_CDC_VA_MACRO_CLK_DIV_16)) - return LPASS_CDC_VA_MACRO_CLK_DIV_8; + if (va_priv->clk_div_switch && + (va_priv->dmic_clk_div == LPASS_CDC_VA_MACRO_CLK_DIV_16)) + return LPASS_CDC_VA_MACRO_CLK_DIV_4; + return va_priv->dmic_clk_div; } @@ -350,7 +345,7 @@ static int lpass_cdc_va_macro_event_handler(struct snd_soc_component *component, return 0; } -static int lpass_cdc_va_macro_swr_clk_event_v2(struct snd_soc_dapm_widget *w, +static int lpass_cdc_va_macro_swr_clk_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { struct snd_soc_component *component = @@ -377,42 +372,6 @@ static int lpass_cdc_va_macro_swr_clk_event_v2(struct snd_soc_dapm_widget *w, return 0; } -static int lpass_cdc_va_macro_swr_pwr_event_v2(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - struct snd_soc_component *component = - snd_soc_dapm_to_component(w->dapm); - int ret = 0; - struct device *va_dev = NULL; - struct lpass_cdc_va_macro_priv *va_priv = NULL; - - if (!lpass_cdc_va_macro_get_data(component, &va_dev, - &va_priv, __func__)) - return -EINVAL; - - dev_dbg(va_dev, "%s: event = %d, lpi_enable = %d\n", - __func__, event, va_priv->lpi_enable); - - if (!va_priv->lpi_enable) - return ret; - - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - msm_cdc_pinctrl_set_wakeup_capable( - va_priv->va_swr_gpio_p, false); - break; - case SND_SOC_DAPM_POST_PMD: - msm_cdc_pinctrl_set_wakeup_capable( - va_priv->va_swr_gpio_p, true); - break; - default: - dev_err(va_priv->dev, - "%s: invalid DAPM event %d\n", __func__, event); - ret = -EINVAL; - } - return ret; -} - static int lpass_cdc_va_macro_swr_pwr_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { @@ -434,28 +393,60 @@ static int lpass_cdc_va_macro_swr_pwr_event(struct snd_soc_dapm_widget *w, switch (event) { case SND_SOC_DAPM_PRE_PMU: - if (va_priv->lpass_audio_hw_vote) { - ret = digital_cdc_rsc_mgr_hw_vote_enable( - va_priv->lpass_audio_hw_vote); - if (ret) - dev_err(va_dev, - "%s: lpass audio hw enable failed\n", + if (va_priv->default_clk_id != VA_CORE_CLK) { + ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev, + va_priv->default_clk_id, + VA_CORE_CLK, + true); + if (ret) { + dev_dbg(component->dev, + "%s: request clock VA_CLK enable failed\n", __func__); - } - if (va_priv->lpi_enable && - !va_priv->disable_afe_wakeup_event_listener) { - lpass_cdc_register_event_listener(component, true); - va_priv->register_event_listener = true; + break; + } + ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev, + va_priv->default_clk_id, + TX_CORE_CLK, + false); + if (ret) { + dev_dbg(component->dev, + "%s: request clock TX_CLK disable failed\n", + __func__); + lpass_cdc_clk_rsc_request_clock(va_priv->dev, + va_priv->default_clk_id, + VA_CORE_CLK, + false); + break; + } } break; case SND_SOC_DAPM_POST_PMD: - if (va_priv->register_event_listener) { - va_priv->register_event_listener = false; - lpass_cdc_register_event_listener(component, false); + if (va_priv->default_clk_id == TX_CORE_CLK) { + ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev, + va_priv->default_clk_id, + TX_CORE_CLK, + true); + if (ret) { + dev_dbg(component->dev, + "%s: request clock TX_CLK enable failed\n", + __func__); + break; + } + ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev, + va_priv->default_clk_id, + VA_CORE_CLK, + false); + if (ret) { + dev_dbg(component->dev, + "%s: request clock VA_CLK disable failed\n", + __func__); + lpass_cdc_clk_rsc_request_clock(va_priv->dev, + va_priv->default_clk_id, + TX_CORE_CLK, + false); + break; + } } - if (va_priv->lpass_audio_hw_vote) - digital_cdc_rsc_mgr_hw_vote_disable( - va_priv->lpass_audio_hw_vote); break; default: dev_err(va_priv->dev, @@ -465,7 +456,7 @@ static int lpass_cdc_va_macro_swr_pwr_event(struct snd_soc_dapm_widget *w, return ret; } -static int lpass_cdc_va_macro_tx_swr_clk_event_v2(struct snd_soc_dapm_widget *w, +static int lpass_cdc_va_macro_tx_swr_clk_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { struct device *va_dev = NULL; @@ -548,9 +539,12 @@ static int lpass_cdc_va_macro_tx_va_mclk_enable( (enable ? "enable" : "disable"), va_priv->va_mclk_users); if (enable) { - if (va_priv->swr_clk_users == 0) + if (va_priv->swr_clk_users == 0) { msm_cdc_pinctrl_select_active_state( va_priv->va_swr_gpio_p); + msm_cdc_pinctrl_set_wakeup_capable( + va_priv->va_swr_gpio_p, false); + } clk_tx_ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev, TX_CORE_CLK, TX_CORE_CLK, @@ -643,9 +637,12 @@ static int lpass_cdc_va_macro_tx_va_mclk_enable( TX_CORE_CLK, TX_CORE_CLK, false); - if (va_priv->swr_clk_users == 0) + if (va_priv->swr_clk_users == 0) { msm_cdc_pinctrl_select_sleep_state( va_priv->va_swr_gpio_p); + msm_cdc_pinctrl_set_wakeup_capable( + va_priv->va_swr_gpio_p, true); + } } return 0; @@ -782,8 +779,6 @@ static bool is_amic_enabled(struct snd_soc_component *component, int decimator) adc_mux_reg = LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1 + LPASS_CDC_VA_MACRO_ADC_MUX_CFG_OFFSET * decimator; if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) { - if (va_priv->version == LPASS_CDC_VERSION_2_1) - return true; adc_reg = LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0 + LPASS_CDC_VA_MACRO_ADC_MUX_CFG_OFFSET * decimator; adc_n = snd_soc_component_read(component, adc_reg) & @@ -909,18 +904,6 @@ static int lpass_cdc_va_macro_put_dec_enum(struct snd_kcontrol *kcontrol, case LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0: mic_sel_reg = LPASS_CDC_VA_TX3_TX_PATH_CFG0; break; - case LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG0: - mic_sel_reg = LPASS_CDC_VA_TX4_TX_PATH_CFG0; - break; - case LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG0: - mic_sel_reg = LPASS_CDC_VA_TX5_TX_PATH_CFG0; - break; - case LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG0: - mic_sel_reg = LPASS_CDC_VA_TX6_TX_PATH_CFG0; - break; - case LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG0: - mic_sel_reg = LPASS_CDC_VA_TX7_TX_PATH_CFG0; - break; default: dev_err(component->dev, "%s: e->reg: 0x%x not expected\n", __func__, e->reg); @@ -940,7 +923,7 @@ static int lpass_cdc_va_macro_put_dec_enum(struct snd_kcontrol *kcontrol, LPASS_CDC_VA_TOP_CSR_DMIC_CFG, 0x80, 0x00); dmic_clk_reg = - LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL + + LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL0 + ((val - 5)/2) * 4; snd_soc_component_update_bits(component, dmic_clk_reg, @@ -1479,6 +1462,10 @@ static int lpass_cdc_va_macro_hw_params(struct snd_pcm_substream *substream, params_channels(params)); sample_rate = params_rate(params); + if (sample_rate > 16000) + va_priv->clk_div_switch = true; + else + va_priv->clk_div_switch = false; switch (sample_rate) { case 8000: tx_fs_rate = 0; @@ -1627,14 +1614,6 @@ LPASS_CDC_VA_MACRO_DAPM_ENUM(va_dec2, LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0, adc_mux_text); LPASS_CDC_VA_MACRO_DAPM_ENUM(va_dec3, LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0, adc_mux_text); -LPASS_CDC_VA_MACRO_DAPM_ENUM(va_dec4, LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG1, - 0, adc_mux_text); -LPASS_CDC_VA_MACRO_DAPM_ENUM(va_dec5, LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG1, - 0, adc_mux_text); -LPASS_CDC_VA_MACRO_DAPM_ENUM(va_dec6, LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG1, - 0, adc_mux_text); -LPASS_CDC_VA_MACRO_DAPM_ENUM(va_dec7, LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG1, - 0, adc_mux_text); static const char * const dmic_mux_text[] = { "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", @@ -1657,26 +1636,10 @@ LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_dmic3, LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0, 4, dmic_mux_text, snd_soc_dapm_get_enum_double, lpass_cdc_va_macro_put_dec_enum); -LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_dmic4, LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG0, - 4, dmic_mux_text, snd_soc_dapm_get_enum_double, - lpass_cdc_va_macro_put_dec_enum); - -LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_dmic5, LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG0, - 4, dmic_mux_text, snd_soc_dapm_get_enum_double, - lpass_cdc_va_macro_put_dec_enum); - -LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_dmic6, LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG0, - 4, dmic_mux_text, snd_soc_dapm_get_enum_double, - lpass_cdc_va_macro_put_dec_enum); - -LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_dmic7, LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG0, - 4, dmic_mux_text, snd_soc_dapm_get_enum_double, - lpass_cdc_va_macro_put_dec_enum); - static const char * const smic_mux_text[] = { - "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", - "SWR_DMIC0", "SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", - "SWR_DMIC4", "SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7" + "ZERO", "SWR_MIC0", "SWR_MIC1", "SWR_MIC2", "SWR_MIC3", + "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7", + "SWR_MIC8", "SWR_MIC9", "SWR_MIC10", "SWR_MIC11" }; LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_smic0, LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0, @@ -1695,44 +1658,6 @@ LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_smic3, LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0, smic_mux_text, snd_soc_dapm_get_enum_double, lpass_cdc_va_macro_put_dec_enum); -LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_smic4, LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG0, - 0, smic_mux_text, snd_soc_dapm_get_enum_double, - lpass_cdc_va_macro_put_dec_enum); - -LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_smic5, LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG0, - 0, smic_mux_text, snd_soc_dapm_get_enum_double, - lpass_cdc_va_macro_put_dec_enum); - -LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_smic6, LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG0, - 0, smic_mux_text, snd_soc_dapm_get_enum_double, - lpass_cdc_va_macro_put_dec_enum); - -LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_smic7, LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG0, - 0, smic_mux_text, snd_soc_dapm_get_enum_double, - lpass_cdc_va_macro_put_dec_enum); - -static const char * const smic_mux_text_v2[] = { - "ZERO", "SWR_MIC0", "SWR_MIC1", "SWR_MIC2", "SWR_MIC3", - "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7", - "SWR_MIC8", "SWR_MIC9", "SWR_MIC10", "SWR_MIC11" -}; - -LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_smic0_v2, LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0, - 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, - lpass_cdc_va_macro_put_dec_enum); - -LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_smic1_v2, LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0, - 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, - lpass_cdc_va_macro_put_dec_enum); - -LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_smic2_v3, LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG0, - 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, - lpass_cdc_va_macro_put_dec_enum); - -LPASS_CDC_VA_MACRO_DAPM_ENUM_EXT(va_smic3_v3, LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0, - 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, - lpass_cdc_va_macro_put_dec_enum); - static const struct snd_kcontrol_new va_aif1_cap_mixer[] = { SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC0, 1, 0, lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), @@ -1742,14 +1667,6 @@ static const struct snd_kcontrol_new va_aif1_cap_mixer[] = { lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC3, 1, 0, lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC4, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC5, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC6, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC7, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), }; static const struct snd_kcontrol_new va_aif2_cap_mixer[] = { @@ -1761,14 +1678,6 @@ static const struct snd_kcontrol_new va_aif2_cap_mixer[] = { lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC3, 1, 0, lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC4, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC5, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC6, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC7, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), }; static const struct snd_kcontrol_new va_aif3_cap_mixer[] = { @@ -1780,203 +1689,6 @@ static const struct snd_kcontrol_new va_aif3_cap_mixer[] = { lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC3, 1, 0, lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC4, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC5, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC6, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC7, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), -}; - -static const struct snd_kcontrol_new va_aif1_cap_mixer_v2[] = { - SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC0, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC1, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), -}; - -static const struct snd_kcontrol_new va_aif2_cap_mixer_v2[] = { - SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC0, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC1, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), -}; - -static const struct snd_kcontrol_new va_aif3_cap_mixer_v2[] = { - SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC0, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC1, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), -}; - -static const struct snd_kcontrol_new va_aif1_cap_mixer_v3[] = { - SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC0, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC1, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC2, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC3, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), -}; - -static const struct snd_kcontrol_new va_aif2_cap_mixer_v3[] = { - SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC0, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC1, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC2, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC3, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), -}; - -static const struct snd_kcontrol_new va_aif3_cap_mixer_v3[] = { - SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC0, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC1, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC2, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), - SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC3, 1, 0, - lpass_cdc_va_macro_tx_mixer_get, lpass_cdc_va_macro_tx_mixer_put), -}; - -static const struct snd_soc_dapm_widget lpass_cdc_va_macro_dapm_widgets_common[] = { - SND_SOC_DAPM_AIF_OUT_E("VA_AIF1 CAP", "VA_AIF1 Capture", 0, - SND_SOC_NOPM, LPASS_CDC_VA_MACRO_AIF1_CAP, 0, - lpass_cdc_va_macro_enable_tx, SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD), - - SND_SOC_DAPM_AIF_OUT_E("VA_AIF2 CAP", "VA_AIF2 Capture", 0, - SND_SOC_NOPM, LPASS_CDC_VA_MACRO_AIF2_CAP, 0, - lpass_cdc_va_macro_enable_tx, SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD), - - SND_SOC_DAPM_AIF_OUT_E("VA_AIF3 CAP", "VA_AIF3 Capture", 0, - SND_SOC_NOPM, LPASS_CDC_VA_MACRO_AIF3_CAP, 0, - lpass_cdc_va_macro_enable_tx, SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD), - - LPASS_CDC_VA_MACRO_DAPM_MUX("VA DMIC MUX0", 0, va_dmic0), - LPASS_CDC_VA_MACRO_DAPM_MUX("VA DMIC MUX1", 0, va_dmic1), - - LPASS_CDC_VA_MACRO_DAPM_MUX("VA SMIC MUX0", 0, va_smic0_v2), - LPASS_CDC_VA_MACRO_DAPM_MUX("VA SMIC MUX1", 0, va_smic1_v2), - - SND_SOC_DAPM_INPUT("VA SWR_INPUT"), - - SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0, - lpass_cdc_va_macro_enable_micbias, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("VA DMIC0", NULL, SND_SOC_NOPM, 0, 0, - lpass_cdc_va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("VA DMIC1", NULL, SND_SOC_NOPM, 0, 0, - lpass_cdc_va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("VA DMIC2", NULL, SND_SOC_NOPM, 0, 0, - lpass_cdc_va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("VA DMIC3", NULL, SND_SOC_NOPM, 0, 0, - lpass_cdc_va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("VA DMIC4", NULL, SND_SOC_NOPM, 0, 0, - lpass_cdc_va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("VA DMIC5", NULL, SND_SOC_NOPM, 0, 0, - lpass_cdc_va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("VA DMIC6", NULL, SND_SOC_NOPM, 0, 0, - lpass_cdc_va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("VA DMIC7", NULL, SND_SOC_NOPM, 0, 0, - lpass_cdc_va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX_E("VA DEC0 MUX", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC0, 0, - &va_dec0_mux, lpass_cdc_va_macro_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX_E("VA DEC1 MUX", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC1, 0, - &va_dec1_mux, lpass_cdc_va_macro_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0, - lpass_cdc_va_macro_mclk_event, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), -}; - -static const struct snd_soc_dapm_widget lpass_cdc_va_macro_dapm_widgets_v2[] = { - SND_SOC_DAPM_MIXER("VA_AIF1_CAP Mixer", SND_SOC_NOPM, - LPASS_CDC_VA_MACRO_AIF1_CAP, 0, - va_aif1_cap_mixer_v2, ARRAY_SIZE(va_aif1_cap_mixer_v2)), - - SND_SOC_DAPM_MIXER("VA_AIF2_CAP Mixer", SND_SOC_NOPM, - LPASS_CDC_VA_MACRO_AIF2_CAP, 0, - va_aif2_cap_mixer_v2, ARRAY_SIZE(va_aif2_cap_mixer_v2)), - - SND_SOC_DAPM_MIXER("VA_AIF3_CAP Mixer", SND_SOC_NOPM, - LPASS_CDC_VA_MACRO_AIF3_CAP, 0, - va_aif3_cap_mixer_v2, ARRAY_SIZE(va_aif3_cap_mixer_v2)), - - SND_SOC_DAPM_SUPPLY_S("VA_SWR_PWR", -1, SND_SOC_NOPM, 0, 0, - lpass_cdc_va_macro_swr_pwr_event_v2, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_SUPPLY_S("VA_TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, - lpass_cdc_va_macro_tx_swr_clk_event_v2, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, - lpass_cdc_va_macro_swr_clk_event_v2, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), -}; - -static const struct snd_soc_dapm_widget lpass_cdc_va_macro_dapm_widgets_v3[] = { - SND_SOC_DAPM_MIXER("VA_AIF1_CAP Mixer", SND_SOC_NOPM, - LPASS_CDC_VA_MACRO_AIF1_CAP, 0, - va_aif1_cap_mixer_v3, ARRAY_SIZE(va_aif1_cap_mixer_v3)), - - SND_SOC_DAPM_MIXER("VA_AIF2_CAP Mixer", SND_SOC_NOPM, - LPASS_CDC_VA_MACRO_AIF2_CAP, 0, - va_aif2_cap_mixer_v3, ARRAY_SIZE(va_aif2_cap_mixer_v3)), - - SND_SOC_DAPM_MIXER("VA_AIF3_CAP Mixer", SND_SOC_NOPM, - LPASS_CDC_VA_MACRO_AIF3_CAP, 0, - va_aif3_cap_mixer_v3, ARRAY_SIZE(va_aif3_cap_mixer_v3)), - - LPASS_CDC_VA_MACRO_DAPM_MUX("VA DMIC MUX2", 0, va_dmic2), - LPASS_CDC_VA_MACRO_DAPM_MUX("VA DMIC MUX3", 0, va_dmic3), - - LPASS_CDC_VA_MACRO_DAPM_MUX("VA SMIC MUX2", 0, va_smic2_v3), - LPASS_CDC_VA_MACRO_DAPM_MUX("VA SMIC MUX3", 0, va_smic3_v3), - - SND_SOC_DAPM_MUX_E("VA DEC2 MUX", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC2, 0, - &va_dec2_mux, lpass_cdc_va_macro_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX_E("VA DEC3 MUX", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC3, 0, - &va_dec3_mux, lpass_cdc_va_macro_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_SUPPLY_S("VA_SWR_PWR", -1, SND_SOC_NOPM, 0, 0, - lpass_cdc_va_macro_swr_pwr_event, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), }; static const struct snd_soc_dapm_widget lpass_cdc_va_macro_dapm_widgets[] = { @@ -2011,21 +1723,15 @@ static const struct snd_soc_dapm_widget lpass_cdc_va_macro_dapm_widgets[] = { LPASS_CDC_VA_MACRO_DAPM_MUX("VA DMIC MUX1", 0, va_dmic1), LPASS_CDC_VA_MACRO_DAPM_MUX("VA DMIC MUX2", 0, va_dmic2), LPASS_CDC_VA_MACRO_DAPM_MUX("VA DMIC MUX3", 0, va_dmic3), - LPASS_CDC_VA_MACRO_DAPM_MUX("VA DMIC MUX4", 0, va_dmic4), - LPASS_CDC_VA_MACRO_DAPM_MUX("VA DMIC MUX5", 0, va_dmic5), - LPASS_CDC_VA_MACRO_DAPM_MUX("VA DMIC MUX6", 0, va_dmic6), - LPASS_CDC_VA_MACRO_DAPM_MUX("VA DMIC MUX7", 0, va_dmic7), LPASS_CDC_VA_MACRO_DAPM_MUX("VA SMIC MUX0", 0, va_smic0), LPASS_CDC_VA_MACRO_DAPM_MUX("VA SMIC MUX1", 0, va_smic1), LPASS_CDC_VA_MACRO_DAPM_MUX("VA SMIC MUX2", 0, va_smic2), LPASS_CDC_VA_MACRO_DAPM_MUX("VA SMIC MUX3", 0, va_smic3), - LPASS_CDC_VA_MACRO_DAPM_MUX("VA SMIC MUX4", 0, va_smic4), - LPASS_CDC_VA_MACRO_DAPM_MUX("VA SMIC MUX5", 0, va_smic5), - LPASS_CDC_VA_MACRO_DAPM_MUX("VA SMIC MUX6", 0, va_smic6), - LPASS_CDC_VA_MACRO_DAPM_MUX("VA SMIC MUX7", 0, va_smic7), - SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0, + SND_SOC_DAPM_INPUT("VA SWR_INPUT"), + + SND_SOC_DAPM_SUPPLY("VA MIC BIAS", SND_SOC_NOPM, 0, 0, lpass_cdc_va_macro_enable_micbias, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), @@ -2061,19 +1767,6 @@ static const struct snd_soc_dapm_widget lpass_cdc_va_macro_dapm_widgets[] = { lpass_cdc_va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_INPUT("VA SWR_ADC0"), - SND_SOC_DAPM_INPUT("VA SWR_ADC1"), - SND_SOC_DAPM_INPUT("VA SWR_ADC2"), - SND_SOC_DAPM_INPUT("VA SWR_ADC3"), - SND_SOC_DAPM_INPUT("VA SWR_MIC0"), - SND_SOC_DAPM_INPUT("VA SWR_MIC1"), - SND_SOC_DAPM_INPUT("VA SWR_MIC2"), - SND_SOC_DAPM_INPUT("VA SWR_MIC3"), - SND_SOC_DAPM_INPUT("VA SWR_MIC4"), - SND_SOC_DAPM_INPUT("VA SWR_MIC5"), - SND_SOC_DAPM_INPUT("VA SWR_MIC6"), - SND_SOC_DAPM_INPUT("VA SWR_MIC7"), - SND_SOC_DAPM_MUX_E("VA DEC0 MUX", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC0, 0, &va_dec0_mux, lpass_cdc_va_macro_enable_dec, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | @@ -2094,42 +1787,24 @@ static const struct snd_soc_dapm_widget lpass_cdc_va_macro_dapm_widgets[] = { SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MUX_E("VA DEC4 MUX", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC4, 0, - &va_dec4_mux, lpass_cdc_va_macro_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0, + lpass_cdc_va_macro_mclk_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MUX_E("VA DEC5 MUX", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC5, 0, - &va_dec5_mux, lpass_cdc_va_macro_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX_E("VA DEC6 MUX", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC6, 0, - &va_dec6_mux, lpass_cdc_va_macro_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX_E("VA DEC7 MUX", SND_SOC_NOPM, LPASS_CDC_VA_MACRO_DEC7, 0, - &va_dec7_mux, lpass_cdc_va_macro_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_SUPPLY_S("VA_SWR_PWR", -1, SND_SOC_NOPM, 0, 0, + SND_SOC_DAPM_SUPPLY_S("VA_SWR_PWR", 0, SND_SOC_NOPM, 0, 0, lpass_cdc_va_macro_swr_pwr_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0, - lpass_cdc_va_macro_mclk_event, + SND_SOC_DAPM_SUPPLY_S("VA_TX_SWR_CLK", -1, SND_SOC_NOPM, 0, 0, + lpass_cdc_va_macro_tx_swr_clk_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", -1, SND_SOC_NOPM, 0, 0, + lpass_cdc_va_macro_swr_clk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), }; -static const struct snd_soc_dapm_widget lpass_cdc_va_macro_wod_dapm_widgets[] = { - SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0, - lpass_cdc_va_macro_mclk_event, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), -}; - -static const struct snd_soc_dapm_route va_audio_map_common[] = { +static const struct snd_soc_dapm_route va_audio_map[] = { {"VA_AIF1 CAP", NULL, "VA_MCLK"}, {"VA_AIF2 CAP", NULL, "VA_MCLK"}, {"VA_AIF3 CAP", NULL, "VA_MCLK"}, @@ -2140,12 +1815,18 @@ static const struct snd_soc_dapm_route va_audio_map_common[] = { {"VA_AIF1_CAP Mixer", "DEC0", "VA DEC0 MUX"}, {"VA_AIF1_CAP Mixer", "DEC1", "VA DEC1 MUX"}, + {"VA_AIF1_CAP Mixer", "DEC2", "VA DEC2 MUX"}, + {"VA_AIF1_CAP Mixer", "DEC3", "VA DEC3 MUX"}, {"VA_AIF2_CAP Mixer", "DEC0", "VA DEC0 MUX"}, {"VA_AIF2_CAP Mixer", "DEC1", "VA DEC1 MUX"}, + {"VA_AIF2_CAP Mixer", "DEC2", "VA DEC2 MUX"}, + {"VA_AIF2_CAP Mixer", "DEC3", "VA DEC3 MUX"}, {"VA_AIF3_CAP Mixer", "DEC0", "VA DEC0 MUX"}, {"VA_AIF3_CAP Mixer", "DEC1", "VA DEC1 MUX"}, + {"VA_AIF3_CAP Mixer", "DEC2", "VA DEC2 MUX"}, + {"VA_AIF3_CAP Mixer", "DEC3", "VA DEC3 MUX"}, {"VA DEC0 MUX", "MSM_DMIC", "VA DMIC MUX0"}, {"VA DMIC MUX0", "DMIC0", "VA DMIC0"}, @@ -2195,31 +1876,6 @@ static const struct snd_soc_dapm_route va_audio_map_common[] = { {"VA SMIC MUX1", "SWR_MIC10", "VA SWR_INPUT"}, {"VA SMIC MUX1", "SWR_MIC11", "VA SWR_INPUT"}, - {"VA SWR_INPUT", NULL, "VA_SWR_PWR"}, - {"VA SWR_INPUT", NULL, "VA_SWR_PWR"}, - {"VA SWR_INPUT", NULL, "VA_SWR_PWR"}, - {"VA SWR_INPUT", NULL, "VA_SWR_PWR"}, - {"VA SWR_INPUT", NULL, "VA_SWR_PWR"}, - {"VA SWR_INPUT", NULL, "VA_SWR_PWR"}, - {"VA SWR_INPUT", NULL, "VA_SWR_PWR"}, - {"VA SWR_INPUT", NULL, "VA_SWR_PWR"}, - {"VA SWR_INPUT", NULL, "VA_SWR_PWR"}, - {"VA SWR_INPUT", NULL, "VA_SWR_PWR"}, - {"VA SWR_INPUT", NULL, "VA_SWR_PWR"}, - {"VA SWR_INPUT", NULL, "VA_SWR_PWR"}, - -}; - -static const struct snd_soc_dapm_route va_audio_map_v3[] = { - {"VA_AIF1_CAP Mixer", "DEC2", "VA DEC2 MUX"}, - {"VA_AIF1_CAP Mixer", "DEC3", "VA DEC3 MUX"}, - - {"VA_AIF2_CAP Mixer", "DEC2", "VA DEC2 MUX"}, - {"VA_AIF2_CAP Mixer", "DEC3", "VA DEC3 MUX"}, - - {"VA_AIF3_CAP Mixer", "DEC2", "VA DEC2 MUX"}, - {"VA_AIF3_CAP Mixer", "DEC3", "VA DEC3 MUX"}, - {"VA DEC2 MUX", "MSM_DMIC", "VA DMIC MUX2"}, {"VA DMIC MUX2", "DMIC0", "VA DMIC0"}, {"VA DMIC MUX2", "DMIC1", "VA DMIC1"}, @@ -2267,256 +1923,14 @@ static const struct snd_soc_dapm_route va_audio_map_v3[] = { {"VA SMIC MUX3", "SWR_MIC9", "VA SWR_INPUT"}, {"VA SMIC MUX3", "SWR_MIC10", "VA SWR_INPUT"}, {"VA SMIC MUX3", "SWR_MIC11", "VA SWR_INPUT"}, -}; -static const struct snd_soc_dapm_route va_audio_map_v2[] = { + {"VA SWR_INPUT", NULL, "VA_SWR_PWR"}, + {"VA_AIF1 CAP", NULL, "VA_SWR_CLK"}, {"VA_AIF2 CAP", NULL, "VA_SWR_CLK"}, {"VA_AIF3 CAP", NULL, "VA_SWR_CLK"}, }; -static const struct snd_soc_dapm_route va_audio_map[] = { - {"VA_AIF1 CAP", NULL, "VA_MCLK"}, - {"VA_AIF2 CAP", NULL, "VA_MCLK"}, - {"VA_AIF3 CAP", NULL, "VA_MCLK"}, - - {"VA_AIF1 CAP", NULL, "VA_AIF1_CAP Mixer"}, - {"VA_AIF2 CAP", NULL, "VA_AIF2_CAP Mixer"}, - {"VA_AIF3 CAP", NULL, "VA_AIF3_CAP Mixer"}, - - {"VA_AIF1_CAP Mixer", "DEC0", "VA DEC0 MUX"}, - {"VA_AIF1_CAP Mixer", "DEC1", "VA DEC1 MUX"}, - {"VA_AIF1_CAP Mixer", "DEC2", "VA DEC2 MUX"}, - {"VA_AIF1_CAP Mixer", "DEC3", "VA DEC3 MUX"}, - {"VA_AIF1_CAP Mixer", "DEC4", "VA DEC4 MUX"}, - {"VA_AIF1_CAP Mixer", "DEC5", "VA DEC5 MUX"}, - {"VA_AIF1_CAP Mixer", "DEC6", "VA DEC6 MUX"}, - {"VA_AIF1_CAP Mixer", "DEC7", "VA DEC7 MUX"}, - - {"VA_AIF2_CAP Mixer", "DEC0", "VA DEC0 MUX"}, - {"VA_AIF2_CAP Mixer", "DEC1", "VA DEC1 MUX"}, - {"VA_AIF2_CAP Mixer", "DEC2", "VA DEC2 MUX"}, - {"VA_AIF2_CAP Mixer", "DEC3", "VA DEC3 MUX"}, - {"VA_AIF2_CAP Mixer", "DEC4", "VA DEC4 MUX"}, - {"VA_AIF2_CAP Mixer", "DEC5", "VA DEC5 MUX"}, - {"VA_AIF2_CAP Mixer", "DEC6", "VA DEC6 MUX"}, - {"VA_AIF2_CAP Mixer", "DEC7", "VA DEC7 MUX"}, - - {"VA_AIF3_CAP Mixer", "DEC0", "VA DEC0 MUX"}, - {"VA_AIF3_CAP Mixer", "DEC1", "VA DEC1 MUX"}, - {"VA_AIF3_CAP Mixer", "DEC2", "VA DEC2 MUX"}, - {"VA_AIF3_CAP Mixer", "DEC3", "VA DEC3 MUX"}, - {"VA_AIF3_CAP Mixer", "DEC4", "VA DEC4 MUX"}, - {"VA_AIF3_CAP Mixer", "DEC5", "VA DEC5 MUX"}, - {"VA_AIF3_CAP Mixer", "DEC6", "VA DEC6 MUX"}, - {"VA_AIF3_CAP Mixer", "DEC7", "VA DEC7 MUX"}, - - {"VA DEC0 MUX", "MSM_DMIC", "VA DMIC MUX0"}, - {"VA DMIC MUX0", "DMIC0", "VA DMIC0"}, - {"VA DMIC MUX0", "DMIC1", "VA DMIC1"}, - {"VA DMIC MUX0", "DMIC2", "VA DMIC2"}, - {"VA DMIC MUX0", "DMIC3", "VA DMIC3"}, - {"VA DMIC MUX0", "DMIC4", "VA DMIC4"}, - {"VA DMIC MUX0", "DMIC5", "VA DMIC5"}, - {"VA DMIC MUX0", "DMIC6", "VA DMIC6"}, - {"VA DMIC MUX0", "DMIC7", "VA DMIC7"}, - - {"VA DEC0 MUX", "SWR_MIC", "VA SMIC MUX0"}, - {"VA SMIC MUX0", "ADC0", "VA SWR_ADC0"}, - {"VA SMIC MUX0", "ADC1", "VA SWR_ADC1"}, - {"VA SMIC MUX0", "ADC2", "VA SWR_ADC2"}, - {"VA SMIC MUX0", "ADC3", "VA SWR_ADC3"}, - {"VA SMIC MUX0", "SWR_DMIC0", "VA SWR_MIC0"}, - {"VA SMIC MUX0", "SWR_DMIC1", "VA SWR_MIC1"}, - {"VA SMIC MUX0", "SWR_DMIC2", "VA SWR_MIC2"}, - {"VA SMIC MUX0", "SWR_DMIC3", "VA SWR_MIC3"}, - {"VA SMIC MUX0", "SWR_DMIC4", "VA SWR_MIC4"}, - {"VA SMIC MUX0", "SWR_DMIC5", "VA SWR_MIC5"}, - {"VA SMIC MUX0", "SWR_DMIC6", "VA SWR_MIC6"}, - {"VA SMIC MUX0", "SWR_DMIC7", "VA SWR_MIC7"}, - - {"VA DEC1 MUX", "MSM_DMIC", "VA DMIC MUX1"}, - {"VA DMIC MUX1", "DMIC0", "VA DMIC0"}, - {"VA DMIC MUX1", "DMIC1", "VA DMIC1"}, - {"VA DMIC MUX1", "DMIC2", "VA DMIC2"}, - {"VA DMIC MUX1", "DMIC3", "VA DMIC3"}, - {"VA DMIC MUX1", "DMIC4", "VA DMIC4"}, - {"VA DMIC MUX1", "DMIC5", "VA DMIC5"}, - {"VA DMIC MUX1", "DMIC6", "VA DMIC6"}, - {"VA DMIC MUX1", "DMIC7", "VA DMIC7"}, - - {"VA DEC1 MUX", "SWR_MIC", "VA SMIC MUX1"}, - {"VA SMIC MUX1", "ADC0", "VA SWR_ADC0"}, - {"VA SMIC MUX1", "ADC1", "VA SWR_ADC1"}, - {"VA SMIC MUX1", "ADC2", "VA SWR_ADC2"}, - {"VA SMIC MUX1", "ADC3", "VA SWR_ADC3"}, - {"VA SMIC MUX1", "SWR_DMIC0", "VA SWR_MIC0"}, - {"VA SMIC MUX1", "SWR_DMIC1", "VA SWR_MIC1"}, - {"VA SMIC MUX1", "SWR_DMIC2", "VA SWR_MIC2"}, - {"VA SMIC MUX1", "SWR_DMIC3", "VA SWR_MIC3"}, - {"VA SMIC MUX1", "SWR_DMIC4", "VA SWR_MIC4"}, - {"VA SMIC MUX1", "SWR_DMIC5", "VA SWR_MIC5"}, - {"VA SMIC MUX1", "SWR_DMIC6", "VA SWR_MIC6"}, - {"VA SMIC MUX1", "SWR_DMIC7", "VA SWR_MIC7"}, - - {"VA DEC2 MUX", "MSM_DMIC", "VA DMIC MUX2"}, - {"VA DMIC MUX2", "DMIC0", "VA DMIC0"}, - {"VA DMIC MUX2", "DMIC1", "VA DMIC1"}, - {"VA DMIC MUX2", "DMIC2", "VA DMIC2"}, - {"VA DMIC MUX2", "DMIC3", "VA DMIC3"}, - {"VA DMIC MUX2", "DMIC4", "VA DMIC4"}, - {"VA DMIC MUX2", "DMIC5", "VA DMIC5"}, - {"VA DMIC MUX2", "DMIC6", "VA DMIC6"}, - {"VA DMIC MUX2", "DMIC7", "VA DMIC7"}, - - {"VA DEC2 MUX", "SWR_MIC", "VA SMIC MUX2"}, - {"VA SMIC MUX2", "ADC0", "VA SWR_ADC0"}, - {"VA SMIC MUX2", "ADC1", "VA SWR_ADC1"}, - {"VA SMIC MUX2", "ADC2", "VA SWR_ADC2"}, - {"VA SMIC MUX2", "ADC3", "VA SWR_ADC3"}, - {"VA SMIC MUX2", "SWR_DMIC0", "VA SWR_MIC0"}, - {"VA SMIC MUX2", "SWR_DMIC1", "VA SWR_MIC1"}, - {"VA SMIC MUX2", "SWR_DMIC2", "VA SWR_MIC2"}, - {"VA SMIC MUX2", "SWR_DMIC3", "VA SWR_MIC3"}, - {"VA SMIC MUX2", "SWR_DMIC4", "VA SWR_MIC4"}, - {"VA SMIC MUX2", "SWR_DMIC5", "VA SWR_MIC5"}, - {"VA SMIC MUX2", "SWR_DMIC6", "VA SWR_MIC6"}, - {"VA SMIC MUX2", "SWR_DMIC7", "VA SWR_MIC7"}, - - {"VA DEC3 MUX", "MSM_DMIC", "VA DMIC MUX3"}, - {"VA DMIC MUX3", "DMIC0", "VA DMIC0"}, - {"VA DMIC MUX3", "DMIC1", "VA DMIC1"}, - {"VA DMIC MUX3", "DMIC2", "VA DMIC2"}, - {"VA DMIC MUX3", "DMIC3", "VA DMIC3"}, - {"VA DMIC MUX3", "DMIC4", "VA DMIC4"}, - {"VA DMIC MUX3", "DMIC5", "VA DMIC5"}, - {"VA DMIC MUX3", "DMIC6", "VA DMIC6"}, - {"VA DMIC MUX3", "DMIC7", "VA DMIC7"}, - - {"VA DEC3 MUX", "SWR_MIC", "VA SMIC MUX3"}, - {"VA SMIC MUX3", "ADC0", "VA SWR_ADC0"}, - {"VA SMIC MUX3", "ADC1", "VA SWR_ADC1"}, - {"VA SMIC MUX3", "ADC2", "VA SWR_ADC2"}, - {"VA SMIC MUX3", "ADC3", "VA SWR_ADC3"}, - {"VA SMIC MUX3", "SWR_DMIC0", "VA SWR_MIC0"}, - {"VA SMIC MUX3", "SWR_DMIC1", "VA SWR_MIC1"}, - {"VA SMIC MUX3", "SWR_DMIC2", "VA SWR_MIC2"}, - {"VA SMIC MUX3", "SWR_DMIC3", "VA SWR_MIC3"}, - {"VA SMIC MUX3", "SWR_DMIC4", "VA SWR_MIC4"}, - {"VA SMIC MUX3", "SWR_DMIC5", "VA SWR_MIC5"}, - {"VA SMIC MUX3", "SWR_DMIC6", "VA SWR_MIC6"}, - {"VA SMIC MUX3", "SWR_DMIC7", "VA SWR_MIC7"}, - - {"VA DEC4 MUX", "MSM_DMIC", "VA DMIC MUX4"}, - {"VA DMIC MUX4", "DMIC0", "VA DMIC0"}, - {"VA DMIC MUX4", "DMIC1", "VA DMIC1"}, - {"VA DMIC MUX4", "DMIC2", "VA DMIC2"}, - {"VA DMIC MUX4", "DMIC3", "VA DMIC3"}, - {"VA DMIC MUX4", "DMIC4", "VA DMIC4"}, - {"VA DMIC MUX4", "DMIC5", "VA DMIC5"}, - {"VA DMIC MUX4", "DMIC6", "VA DMIC6"}, - {"VA DMIC MUX4", "DMIC7", "VA DMIC7"}, - - {"VA DEC4 MUX", "SWR_MIC", "VA SMIC MUX4"}, - {"VA SMIC MUX4", "ADC0", "VA SWR_ADC0"}, - {"VA SMIC MUX4", "ADC1", "VA SWR_ADC1"}, - {"VA SMIC MUX4", "ADC2", "VA SWR_ADC2"}, - {"VA SMIC MUX4", "ADC3", "VA SWR_ADC3"}, - {"VA SMIC MUX4", "SWR_DMIC0", "VA SWR_MIC0"}, - {"VA SMIC MUX4", "SWR_DMIC1", "VA SWR_MIC1"}, - {"VA SMIC MUX4", "SWR_DMIC2", "VA SWR_MIC2"}, - {"VA SMIC MUX4", "SWR_DMIC3", "VA SWR_MIC3"}, - {"VA SMIC MUX4", "SWR_DMIC4", "VA SWR_MIC4"}, - {"VA SMIC MUX4", "SWR_DMIC5", "VA SWR_MIC5"}, - {"VA SMIC MUX4", "SWR_DMIC6", "VA SWR_MIC6"}, - {"VA SMIC MUX4", "SWR_DMIC7", "VA SWR_MIC7"}, - - {"VA DEC5 MUX", "MSM_DMIC", "VA DMIC MUX5"}, - {"VA DMIC MUX5", "DMIC0", "VA DMIC0"}, - {"VA DMIC MUX5", "DMIC1", "VA DMIC1"}, - {"VA DMIC MUX5", "DMIC2", "VA DMIC2"}, - {"VA DMIC MUX5", "DMIC3", "VA DMIC3"}, - {"VA DMIC MUX5", "DMIC4", "VA DMIC4"}, - {"VA DMIC MUX5", "DMIC5", "VA DMIC5"}, - {"VA DMIC MUX5", "DMIC6", "VA DMIC6"}, - {"VA DMIC MUX5", "DMIC7", "VA DMIC7"}, - - {"VA DEC5 MUX", "SWR_MIC", "VA SMIC MUX5"}, - {"VA SMIC MUX5", "ADC0", "VA SWR_ADC0"}, - {"VA SMIC MUX5", "ADC1", "VA SWR_ADC1"}, - {"VA SMIC MUX5", "ADC2", "VA SWR_ADC2"}, - {"VA SMIC MUX5", "ADC3", "VA SWR_ADC3"}, - {"VA SMIC MUX5", "SWR_DMIC0", "VA SWR_MIC0"}, - {"VA SMIC MUX5", "SWR_DMIC1", "VA SWR_MIC1"}, - {"VA SMIC MUX5", "SWR_DMIC2", "VA SWR_MIC2"}, - {"VA SMIC MUX5", "SWR_DMIC3", "VA SWR_MIC3"}, - {"VA SMIC MUX5", "SWR_DMIC4", "VA SWR_MIC4"}, - {"VA SMIC MUX5", "SWR_DMIC5", "VA SWR_MIC5"}, - {"VA SMIC MUX5", "SWR_DMIC6", "VA SWR_MIC6"}, - {"VA SMIC MUX5", "SWR_DMIC7", "VA SWR_MIC7"}, - - {"VA DEC6 MUX", "MSM_DMIC", "VA DMIC MUX6"}, - {"VA DMIC MUX6", "DMIC0", "VA DMIC0"}, - {"VA DMIC MUX6", "DMIC1", "VA DMIC1"}, - {"VA DMIC MUX6", "DMIC2", "VA DMIC2"}, - {"VA DMIC MUX6", "DMIC3", "VA DMIC3"}, - {"VA DMIC MUX6", "DMIC4", "VA DMIC4"}, - {"VA DMIC MUX6", "DMIC5", "VA DMIC5"}, - {"VA DMIC MUX6", "DMIC6", "VA DMIC6"}, - {"VA DMIC MUX6", "DMIC7", "VA DMIC7"}, - - {"VA DEC6 MUX", "SWR_MIC", "VA SMIC MUX6"}, - {"VA SMIC MUX6", "ADC0", "VA SWR_ADC0"}, - {"VA SMIC MUX6", "ADC1", "VA SWR_ADC1"}, - {"VA SMIC MUX6", "ADC2", "VA SWR_ADC2"}, - {"VA SMIC MUX6", "ADC3", "VA SWR_ADC3"}, - {"VA SMIC MUX6", "SWR_DMIC0", "VA SWR_MIC0"}, - {"VA SMIC MUX6", "SWR_DMIC1", "VA SWR_MIC1"}, - {"VA SMIC MUX6", "SWR_DMIC2", "VA SWR_MIC2"}, - {"VA SMIC MUX6", "SWR_DMIC3", "VA SWR_MIC3"}, - {"VA SMIC MUX6", "SWR_DMIC4", "VA SWR_MIC4"}, - {"VA SMIC MUX6", "SWR_DMIC5", "VA SWR_MIC5"}, - {"VA SMIC MUX6", "SWR_DMIC6", "VA SWR_MIC6"}, - {"VA SMIC MUX6", "SWR_DMIC7", "VA SWR_MIC7"}, - - {"VA DEC7 MUX", "MSM_DMIC", "VA DMIC MUX7"}, - {"VA DMIC MUX7", "DMIC0", "VA DMIC0"}, - {"VA DMIC MUX7", "DMIC1", "VA DMIC1"}, - {"VA DMIC MUX7", "DMIC2", "VA DMIC2"}, - {"VA DMIC MUX7", "DMIC3", "VA DMIC3"}, - {"VA DMIC MUX7", "DMIC4", "VA DMIC4"}, - {"VA DMIC MUX7", "DMIC5", "VA DMIC5"}, - {"VA DMIC MUX7", "DMIC6", "VA DMIC6"}, - {"VA DMIC MUX7", "DMIC7", "VA DMIC7"}, - - {"VA DEC7 MUX", "SWR_MIC", "VA SMIC MUX7"}, - {"VA SMIC MUX7", "ADC0", "VA SWR_ADC0"}, - {"VA SMIC MUX7", "ADC1", "VA SWR_ADC1"}, - {"VA SMIC MUX7", "ADC2", "VA SWR_ADC2"}, - {"VA SMIC MUX7", "ADC3", "VA SWR_ADC3"}, - {"VA SMIC MUX7", "SWR_DMIC0", "VA SWR_MIC0"}, - {"VA SMIC MUX7", "SWR_DMIC1", "VA SWR_MIC1"}, - {"VA SMIC MUX7", "SWR_DMIC2", "VA SWR_MIC2"}, - {"VA SMIC MUX7", "SWR_DMIC3", "VA SWR_MIC3"}, - {"VA SMIC MUX7", "SWR_DMIC4", "VA SWR_MIC4"}, - {"VA SMIC MUX7", "SWR_DMIC5", "VA SWR_MIC5"}, - {"VA SMIC MUX7", "SWR_DMIC6", "VA SWR_MIC6"}, - {"VA SMIC MUX7", "SWR_DMIC7", "VA SWR_MIC7"}, - - {"VA SWR_ADC0", NULL, "VA_SWR_PWR"}, - {"VA SWR_ADC1", NULL, "VA_SWR_PWR"}, - {"VA SWR_ADC2", NULL, "VA_SWR_PWR"}, - {"VA SWR_ADC3", NULL, "VA_SWR_PWR"}, - {"VA SWR_MIC0", NULL, "VA_SWR_PWR"}, - {"VA SWR_MIC1", NULL, "VA_SWR_PWR"}, - {"VA SWR_MIC2", NULL, "VA_SWR_PWR"}, - {"VA SWR_MIC3", NULL, "VA_SWR_PWR"}, - {"VA SWR_MIC4", NULL, "VA_SWR_PWR"}, - {"VA SWR_MIC5", NULL, "VA_SWR_PWR"}, - {"VA SWR_MIC6", NULL, "VA_SWR_PWR"}, - {"VA SWR_MIC7", NULL, "VA_SWR_PWR"}, -}; - static const char * const dec_mode_mux_text[] = { "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF", }; @@ -2538,18 +1952,6 @@ static const struct snd_kcontrol_new lpass_cdc_va_macro_snd_controls[] = { SOC_SINGLE_S8_TLV("VA_DEC3 Volume", LPASS_CDC_VA_TX3_TX_VOL_CTL, -84, 40, digital_gain), - SOC_SINGLE_S8_TLV("VA_DEC4 Volume", - LPASS_CDC_VA_TX4_TX_VOL_CTL, - -84, 40, digital_gain), - SOC_SINGLE_S8_TLV("VA_DEC5 Volume", - LPASS_CDC_VA_TX5_TX_VOL_CTL, - -84, 40, digital_gain), - SOC_SINGLE_S8_TLV("VA_DEC6 Volume", - LPASS_CDC_VA_TX6_TX_VOL_CTL, - -84, 40, digital_gain), - SOC_SINGLE_S8_TLV("VA_DEC7 Volume", - LPASS_CDC_VA_TX7_TX_VOL_CTL, - -84, 40, digital_gain), SOC_SINGLE_EXT("LPI Enable", 0, 0, 1, 0, lpass_cdc_va_macro_lpi_get, lpass_cdc_va_macro_lpi_put), @@ -2566,27 +1968,6 @@ static const struct snd_kcontrol_new lpass_cdc_va_macro_snd_controls[] = { lpass_cdc_va_macro_dec_mode_get, lpass_cdc_va_macro_dec_mode_put), }; -static const struct snd_kcontrol_new lpass_cdc_va_macro_snd_controls_common[] = -{ - SOC_SINGLE_S8_TLV("VA_DEC0 Volume", - LPASS_CDC_VA_TX0_TX_VOL_CTL, - -84, 40, digital_gain), - SOC_SINGLE_S8_TLV("VA_DEC1 Volume", - LPASS_CDC_VA_TX1_TX_VOL_CTL, - -84, 40, digital_gain), - SOC_SINGLE_EXT("LPI Enable", 0, 0, 1, 0, - lpass_cdc_va_macro_lpi_get, lpass_cdc_va_macro_lpi_put), -}; - -static const struct snd_kcontrol_new lpass_cdc_va_macro_snd_controls_v3[] = { - SOC_SINGLE_S8_TLV("VA_DEC2 Volume", - LPASS_CDC_VA_TX2_TX_VOL_CTL, - -84, 40, digital_gain), - SOC_SINGLE_S8_TLV("VA_DEC3 Volume", - LPASS_CDC_VA_TX3_TX_VOL_CTL, - -84, 40, digital_gain), -}; - static int lpass_cdc_va_macro_validate_dmic_sample_rate(u32 dmic_sample_rate, struct lpass_cdc_va_macro_priv *va_priv) { @@ -2659,93 +2040,25 @@ static int lpass_cdc_va_macro_init(struct snd_soc_component *component) } va_priv->lpi_enable = false; - va_priv->register_event_listener = false; - - if (va_priv->va_without_decimation) { - ret = snd_soc_dapm_new_controls(dapm, - lpass_cdc_va_macro_wod_dapm_widgets, - ARRAY_SIZE(lpass_cdc_va_macro_wod_dapm_widgets)); - if (ret < 0) { - dev_err(va_dev, - "%s: Failed to add without dec controls\n", - __func__); - return ret; - } - va_priv->component = component; - return 0; - } + //va_priv->register_event_listener = false; va_priv->version = lpass_cdc_get_version(va_dev); - if (va_priv->version >= LPASS_CDC_VERSION_2_0) { - ret = snd_soc_dapm_new_controls(dapm, - lpass_cdc_va_macro_dapm_widgets_common, - ARRAY_SIZE(lpass_cdc_va_macro_dapm_widgets_common)); - if (ret < 0) { - dev_err(va_dev, "%s: Failed to add controls\n", - __func__); - return ret; - } - if (va_priv->version == LPASS_CDC_VERSION_2_1) - ret = snd_soc_dapm_new_controls(dapm, - lpass_cdc_va_macro_dapm_widgets_v2, - ARRAY_SIZE(lpass_cdc_va_macro_dapm_widgets_v2)); - else if (va_priv->version == LPASS_CDC_VERSION_2_0) - ret = snd_soc_dapm_new_controls(dapm, - lpass_cdc_va_macro_dapm_widgets_v3, - ARRAY_SIZE(lpass_cdc_va_macro_dapm_widgets_v3)); - if (ret < 0) { - dev_err(va_dev, "%s: Failed to add controls\n", - __func__); - return ret; - } - } else { - ret = snd_soc_dapm_new_controls(dapm, - lpass_cdc_va_macro_dapm_widgets, - ARRAY_SIZE(lpass_cdc_va_macro_dapm_widgets)); - if (ret < 0) { - dev_err(va_dev, "%s: Failed to add controls\n", - __func__); - return ret; - } + + ret = snd_soc_dapm_new_controls(dapm, + lpass_cdc_va_macro_dapm_widgets, + ARRAY_SIZE(lpass_cdc_va_macro_dapm_widgets)); + if (ret < 0) { + dev_err(va_dev, "%s: Failed to add controls\n", + __func__); + return ret; } - if (va_priv->version >= LPASS_CDC_VERSION_2_0) { - ret = snd_soc_dapm_add_routes(dapm, - va_audio_map_common, - ARRAY_SIZE(va_audio_map_common)); - if (ret < 0) { - dev_err(va_dev, "%s: Failed to add routes\n", - __func__); - return ret; - } - if (va_priv->version == LPASS_CDC_VERSION_2_0) { - ret = snd_soc_dapm_add_routes(dapm, - va_audio_map_v3, - ARRAY_SIZE(va_audio_map_v3)); - if (ret < 0) { - dev_err(va_dev, "%s: Failed to add routes\n", - __func__); - return ret; - } - } - if (va_priv->version == LPASS_CDC_VERSION_2_1) { - ret = snd_soc_dapm_add_routes(dapm, - va_audio_map_v2, - ARRAY_SIZE(va_audio_map_v2)); - if (ret < 0) { - dev_err(va_dev, "%s: Failed to add routes\n", - __func__); - return ret; - } - } - } else { - ret = snd_soc_dapm_add_routes(dapm, va_audio_map, - ARRAY_SIZE(va_audio_map)); - if (ret < 0) { - dev_err(va_dev, "%s: Failed to add routes\n", - __func__); - return ret; - } + ret = snd_soc_dapm_add_routes(dapm, va_audio_map, + ARRAY_SIZE(va_audio_map)); + if (ret < 0) { + dev_err(va_dev, "%s: Failed to add routes\n", + __func__); + return ret; } ret = snd_soc_dapm_new_widgets(dapm->card); @@ -2753,54 +2066,20 @@ static int lpass_cdc_va_macro_init(struct snd_soc_component *component) dev_err(va_dev, "%s: Failed to add widgets\n", __func__); return ret; } - if (va_priv->version >= LPASS_CDC_VERSION_2_0) { - ret = snd_soc_add_component_controls(component, - lpass_cdc_va_macro_snd_controls_common, - ARRAY_SIZE(lpass_cdc_va_macro_snd_controls_common)); - if (ret < 0) { - dev_err(va_dev, "%s: Failed to add snd_ctls\n", - __func__); - return ret; - } - if (va_priv->version == LPASS_CDC_VERSION_2_0) - ret = snd_soc_add_component_controls(component, - lpass_cdc_va_macro_snd_controls_v3, - ARRAY_SIZE(lpass_cdc_va_macro_snd_controls_v3)); - if (ret < 0) { - dev_err(va_dev, "%s: Failed to add snd_ctls\n", - __func__); - return ret; - } - } else { - ret = snd_soc_add_component_controls(component, - lpass_cdc_va_macro_snd_controls, - ARRAY_SIZE(lpass_cdc_va_macro_snd_controls)); - if (ret < 0) { - dev_err(va_dev, "%s: Failed to add snd_ctls\n", - __func__); - return ret; - } + + ret = snd_soc_add_component_controls(component, + lpass_cdc_va_macro_snd_controls, + ARRAY_SIZE(lpass_cdc_va_macro_snd_controls)); + if (ret < 0) { + dev_err(va_dev, "%s: Failed to add snd_ctls\n", + __func__); + return ret; } snd_soc_dapm_ignore_suspend(dapm, "VA_AIF1 Capture"); snd_soc_dapm_ignore_suspend(dapm, "VA_AIF2 Capture"); snd_soc_dapm_ignore_suspend(dapm, "VA_AIF3 Capture"); - if (va_priv->version >= LPASS_CDC_VERSION_2_0) { - snd_soc_dapm_ignore_suspend(dapm, "VA SWR_INPUT"); - } else { - snd_soc_dapm_ignore_suspend(dapm, "VA SWR_ADC0"); - snd_soc_dapm_ignore_suspend(dapm, "VA SWR_ADC1"); - snd_soc_dapm_ignore_suspend(dapm, "VA SWR_ADC2"); - snd_soc_dapm_ignore_suspend(dapm, "VA SWR_ADC3"); - snd_soc_dapm_ignore_suspend(dapm, "VA SWR_MIC0"); - snd_soc_dapm_ignore_suspend(dapm, "VA SWR_MIC1"); - snd_soc_dapm_ignore_suspend(dapm, "VA SWR_MIC2"); - snd_soc_dapm_ignore_suspend(dapm, "VA SWR_MIC3"); - snd_soc_dapm_ignore_suspend(dapm, "VA SWR_MIC4"); - snd_soc_dapm_ignore_suspend(dapm, "VA SWR_MIC5"); - snd_soc_dapm_ignore_suspend(dapm, "VA SWR_MIC6"); - snd_soc_dapm_ignore_suspend(dapm, "VA SWR_MIC7"); - } + snd_soc_dapm_ignore_suspend(dapm, "VA SWR_INPUT"); snd_soc_dapm_sync(dapm); for (i = 0; i < LPASS_CDC_VA_MACRO_NUM_DECIMATORS; i++) { @@ -2818,14 +2097,12 @@ static int lpass_cdc_va_macro_init(struct snd_soc_component *component) } va_priv->component = component; - if (va_priv->version == LPASS_CDC_VERSION_2_1) { - snd_soc_component_update_bits(component, - LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE, 0xCC); - snd_soc_component_update_bits(component, - LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE, 0xCC); - snd_soc_component_update_bits(component, - LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE, 0xCC); - } + snd_soc_component_update_bits(component, + LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE, 0xCC); + snd_soc_component_update_bits(component, + LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE, 0xCC); + snd_soc_component_update_bits(component, + LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE, 0xCC); return 0; } @@ -2996,17 +2273,11 @@ static int lpass_cdc_va_macro_reg_wake_irq(struct snd_soc_component *component, } static void lpass_cdc_va_macro_init_ops(struct macro_ops *ops, - char __iomem *va_io_base, - bool va_without_decimation) + char __iomem *va_io_base) { memset(ops, 0, sizeof(struct macro_ops)); - if (!va_without_decimation) { - ops->dai_ptr = lpass_cdc_va_macro_dai; - ops->num_dais = ARRAY_SIZE(lpass_cdc_va_macro_dai); - } else { - ops->dai_ptr = NULL; - ops->num_dais = 0; - } + ops->dai_ptr = lpass_cdc_va_macro_dai; + ops->num_dais = ARRAY_SIZE(lpass_cdc_va_macro_dai); ops->init = lpass_cdc_va_macro_init; ops->exit = lpass_cdc_va_macro_deinit; ops->io_base = va_io_base; @@ -3022,7 +2293,6 @@ static int lpass_cdc_va_macro_probe(struct platform_device *pdev) struct lpass_cdc_va_macro_priv *va_priv; u32 va_base_addr, sample_rate = 0; char __iomem *va_io_base; - bool va_without_decimation = false; const char *micb_supply_str = "va-vdd-micb-supply"; const char *micb_supply_str1 = "va-vdd-micb"; const char *micb_voltage_str = "qcom,va-vdd-micb-voltage"; @@ -3032,10 +2302,7 @@ static int lpass_cdc_va_macro_probe(struct platform_device *pdev) u32 default_clk_id = 0; struct clk *lpass_audio_hw_vote = NULL; u32 is_used_va_swr_gpio = 0; - u32 disable_afe_wakeup_event_listener = 0; const char *is_used_va_swr_gpio_dt = "qcom,is-used-swr-gpio"; - const char *disable_afe_wakeup_event_listener_dt = - "qcom,disable-afe-wakeup-event-listener"; va_priv = devm_kzalloc(&pdev->dev, sizeof(struct lpass_cdc_va_macro_priv), GFP_KERNEL); @@ -3050,10 +2317,7 @@ static int lpass_cdc_va_macro_probe(struct platform_device *pdev) __func__, "reg"); return ret; } - va_without_decimation = of_property_read_bool(pdev->dev.parent->of_node, - "qcom,va-without-decimation"); - va_priv->va_without_decimation = va_without_decimation; ret = of_property_read_u32(pdev->dev.of_node, dmic_sample_rate, &sample_rate); if (ret) { @@ -3079,18 +2343,6 @@ static int lpass_cdc_va_macro_probe(struct platform_device *pdev) } } - if (of_find_property(pdev->dev.of_node, - disable_afe_wakeup_event_listener_dt, NULL)) { - ret = of_property_read_u32(pdev->dev.of_node, - disable_afe_wakeup_event_listener_dt, - &disable_afe_wakeup_event_listener); - if (ret) - dev_dbg(&pdev->dev, "%s: error reading %s in dt\n", - __func__, disable_afe_wakeup_event_listener_dt); - } - va_priv->disable_afe_wakeup_event_listener = - disable_afe_wakeup_event_listener; - va_priv->va_swr_gpio_p = of_parse_phandle(pdev->dev.of_node, "qcom,va-swr-gpios", 0); if (!va_priv->va_swr_gpio_p && is_used_va_swr_gpio) { @@ -3181,7 +2433,7 @@ static int lpass_cdc_va_macro_probe(struct platform_device *pdev) mutex_init(&va_priv->mclk_lock); dev_set_drvdata(&pdev->dev, va_priv); - lpass_cdc_va_macro_init_ops(&ops, va_io_base, va_without_decimation); + lpass_cdc_va_macro_init_ops(&ops, va_io_base); ops.clk_id_req = va_priv->default_clk_id; ops.default_clk_id = va_priv->default_clk_id; ret = lpass_cdc_register_macro(&pdev->dev, VA_MACRO, &ops); diff --git a/asoc/codecs/lpass-cdc/lpass-cdc-wsa-macro.c b/asoc/codecs/lpass-cdc/lpass-cdc-wsa-macro.c index 140314ebc3..509c2df343 100644 --- a/asoc/codecs/lpass-cdc/lpass-cdc-wsa-macro.c +++ b/asoc/codecs/lpass-cdc/lpass-cdc-wsa-macro.c @@ -2791,30 +2791,8 @@ static void lpass_cdc_wsa_macro_init_bcl_pmic_reg(struct snd_soc_component *comp switch (wsa_priv->bcl_pmic_params.id) { case 0: - /* Enable ID0 to listen to respective PMIC group interrupts */ - snd_soc_component_update_bits(component, - LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1, 0x02, 0x02); - /* Update MC_SID0 */ - snd_soc_component_update_bits(component, - LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1, 0x0F, - wsa_priv->bcl_pmic_params.sid); - /* Update MC_PPID0 */ - snd_soc_component_update_bits(component, - LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2, 0xFF, - wsa_priv->bcl_pmic_params.ppid); break; case 1: - /* Enable ID1 to listen to respective PMIC group interrupts */ - snd_soc_component_update_bits(component, - LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1, 0x01, 0x01); - /* Update MC_SID1 */ - snd_soc_component_update_bits(component, - LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3, 0x0F, - wsa_priv->bcl_pmic_params.sid); - /* Update MC_PPID1 */ - snd_soc_component_update_bits(component, - LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4, 0xFF, - wsa_priv->bcl_pmic_params.ppid); break; default: dev_err(wsa_dev, "%s: PMIC ID is invalid %d\n", diff --git a/asoc/codecs/lpass-cdc/lpass-cdc.c b/asoc/codecs/lpass-cdc/lpass-cdc.c index 39fb0c1574..f3f322c2cb 100644 --- a/asoc/codecs/lpass-cdc/lpass-cdc.c +++ b/asoc/codecs/lpass-cdc/lpass-cdc.c @@ -108,30 +108,9 @@ static int __lpass_cdc_reg_read(struct lpass_cdc_priv *priv, goto ssr_err; } - if (priv->version < LPASS_CDC_VERSION_2_0) { - /* Request Clk before register access */ - ret = lpass_cdc_clk_rsc_request_clock(priv->macro_params[macro_id].dev, - priv->macro_params[macro_id].default_clk_id, - priv->macro_params[macro_id].clk_id_req, - true); - if (ret < 0) { - dev_err_ratelimited(priv->dev, - "%s: Failed to enable clock, ret:%d\n", - __func__, ret); - goto err; - } - } - lpass_cdc_ahb_read_device( priv->macro_params[macro_id].io_base, reg, val); - if (priv->version < LPASS_CDC_VERSION_2_0) - lpass_cdc_clk_rsc_request_clock(priv->macro_params[macro_id].dev, - priv->macro_params[macro_id].default_clk_id, - priv->macro_params[macro_id].clk_id_req, - false); - -err: if (priv->macro_params[VA_MACRO].dev) { pm_runtime_mark_last_busy(priv->macro_params[VA_MACRO].dev); pm_runtime_put_autosuspend(priv->macro_params[VA_MACRO].dev); @@ -159,30 +138,9 @@ static int __lpass_cdc_reg_write(struct lpass_cdc_priv *priv, goto ssr_err; } - if (priv->version < LPASS_CDC_VERSION_2_0) { - /* Request Clk before register access */ - ret = lpass_cdc_clk_rsc_request_clock(priv->macro_params[macro_id].dev, - priv->macro_params[macro_id].default_clk_id, - priv->macro_params[macro_id].clk_id_req, - true); - if (ret < 0) { - dev_err_ratelimited(priv->dev, - "%s: Failed to enable clock, ret:%d\n", - __func__, ret); - goto err; - } - } - lpass_cdc_ahb_write_device( priv->macro_params[macro_id].io_base, reg, val); - if (priv->version < LPASS_CDC_VERSION_2_0) - lpass_cdc_clk_rsc_request_clock(priv->macro_params[macro_id].dev, - priv->macro_params[macro_id].default_clk_id, - priv->macro_params[macro_id].clk_id_req, - false); - -err: if (priv->macro_params[VA_MACRO].dev) { pm_runtime_mark_last_busy(priv->macro_params[VA_MACRO].dev); pm_runtime_put_autosuspend(priv->macro_params[VA_MACRO].dev); @@ -694,11 +652,9 @@ int lpass_cdc_register_macro(struct device *dev, u16 macro_id, if (macro_id == TX_MACRO || macro_id == VA_MACRO) priv->macro_params[macro_id].clk_div_get = ops->clk_div_get; - if (priv->version == LPASS_CDC_VERSION_2_1) { - if (macro_id == VA_MACRO) - priv->macro_params[macro_id].reg_wake_irq = + if (macro_id == VA_MACRO) + priv->macro_params[macro_id].reg_wake_irq = ops->reg_wake_irq; - } priv->num_dais += ops->num_dais; priv->num_macros_registered++; priv->macros_supported[macro_id] = true; @@ -1047,15 +1003,9 @@ int lpass_cdc_register_wake_irq(struct snd_soc_component *component, return -EINVAL; } - if (priv->version == LPASS_CDC_VERSION_2_1) { - if (priv->macro_params[VA_MACRO].reg_wake_irq) - priv->macro_params[VA_MACRO].reg_wake_irq( - component, ipc_wakeup); - } else { - if (priv->macro_params[TX_MACRO].reg_wake_irq) - priv->macro_params[TX_MACRO].reg_wake_irq( - component, ipc_wakeup); - } + if (priv->macro_params[VA_MACRO].reg_wake_irq) + priv->macro_params[VA_MACRO].reg_wake_irq( + component, ipc_wakeup); return 0; } @@ -1314,10 +1264,6 @@ static int lpass_cdc_probe(struct platform_device *pdev) __func__, priv->num_macros, MAX_MACRO); return -EINVAL; } - priv->va_without_decimation = of_property_read_bool(pdev->dev.of_node, - "qcom,va-without-decimation"); - if (priv->va_without_decimation) - lpass_cdc_reg_access[VA_MACRO] = lpass_cdc_va_top_reg_access; ret = of_property_read_u32(pdev->dev.of_node, "qcom,lpass-cdc-version", &priv->version); @@ -1326,12 +1272,6 @@ static int lpass_cdc_probe(struct platform_device *pdev) __func__); ret = 0; } - if (priv->version == LPASS_CDC_VERSION_2_1) { - lpass_cdc_reg_access[TX_MACRO] = lpass_cdc_tx_reg_access_v2; - lpass_cdc_reg_access[VA_MACRO] = lpass_cdc_va_reg_access_v2; - } else if (priv->version == LPASS_CDC_VERSION_2_0) { - lpass_cdc_reg_access[VA_MACRO] = lpass_cdc_va_reg_access_v3; - } priv->dev = &pdev->dev; priv->dev_up = true; diff --git a/asoc/codecs/lpass-cdc/lpass-cdc.h b/asoc/codecs/lpass-cdc/lpass-cdc.h index c57b9d52c9..3254a06f31 100644 --- a/asoc/codecs/lpass-cdc/lpass-cdc.h +++ b/asoc/codecs/lpass-cdc/lpass-cdc.h @@ -20,6 +20,7 @@ enum { RX_MACRO, WSA_MACRO, VA_MACRO, + WSA2_MACRO, MAX_MACRO };