fw-api: Fix compilation issue for tx monitor

Fix compilation issue for tx monitor

Change-Id: I5debda461920820ea1d7fc48d313feb5f939b3b3
CRs-Fixed: 3185686

hw/qcn9224/ack_report.h

@@ -0,0 +1,94 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _ACK_REPORT_H_
+#define _ACK_REPORT_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_ACK_REPORT 1
+
+
+struct ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t selfgen_response_reason                                 :  4, // [3:0]
+                      ax_trigger_type                                         :  4, // [7:4]
+                      sr_ppdu                                                 :  1, // [8:8]
+                      reserved                                                :  7, // [15:9]
+                      frame_control                                           : 16; // [31:16]
+#else
+             uint32_t frame_control                                           : 16, // [31:16]
+                      reserved                                                :  7, // [15:9]
+                      sr_ppdu                                                 :  1, // [8:8]
+                      ax_trigger_type                                         :  4, // [7:4]
+                      selfgen_response_reason                                 :  4; // [3:0]
+#endif
+};
+
+
+
+
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET                                   0x00000000
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB                                      0
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB                                      3
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK                                     0x0000000f
+
+
+
+
+#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET                                           0x00000000
+#define ACK_REPORT_AX_TRIGGER_TYPE_LSB                                              4
+#define ACK_REPORT_AX_TRIGGER_TYPE_MSB                                              7
+#define ACK_REPORT_AX_TRIGGER_TYPE_MASK                                             0x000000f0
+
+
+
+
+#define ACK_REPORT_SR_PPDU_OFFSET                                                   0x00000000
+#define ACK_REPORT_SR_PPDU_LSB                                                      8
+#define ACK_REPORT_SR_PPDU_MSB                                                      8
+#define ACK_REPORT_SR_PPDU_MASK                                                     0x00000100
+
+
+
+
+#define ACK_REPORT_RESERVED_OFFSET                                                  0x00000000
+#define ACK_REPORT_RESERVED_LSB                                                     9
+#define ACK_REPORT_RESERVED_MSB                                                     15
+#define ACK_REPORT_RESERVED_MASK                                                    0x0000fe00
+
+
+
+
+#define ACK_REPORT_FRAME_CONTROL_OFFSET                                             0x00000000
+#define ACK_REPORT_FRAME_CONTROL_LSB                                                16
+#define ACK_REPORT_FRAME_CONTROL_MSB                                                31
+#define ACK_REPORT_FRAME_CONTROL_MASK                                               0xffff0000
+
+
+
+
+#endif

hw/qcn9224/eht_sig_usr_mu_mimo_info.h

@@ -0,0 +1,154 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_
+#define _EHT_SIG_USR_MU_MIMO_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2
+
+
+struct eht_sig_usr_mu_mimo_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11, // [10:0]
+                      sta_mcs                                                 :  4, // [14:11]
+                      sta_coding                                              :  1, // [15:15]
+                      sta_spatial_config                                      :  6, // [21:16]
+                      reserved_0a                                             :  1, // [22:22]
+                      rx_integrity_check_passed                               :  1, // [23:23]
+                      subband80_cc_mask                                       :  8; // [31:24]
+             uint32_t user_order_subband80_0                                  :  8, // [7:0]
+                      user_order_subband80_1                                  :  8, // [15:8]
+                      user_order_subband80_2                                  :  8, // [23:16]
+                      user_order_subband80_3                                  :  8; // [31:24]
+#else
+             uint32_t subband80_cc_mask                                       :  8, // [31:24]
+                      rx_integrity_check_passed                               :  1, // [23:23]
+                      reserved_0a                                             :  1, // [22:22]
+                      sta_spatial_config                                      :  6, // [21:16]
+                      sta_coding                                              :  1, // [15:15]
+                      sta_mcs                                                 :  4, // [14:11]
+                      sta_id                                                  : 11; // [10:0]
+             uint32_t user_order_subband80_3                                  :  8, // [31:24]
+                      user_order_subband80_2                                  :  8, // [23:16]
+                      user_order_subband80_1                                  :  8, // [15:8]
+                      user_order_subband80_0                                  :  8; // [7:0]
+#endif
+};
+
+
+
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET                                      0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB                                         0
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB                                         10
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK                                        0x000007ff
+
+
+
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET                                     0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB                                        11
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB                                        14
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK                                       0x00007800
+
+
+
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET                                  0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB                                     15
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB                                     15
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK                                    0x00008000
+
+
+
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET                          0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB                             16
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB                             21
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK                            0x003f0000
+
+
+
+
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET                                 0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB                                    22
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB                                    22
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK                                   0x00400000
+
+
+
+
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                   0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                      23
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                      23
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                     0x00800000
+
+
+
+
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET                           0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB                              24
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB                              31
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK                             0xff000000
+
+
+
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB                         0
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB                         7
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK                        0x000000ff
+
+
+
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB                         8
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB                         15
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK                        0x0000ff00
+
+
+
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB                         16
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB                         23
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK                        0x00ff0000
+
+
+
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB                         24
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB                         31
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK                        0xff000000
+
+
+
+
+#endif

hw/qcn9224/eht_sig_usr_ofdma_info.h

@@ -0,0 +1,174 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _EHT_SIG_USR_OFDMA_INFO_H_
+#define _EHT_SIG_USR_OFDMA_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2
+
+
+struct eht_sig_usr_ofdma_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11, // [10:0]
+                      sta_mcs                                                 :  4, // [14:11]
+                      validate_0a                                             :  1, // [15:15]
+                      nss                                                     :  4, // [19:16]
+                      txbf                                                    :  1, // [20:20]
+                      sta_coding                                              :  1, // [21:21]
+                      reserved_0b                                             :  1, // [22:22]
+                      rx_integrity_check_passed                               :  1, // [23:23]
+                      subband80_cc_mask                                       :  8; // [31:24]
+             uint32_t user_order_subband80_0                                  :  8, // [7:0]
+                      user_order_subband80_1                                  :  8, // [15:8]
+                      user_order_subband80_2                                  :  8, // [23:16]
+                      user_order_subband80_3                                  :  8; // [31:24]
+#else
+             uint32_t subband80_cc_mask                                       :  8, // [31:24]
+                      rx_integrity_check_passed                               :  1, // [23:23]
+                      reserved_0b                                             :  1, // [22:22]
+                      sta_coding                                              :  1, // [21:21]
+                      txbf                                                    :  1, // [20:20]
+                      nss                                                     :  4, // [19:16]
+                      validate_0a                                             :  1, // [15:15]
+                      sta_mcs                                                 :  4, // [14:11]
+                      sta_id                                                  : 11; // [10:0]
+             uint32_t user_order_subband80_3                                  :  8, // [31:24]
+                      user_order_subband80_2                                  :  8, // [23:16]
+                      user_order_subband80_1                                  :  8, // [15:8]
+                      user_order_subband80_0                                  :  8; // [7:0]
+#endif
+};
+
+
+
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET                                        0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB                                           0
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB                                           10
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK                                          0x000007ff
+
+
+
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET                                       0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB                                          11
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB                                          14
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK                                         0x00007800
+
+
+
+
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET                                   0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB                                      15
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB                                      15
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK                                     0x00008000
+
+
+
+
+#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET                                           0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB                                              16
+#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB                                              19
+#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK                                             0x000f0000
+
+
+
+
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET                                          0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB                                             20
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB                                             20
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK                                            0x00100000
+
+
+
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET                                    0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB                                       21
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB                                       21
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK                                      0x00200000
+
+
+
+
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET                                   0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB                                      22
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB                                      22
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK                                     0x00400000
+
+
+
+
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                     0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                        23
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                        23
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                       0x00800000
+
+
+
+
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET                             0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB                                24
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB                                31
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK                               0xff000000
+
+
+
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB                           0
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB                           7
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK                          0x000000ff
+
+
+
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB                           8
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB                           15
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK                          0x0000ff00
+
+
+
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB                           16
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB                           23
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK                          0x00ff0000
+
+
+
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB                           24
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB                           31
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK                          0xff000000
+
+
+
+
+#endif

hw/qcn9224/eht_sig_usr_su_info.h

@@ -0,0 +1,124 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _EHT_SIG_USR_SU_INFO_H_
+#define _EHT_SIG_USR_SU_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1
+
+
+struct eht_sig_usr_su_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11, // [10:0]
+                      sta_mcs                                                 :  4, // [14:11]
+                      validate_0a                                             :  1, // [15:15]
+                      nss                                                     :  4, // [19:16]
+                      txbf                                                    :  1, // [20:20]
+                      sta_coding                                              :  1, // [21:21]
+                      reserved_0b                                             :  9, // [30:22]
+                      rx_integrity_check_passed                               :  1; // [31:31]
+#else
+             uint32_t rx_integrity_check_passed                               :  1, // [31:31]
+                      reserved_0b                                             :  9, // [30:22]
+                      sta_coding                                              :  1, // [21:21]
+                      txbf                                                    :  1, // [20:20]
+                      nss                                                     :  4, // [19:16]
+                      validate_0a                                             :  1, // [15:15]
+                      sta_mcs                                                 :  4, // [14:11]
+                      sta_id                                                  : 11; // [10:0]
+#endif
+};
+
+
+
+
+#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET                                           0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_ID_LSB                                              0
+#define EHT_SIG_USR_SU_INFO_STA_ID_MSB                                              10
+#define EHT_SIG_USR_SU_INFO_STA_ID_MASK                                             0x000007ff
+
+
+
+
+#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET                                          0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB                                             11
+#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB                                             14
+#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK                                            0x00007800
+
+
+
+
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET                                      0x00000000
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB                                         15
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB                                         15
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK                                        0x00008000
+
+
+
+
+#define EHT_SIG_USR_SU_INFO_NSS_OFFSET                                              0x00000000
+#define EHT_SIG_USR_SU_INFO_NSS_LSB                                                 16
+#define EHT_SIG_USR_SU_INFO_NSS_MSB                                                 19
+#define EHT_SIG_USR_SU_INFO_NSS_MASK                                                0x000f0000
+
+
+
+
+#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET                                             0x00000000
+#define EHT_SIG_USR_SU_INFO_TXBF_LSB                                                20
+#define EHT_SIG_USR_SU_INFO_TXBF_MSB                                                20
+#define EHT_SIG_USR_SU_INFO_TXBF_MASK                                               0x00100000
+
+
+
+
+#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET                                       0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB                                          21
+#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB                                          21
+#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK                                         0x00200000
+
+
+
+
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET                                      0x00000000
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB                                         22
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB                                         30
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK                                        0x7fc00000
+
+
+
+
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                        0x00000000
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                           31
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                           31
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                          0x80000000
+
+
+
+
+#endif

hw/qcn9224/he_sig_a_mu_ul_info.h

@@ -0,0 +1,164 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _HE_SIG_A_MU_UL_INFO_H_
+#define _HE_SIG_A_MU_UL_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
+
+
+struct he_sig_a_mu_ul_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t format_indication                                       :  1, // [0:0]
+                      bss_color_id                                            :  6, // [6:1]
+                      spatial_reuse                                           : 16, // [22:7]
+                      reserved_0a                                             :  1, // [23:23]
+                      transmit_bw                                             :  2, // [25:24]
+                      reserved_0b                                             :  6; // [31:26]
+             uint32_t txop_duration                                           :  7, // [6:0]
+                      reserved_1a                                             :  9, // [15:7]
+                      crc                                                     :  4, // [19:16]
+                      tail                                                    :  6, // [25:20]
+                      reserved_1b                                             :  5, // [30:26]
+                      rx_integrity_check_passed                               :  1; // [31:31]
+#else
+             uint32_t reserved_0b                                             :  6, // [31:26]
+                      transmit_bw                                             :  2, // [25:24]
+                      reserved_0a                                             :  1, // [23:23]
+                      spatial_reuse                                           : 16, // [22:7]
+                      bss_color_id                                            :  6, // [6:1]
+                      format_indication                                       :  1; // [0:0]
+             uint32_t rx_integrity_check_passed                               :  1, // [31:31]
+                      reserved_1b                                             :  5, // [30:26]
+                      tail                                                    :  6, // [25:20]
+                      crc                                                     :  4, // [19:16]
+                      reserved_1a                                             :  9, // [15:7]
+                      txop_duration                                           :  7; // [6:0]
+#endif
+};
+
+
+
+
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET                                0x00000000
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB                                   0
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB                                   0
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK                                  0x00000001
+
+
+
+
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB                                        1
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB                                        6
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK                                       0x0000007e
+
+
+
+
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET                                    0x00000000
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB                                       7
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB                                       22
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK                                      0x007fff80
+
+
+
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB                                         23
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB                                         23
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK                                        0x00800000
+
+
+
+
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB                                         24
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB                                         25
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK                                        0x03000000
+
+
+
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB                                         26
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB                                         31
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK                                        0xfc000000
+
+
+
+
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET                                    0x00000004
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB                                       0
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB                                       6
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK                                      0x0000007f
+
+
+
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB                                         7
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB                                         15
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK                                        0x0000ff80
+
+
+
+
+#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET                                              0x00000004
+#define HE_SIG_A_MU_UL_INFO_CRC_LSB                                                 16
+#define HE_SIG_A_MU_UL_INFO_CRC_MSB                                                 19
+#define HE_SIG_A_MU_UL_INFO_CRC_MASK                                                0x000f0000
+
+
+
+
+#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET                                             0x00000004
+#define HE_SIG_A_MU_UL_INFO_TAIL_LSB                                                20
+#define HE_SIG_A_MU_UL_INFO_TAIL_MSB                                                25
+#define HE_SIG_A_MU_UL_INFO_TAIL_MASK                                               0x03f00000
+
+
+
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB                                         26
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB                                         30
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK                                        0x7c000000
+
+
+
+
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                        0x00000004
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                           31
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                           31
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                          0x80000000
+
+
+
+
+#endif

hw/qcn9224/no_ack_report.h

@@ -0,0 +1,174 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _NO_ACK_REPORT_H_
+#define _NO_ACK_REPORT_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_NO_ACK_REPORT 4
+
+
+struct no_ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t no_ack_transmit_reason                                  :  4, // [3:0]
+                      macrx_abort_reason                                      :  4, // [7:4]
+                      phyrx_abort_reason                                      :  8, // [15:8]
+                      frame_control                                           : 16; // [31:16]
+             uint32_t rx_ppdu_duration                                        : 24, // [23:0]
+                      sr_ppdu_during_obss                                     :  1, // [24:24]
+                      selfgen_response_reason_to_sr_ppdu                      :  4, // [28:25]
+                      reserved_1                                              :  3; // [31:29]
+             uint32_t pre_bt_broadcast_status_details                         : 12, // [11:0]
+                      first_bt_broadcast_status_details                       : 12, // [23:12]
+                      reserved_2                                              :  8; // [31:24]
+             uint32_t second_bt_broadcast_status_details                      : 12, // [11:0]
+                      reserved_3                                              : 20; // [31:12]
+#else
+             uint32_t frame_control                                           : 16, // [31:16]
+                      phyrx_abort_reason                                      :  8, // [15:8]
+                      macrx_abort_reason                                      :  4, // [7:4]
+                      no_ack_transmit_reason                                  :  4; // [3:0]
+             uint32_t reserved_1                                              :  3, // [31:29]
+                      selfgen_response_reason_to_sr_ppdu                      :  4, // [28:25]
+                      sr_ppdu_during_obss                                     :  1, // [24:24]
+                      rx_ppdu_duration                                        : 24; // [23:0]
+             uint32_t reserved_2                                              :  8, // [31:24]
+                      first_bt_broadcast_status_details                       : 12, // [23:12]
+                      pre_bt_broadcast_status_details                         : 12; // [11:0]
+             uint32_t reserved_3                                              : 20, // [31:12]
+                      second_bt_broadcast_status_details                      : 12; // [11:0]
+#endif
+};
+
+
+
+
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET                                 0x00000000
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB                                    0
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB                                    3
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK                                   0x0000000f
+
+
+
+
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET                                     0x00000000
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB                                        4
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB                                        7
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK                                       0x000000f0
+
+
+
+
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET                                     0x00000000
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB                                        8
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB                                        15
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK                                       0x0000ff00
+
+
+
+
+#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET                                          0x00000000
+#define NO_ACK_REPORT_FRAME_CONTROL_LSB                                             16
+#define NO_ACK_REPORT_FRAME_CONTROL_MSB                                             31
+#define NO_ACK_REPORT_FRAME_CONTROL_MASK                                            0xffff0000
+
+
+
+
+#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET                                       0x00000004
+#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB                                          0
+#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB                                          23
+#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK                                         0x00ffffff
+
+
+
+
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET                                    0x00000004
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB                                       24
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB                                       24
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK                                      0x01000000
+
+
+
+
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET                     0x00000004
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB                        25
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB                        28
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK                       0x1e000000
+
+
+
+
+#define NO_ACK_REPORT_RESERVED_1_OFFSET                                             0x00000004
+#define NO_ACK_REPORT_RESERVED_1_LSB                                                29
+#define NO_ACK_REPORT_RESERVED_1_MSB                                                31
+#define NO_ACK_REPORT_RESERVED_1_MASK                                               0xe0000000
+
+
+
+
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET                        0x00000008
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB                           0
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB                           11
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK                          0x00000fff
+
+
+
+
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET                      0x00000008
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB                         12
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB                         23
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK                        0x00fff000
+
+
+
+
+#define NO_ACK_REPORT_RESERVED_2_OFFSET                                             0x00000008
+#define NO_ACK_REPORT_RESERVED_2_LSB                                                24
+#define NO_ACK_REPORT_RESERVED_2_MSB                                                31
+#define NO_ACK_REPORT_RESERVED_2_MASK                                               0xff000000
+
+
+
+
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET                     0x0000000c
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB                        0
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB                        11
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK                       0x00000fff
+
+
+
+
+#define NO_ACK_REPORT_RESERVED_3_OFFSET                                             0x0000000c
+#define NO_ACK_REPORT_RESERVED_3_LSB                                                12
+#define NO_ACK_REPORT_RESERVED_3_MSB                                                31
+#define NO_ACK_REPORT_RESERVED_3_MASK                                               0xfffff000
+
+
+
+
+#endif

hw/qcn9224/pdg_response_rate_setting.h

@@ -0,0 +1,597 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _PDG_RESPONSE_RATE_SETTING_H_
+#define _PDG_RESPONSE_RATE_SETTING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "mlo_sta_id_details.h"
+#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7
+
+
+struct pdg_response_rate_setting {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             :  1, // [0:0]
+                      tx_antenna_sector_ctrl                                  : 24, // [24:1]
+                      pkt_type                                                :  4, // [28:25]
+                      smoothing                                               :  1, // [29:29]
+                      ldpc                                                    :  1, // [30:30]
+                      stbc                                                    :  1; // [31:31]
+             uint32_t alt_tx_pwr                                              :  8, // [7:0]
+                      alt_min_tx_pwr                                          :  8, // [15:8]
+                      alt_nss                                                 :  3, // [18:16]
+                      alt_tx_chain_mask                                       :  8, // [26:19]
+                      alt_bw                                                  :  3, // [29:27]
+                      stf_ltf_3db_boost                                       :  1, // [30:30]
+                      force_extra_symbol                                      :  1; // [31:31]
+             uint32_t alt_rate_mcs                                            :  4, // [3:0]
+                      nss                                                     :  3, // [6:4]
+                      dpd_enable                                              :  1, // [7:7]
+                      tx_pwr                                                  :  8, // [15:8]
+                      min_tx_pwr                                              :  8, // [23:16]
+                      tx_chain_mask                                           :  8; // [31:24]
+             uint32_t reserved_3a                                             :  8, // [7:0]
+                      sgi                                                     :  2, // [9:8]
+                      rate_mcs                                                :  4, // [13:10]
+                      reserved_3b                                             :  2, // [15:14]
+                      tx_pwr_1                                                :  8, // [23:16]
+                      alt_tx_pwr_1                                            :  8; // [31:24]
+             uint32_t aggregation                                             :  1, // [0:0]
+                      dot11ax_bss_color_id                                    :  6, // [6:1]
+                      dot11ax_spatial_reuse                                   :  4, // [10:7]
+                      dot11ax_cp_ltf_size                                     :  2, // [12:11]
+                      dot11ax_dcm                                             :  1, // [13:13]
+                      dot11ax_doppler_indication                              :  1, // [14:14]
+                      dot11ax_su_extended                                     :  1, // [15:15]
+                      dot11ax_min_packet_extension                            :  2, // [17:16]
+                      dot11ax_pe_nss                                          :  3, // [20:18]
+                      dot11ax_pe_content                                      :  1, // [21:21]
+                      dot11ax_pe_ltf_size                                     :  2, // [23:22]
+                      dot11ax_chain_csd_en                                    :  1, // [24:24]
+                      dot11ax_pe_chain_csd_en                                 :  1, // [25:25]
+                      dot11ax_dl_ul_flag                                      :  1, // [26:26]
+                      reserved_4a                                             :  5; // [31:27]
+             uint32_t dot11ax_ext_ru_start_index                              :  4, // [3:0]
+                      dot11ax_ext_ru_size                                     :  4, // [7:4]
+                      eht_duplicate_mode                                      :  2, // [9:8]
+                      he_sigb_dcm                                             :  1, // [10:10]
+                      he_sigb_0_mcs                                           :  3, // [13:11]
+                      num_he_sigb_sym                                         :  5, // [18:14]
+                      required_response_time_source                           :  1, // [19:19]
+                      reserved_5a                                             :  6, // [25:20]
+                      u_sig_puncture_pattern_encoding                         :  6; // [31:26]
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint16_t required_response_time                                  : 12, // [27:16]
+                      dot11be_params_placeholder                              :  4; // [31:28]
+#else
+             uint32_t stbc                                                    :  1, // [31:31]
+                      ldpc                                                    :  1, // [30:30]
+                      smoothing                                               :  1, // [29:29]
+                      pkt_type                                                :  4, // [28:25]
+                      tx_antenna_sector_ctrl                                  : 24, // [24:1]
+                      reserved_0a                                             :  1; // [0:0]
+             uint32_t force_extra_symbol                                      :  1, // [31:31]
+                      stf_ltf_3db_boost                                       :  1, // [30:30]
+                      alt_bw                                                  :  3, // [29:27]
+                      alt_tx_chain_mask                                       :  8, // [26:19]
+                      alt_nss                                                 :  3, // [18:16]
+                      alt_min_tx_pwr                                          :  8, // [15:8]
+                      alt_tx_pwr                                              :  8; // [7:0]
+             uint32_t tx_chain_mask                                           :  8, // [31:24]
+                      min_tx_pwr                                              :  8, // [23:16]
+                      tx_pwr                                                  :  8, // [15:8]
+                      dpd_enable                                              :  1, // [7:7]
+                      nss                                                     :  3, // [6:4]
+                      alt_rate_mcs                                            :  4; // [3:0]
+             uint32_t alt_tx_pwr_1                                            :  8, // [31:24]
+                      tx_pwr_1                                                :  8, // [23:16]
+                      reserved_3b                                             :  2, // [15:14]
+                      rate_mcs                                                :  4, // [13:10]
+                      sgi                                                     :  2, // [9:8]
+                      reserved_3a                                             :  8; // [7:0]
+             uint32_t reserved_4a                                             :  5, // [31:27]
+                      dot11ax_dl_ul_flag                                      :  1, // [26:26]
+                      dot11ax_pe_chain_csd_en                                 :  1, // [25:25]
+                      dot11ax_chain_csd_en                                    :  1, // [24:24]
+                      dot11ax_pe_ltf_size                                     :  2, // [23:22]
+                      dot11ax_pe_content                                      :  1, // [21:21]
+                      dot11ax_pe_nss                                          :  3, // [20:18]
+                      dot11ax_min_packet_extension                            :  2, // [17:16]
+                      dot11ax_su_extended                                     :  1, // [15:15]
+                      dot11ax_doppler_indication                              :  1, // [14:14]
+                      dot11ax_dcm                                             :  1, // [13:13]
+                      dot11ax_cp_ltf_size                                     :  2, // [12:11]
+                      dot11ax_spatial_reuse                                   :  4, // [10:7]
+                      dot11ax_bss_color_id                                    :  6, // [6:1]
+                      aggregation                                             :  1; // [0:0]
+             uint32_t u_sig_puncture_pattern_encoding                         :  6, // [31:26]
+                      reserved_5a                                             :  6, // [25:20]
+                      required_response_time_source                           :  1, // [19:19]
+                      num_he_sigb_sym                                         :  5, // [18:14]
+                      he_sigb_0_mcs                                           :  3, // [13:11]
+                      he_sigb_dcm                                             :  1, // [10:10]
+                      eht_duplicate_mode                                      :  2, // [9:8]
+                      dot11ax_ext_ru_size                                     :  4, // [7:4]
+                      dot11ax_ext_ru_start_index                              :  4; // [3:0]
+             uint32_t dot11be_params_placeholder                              :  4, // [31:28]
+                      required_response_time                                  : 12; // [27:16]
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+#endif
+};
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET                                0x00000000
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK                                  0x00000001
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET                     0x00000000
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB                        1
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB                        24
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK                       0x01fffffe
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET                                   0x00000000
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB                                      25
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB                                      28
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK                                     0x1e000000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET                                  0x00000000
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB                                     29
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB                                     29
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK                                    0x20000000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET                                       0x00000000
+#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB                                          30
+#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB                                          30
+#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK                                         0x40000000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET                                       0x00000000
+#define PDG_RESPONSE_RATE_SETTING_STBC_LSB                                          31
+#define PDG_RESPONSE_RATE_SETTING_STBC_MSB                                          31
+#define PDG_RESPONSE_RATE_SETTING_STBC_MASK                                         0x80000000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET                                 0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB                                    0
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB                                    7
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK                                   0x000000ff
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET                             0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB                                8
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB                                15
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK                               0x0000ff00
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET                                    0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB                                       16
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB                                       18
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK                                      0x00070000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET                          0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB                             19
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB                             26
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK                            0x07f80000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET                                     0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB                                        27
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB                                        29
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK                                       0x38000000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET                          0x00000004
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB                             30
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB                             30
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK                            0x40000000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET                         0x00000004
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB                            31
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB                            31
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK                           0x80000000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET                               0x00000008
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB                                  0
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB                                  3
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK                                 0x0000000f
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET                                        0x00000008
+#define PDG_RESPONSE_RATE_SETTING_NSS_LSB                                           4
+#define PDG_RESPONSE_RATE_SETTING_NSS_MSB                                           6
+#define PDG_RESPONSE_RATE_SETTING_NSS_MASK                                          0x00000070
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET                                 0x00000008
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB                                    7
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB                                    7
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK                                   0x00000080
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET                                     0x00000008
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB                                        8
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB                                        15
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK                                       0x0000ff00
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET                                 0x00000008
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB                                    16
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB                                    23
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK                                   0x00ff0000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET                              0x00000008
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB                                 24
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB                                 31
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK                                0xff000000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET                                0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB                                   7
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK                                  0x000000ff
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET                                        0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_SGI_LSB                                           8
+#define PDG_RESPONSE_RATE_SETTING_SGI_MSB                                           9
+#define PDG_RESPONSE_RATE_SETTING_SGI_MASK                                          0x00000300
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET                                   0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB                                      10
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB                                      13
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK                                     0x00003c00
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET                                0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB                                   14
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB                                   15
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK                                  0x0000c000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET                                   0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB                                      16
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB                                      23
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK                                     0x00ff0000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET                               0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB                                  24
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB                                  31
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK                                 0xff000000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET                                0x00000010
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK                                  0x00000001
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET                       0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB                          1
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB                          6
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK                         0x0000007e
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET                      0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB                         7
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB                         10
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK                        0x00000780
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET                        0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB                           11
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB                           12
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK                          0x00001800
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET                                0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB                                   13
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB                                   13
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK                                  0x00002000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET                 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB                    14
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB                    14
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK                   0x00004000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET                        0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB                           15
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB                           15
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK                          0x00008000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET               0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB                  16
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB                  17
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK                 0x00030000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET                             0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB                                18
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB                                20
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK                               0x001c0000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET                         0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB                            21
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB                            21
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK                           0x00200000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET                        0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB                           22
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB                           23
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK                          0x00c00000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET                       0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB                          24
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB                          24
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK                         0x01000000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET                    0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB                       25
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB                       25
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK                      0x02000000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET                         0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB                            26
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB                            26
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK                           0x04000000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET                                0x00000010
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB                                   27
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB                                   31
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK                                  0xf8000000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET                 0x00000014
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB                    0
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB                    3
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK                   0x0000000f
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET                        0x00000014
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB                           4
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB                           7
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK                          0x000000f0
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET                         0x00000014
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB                            8
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB                            9
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK                           0x00000300
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET                                0x00000014
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB                                   10
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB                                   10
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK                                  0x00000400
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET                              0x00000014
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB                                 11
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB                                 13
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK                                0x00003800
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET                            0x00000014
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB                               14
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB                               18
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK                              0x0007c000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET              0x00000014
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB                 19
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB                 19
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK                0x00080000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET                                0x00000014
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB                                   20
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB                                   25
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK                                  0x03f00000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET            0x00000014
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB               26
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB               31
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK              0xfc000000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET      0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB         0
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB         9
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK        0x000003ff
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET   0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB      10
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB      10
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK     0x00000400
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB   11
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB   11
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK  0x00000800
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB   12
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB   12
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK  0x00001000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET          0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB             13
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB             15
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK            0x0000e000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET                     0x00000018
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB                        16
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB                        27
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK                       0x0fff0000
+
+
+
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET                 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB                    28
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB                    31
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK                   0xf0000000
+
+
+
+
+#endif

hw/qcn9224/phytx_abort_request_info.h

@@ -0,0 +1,74 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _PHYTX_ABORT_REQUEST_INFO_H_
+#define _PHYTX_ABORT_REQUEST_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1
+
+
+struct phytx_abort_request_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t phytx_abort_reason                                      :  8, // [7:0]
+                      user_number                                             :  6, // [13:8]
+                      reserved                                                :  2; // [15:14]
+#else
+             uint16_t reserved                                                :  2, // [15:14]
+                      user_number                                             :  6, // [13:8]
+                      phytx_abort_reason                                      :  8; // [7:0]
+#endif
+};
+
+
+
+
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET                          0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB                             0
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB                             7
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK                            0x000000ff
+
+
+
+
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET                                 0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB                                    8
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB                                    13
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK                                   0x00003f00
+
+
+
+
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET                                    0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB                                       14
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB                                       15
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK                                      0x0000c000
+
+
+
+
+#endif

hw/qcn9224/received_response_user_info.h

@@ -0,0 +1,314 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _RECEIVED_RESPONSE_USER_INFO_H_
+#define _RECEIVED_RESPONSE_USER_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8
+
+
+struct received_response_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mpdu_fcs_pass_count                                     : 12, // [11:0]
+                      mpdu_fcs_fail_count                                     : 12, // [23:12]
+                      qosnull_frame_count                                     :  4, // [27:24]
+                      reserved_0a                                             :  3, // [30:28]
+                      user_info_valid                                         :  1; // [31:31]
+             uint32_t null_delimiter_count                                    : 22, // [21:0]
+                      reserved_1a                                             :  9, // [30:22]
+                      ht_control_valid                                        :  1; // [31:31]
+             uint32_t ht_control                                              : 32; // [31:0]
+             uint32_t qos_control_valid                                       : 16, // [15:0]
+                      eosp                                                    : 16; // [31:16]
+             uint32_t qos_control_15_8_tid_0                                  :  8, // [7:0]
+                      qos_control_15_8_tid_1                                  :  8, // [15:8]
+                      qos_control_15_8_tid_2                                  :  8, // [23:16]
+                      qos_control_15_8_tid_3                                  :  8; // [31:24]
+             uint32_t qos_control_15_8_tid_4                                  :  8, // [7:0]
+                      qos_control_15_8_tid_5                                  :  8, // [15:8]
+                      qos_control_15_8_tid_6                                  :  8, // [23:16]
+                      qos_control_15_8_tid_7                                  :  8; // [31:24]
+             uint32_t qos_control_15_8_tid_8                                  :  8, // [7:0]
+                      qos_control_15_8_tid_9                                  :  8, // [15:8]
+                      qos_control_15_8_tid_10                                 :  8, // [23:16]
+                      qos_control_15_8_tid_11                                 :  8; // [31:24]
+             uint32_t qos_control_15_8_tid_12                                 :  8, // [7:0]
+                      qos_control_15_8_tid_13                                 :  8, // [15:8]
+                      qos_control_15_8_tid_14                                 :  8, // [23:16]
+                      qos_control_15_8_tid_15                                 :  8; // [31:24]
+#else
+             uint32_t user_info_valid                                         :  1, // [31:31]
+                      reserved_0a                                             :  3, // [30:28]
+                      qosnull_frame_count                                     :  4, // [27:24]
+                      mpdu_fcs_fail_count                                     : 12, // [23:12]
+                      mpdu_fcs_pass_count                                     : 12; // [11:0]
+             uint32_t ht_control_valid                                        :  1, // [31:31]
+                      reserved_1a                                             :  9, // [30:22]
+                      null_delimiter_count                                    : 22; // [21:0]
+             uint32_t ht_control                                              : 32; // [31:0]
+             uint32_t eosp                                                    : 16, // [31:16]
+                      qos_control_valid                                       : 16; // [15:0]
+             uint32_t qos_control_15_8_tid_3                                  :  8, // [31:24]
+                      qos_control_15_8_tid_2                                  :  8, // [23:16]
+                      qos_control_15_8_tid_1                                  :  8, // [15:8]
+                      qos_control_15_8_tid_0                                  :  8; // [7:0]
+             uint32_t qos_control_15_8_tid_7                                  :  8, // [31:24]
+                      qos_control_15_8_tid_6                                  :  8, // [23:16]
+                      qos_control_15_8_tid_5                                  :  8, // [15:8]
+                      qos_control_15_8_tid_4                                  :  8; // [7:0]
+             uint32_t qos_control_15_8_tid_11                                 :  8, // [31:24]
+                      qos_control_15_8_tid_10                                 :  8, // [23:16]
+                      qos_control_15_8_tid_9                                  :  8, // [15:8]
+                      qos_control_15_8_tid_8                                  :  8; // [7:0]
+             uint32_t qos_control_15_8_tid_15                                 :  8, // [31:24]
+                      qos_control_15_8_tid_14                                 :  8, // [23:16]
+                      qos_control_15_8_tid_13                                 :  8, // [15:8]
+                      qos_control_15_8_tid_12                                 :  8; // [7:0]
+#endif
+};
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET                      0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB                         0
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB                         11
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK                        0x00000fff
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET                      0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB                         12
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB                         23
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK                        0x00fff000
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET                      0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB                         24
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB                         27
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK                        0x0f000000
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET                              0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB                                 28
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB                                 30
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK                                0x70000000
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET                          0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB                             31
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB                             31
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK                            0x80000000
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET                     0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB                        0
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB                        21
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK                       0x003fffff
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET                              0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB                                 22
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB                                 30
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK                                0x7fc00000
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET                         0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB                            31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB                            31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK                           0x80000000
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET                               0x00000008
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB                                  0
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB                                  31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK                                 0xffffffff
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET                        0x0000000c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB                           0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB                           15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK                          0x0000ffff
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET                                     0x0000000c
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB                                        16
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB                                        31
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK                                       0xffff0000
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB                      0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB                      7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK                     0x000000ff
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB                      8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB                      15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK                     0x0000ff00
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB                      16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB                      23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK                     0x00ff0000
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB                      24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB                      31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK                     0xff000000
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB                      0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB                      7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK                     0x000000ff
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB                      8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB                      15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK                     0x0000ff00
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB                      16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB                      23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK                     0x00ff0000
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB                      24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB                      31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK                     0xff000000
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET                   0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB                      0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB                      7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK                     0x000000ff
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET                   0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB                      8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB                      15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK                     0x0000ff00
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET                  0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB                     16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB                     23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK                    0x00ff0000
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET                  0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB                     24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB                     31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK                    0xff000000
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB                     0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB                     7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK                    0x000000ff
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB                     8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB                     15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK                    0x0000ff00
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB                     16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB                     23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK                    0x00ff0000
+
+
+
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB                     24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB                     31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK                    0xff000000
+
+
+
+
+#endif

hw/qcn9224/received_trigger_info_details.h

@@ -0,0 +1,214 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_
+#define _RECEIVED_TRIGGER_INFO_DETAILS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5
+
+
+struct received_trigger_info_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t trigger_type                                            :  4, // [3:0]
+                      ax_trigger_source                                       :  1, // [4:4]
+                      ax_trigger_type                                         :  4, // [8:5]
+                      trigger_source_sta_full_aid                             : 13, // [21:9]
+                      frame_control_valid                                     :  1, // [22:22]
+                      qos_control_valid                                       :  1, // [23:23]
+                      he_control_info_valid                                   :  1, // [24:24]
+                      ranging_trigger_subtype                                 :  4, // [28:25]
+                      reserved_0b                                             :  3; // [31:29]
+             uint32_t phy_ppdu_id                                             : 16, // [15:0]
+                      lsig_response_length                                    : 12, // [27:16]
+                      reserved_1a                                             :  4; // [31:28]
+             uint32_t frame_control                                           : 16, // [15:0]
+                      qos_control                                             : 16; // [31:16]
+             uint32_t sw_peer_id                                              : 16, // [15:0]
+                      reserved_3a                                             : 16; // [31:16]
+             uint32_t he_control                                              : 32; // [31:0]
+#else
+             uint32_t reserved_0b                                             :  3, // [31:29]
+                      ranging_trigger_subtype                                 :  4, // [28:25]
+                      he_control_info_valid                                   :  1, // [24:24]
+                      qos_control_valid                                       :  1, // [23:23]
+                      frame_control_valid                                     :  1, // [22:22]
+                      trigger_source_sta_full_aid                             : 13, // [21:9]
+                      ax_trigger_type                                         :  4, // [8:5]
+                      ax_trigger_source                                       :  1, // [4:4]
+                      trigger_type                                            :  4; // [3:0]
+             uint32_t reserved_1a                                             :  4, // [31:28]
+                      lsig_response_length                                    : 12, // [27:16]
+                      phy_ppdu_id                                             : 16; // [15:0]
+             uint32_t qos_control                                             : 16, // [31:16]
+                      frame_control                                           : 16; // [15:0]
+             uint32_t reserved_3a                                             : 16, // [31:16]
+                      sw_peer_id                                              : 16; // [15:0]
+             uint32_t he_control                                              : 32; // [31:0]
+#endif
+};
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET                           0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB                              0
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB                              3
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK                             0x0000000f
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET                      0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB                         4
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB                         4
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK                        0x00000010
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET                        0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB                           5
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB                           8
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK                          0x000001e0
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET            0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB               9
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB               21
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK              0x003ffe00
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET                    0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB                       22
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB                       22
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK                      0x00400000
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET                      0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB                         23
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB                         23
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK                        0x00800000
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET                  0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB                     24
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB                     24
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK                    0x01000000
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET                0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB                   25
+#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB                   28
+#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK                  0x1e000000
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_OFFSET                            0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_LSB                               29
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MASK                              0xe0000000
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET                            0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB                               0
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB                               15
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK                              0x0000ffff
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET                   0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB                      16
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB                      27
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK                     0x0fff0000
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET                            0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB                               28
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK                              0xf0000000
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET                          0x00000008
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB                             0
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB                             15
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK                            0x0000ffff
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET                            0x00000008
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB                               16
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK                              0xffff0000
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET                             0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB                                0
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB                                15
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK                               0x0000ffff
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET                            0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB                               16
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK                              0xffff0000
+
+
+
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET                             0x00000010
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB                                0
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB                                31
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK                               0xffffffff
+
+
+
+
+#endif

hw/qcn9224/ru_allocation_160_info.h

@@ -0,0 +1,183 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _RU_ALLOCATION_160_INFO_H_
+#define _RU_ALLOCATION_160_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4
+
+
+struct ru_allocation_160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ru_allocation_band0_0                                   :  9, // [8:0]
+                      ru_allocation_band0_1                                   :  9, // [17:9]
+                      reserved_0a                                             :  6, // [23:18]
+                      ru_allocations_01_subband80_mask                        :  4, // [27:24]
+                      ru_allocations_23_subband80_mask                        :  4; // [31:28]
+             uint32_t ru_allocation_band0_2                                   :  9, // [8:0]
+                      ru_allocation_band0_3                                   :  9, // [17:9]
+                      reserved_1a                                             : 14; // [31:18]
+             uint32_t ru_allocation_band1_0                                   :  9, // [8:0]
+                      ru_allocation_band1_1                                   :  9, // [17:9]
+                      reserved_2a                                             : 14; // [31:18]
+             uint32_t ru_allocation_band1_2                                   :  9, // [8:0]
+                      ru_allocation_band1_3                                   :  9, // [17:9]
+                      reserved_3a                                             : 14; // [31:18]
+#else
+             uint32_t ru_allocations_23_subband80_mask                        :  4, // [31:28]
+                      ru_allocations_01_subband80_mask                        :  4, // [27:24]
+                      reserved_0a                                             :  6, // [23:18]
+                      ru_allocation_band0_1                                   :  9, // [17:9]
+                      ru_allocation_band0_0                                   :  9; // [8:0]
+             uint32_t reserved_1a                                             : 14, // [31:18]
+                      ru_allocation_band0_3                                   :  9, // [17:9]
+                      ru_allocation_band0_2                                   :  9; // [8:0]
+             uint32_t reserved_2a                                             : 14, // [31:18]
+                      ru_allocation_band1_1                                   :  9, // [17:9]
+                      ru_allocation_band1_0                                   :  9; // [8:0]
+             uint32_t reserved_3a                                             : 14, // [31:18]
+                      ru_allocation_band1_3                                   :  9, // [17:9]
+                      ru_allocation_band1_2                                   :  9; // [8:0]
+#endif
+};
+
+
+
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET                         0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK                           0x000001ff
+
+
+
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET                         0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK                           0x0003fe00
+
+
+
+
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET                                   0x00000000
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB                                      23
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK                                     0x00fc0000
+
+
+
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET              0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB                 24
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB                 27
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK                0x0f000000
+
+
+
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET              0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB                 28
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB                 31
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK                0xf0000000
+
+
+
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET                         0x00000004
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK                           0x000001ff
+
+
+
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET                         0x00000004
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK                           0x0003fe00
+
+
+
+
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET                                   0x00000004
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB                                      31
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK                                     0xfffc0000
+
+
+
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET                         0x00000008
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK                           0x000001ff
+
+
+
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET                         0x00000008
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK                           0x0003fe00
+
+
+
+
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET                                   0x00000008
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB                                      31
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK                                     0xfffc0000
+
+
+
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET                         0x0000000c
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK                           0x000001ff
+
+
+
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET                         0x0000000c
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK                           0x0003fe00
+
+
+
+
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET                                   0x0000000c
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB                                      31
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK                                     0xfffc0000
+
+
+
+#endif

hw/qcn9224/service_info.h

@@ -0,0 +1,84 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _SERVICE_INFO_H_
+#define _SERVICE_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_SERVICE_INFO 1
+
+
+struct service_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t scrambler_seed                                          :  7, // [6:0]
+                      reserved                                                :  1, // [7:7]
+                      sig_b_crc_user                                          :  8, // [15:8]
+                      reserved_1                                              : 16; // [31:16]
+#else
+             uint32_t reserved_1                                              : 16, // [31:16]
+                      sig_b_crc_user                                          :  8, // [15:8]
+                      reserved                                                :  1, // [7:7]
+                      scrambler_seed                                          :  7; // [6:0]
+#endif
+};
+
+
+
+
+#define SERVICE_INFO_SCRAMBLER_SEED_OFFSET                                          0x00000000
+#define SERVICE_INFO_SCRAMBLER_SEED_LSB                                             0
+#define SERVICE_INFO_SCRAMBLER_SEED_MSB                                             6
+#define SERVICE_INFO_SCRAMBLER_SEED_MASK                                            0x0000007f
+
+
+
+
+#define SERVICE_INFO_RESERVED_OFFSET                                                0x00000000
+#define SERVICE_INFO_RESERVED_LSB                                                   7
+#define SERVICE_INFO_RESERVED_MSB                                                   7
+#define SERVICE_INFO_RESERVED_MASK                                                  0x00000080
+
+
+
+
+#define SERVICE_INFO_SIG_B_CRC_USER_OFFSET                                          0x00000000
+#define SERVICE_INFO_SIG_B_CRC_USER_LSB                                             8
+#define SERVICE_INFO_SIG_B_CRC_USER_MSB                                             15
+#define SERVICE_INFO_SIG_B_CRC_USER_MASK                                            0x0000ff00
+
+
+
+
+#define SERVICE_INFO_RESERVED_1_OFFSET                                              0x00000000
+#define SERVICE_INFO_RESERVED_1_LSB                                                 16
+#define SERVICE_INFO_RESERVED_1_MSB                                                 31
+#define SERVICE_INFO_RESERVED_1_MASK                                                0xffff0000
+
+
+
+
+#endif

hw/qcn9224/txpcu_buffer_basics.h

@@ -0,0 +1,74 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _TXPCU_BUFFER_BASICS_H_
+#define _TXPCU_BUFFER_BASICS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1
+
+
+struct txpcu_buffer_basics {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t available_memory                                        :  8, // [7:0]
+                      partial_tx_data_tlv_count                               :  8, // [15:8]
+                      tx_data_tlv_count                                       : 16; // [31:16]
+#else
+             uint32_t tx_data_tlv_count                                       : 16, // [31:16]
+                      partial_tx_data_tlv_count                               :  8, // [15:8]
+                      available_memory                                        :  8; // [7:0]
+#endif
+};
+
+
+
+
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET                                 0x00000000
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB                                    0
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB                                    7
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK                                   0x000000ff
+
+
+
+
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET                        0x00000000
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB                           8
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB                           15
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK                          0x0000ff00
+
+
+
+
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET                                0x00000000
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB                                   16
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB                                   31
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK                                  0xffff0000
+
+
+
+
+#endif

hw/qcn9224/u_sig_eht_su_mu_info.h

@@ -0,0 +1,244 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _U_SIG_EHT_SU_MU_INFO_H_
+#define _U_SIG_EHT_SU_MU_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2
+
+
+struct u_sig_eht_su_mu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_version                                             :  3, // [2:0]
+                      transmit_bw                                             :  3, // [5:3]
+                      dl_ul_flag                                              :  1, // [6:6]
+                      bss_color_id                                            :  6, // [12:7]
+                      txop_duration                                           :  7, // [19:13]
+                      disregard_0a                                            :  5, // [24:20]
+                      validate_0b                                             :  1, // [25:25]
+                      reserved_0c                                             :  6; // [31:26]
+             uint32_t eht_ppdu_sig_cmn_type                                   :  2, // [1:0]
+                      validate_1a                                             :  1, // [2:2]
+                      punctured_channel_information                           :  5, // [7:3]
+                      validate_1b                                             :  1, // [8:8]
+                      mcs_of_eht_sig                                          :  2, // [10:9]
+                      num_eht_sig_symbols                                     :  5, // [15:11]
+                      crc                                                     :  4, // [19:16]
+                      tail                                                    :  6, // [25:20]
+                      dot11ax_su_extended                                     :  1, // [26:26]
+                      reserved_1d                                             :  3, // [29:27]
+                      rx_ndp                                                  :  1, // [30:30]
+                      rx_integrity_check_passed                               :  1; // [31:31]
+#else
+             uint32_t reserved_0c                                             :  6, // [31:26]
+                      validate_0b                                             :  1, // [25:25]
+                      disregard_0a                                            :  5, // [24:20]
+                      txop_duration                                           :  7, // [19:13]
+                      bss_color_id                                            :  6, // [12:7]
+                      dl_ul_flag                                              :  1, // [6:6]
+                      transmit_bw                                             :  3, // [5:3]
+                      phy_version                                             :  3; // [2:0]
+             uint32_t rx_integrity_check_passed                               :  1, // [31:31]
+                      rx_ndp                                                  :  1, // [30:30]
+                      reserved_1d                                             :  3, // [29:27]
+                      dot11ax_su_extended                                     :  1, // [26:26]
+                      tail                                                    :  6, // [25:20]
+                      crc                                                     :  4, // [19:16]
+                      num_eht_sig_symbols                                     :  5, // [15:11]
+                      mcs_of_eht_sig                                          :  2, // [10:9]
+                      validate_1b                                             :  1, // [8:8]
+                      punctured_channel_information                           :  5, // [7:3]
+                      validate_1a                                             :  1, // [2:2]
+                      eht_ppdu_sig_cmn_type                                   :  2; // [1:0]
+#endif
+};
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB                                        0
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB                                        2
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK                                       0x00000007
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB                                        3
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB                                        5
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK                                       0x00000038
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET                                      0x00000000
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB                                         6
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB                                         6
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK                                        0x00000040
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET                                    0x00000000
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB                                       7
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB                                       12
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK                                      0x00001f80
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET                                   0x00000000
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB                                      13
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB                                      19
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK                                     0x000fe000
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET                                    0x00000000
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB                                       20
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB                                       24
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK                                      0x01f00000
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB                                        25
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB                                        25
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK                                       0x02000000
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB                                        26
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB                                        31
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK                                       0xfc000000
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET                           0x00000004
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB                              0
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB                              1
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK                             0x00000003
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET                                     0x00000004
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB                                        2
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB                                        2
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK                                       0x00000004
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET                   0x00000004
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB                      3
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB                      7
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK                     0x000000f8
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET                                     0x00000004
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB                                        8
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB                                        8
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK                                       0x00000100
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET                                  0x00000004
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB                                     9
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB                                     10
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK                                    0x00000600
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET                             0x00000004
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB                                11
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB                                15
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK                               0x0000f800
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET                                             0x00000004
+#define U_SIG_EHT_SU_MU_INFO_CRC_LSB                                                16
+#define U_SIG_EHT_SU_MU_INFO_CRC_MSB                                                19
+#define U_SIG_EHT_SU_MU_INFO_CRC_MASK                                               0x000f0000
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET                                            0x00000004
+#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB                                               20
+#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB                                               25
+#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK                                              0x03f00000
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET                             0x00000004
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB                                26
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB                                26
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK                               0x04000000
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET                                     0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB                                        27
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB                                        29
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK                                       0x38000000
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET                                          0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB                                             30
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB                                             30
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK                                            0x40000000
+
+
+
+
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                       0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                          31
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                          31
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                         0x80000000
+
+
+
+
+#endif

hw/qcn9224/u_sig_eht_tb_info.h

@@ -0,0 +1,192 @@
+
+/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _U_SIG_EHT_TB_INFO_H_
+#define _U_SIG_EHT_TB_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2
+
+
+struct u_sig_eht_tb_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_version                                             :  3, // [2:0]
+                      transmit_bw                                             :  3, // [5:3]
+                      dl_ul_flag                                              :  1, // [6:6]
+                      bss_color_id                                            :  6, // [12:7]
+                      txop_duration                                           :  7, // [19:13]
+                      disregard_0a                                            :  6, // [25:20]
+                      reserved_0c                                             :  6; // [31:26]
+             uint32_t eht_ppdu_sig_cmn_type                                   :  2, // [1:0]
+                      validate_1a                                             :  1, // [2:2]
+                      spatial_reuse                                           :  8, // [10:3]
+                      disregard_1b                                            :  5, // [15:11]
+                      crc                                                     :  4, // [19:16]
+                      tail                                                    :  6, // [25:20]
+                      reserved_1c                                             :  5, // [30:26]
+                      rx_integrity_check_passed                               :  1; // [31:31]
+#else
+             uint32_t reserved_0c                                             :  6, // [31:26]
+                      disregard_0a                                            :  6, // [25:20]
+                      txop_duration                                           :  7, // [19:13]
+                      bss_color_id                                            :  6, // [12:7]
+                      dl_ul_flag                                              :  1, // [6:6]
+                      transmit_bw                                             :  3, // [5:3]
+                      phy_version                                             :  3; // [2:0]
+             uint32_t rx_integrity_check_passed                               :  1, // [31:31]
+                      reserved_1c                                             :  5, // [30:26]
+                      tail                                                    :  6, // [25:20]
+                      crc                                                     :  4, // [19:16]
+                      disregard_1b                                            :  5, // [15:11]
+                      spatial_reuse                                           :  8, // [10:3]
+                      validate_1a                                             :  1, // [2:2]
+                      eht_ppdu_sig_cmn_type                                   :  2; // [1:0]
+#endif
+};
+
+
+
+
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET                                        0x00000000
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB                                           0
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB                                           2
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK                                          0x00000007
+
+
+
+
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET                                        0x00000000
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB                                           3
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB                                           5
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK                                          0x00000038
+
+
+
+
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET                                         0x00000000
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB                                            6
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB                                            6
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK                                           0x00000040
+
+
+
+
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET                                       0x00000000
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB                                          7
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB                                          12
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK                                         0x00001f80
+
+
+
+
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET                                      0x00000000
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB                                         13
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB                                         19
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK                                        0x000fe000
+
+
+
+
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET                                       0x00000000
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB                                          20
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB                                          25
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK                                         0x03f00000
+
+
+
+
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET                                        0x00000000
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB                                           26
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB                                           31
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK                                          0xfc000000
+
+
+
+
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET                              0x00000004
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB                                 0
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB                                 1
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK                                0x00000003
+
+
+
+
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET                                        0x00000004
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB                                           2
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB                                           2
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK                                          0x00000004
+
+
+
+
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET                                      0x00000004
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB                                         3
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB                                         10
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK                                        0x000007f8
+
+
+
+
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET                                       0x00000004
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB                                          11
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB                                          15
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK                                         0x0000f800
+
+
+
+
+#define U_SIG_EHT_TB_INFO_CRC_OFFSET                                                0x00000004
+#define U_SIG_EHT_TB_INFO_CRC_LSB                                                   16
+#define U_SIG_EHT_TB_INFO_CRC_MSB                                                   19
+#define U_SIG_EHT_TB_INFO_CRC_MASK                                                  0x000f0000
+
+
+
+
+#define U_SIG_EHT_TB_INFO_TAIL_OFFSET                                               0x00000004
+#define U_SIG_EHT_TB_INFO_TAIL_LSB                                                  20
+#define U_SIG_EHT_TB_INFO_TAIL_MSB                                                  25
+#define U_SIG_EHT_TB_INFO_TAIL_MASK                                                 0x03f00000
+
+
+
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET                                        0x00000004
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB                                           26
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB                                           30
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK                                          0x7c000000
+
+
+
+
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000004
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
+
+
+
+
+#endif

hw/qcn9224/unallocated_ru_160_info.h

@@ -0,0 +1,84 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _UNALLOCATED_RU_160_INFO_H_
+#define _UNALLOCATED_RU_160_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1
+
+
+struct unallocated_ru_160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t subband80_0_cc0                                         :  8, // [7:0]
+                      subband80_0_cc1                                         :  8, // [15:8]
+                      subband80_1_cc0                                         :  8, // [23:16]
+                      subband80_1_cc1                                         :  8; // [31:24]
+#else
+             uint32_t subband80_1_cc1                                         :  8, // [31:24]
+                      subband80_1_cc0                                         :  8, // [23:16]
+                      subband80_0_cc1                                         :  8, // [15:8]
+                      subband80_0_cc0                                         :  8; // [7:0]
+#endif
+};
+
+
+
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB                                 0
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB                                 7
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK                                0x000000ff
+
+
+
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB                                 8
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB                                 15
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK                                0x0000ff00
+
+
+
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB                                 16
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB                                 23
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK                                0x00ff0000
+
+
+
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB                                 24
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB                                 31
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK                                0xff000000
+
+
+
+
+#endif

hw/qcn9224/vht_sig_b_mu160_info.h

@@ -0,0 +1,364 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _VHT_SIG_B_MU160_INFO_H_
+#define _VHT_SIG_B_MU160_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8
+
+
+struct vht_sig_b_mu160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 19, // [18:0]
+                      mcs                                                     :  4, // [22:19]
+                      tail                                                    :  6, // [28:23]
+                      reserved_0                                              :  3; // [31:29]
+             uint32_t length_copy_a                                           : 19, // [18:0]
+                      mcs_copy_a                                              :  4, // [22:19]
+                      tail_copy_a                                             :  6, // [28:23]
+                      reserved_1                                              :  3; // [31:29]
+             uint32_t length_copy_b                                           : 19, // [18:0]
+                      mcs_copy_b                                              :  4, // [22:19]
+                      tail_copy_b                                             :  6, // [28:23]
+                      reserved_2                                              :  3; // [31:29]
+             uint32_t length_copy_c                                           : 19, // [18:0]
+                      mcs_copy_c                                              :  4, // [22:19]
+                      tail_copy_c                                             :  6, // [28:23]
+                      reserved_3                                              :  3; // [31:29]
+             uint32_t length_copy_d                                           : 19, // [18:0]
+                      mcs_copy_d                                              :  4, // [22:19]
+                      tail_copy_d                                             :  6, // [28:23]
+                      reserved_4                                              :  3; // [31:29]
+             uint32_t length_copy_e                                           : 19, // [18:0]
+                      mcs_copy_e                                              :  4, // [22:19]
+                      tail_copy_e                                             :  6, // [28:23]
+                      reserved_5                                              :  3; // [31:29]
+             uint32_t length_copy_f                                           : 19, // [18:0]
+                      mcs_copy_f                                              :  4, // [22:19]
+                      tail_copy_f                                             :  6, // [28:23]
+                      mu_user_number                                          :  3; // [31:29]
+             uint32_t length_copy_g                                           : 19, // [18:0]
+                      mcs_copy_g                                              :  4, // [22:19]
+                      tail_copy_g                                             :  6, // [28:23]
+                      reserved_7                                              :  3; // [31:29]
+#else
+             uint32_t reserved_0                                              :  3, // [31:29]
+                      tail                                                    :  6, // [28:23]
+                      mcs                                                     :  4, // [22:19]
+                      length                                                  : 19; // [18:0]
+             uint32_t reserved_1                                              :  3, // [31:29]
+                      tail_copy_a                                             :  6, // [28:23]
+                      mcs_copy_a                                              :  4, // [22:19]
+                      length_copy_a                                           : 19; // [18:0]
+             uint32_t reserved_2                                              :  3, // [31:29]
+                      tail_copy_b                                             :  6, // [28:23]
+                      mcs_copy_b                                              :  4, // [22:19]
+                      length_copy_b                                           : 19; // [18:0]
+             uint32_t reserved_3                                              :  3, // [31:29]
+                      tail_copy_c                                             :  6, // [28:23]
+                      mcs_copy_c                                              :  4, // [22:19]
+                      length_copy_c                                           : 19; // [18:0]
+             uint32_t reserved_4                                              :  3, // [31:29]
+                      tail_copy_d                                             :  6, // [28:23]
+                      mcs_copy_d                                              :  4, // [22:19]
+                      length_copy_d                                           : 19; // [18:0]
+             uint32_t reserved_5                                              :  3, // [31:29]
+                      tail_copy_e                                             :  6, // [28:23]
+                      mcs_copy_e                                              :  4, // [22:19]
+                      length_copy_e                                           : 19; // [18:0]
+             uint32_t mu_user_number                                          :  3, // [31:29]
+                      tail_copy_f                                             :  6, // [28:23]
+                      mcs_copy_f                                              :  4, // [22:19]
+                      length_copy_f                                           : 19; // [18:0]
+             uint32_t reserved_7                                              :  3, // [31:29]
+                      tail_copy_g                                             :  6, // [28:23]
+                      mcs_copy_g                                              :  4, // [22:19]
+                      length_copy_g                                           : 19; // [18:0]
+#endif
+};
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET                                          0x00000000
+#define VHT_SIG_B_MU160_INFO_LENGTH_LSB                                             0
+#define VHT_SIG_B_MU160_INFO_LENGTH_MSB                                             18
+#define VHT_SIG_B_MU160_INFO_LENGTH_MASK                                            0x0007ffff
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_MCS_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU160_INFO_MCS_LSB                                                19
+#define VHT_SIG_B_MU160_INFO_MCS_MSB                                                22
+#define VHT_SIG_B_MU160_INFO_MCS_MASK                                               0x00780000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET                                            0x00000000
+#define VHT_SIG_B_MU160_INFO_TAIL_LSB                                               23
+#define VHT_SIG_B_MU160_INFO_TAIL_MSB                                               28
+#define VHT_SIG_B_MU160_INFO_TAIL_MASK                                              0x1f800000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET                                      0x00000000
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK                                        0xe0000000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET                                   0x00000004
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK                                     0x0007ffff
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK                                        0x00780000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET                                     0x00000004
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK                                       0x1f800000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK                                        0xe0000000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET                                   0x00000008
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK                                     0x0007ffff
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET                                      0x00000008
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK                                        0x00780000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET                                     0x00000008
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK                                       0x1f800000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET                                      0x00000008
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK                                        0xe0000000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET                                   0x0000000c
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK                                     0x0007ffff
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET                                      0x0000000c
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK                                        0x00780000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET                                     0x0000000c
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK                                       0x1f800000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET                                      0x0000000c
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK                                        0xe0000000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET                                   0x00000010
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK                                     0x0007ffff
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET                                      0x00000010
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK                                        0x00780000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET                                     0x00000010
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK                                       0x1f800000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET                                      0x00000010
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK                                        0xe0000000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET                                   0x00000014
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK                                     0x0007ffff
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET                                      0x00000014
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK                                        0x00780000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET                                     0x00000014
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK                                       0x1f800000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET                                      0x00000014
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK                                        0xe0000000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET                                   0x00000018
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK                                     0x0007ffff
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET                                      0x00000018
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK                                        0x00780000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET                                     0x00000018
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK                                       0x1f800000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET                                  0x00000018
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB                                     29
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB                                     31
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK                                    0xe0000000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET                                   0x0000001c
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK                                     0x0007ffff
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET                                      0x0000001c
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK                                        0x00780000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET                                     0x0000001c
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK                                       0x1f800000
+
+
+
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET                                      0x0000001c
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK                                        0xe0000000
+
+
+
+
+#endif

hw/qcn9224/vht_sig_b_mu20_info.h

@@ -0,0 +1,94 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _VHT_SIG_B_MU20_INFO_H_
+#define _VHT_SIG_B_MU20_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1
+
+
+struct vht_sig_b_mu20_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 16, // [15:0]
+                      mcs                                                     :  4, // [19:16]
+                      tail                                                    :  6, // [25:20]
+                      mu_user_number                                          :  3, // [28:26]
+                      reserved_0                                              :  3; // [31:29]
+#else
+             uint32_t reserved_0                                              :  3, // [31:29]
+                      mu_user_number                                          :  3, // [28:26]
+                      tail                                                    :  6, // [25:20]
+                      mcs                                                     :  4, // [19:16]
+                      length                                                  : 16; // [15:0]
+#endif
+};
+
+
+
+
+#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_MU20_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_MU20_INFO_LENGTH_MSB                                              15
+#define VHT_SIG_B_MU20_INFO_LENGTH_MASK                                             0x0000ffff
+
+
+
+
+#define VHT_SIG_B_MU20_INFO_MCS_OFFSET                                              0x00000000
+#define VHT_SIG_B_MU20_INFO_MCS_LSB                                                 16
+#define VHT_SIG_B_MU20_INFO_MCS_MSB                                                 19
+#define VHT_SIG_B_MU20_INFO_MCS_MASK                                                0x000f0000
+
+
+
+
+#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU20_INFO_TAIL_LSB                                                20
+#define VHT_SIG_B_MU20_INFO_TAIL_MSB                                                25
+#define VHT_SIG_B_MU20_INFO_TAIL_MASK                                               0x03f00000
+
+
+
+
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET                                   0x00000000
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB                                      26
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB                                      28
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK                                     0x1c000000
+
+
+
+
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB                                          29
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB                                          31
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK                                         0xe0000000
+
+
+
+
+#endif

hw/qcn9224/vht_sig_b_mu40_info.h

@@ -0,0 +1,134 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _VHT_SIG_B_MU40_INFO_H_
+#define _VHT_SIG_B_MU40_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2
+
+
+struct vht_sig_b_mu40_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 17, // [16:0]
+                      mcs                                                     :  4, // [20:17]
+                      tail                                                    :  6, // [26:21]
+                      reserved_0                                              :  2, // [28:27]
+                      mu_user_number                                          :  3; // [31:29]
+             uint32_t length_copy                                             : 17, // [16:0]
+                      mcs_copy                                                :  4, // [20:17]
+                      tail_copy                                               :  6, // [26:21]
+                      reserved_1                                              :  5; // [31:27]
+#else
+             uint32_t mu_user_number                                          :  3, // [31:29]
+                      reserved_0                                              :  2, // [28:27]
+                      tail                                                    :  6, // [26:21]
+                      mcs                                                     :  4, // [20:17]
+                      length                                                  : 17; // [16:0]
+             uint32_t reserved_1                                              :  5, // [31:27]
+                      tail_copy                                               :  6, // [26:21]
+                      mcs_copy                                                :  4, // [20:17]
+                      length_copy                                             : 17; // [16:0]
+#endif
+};
+
+
+
+
+#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_MU40_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_MU40_INFO_LENGTH_MSB                                              16
+#define VHT_SIG_B_MU40_INFO_LENGTH_MASK                                             0x0001ffff
+
+
+
+
+#define VHT_SIG_B_MU40_INFO_MCS_OFFSET                                              0x00000000
+#define VHT_SIG_B_MU40_INFO_MCS_LSB                                                 17
+#define VHT_SIG_B_MU40_INFO_MCS_MSB                                                 20
+#define VHT_SIG_B_MU40_INFO_MCS_MASK                                                0x001e0000
+
+
+
+
+#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU40_INFO_TAIL_LSB                                                21
+#define VHT_SIG_B_MU40_INFO_TAIL_MSB                                                26
+#define VHT_SIG_B_MU40_INFO_TAIL_MASK                                               0x07e00000
+
+
+
+
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB                                          27
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB                                          28
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK                                         0x18000000
+
+
+
+
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET                                   0x00000000
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB                                      29
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB                                      31
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK                                     0xe0000000
+
+
+
+
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB                                         0
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB                                         16
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK                                        0x0001ffff
+
+
+
+
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET                                         0x00000004
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB                                            17
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB                                            20
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK                                           0x001e0000
+
+
+
+
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET                                        0x00000004
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB                                           21
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB                                           26
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK                                          0x07e00000
+
+
+
+
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB                                          27
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB                                          31
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK                                         0xf8000000
+
+
+
+
+#endif

hw/qcn9224/vht_sig_b_mu80_info.h

@@ -0,0 +1,203 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _VHT_SIG_B_MU80_INFO_H_
+#define _VHT_SIG_B_MU80_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4
+
+
+struct vht_sig_b_mu80_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 19, // [18:0]
+                      mcs                                                     :  4, // [22:19]
+                      tail                                                    :  6, // [28:23]
+                      reserved_0                                              :  3; // [31:29]
+             uint32_t length_copy_a                                           : 19, // [18:0]
+                      mcs_copy_a                                              :  4, // [22:19]
+                      tail_copy_a                                             :  6, // [28:23]
+                      reserved_1                                              :  3; // [31:29]
+             uint32_t length_copy_b                                           : 19, // [18:0]
+                      mcs_copy_b                                              :  4, // [22:19]
+                      tail_copy_b                                             :  6, // [28:23]
+                      mu_user_number                                          :  3; // [31:29]
+             uint32_t length_copy_c                                           : 19, // [18:0]
+                      mcs_copy_c                                              :  4, // [22:19]
+                      tail_copy_c                                             :  6, // [28:23]
+                      reserved_3                                              :  3; // [31:29]
+#else
+             uint32_t reserved_0                                              :  3, // [31:29]
+                      tail                                                    :  6, // [28:23]
+                      mcs                                                     :  4, // [22:19]
+                      length                                                  : 19; // [18:0]
+             uint32_t reserved_1                                              :  3, // [31:29]
+                      tail_copy_a                                             :  6, // [28:23]
+                      mcs_copy_a                                              :  4, // [22:19]
+                      length_copy_a                                           : 19; // [18:0]
+             uint32_t mu_user_number                                          :  3, // [31:29]
+                      tail_copy_b                                             :  6, // [28:23]
+                      mcs_copy_b                                              :  4, // [22:19]
+                      length_copy_b                                           : 19; // [18:0]
+             uint32_t reserved_3                                              :  3, // [31:29]
+                      tail_copy_c                                             :  6, // [28:23]
+                      mcs_copy_c                                              :  4, // [22:19]
+                      length_copy_c                                           : 19; // [18:0]
+#endif
+};
+
+
+
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_MU80_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_MU80_INFO_LENGTH_MSB                                              18
+#define VHT_SIG_B_MU80_INFO_LENGTH_MASK                                             0x0007ffff
+
+
+
+
+#define VHT_SIG_B_MU80_INFO_MCS_OFFSET                                              0x00000000
+#define VHT_SIG_B_MU80_INFO_MCS_LSB                                                 19
+#define VHT_SIG_B_MU80_INFO_MCS_MSB                                                 22
+#define VHT_SIG_B_MU80_INFO_MCS_MASK                                                0x00780000
+
+
+
+
+#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU80_INFO_TAIL_LSB                                                23
+#define VHT_SIG_B_MU80_INFO_TAIL_MSB                                                28
+#define VHT_SIG_B_MU80_INFO_TAIL_MASK                                               0x1f800000
+
+
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB                                          29
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB                                          31
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK                                         0xe0000000
+
+
+
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET                                    0x00000004
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB                                       0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB                                       18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK                                      0x0007ffff
+
+
+
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET                                       0x00000004
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB                                          19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB                                          22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK                                         0x00780000
+
+
+
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB                                         23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB                                         28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK                                        0x1f800000
+
+
+
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB                                          29
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB                                          31
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK                                         0xe0000000
+
+
+
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET                                    0x00000008
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB                                       0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB                                       18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK                                      0x0007ffff
+
+
+
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET                                       0x00000008
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB                                          19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB                                          22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK                                         0x00780000
+
+
+
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET                                      0x00000008
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB                                         23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB                                         28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK                                        0x1f800000
+
+
+
+
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET                                   0x00000008
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB                                      29
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB                                      31
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK                                     0xe0000000
+
+
+
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET                                    0x0000000c
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB                                       0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB                                       18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK                                      0x0007ffff
+
+
+
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET                                       0x0000000c
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB                                          19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB                                          22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK                                         0x00780000
+
+
+
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET                                      0x0000000c
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB                                         23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB                                         28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK                                        0x1f800000
+
+
+
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET                                       0x0000000c
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB                                          29
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB                                          31
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK                                         0xe0000000
+
+
+
+
+#endif

hw/qcn9224/vht_sig_b_su160_info.h

@@ -0,0 +1,444 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _VHT_SIG_B_SU160_INFO_H_
+#define _VHT_SIG_B_SU160_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8
+
+
+struct vht_sig_b_su160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 21, // [20:0]
+                      vhtb_reserved                                           :  2, // [22:21]
+                      tail                                                    :  6, // [28:23]
+                      reserved_0                                              :  2, // [30:29]
+                      rx_ndp                                                  :  1; // [31:31]
+             uint32_t length_copy_a                                           : 21, // [20:0]
+                      vhtb_reserved_copy_a                                    :  2, // [22:21]
+                      tail_copy_a                                             :  6, // [28:23]
+                      reserved_1                                              :  2, // [30:29]
+                      rx_ndp_copy_a                                           :  1; // [31:31]
+             uint32_t length_copy_b                                           : 21, // [20:0]
+                      vhtb_reserved_copy_b                                    :  2, // [22:21]
+                      tail_copy_b                                             :  6, // [28:23]
+                      reserved_2                                              :  2, // [30:29]
+                      rx_ndp_copy_b                                           :  1; // [31:31]
+             uint32_t length_copy_c                                           : 21, // [20:0]
+                      vhtb_reserved_copy_c                                    :  2, // [22:21]
+                      tail_copy_c                                             :  6, // [28:23]
+                      reserved_3                                              :  2, // [30:29]
+                      rx_ndp_copy_c                                           :  1; // [31:31]
+             uint32_t length_copy_d                                           : 21, // [20:0]
+                      vhtb_reserved_copy_d                                    :  2, // [22:21]
+                      tail_copy_d                                             :  6, // [28:23]
+                      reserved_4                                              :  2, // [30:29]
+                      rx_ndp_copy_d                                           :  1; // [31:31]
+             uint32_t length_copy_e                                           : 21, // [20:0]
+                      vhtb_reserved_copy_e                                    :  2, // [22:21]
+                      tail_copy_e                                             :  6, // [28:23]
+                      reserved_5                                              :  2, // [30:29]
+                      rx_ndp_copy_e                                           :  1; // [31:31]
+             uint32_t length_copy_f                                           : 21, // [20:0]
+                      vhtb_reserved_copy_f                                    :  2, // [22:21]
+                      tail_copy_f                                             :  6, // [28:23]
+                      reserved_6                                              :  2, // [30:29]
+                      rx_ndp_copy_f                                           :  1; // [31:31]
+             uint32_t length_copy_g                                           : 21, // [20:0]
+                      vhtb_reserved_copy_g                                    :  2, // [22:21]
+                      tail_copy_g                                             :  6, // [28:23]
+                      reserved_7                                              :  2, // [30:29]
+                      rx_ndp_copy_g                                           :  1; // [31:31]
+#else
+             uint32_t rx_ndp                                                  :  1, // [31:31]
+                      reserved_0                                              :  2, // [30:29]
+                      tail                                                    :  6, // [28:23]
+                      vhtb_reserved                                           :  2, // [22:21]
+                      length                                                  : 21; // [20:0]
+             uint32_t rx_ndp_copy_a                                           :  1, // [31:31]
+                      reserved_1                                              :  2, // [30:29]
+                      tail_copy_a                                             :  6, // [28:23]
+                      vhtb_reserved_copy_a                                    :  2, // [22:21]
+                      length_copy_a                                           : 21; // [20:0]
+             uint32_t rx_ndp_copy_b                                           :  1, // [31:31]
+                      reserved_2                                              :  2, // [30:29]
+                      tail_copy_b                                             :  6, // [28:23]
+                      vhtb_reserved_copy_b                                    :  2, // [22:21]
+                      length_copy_b                                           : 21; // [20:0]
+             uint32_t rx_ndp_copy_c                                           :  1, // [31:31]
+                      reserved_3                                              :  2, // [30:29]
+                      tail_copy_c                                             :  6, // [28:23]
+                      vhtb_reserved_copy_c                                    :  2, // [22:21]
+                      length_copy_c                                           : 21; // [20:0]
+             uint32_t rx_ndp_copy_d                                           :  1, // [31:31]
+                      reserved_4                                              :  2, // [30:29]
+                      tail_copy_d                                             :  6, // [28:23]
+                      vhtb_reserved_copy_d                                    :  2, // [22:21]
+                      length_copy_d                                           : 21; // [20:0]
+             uint32_t rx_ndp_copy_e                                           :  1, // [31:31]
+                      reserved_5                                              :  2, // [30:29]
+                      tail_copy_e                                             :  6, // [28:23]
+                      vhtb_reserved_copy_e                                    :  2, // [22:21]
+                      length_copy_e                                           : 21; // [20:0]
+             uint32_t rx_ndp_copy_f                                           :  1, // [31:31]
+                      reserved_6                                              :  2, // [30:29]
+                      tail_copy_f                                             :  6, // [28:23]
+                      vhtb_reserved_copy_f                                    :  2, // [22:21]
+                      length_copy_f                                           : 21; // [20:0]
+             uint32_t rx_ndp_copy_g                                           :  1, // [31:31]
+                      reserved_7                                              :  2, // [30:29]
+                      tail_copy_g                                             :  6, // [28:23]
+                      vhtb_reserved_copy_g                                    :  2, // [22:21]
+                      length_copy_g                                           : 21; // [20:0]
+#endif
+};
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET                                          0x00000000
+#define VHT_SIG_B_SU160_INFO_LENGTH_LSB                                             0
+#define VHT_SIG_B_SU160_INFO_LENGTH_MSB                                             20
+#define VHT_SIG_B_SU160_INFO_LENGTH_MASK                                            0x001fffff
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET                                   0x00000000
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB                                      21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB                                      22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK                                     0x00600000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET                                            0x00000000
+#define VHT_SIG_B_SU160_INFO_TAIL_LSB                                               23
+#define VHT_SIG_B_SU160_INFO_TAIL_MSB                                               28
+#define VHT_SIG_B_SU160_INFO_TAIL_MASK                                              0x1f800000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET                                      0x00000000
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK                                        0x60000000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET                                          0x00000000
+#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB                                             31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB                                             31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK                                            0x80000000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET                                   0x00000004
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK                                     0x001fffff
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET                            0x00000004
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK                              0x00600000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET                                     0x00000004
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK                                       0x1f800000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK                                        0x60000000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET                                   0x00000004
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK                                     0x80000000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET                                   0x00000008
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK                                     0x001fffff
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET                            0x00000008
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK                              0x00600000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET                                     0x00000008
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK                                       0x1f800000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET                                      0x00000008
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK                                        0x60000000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET                                   0x00000008
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK                                     0x80000000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET                                   0x0000000c
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK                                     0x001fffff
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET                            0x0000000c
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK                              0x00600000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET                                     0x0000000c
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK                                       0x1f800000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET                                      0x0000000c
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK                                        0x60000000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET                                   0x0000000c
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK                                     0x80000000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET                                   0x00000010
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK                                     0x001fffff
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET                            0x00000010
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK                              0x00600000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET                                     0x00000010
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK                                       0x1f800000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET                                      0x00000010
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK                                        0x60000000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET                                   0x00000010
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK                                     0x80000000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET                                   0x00000014
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK                                     0x001fffff
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET                            0x00000014
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK                              0x00600000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET                                     0x00000014
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK                                       0x1f800000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET                                      0x00000014
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK                                        0x60000000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET                                   0x00000014
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK                                     0x80000000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET                                   0x00000018
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK                                     0x001fffff
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET                            0x00000018
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK                              0x00600000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET                                     0x00000018
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK                                       0x1f800000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET                                      0x00000018
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK                                        0x60000000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET                                   0x00000018
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK                                     0x80000000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET                                   0x0000001c
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK                                     0x001fffff
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET                            0x0000001c
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK                              0x00600000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET                                     0x0000001c
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK                                       0x1f800000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET                                      0x0000001c
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK                                        0x60000000
+
+
+
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET                                   0x0000001c
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK                                     0x80000000
+
+
+
+
+#endif

hw/qcn9224/vht_sig_b_su20_info.h

@@ -0,0 +1,94 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _VHT_SIG_B_SU20_INFO_H_
+#define _VHT_SIG_B_SU20_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1
+
+
+struct vht_sig_b_su20_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 17, // [16:0]
+                      vhtb_reserved                                           :  3, // [19:17]
+                      tail                                                    :  6, // [25:20]
+                      reserved                                                :  5, // [30:26]
+                      rx_ndp                                                  :  1; // [31:31]
+#else
+             uint32_t rx_ndp                                                  :  1, // [31:31]
+                      reserved                                                :  5, // [30:26]
+                      tail                                                    :  6, // [25:20]
+                      vhtb_reserved                                           :  3, // [19:17]
+                      length                                                  : 17; // [16:0]
+#endif
+};
+
+
+
+
+#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU20_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_SU20_INFO_LENGTH_MSB                                              16
+#define VHT_SIG_B_SU20_INFO_LENGTH_MASK                                             0x0001ffff
+
+
+
+
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET                                    0x00000000
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB                                       17
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB                                       19
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK                                      0x000e0000
+
+
+
+
+#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_SU20_INFO_TAIL_LSB                                                20
+#define VHT_SIG_B_SU20_INFO_TAIL_MSB                                                25
+#define VHT_SIG_B_SU20_INFO_TAIL_MASK                                               0x03f00000
+
+
+
+
+#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET                                         0x00000000
+#define VHT_SIG_B_SU20_INFO_RESERVED_LSB                                            26
+#define VHT_SIG_B_SU20_INFO_RESERVED_MSB                                            30
+#define VHT_SIG_B_SU20_INFO_RESERVED_MASK                                           0x7c000000
+
+
+
+
+#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB                                              31
+#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB                                              31
+#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK                                             0x80000000
+
+
+
+
+#endif

hw/qcn9224/vht_sig_b_su40_info.h

@@ -0,0 +1,144 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _VHT_SIG_B_SU40_INFO_H_
+#define _VHT_SIG_B_SU40_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2
+
+
+struct vht_sig_b_su40_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 19, // [18:0]
+                      vhtb_reserved                                           :  2, // [20:19]
+                      tail                                                    :  6, // [26:21]
+                      reserved                                                :  4, // [30:27]
+                      rx_ndp                                                  :  1; // [31:31]
+             uint32_t length_copy                                             : 19, // [18:0]
+                      vhtb_reserved_copy                                      :  2, // [20:19]
+                      tail_copy                                               :  6, // [26:21]
+                      reserved_copy                                           :  4, // [30:27]
+                      rx_ndp_copy                                             :  1; // [31:31]
+#else
+             uint32_t rx_ndp                                                  :  1, // [31:31]
+                      reserved                                                :  4, // [30:27]
+                      tail                                                    :  6, // [26:21]
+                      vhtb_reserved                                           :  2, // [20:19]
+                      length                                                  : 19; // [18:0]
+             uint32_t rx_ndp_copy                                             :  1, // [31:31]
+                      reserved_copy                                           :  4, // [30:27]
+                      tail_copy                                               :  6, // [26:21]
+                      vhtb_reserved_copy                                      :  2, // [20:19]
+                      length_copy                                             : 19; // [18:0]
+#endif
+};
+
+
+
+
+#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU40_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_SU40_INFO_LENGTH_MSB                                              18
+#define VHT_SIG_B_SU40_INFO_LENGTH_MASK                                             0x0007ffff
+
+
+
+
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET                                    0x00000000
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB                                       19
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB                                       20
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK                                      0x00180000
+
+
+
+
+#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_SU40_INFO_TAIL_LSB                                                21
+#define VHT_SIG_B_SU40_INFO_TAIL_MSB                                                26
+#define VHT_SIG_B_SU40_INFO_TAIL_MASK                                               0x07e00000
+
+
+
+
+#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET                                         0x00000000
+#define VHT_SIG_B_SU40_INFO_RESERVED_LSB                                            27
+#define VHT_SIG_B_SU40_INFO_RESERVED_MSB                                            30
+#define VHT_SIG_B_SU40_INFO_RESERVED_MASK                                           0x78000000
+
+
+
+
+#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB                                              31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB                                              31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK                                             0x80000000
+
+
+
+
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB                                         0
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB                                         18
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK                                        0x0007ffff
+
+
+
+
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET                               0x00000004
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB                                  19
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB                                  20
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK                                 0x00180000
+
+
+
+
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET                                        0x00000004
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB                                           21
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB                                           26
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK                                          0x07e00000
+
+
+
+
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET                                    0x00000004
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB                                       27
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB                                       30
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK                                      0x78000000
+
+
+
+
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB                                         31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB                                         31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK                                        0x80000000
+
+
+
+
+#endif

hw/qcn9224/vht_sig_b_su80_info.h

@@ -0,0 +1,244 @@
+
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+
+
+
+
+
+
+
+#ifndef _VHT_SIG_B_SU80_INFO_H_
+#define _VHT_SIG_B_SU80_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4
+
+
+struct vht_sig_b_su80_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 21, // [20:0]
+                      vhtb_reserved                                           :  2, // [22:21]
+                      tail                                                    :  6, // [28:23]
+                      reserved_0                                              :  2, // [30:29]
+                      rx_ndp                                                  :  1; // [31:31]
+             uint32_t length_copy_a                                           : 21, // [20:0]
+                      vhtb_reserved_copy_a                                    :  2, // [22:21]
+                      tail_copy_a                                             :  6, // [28:23]
+                      reserved_1                                              :  2, // [30:29]
+                      rx_ndp_copy_a                                           :  1; // [31:31]
+             uint32_t length_copy_b                                           : 21, // [20:0]
+                      vhtb_reserved_copy_b                                    :  2, // [22:21]
+                      tail_copy_b                                             :  6, // [28:23]
+                      reserved_2                                              :  2, // [30:29]
+                      rx_ndp_copy_b                                           :  1; // [31:31]
+             uint32_t length_copy_c                                           : 21, // [20:0]
+                      vhtb_reserved_copy_c                                    :  2, // [22:21]
+                      tail_copy_c                                             :  6, // [28:23]
+                      reserved_3                                              :  2, // [30:29]
+                      rx_ndp_copy_c                                           :  1; // [31:31]
+#else
+             uint32_t rx_ndp                                                  :  1, // [31:31]
+                      reserved_0                                              :  2, // [30:29]
+                      tail                                                    :  6, // [28:23]
+                      vhtb_reserved                                           :  2, // [22:21]
+                      length                                                  : 21; // [20:0]
+             uint32_t rx_ndp_copy_a                                           :  1, // [31:31]
+                      reserved_1                                              :  2, // [30:29]
+                      tail_copy_a                                             :  6, // [28:23]
+                      vhtb_reserved_copy_a                                    :  2, // [22:21]
+                      length_copy_a                                           : 21; // [20:0]
+             uint32_t rx_ndp_copy_b                                           :  1, // [31:31]
+                      reserved_2                                              :  2, // [30:29]
+                      tail_copy_b                                             :  6, // [28:23]
+                      vhtb_reserved_copy_b                                    :  2, // [22:21]
+                      length_copy_b                                           : 21; // [20:0]
+             uint32_t rx_ndp_copy_c                                           :  1, // [31:31]
+                      reserved_3                                              :  2, // [30:29]
+                      tail_copy_c                                             :  6, // [28:23]
+                      vhtb_reserved_copy_c                                    :  2, // [22:21]
+                      length_copy_c                                           : 21; // [20:0]
+#endif
+};
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU80_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_SU80_INFO_LENGTH_MSB                                              20
+#define VHT_SIG_B_SU80_INFO_LENGTH_MASK                                             0x001fffff
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET                                    0x00000000
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB                                       21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB                                       22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK                                      0x00600000
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_SU80_INFO_TAIL_LSB                                                23
+#define VHT_SIG_B_SU80_INFO_TAIL_MSB                                                28
+#define VHT_SIG_B_SU80_INFO_TAIL_MASK                                               0x1f800000
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK                                         0x60000000
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB                                              31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB                                              31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK                                             0x80000000
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET                                    0x00000004
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB                                       0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB                                       20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK                                      0x001fffff
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET                             0x00000004
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB                                21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB                                22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK                               0x00600000
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB                                         23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB                                         28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK                                        0x1f800000
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK                                         0x60000000
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET                                    0x00000004
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK                                      0x80000000
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET                                    0x00000008
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB                                       0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB                                       20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK                                      0x001fffff
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET                             0x00000008
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB                                21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB                                22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK                               0x00600000
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET                                      0x00000008
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB                                         23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB                                         28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK                                        0x1f800000
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET                                       0x00000008
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK                                         0x60000000
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET                                    0x00000008
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK                                      0x80000000
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET                                    0x0000000c
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB                                       0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB                                       20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK                                      0x001fffff
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET                             0x0000000c
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB                                21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB                                22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK                               0x00600000
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET                                      0x0000000c
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB                                         23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB                                         28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK                                        0x1f800000
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET                                       0x0000000c
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK                                         0x60000000
+
+
+
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET                                    0x0000000c
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK                                      0x80000000
+
+
+
+
+#endif