Merge "disp: msm: sde: avoid physical encoder disable(s) in trusted VM"

msm/sde/sde_core_irq.c

@@ -464,6 +464,7 @@ void sde_core_irq_preinstall(struct sde_kms *sde_kms)
 		return;
 	}
 
+	if (!sde_in_trusted_vm(sde_kms)) {
 		rc = pm_runtime_get_sync(sde_kms->dev->dev);
 		if (rc < 0) {
 			SDE_ERROR("failed to enable power resource %d\n", rc);
@@ -473,7 +474,9 @@ void sde_core_irq_preinstall(struct sde_kms *sde_kms)
 
 		sde_clear_all_irqs(sde_kms);
 		sde_disable_all_irqs(sde_kms);
+
 		pm_runtime_put_sync(sde_kms->dev->dev);
+	}
 
 	spin_lock_init(&sde_kms->irq_obj.cb_lock);
 

msm/sde/sde_encoder.c

@@ -2802,6 +2802,7 @@ static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
 	 * and after physical encoder is disabled, to make sure timing
 	 * engine is already disabled (for video mode).
 	 */
+	if (!sde_in_trusted_vm(sde_kms))
 		sde_encoder_dce_disable(sde_enc);
 
 	sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP);

msm/sde/sde_encoder_phys_cmd.c

@@ -1315,13 +1315,16 @@ static void sde_encoder_phys_cmd_disable(struct sde_encoder_phys *phys_enc)
 		return;
 	}
 
-	if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.enable_tearcheck)
+	if (!sde_in_trusted_vm(phys_enc->sde_kms)) {
+		if (phys_enc->has_intf_te &&
+				phys_enc->hw_intf->ops.enable_tearcheck)
 			phys_enc->hw_intf->ops.enable_tearcheck(
 					phys_enc->hw_intf,
 					false);
 		else if (phys_enc->hw_pp->ops.enable_tearcheck)
 			phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp,
 					false);
+	}
 
 	phys_enc->enable_state = SDE_ENC_DISABLED;
 }

msm/sde/sde_encoder_phys_vid.c

@@ -1061,6 +1061,9 @@ static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc)
 		return;
 	}
 
+	if (sde_in_trusted_vm(phys_enc->sde_kms))
+		goto exit;
+
 	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
 	phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);
 	sde_encoder_phys_inc_pending(phys_enc);

msm/sde/sde_hw_catalog.c

@@ -201,6 +201,7 @@ enum sde_prop {
 	PIPE_ORDER_VERSION,
 	SEC_SID_MASK,
 	BASE_LAYER,
+	TRUSTED_VM_ENV,
 	SDE_PROP_MAX,
 };
 
@@ -572,6 +573,7 @@ static struct sde_prop_type sde_prop[] = {
 			PROP_TYPE_U32},
 	{SEC_SID_MASK, "qcom,sde-secure-sid-mask", false, PROP_TYPE_U32_ARRAY},
 	{BASE_LAYER, "qcom,sde-mixer-stage-base-layer", false, PROP_TYPE_BOOL},
+	{TRUSTED_VM_ENV, "qcom,sde-trusted-vm-env", false, PROP_TYPE_BOOL},
 };
 
 static struct sde_prop_type sde_perf_prop[] = {
@@ -3748,6 +3750,8 @@ static void _sde_top_parse_dt_helper(struct sde_mdss_cfg *cfg,
 	cfg->has_base_layer = PROP_VALUE_ACCESS(props->values, BASE_LAYER, 0);
 	cfg->qseed_hw_version = PROP_VALUE_ACCESS(props->values,
 			 QSEED_HW_VERSION, 0);
+	cfg->trusted_vm_env = PROP_VALUE_ACCESS(props->values, TRUSTED_VM_ENV,
+			 0);
 }
 
 static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)

msm/sde/sde_hw_catalog.h

@@ -1362,6 +1362,8 @@ struct sde_perf_cfg {
  * this HW version. Contains number of instances,
  * register offsets, capabilities of the all MDSS HW sub-blocks.
  *
+ * @trusted_vm_env	set to true, if the driver is executing in
+ *			the trusted VM. false, otherwise.
  * @max_sspp_linewidth max source pipe line width support.
  * @vig_sspp_linewidth max vig source pipe line width support.
  * @scaling_linewidth max vig source pipe linewidth for scaling usecases
@@ -1434,6 +1436,7 @@ struct sde_perf_cfg {
  */
 struct sde_mdss_cfg {
 	u32 hwversion;
+	bool trusted_vm_env;
 
 	u32 max_sspp_linewidth;
 	u32 vig_sspp_linewidth;

msm/sde/sde_hw_cdm.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  */
 
 #include "sde_hw_mdss.h"
@@ -341,6 +341,7 @@ struct sde_hw_cdm *sde_hw_cdm_init(enum sde_cdm idx,
 	 * Perform any default initialization for the chroma down module
 	 * @setup default csc coefficients
 	 */
+	if (!m->trusted_vm_env)
 		sde_hw_cdm_setup_csc_10bit(c, &rgb2yuv_cfg);
 
 	return c;

msm/sde/sde_kms.c

@@ -3156,15 +3156,20 @@ static void sde_kms_handle_power_event(u32 event_type, void *usr)
 
 	if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
 		sde_irq_update(msm_kms, true);
-		if (sde_kms->splash_data.num_splash_displays)
+		sde_kms->first_kickoff = true;
+		if (sde_kms->splash_data.num_splash_displays ||
+				sde_in_trusted_vm(sde_kms))
 			return;
+
 		sde_vbif_init_memtypes(sde_kms);
 		sde_kms_init_shared_hw(sde_kms);
 		_sde_kms_set_lutdma_vbif_remap(sde_kms);
-		sde_kms->first_kickoff = true;
 	} else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
 		sde_irq_update(msm_kms, false);
 		sde_kms->first_kickoff = false;
+		if (sde_in_trusted_vm(sde_kms))
+			return;
+
 		_sde_kms_active_override(sde_kms, true);
 		if (!is_sde_rsc_available(SDE_RSC_INDEX))
 			sde_vbif_axi_halt_request(sde_kms);

msm/sde/sde_kms.h

@@ -642,6 +642,19 @@ static inline bool sde_kms_rect_is_null(const struct sde_rect *r)
 	return (!r->w || !r->h);
 }
 
+/*
+ * sde_in_trusted_vm - checks the executing VM
+ * return: true, if the device driver is executing in the trusted VM
+ *         false, if the device driver is executing in the primary VM
+ */
+static inline bool sde_in_trusted_vm(const struct sde_kms *sde_kms)
+{
+	if (sde_kms && sde_kms->catalog)
+		return sde_kms->catalog->trusted_vm_env;
+
+	return false;
+}
+
 /**
  * Vblank enable/disable functions
  */

msm/sde_power_handle.c

@@ -446,8 +446,7 @@ static int sde_power_mnoc_bus_parse(struct platform_device *pdev,
 
 	/* at least one databus path is required */
 	if (!pdbus->data_paths_cnt) {
-		pr_err("missing required interconnect:%s, rc:%d\n", name, rc);
-		return -EINVAL;
+		pr_info("mnoc interconnect path(s) not defined, rc: %d\n", rc);
 	} else if (rc) {
 		pr_info("ignoring error %d for non-primary data path\n", rc);
 		rc = 0;