Merge "disp: msm: sde: avoid physical encoder disable(s) in trusted VM"

This commit is contained in:
qctecmdr
2020-06-28 01:57:54 -07:00
committed by Gerrit - the friendly Code Review server
10 changed files with 58 additions and 23 deletions

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@@ -464,16 +464,19 @@ void sde_core_irq_preinstall(struct sde_kms *sde_kms)
return; return;
} }
rc = pm_runtime_get_sync(sde_kms->dev->dev); if (!sde_in_trusted_vm(sde_kms)) {
if (rc < 0) { rc = pm_runtime_get_sync(sde_kms->dev->dev);
SDE_ERROR("failed to enable power resource %d\n", rc); if (rc < 0) {
SDE_EVT32(rc, SDE_EVTLOG_ERROR); SDE_ERROR("failed to enable power resource %d\n", rc);
return; SDE_EVT32(rc, SDE_EVTLOG_ERROR);
} return;
}
sde_clear_all_irqs(sde_kms); sde_clear_all_irqs(sde_kms);
sde_disable_all_irqs(sde_kms); sde_disable_all_irqs(sde_kms);
pm_runtime_put_sync(sde_kms->dev->dev);
pm_runtime_put_sync(sde_kms->dev->dev);
}
spin_lock_init(&sde_kms->irq_obj.cb_lock); spin_lock_init(&sde_kms->irq_obj.cb_lock);

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@@ -2802,7 +2802,8 @@ static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
* and after physical encoder is disabled, to make sure timing * and after physical encoder is disabled, to make sure timing
* engine is already disabled (for video mode). * engine is already disabled (for video mode).
*/ */
sde_encoder_dce_disable(sde_enc); if (!sde_in_trusted_vm(sde_kms))
sde_encoder_dce_disable(sde_enc);
sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP); sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP);

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@@ -1315,13 +1315,16 @@ static void sde_encoder_phys_cmd_disable(struct sde_encoder_phys *phys_enc)
return; return;
} }
if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.enable_tearcheck) if (!sde_in_trusted_vm(phys_enc->sde_kms)) {
phys_enc->hw_intf->ops.enable_tearcheck( if (phys_enc->has_intf_te &&
phys_enc->hw_intf, phys_enc->hw_intf->ops.enable_tearcheck)
false); phys_enc->hw_intf->ops.enable_tearcheck(
else if (phys_enc->hw_pp->ops.enable_tearcheck) phys_enc->hw_intf,
phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, false);
false); else if (phys_enc->hw_pp->ops.enable_tearcheck)
phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp,
false);
}
phys_enc->enable_state = SDE_ENC_DISABLED; phys_enc->enable_state = SDE_ENC_DISABLED;
} }

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@@ -1061,6 +1061,9 @@ static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc)
return; return;
} }
if (sde_in_trusted_vm(phys_enc->sde_kms))
goto exit;
spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0); phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);
sde_encoder_phys_inc_pending(phys_enc); sde_encoder_phys_inc_pending(phys_enc);

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@@ -201,6 +201,7 @@ enum sde_prop {
PIPE_ORDER_VERSION, PIPE_ORDER_VERSION,
SEC_SID_MASK, SEC_SID_MASK,
BASE_LAYER, BASE_LAYER,
TRUSTED_VM_ENV,
SDE_PROP_MAX, SDE_PROP_MAX,
}; };
@@ -572,6 +573,7 @@ static struct sde_prop_type sde_prop[] = {
PROP_TYPE_U32}, PROP_TYPE_U32},
{SEC_SID_MASK, "qcom,sde-secure-sid-mask", false, PROP_TYPE_U32_ARRAY}, {SEC_SID_MASK, "qcom,sde-secure-sid-mask", false, PROP_TYPE_U32_ARRAY},
{BASE_LAYER, "qcom,sde-mixer-stage-base-layer", false, PROP_TYPE_BOOL}, {BASE_LAYER, "qcom,sde-mixer-stage-base-layer", false, PROP_TYPE_BOOL},
{TRUSTED_VM_ENV, "qcom,sde-trusted-vm-env", false, PROP_TYPE_BOOL},
}; };
static struct sde_prop_type sde_perf_prop[] = { static struct sde_prop_type sde_perf_prop[] = {
@@ -3748,6 +3750,8 @@ static void _sde_top_parse_dt_helper(struct sde_mdss_cfg *cfg,
cfg->has_base_layer = PROP_VALUE_ACCESS(props->values, BASE_LAYER, 0); cfg->has_base_layer = PROP_VALUE_ACCESS(props->values, BASE_LAYER, 0);
cfg->qseed_hw_version = PROP_VALUE_ACCESS(props->values, cfg->qseed_hw_version = PROP_VALUE_ACCESS(props->values,
QSEED_HW_VERSION, 0); QSEED_HW_VERSION, 0);
cfg->trusted_vm_env = PROP_VALUE_ACCESS(props->values, TRUSTED_VM_ENV,
0);
} }
static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)

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@@ -1362,6 +1362,8 @@ struct sde_perf_cfg {
* this HW version. Contains number of instances, * this HW version. Contains number of instances,
* register offsets, capabilities of the all MDSS HW sub-blocks. * register offsets, capabilities of the all MDSS HW sub-blocks.
* *
* @trusted_vm_env set to true, if the driver is executing in
* the trusted VM. false, otherwise.
* @max_sspp_linewidth max source pipe line width support. * @max_sspp_linewidth max source pipe line width support.
* @vig_sspp_linewidth max vig source pipe line width support. * @vig_sspp_linewidth max vig source pipe line width support.
* @scaling_linewidth max vig source pipe linewidth for scaling usecases * @scaling_linewidth max vig source pipe linewidth for scaling usecases
@@ -1434,6 +1436,7 @@ struct sde_perf_cfg {
*/ */
struct sde_mdss_cfg { struct sde_mdss_cfg {
u32 hwversion; u32 hwversion;
bool trusted_vm_env;
u32 max_sspp_linewidth; u32 max_sspp_linewidth;
u32 vig_sspp_linewidth; u32 vig_sspp_linewidth;

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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
*/ */
#include "sde_hw_mdss.h" #include "sde_hw_mdss.h"
@@ -341,7 +341,8 @@ struct sde_hw_cdm *sde_hw_cdm_init(enum sde_cdm idx,
* Perform any default initialization for the chroma down module * Perform any default initialization for the chroma down module
* @setup default csc coefficients * @setup default csc coefficients
*/ */
sde_hw_cdm_setup_csc_10bit(c, &rgb2yuv_cfg); if (!m->trusted_vm_env)
sde_hw_cdm_setup_csc_10bit(c, &rgb2yuv_cfg);
return c; return c;

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@@ -3156,15 +3156,20 @@ static void sde_kms_handle_power_event(u32 event_type, void *usr)
if (event_type == SDE_POWER_EVENT_POST_ENABLE) { if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
sde_irq_update(msm_kms, true); sde_irq_update(msm_kms, true);
if (sde_kms->splash_data.num_splash_displays) sde_kms->first_kickoff = true;
if (sde_kms->splash_data.num_splash_displays ||
sde_in_trusted_vm(sde_kms))
return; return;
sde_vbif_init_memtypes(sde_kms); sde_vbif_init_memtypes(sde_kms);
sde_kms_init_shared_hw(sde_kms); sde_kms_init_shared_hw(sde_kms);
_sde_kms_set_lutdma_vbif_remap(sde_kms); _sde_kms_set_lutdma_vbif_remap(sde_kms);
sde_kms->first_kickoff = true;
} else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) { } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
sde_irq_update(msm_kms, false); sde_irq_update(msm_kms, false);
sde_kms->first_kickoff = false; sde_kms->first_kickoff = false;
if (sde_in_trusted_vm(sde_kms))
return;
_sde_kms_active_override(sde_kms, true); _sde_kms_active_override(sde_kms, true);
if (!is_sde_rsc_available(SDE_RSC_INDEX)) if (!is_sde_rsc_available(SDE_RSC_INDEX))
sde_vbif_axi_halt_request(sde_kms); sde_vbif_axi_halt_request(sde_kms);

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@@ -642,6 +642,19 @@ static inline bool sde_kms_rect_is_null(const struct sde_rect *r)
return (!r->w || !r->h); return (!r->w || !r->h);
} }
/*
* sde_in_trusted_vm - checks the executing VM
* return: true, if the device driver is executing in the trusted VM
* false, if the device driver is executing in the primary VM
*/
static inline bool sde_in_trusted_vm(const struct sde_kms *sde_kms)
{
if (sde_kms && sde_kms->catalog)
return sde_kms->catalog->trusted_vm_env;
return false;
}
/** /**
* Vblank enable/disable functions * Vblank enable/disable functions
*/ */

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@@ -446,8 +446,7 @@ static int sde_power_mnoc_bus_parse(struct platform_device *pdev,
/* at least one databus path is required */ /* at least one databus path is required */
if (!pdbus->data_paths_cnt) { if (!pdbus->data_paths_cnt) {
pr_err("missing required interconnect:%s, rc:%d\n", name, rc); pr_info("mnoc interconnect path(s) not defined, rc: %d\n", rc);
return -EINVAL;
} else if (rc) { } else if (rc) {
pr_info("ignoring error %d for non-primary data path\n", rc); pr_info("ignoring error %d for non-primary data path\n", rc);
rc = 0; rc = 0;