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fw-api: Add E3 headers for qcn9000

Added qcn9000 headers corresponding to version E3

Change-Id: I782eefb47623f0ad211c0a2233bd64ba7e202f69
Nandha Kishore Easwaran 5 年之前
父節點
當前提交
e2028b05ad

File diff suppressed because it is too large
+ 141 - 361
hw/qcn9000/mac_tcl_reg_seq_hwioreg.h


+ 4 - 85
hw/qcn9000/msmhwiobase.h

@@ -25,9 +25,6 @@
 */
 /*
   ===========================================================================
-
-
-  ===========================================================================
 */
 
 /*----------------------------------------------------------------------------
@@ -134,14 +131,6 @@
 #define BLSP1_BLSP_BASE_SIZE                                        0x00040000
 #define BLSP1_BLSP_BASE_PHYS                                        0x01b40000
 
-/*----------------------------------------------------------------------------
- * BASE: CE_WFSS_CE_REG
- *--------------------------------------------------------------------------*/
-
-#define CE_WFSS_CE_REG_BASE                                         0x01b80000
-#define CE_WFSS_CE_REG_BASE_SIZE                                    0x0001c000
-#define CE_WFSS_CE_REG_BASE_PHYS                                    0x01b80000
-
 /*----------------------------------------------------------------------------
  * BASE: MEMSS_CSR
  *--------------------------------------------------------------------------*/
@@ -206,14 +195,6 @@
 #define SECURITY_CONTROL_WLAN_BASE_SIZE                             0x00008000
 #define SECURITY_CONTROL_WLAN_BASE_PHYS                             0x01e20000
 
-/*----------------------------------------------------------------------------
- * BASE: EDPD_EDPD_CAL_ACC
- *--------------------------------------------------------------------------*/
-
-#define EDPD_EDPD_CAL_ACC_BASE                                      0x01e28000
-#define EDPD_EDPD_CAL_ACC_BASE_SIZE                                 0x00004000
-#define EDPD_EDPD_CAL_ACC_BASE_PHYS                                 0x01e28000
-
 /*----------------------------------------------------------------------------
  * BASE: CPR_CX_CPR3
  *--------------------------------------------------------------------------*/
@@ -283,7 +264,7 @@
  *--------------------------------------------------------------------------*/
 
 #define SYSTEM_NOC_BASE                                             0x01e80000
-#define SYSTEM_NOC_BASE_SIZE                                        0x0000a000
+#define SYSTEM_NOC_BASE_SIZE                                        0x00003280
 #define SYSTEM_NOC_BASE_PHYS                                        0x01e80000
 
 /*----------------------------------------------------------------------------
@@ -291,7 +272,7 @@
  *--------------------------------------------------------------------------*/
 
 #define PC_NOC_BASE                                                 0x01f00000
-#define PC_NOC_BASE_SIZE                                            0x00004200
+#define PC_NOC_BASE_SIZE                                            0x00001180
 #define PC_NOC_BASE_PHYS                                            0x01f00000
 
 /*----------------------------------------------------------------------------
@@ -299,7 +280,7 @@
  *--------------------------------------------------------------------------*/
 
 #define WLAON_WL_AON_REG_BASE                                       0x01f80000
-#define WLAON_WL_AON_REG_BASE_SIZE                                  0x00000708
+#define WLAON_WL_AON_REG_BASE_SIZE                                  0x00000704
 #define WLAON_WL_AON_REG_BASE_PHYS                                  0x01f80000
 
 /*----------------------------------------------------------------------------
@@ -315,7 +296,7 @@
  *--------------------------------------------------------------------------*/
 
 #define PMU_WLAN_PMU_BASE                                           0x01f88000
-#define PMU_WLAN_PMU_BASE_SIZE                                      0x000000d4
+#define PMU_WLAN_PMU_BASE_SIZE                                      0x00000338
 #define PMU_WLAN_PMU_BASE_PHYS                                      0x01f88000
 
 /*----------------------------------------------------------------------------
@@ -326,14 +307,6 @@
 #define PMU_NOC_BASE_SIZE                                           0x00000080
 #define PMU_NOC_BASE_PHYS                                           0x01f8a000
 
-/*----------------------------------------------------------------------------
- * BASE: BT_SEC_REG_SECURITY_CONTROL_BT
- *--------------------------------------------------------------------------*/
-
-#define BT_SEC_REG_SECURITY_CONTROL_BT_BASE                         0x01f90000
-#define BT_SEC_REG_SECURITY_CONTROL_BT_BASE_SIZE                    0x00008000
-#define BT_SEC_REG_SECURITY_CONTROL_BT_BASE_PHYS                    0x01f90000
-
 /*----------------------------------------------------------------------------
  * BASE: PCIE_ATU_REGION
  *--------------------------------------------------------------------------*/
@@ -358,59 +331,5 @@
 #define PCIE_ATU_REGION_END_BASE_SIZE                               0x100000000
 #define PCIE_ATU_REGION_END_BASE_PHYS                               0x43ffffff
 
-/*----------------------------------------------------------------------------
- * BASE: MEM_SS_RAM_START_ADDRESS
- *--------------------------------------------------------------------------*/
-
-#define MEM_SS_RAM_START_ADDRESS_BASE                               0x1400000
-#define MEM_SS_RAM_START_ADDRESS_BASE_SIZE                          0x100000000
-#define MEM_SS_RAM_START_ADDRESS_BASE_PHYS                          0x1400000
-
-/*----------------------------------------------------------------------------
- * BASE: MEM_SS_RAM_SIZE
- *--------------------------------------------------------------------------*/
-#define MEM_SS_RAM_SIZE_BASE                                        0x003a0000
-#define MEM_SS_RAM_SIZE_BASE_SIZE                                   0x100000000
-#define MEM_SS_RAM_SIZE_BASE_PHYS                                   0x003a0000
-
-/*----------------------------------------------------------------------------
- * BASE: MEM_SS_RAM_END_ADDRESS
- *--------------------------------------------------------------------------*/
-
-#define MEM_SS_RAM_END_ADDRESS_BASE                                 0x0179ffff
-#define MEM_SS_RAM_END_ADDRESS_BASE_SIZE                            0x100000000
-#define MEM_SS_RAM_END_ADDRESS_BASE_PHYS                            0x0179ffff
-
-/*----------------------------------------------------------------------------
- * BASE: MEM_SS_ROM_START_ADDRESS
- *--------------------------------------------------------------------------*/
-
-#define MEM_SS_ROM_START_ADDRESS_BASE                               0x00800000
-#define MEM_SS_ROM_START_ADDRESS_BASE_SIZE                          0x100000000
-#define MEM_SS_ROM_START_ADDRESS_BASE_PHYS                          0x00800000
-
-/*----------------------------------------------------------------------------
- * BASE: MEM_SS_ROM_END_ADDRESS
- *--------------------------------------------------------------------------*/
-
-#define MEM_SS_ROM_END_ADDRESS_BASE                                 0x008bffff
-#define MEM_SS_ROM_END_ADDRESS_BASE_SIZE                            0x100000000
-#define MEM_SS_ROM_END_ADDRESS_BASE_PHYS                            0x008bffff
-
-/*----------------------------------------------------------------------------
- * BASE: MEM_SS_ROM_SIZE
- *--------------------------------------------------------------------------*/
-
-#define MEM_SS_ROM_SIZE_BASE                                        0x000c0000
-#define MEM_SS_ROM_SIZE_BASE_SIZE                                   0x100000000
-#define MEM_SS_ROM_SIZE_BASE_PHYS                                   0x000c0000
-
-/*----------------------------------------------------------------------------
- * BASE: QDSP6V67SS_WLAN
- *--------------------------------------------------------------------------*/
-
-#define QDSP6V67SS_WLAN_BASE                                        0x00000000
-#define QDSP6V67SS_WLAN_BASE_SIZE                                   0x01000000
-#define QDSP6V67SS_WLAN_BASE_PHYS                                   0x00000000
 
 #endif /* __MSMHWIOBASE_H__ */

+ 0 - 861
hw/qcn9000/msmhwioreg.h

@@ -1,861 +0,0 @@
-/*
- * Copyright (c) 2019, The Linux Foundation. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef __MSMHWIOREG_H__
-#define __MSMHWIOREG_H__
-/*
-===========================================================================
-*/
-/**
-  @file msmhwioreg.h
-  @brief Auto-generated HWIO interface include file.
-
-  This file contains HWIO register definitions for the following bases:
-    .*
-
-  'Include' filters applied: <none>
-  'Exclude' filters applied: RESERVED 
-
-  Attribute definitions for the HWIO_*_ATTR macros are as follows:
-    0x0: Command register
-    0x1: Read-Only
-    0x2: Write-Only
-    0x3: Read/Write
-*/
-/*
-  ===========================================================================
-
-
-  ===========================================================================
-*/
-
-#include "msmhwiobase.h"
-
-/*----------------------------------------------------------------------------
- * MODULE: CE_CE_COMMON_WFSS_CE_COMMON_REG
- *--------------------------------------------------------------------------*/
-
-#define CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE                                                                    (CE_WFSS_CE_REG_BASE      + 0x00018000)
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR                                                   (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000000)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK                                                   0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_POR                                                    0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_POR_RMSK                                               0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ATTR                                                          0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK                                             0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT                                                    0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR                                                   (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000004)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK                                                         0xff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_POR                                                    0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_POR_RMSK                                               0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ATTR                                                          0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK                                                   0xff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT                                                    0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR                                                  (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000008)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK                                                       0xfff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_POR                                                   0x00000211
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_POR_RMSK                                              0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ATTR                                                         0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK                                      0xe00
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT                                        0x9
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK                                      0x1f0
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT                                        0x4
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK                                        0xf
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT                                        0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR                                               (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000000c)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK                                                      0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_POR                                                0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_POR_RMSK                                           0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ATTR                                                      0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK                               0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT                               0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR                                              (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000010)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK                                              0x80000fff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_POR                                               0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_POR_RMSK                                          0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ATTR                                                     0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK                            0x80000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT                                  0x1f
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_BMSK                                             0x800
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_SHFT                                               0xb
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK                                          0x400
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT                                            0xa
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_BMSK                                           0x200
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_SHFT                                             0x9
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK                                      0x100
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT                                        0x8
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK                                       0x80
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT                                        0x7
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK                                         0x40
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT                                          0x6
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK                                    0x20
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT                                     0x5
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK                                    0x10
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT                                     0x4
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK                                         0x8
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT                                         0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK                                         0x4
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT                                         0x2
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_BMSK                                              0x2
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_SHFT                                              0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_BMSK                                                0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_SHFT                                                0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR                                                    (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000014)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK                                                     0x1010101
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_POR                                                     0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_POR_RMSK                                                0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ATTR                                                           0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK                                 0x1000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT                                      0x18
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK                                    0x10000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT                                       0x10
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK                                      0x100
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT                                        0x8
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK                                         0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT                                         0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR                                                   (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000018)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK                                                     0x3f3f3f
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_POR                                                    0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_POR_RMSK                                               0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ATTR                                                          0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK                                0x3f0000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT                                    0x10
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK                                       0x3f00
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT                                          0x8
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK                                         0x3f
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT                                          0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR                                             (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000001c)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK                                             0xffff3f3f
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_POR                                              0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_POR_RMSK                                         0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ATTR                                                    0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK           0xff000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT                 0x18
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK            0xff0000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT                0x10
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK                   0x3f00
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT                      0x8
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK                    0x3f
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT                     0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR                                             (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000020)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK                                             0xffff3f3f
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_POR                                              0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_POR_RMSK                                         0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ATTR                                                    0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK           0xff000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT                 0x18
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK            0xff0000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT                0x10
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK                   0x3f00
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT                      0x8
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK                    0x3f
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT                     0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR                                                (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000024)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK                                                 0xfffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_POR                                                 0x00240000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_POR_RMSK                                            0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ATTR                                                       0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK                            0x8000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT                                 0x1b
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK                            0x4000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT                                 0x1a
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK                           0x2000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT                                0x19
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK                       0x1000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT                            0x18
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK                        0x800000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT                            0x17
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK                             0x700000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT                                 0x14
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK                               0xe0000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT                                  0x11
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK                          0x1fe00
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT                              0x9
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK                        0x1fe
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT                          0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK                                       0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT                                       0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR                                                (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000028)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK                                                0xffff0001
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_POR                                                 0x00ff0000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_POR_RMSK                                            0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ATTR                                                       0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK                                 0xffff0000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT                                       0x10
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK                                      0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT                                      0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR                                                 (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000002c)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK                                                     0xffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_POR                                                  0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_POR_RMSK                                             0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ATTR                                                        0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK                                     0xffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT                                        0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR                                               (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000030)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK                                               0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_POR                                                0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_POR_RMSK                                           0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ATTR                                                      0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK                             0xffff0000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT                                   0x10
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK                                0xffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT                                   0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR                                             (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000034)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK                                                0xfffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_POR                                              0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_POR_RMSK                                         0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ATTR                                                    0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK                              0xe0000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT                                 0x11
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK                                 0x10000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT                                    0x10
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK                                 0xffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT                                    0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR                                             (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000038)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK                                                0xfffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_POR                                              0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_POR_RMSK                                         0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ATTR                                                    0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK                              0xe0000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT                                 0x11
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK                                 0x10000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT                                    0x10
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK                                 0xffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT                                    0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR                                   (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000003c)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK                                   0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_POR                                    0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_POR_RMSK                               0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ATTR                                          0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK                             0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT                                    0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR                                   (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000040)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK                                   0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_POR                                    0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_POR_RMSK                               0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ATTR                                          0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK                             0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT                                    0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR                                   (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000044)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK                                   0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_POR                                    0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_POR_RMSK                               0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ATTR                                          0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK                             0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT                                    0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR                                   (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000048)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK                                   0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_POR                                    0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_POR_RMSK                               0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ATTR                                          0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK                             0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT                                    0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR                                                       (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000004c)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK                                                        0x1ffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_POR                                                        0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_POR_RMSK                                                   0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ATTR                                                              0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_BMSK                                                0x1000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_SHFT                                                     0x18
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_BMSK                                             0xfff000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT                                                  0xc
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK                                                0xfff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT                                                  0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR                                                       (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000050)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK                                                            0xfff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_POR                                                        0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_POR_RMSK                                                   0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ATTR                                                              0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK                                                0xfff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT                                                  0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR                                                        (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000054)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK                                                          0xffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_POR                                                         0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_POR_RMSK                                                    0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ATTR                                                               0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK                                                     0xfff000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT                                                          0xc
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK                                                         0xfff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT                                                           0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR                                                     (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000058)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK                                                      0x1ffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_POR                                                      0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_POR_RMSK                                                 0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ATTR                                                            0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_BMSK                                              0x1000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_SHFT                                                   0x18
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_BMSK                                           0xfff000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_SHFT                                                0xc
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK                                              0xfff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT                                                0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR                                                     (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000005c)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK                                                          0xfff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_POR                                                      0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_POR_RMSK                                                 0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ATTR                                                            0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK                                              0xfff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT                                                0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR                                            (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000060)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK                                            0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_POR                                             0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_POR_RMSK                                        0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ATTR                                                   0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK                                     0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT                                            0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR                                            (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000064)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK                                            0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_POR                                             0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_POR_RMSK                                        0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ATTR                                                   0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK                                     0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT                                            0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR                                            (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000068)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK                                                   0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_POR                                             0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_POR_RMSK                                        0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ATTR                                                   0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_BMSK                                            0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_SHFT                                            0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR                                                 (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000006c)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK                                                 0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POR                                                  0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POR_RMSK                                             0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ATTR                                                        0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_BMSK                                          0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_SHFT                                                 0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR                                                 (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000070)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK                                                 0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POR                                                  0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POR_RMSK                                             0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ATTR                                                        0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_BMSK                                          0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_SHFT                                                 0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR                                                 (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000074)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK                                                        0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POR                                                  0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POR_RMSK                                             0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ATTR                                                        0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_BMSK                                                 0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_SHFT                                                 0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR                                                     (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000078)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK                                                     0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_POR                                                      0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_POR_RMSK                                                 0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ATTR                                                            0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK                                               0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT                                                      0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR                                                     (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000007c)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK                                                     0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_POR                                                      0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_POR_RMSK                                                 0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ATTR                                                            0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK                                               0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT                                                      0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR                                                     (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000080)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK                                                     0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_POR                                                      0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_POR_RMSK                                                 0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ATTR                                                            0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK                                               0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT                                                      0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR                                                     (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000084)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK                                                     0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_POR                                                      0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_POR_RMSK                                                 0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ATTR                                                            0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK                                               0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT                                                      0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR                                                  (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000088)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK                                                  0xfffdffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_POR                                                   0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_POR_RMSK                                              0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ATTR                                                         0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CLK_EXTEND_BMSK                                       0x80000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CLK_EXTEND_SHFT                                             0x1f
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_WRAPPER_REG_CLK_BMSK                                  0x40000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_WRAPPER_REG_CLK_SHFT                                        0x1e
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_REG_CLK_BMSK                                      0x3ffc0000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_REG_CLK_SHFT                                            0x12
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_BMSK                                              0x10000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_SHFT                                                 0x10
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_BMSK                                              0xf000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_SHFT                                                 0xc
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_BMSK                                          0xfff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_SHFT                                            0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR                                                  (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000008c)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK                                                    0xffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_POR                                                   0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_POR_RMSK                                              0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ATTR                                                         0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_DST_SRNG_CLK_BMSK                                       0xfff000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_DST_SRNG_CLK_SHFT                                            0xc
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_BMSK                                          0xfff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_SHFT                                            0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR                                                  (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000090)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK                                                      0x1fff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_POR                                                   0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_POR_RMSK                                              0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ATTR                                                         0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_TZ_CLK_BMSK                                               0x1000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_TZ_CLK_SHFT                                                  0xc
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_BMSK                                          0xfff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_SHFT                                            0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR                                                     (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000094)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK                                                          0xfff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_POR                                                      0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_POR_RMSK                                                 0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ATTR                                                            0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_BMSK                                                 0xfff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_SHFT                                                   0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR                                            (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000098)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK                                            0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_POR                                             0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_POR_RMSK                                        0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ATTR                                                   0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_BMSK                                      0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_SHFT                                             0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR                                                 (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000009c)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK                                                 0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_POR                                                  0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_POR_RMSK                                             0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ATTR                                                        0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_BMSK                                             0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_SHFT                                                    0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR                                                       (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000400)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK                                                          0x100ff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_POR                                                        0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_POR_RMSK                                                   0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ATTR                                                              0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK                     0x10000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT                        0x10
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK                                          0xff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT                                           0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR                                                     (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000404)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK                                                     0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_POR                                                      0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_POR_RMSK                                                 0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ATTR                                                            0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK                                                0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT                                                       0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR                                                     (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000408)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK                                                     0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_POR                                                      0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_POR_RMSK                                                 0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ATTR                                                            0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK                                                0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT                                                       0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR                                                        (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x0000040c)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK                                                        0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_POR                                                         0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_POR_RMSK                                                    0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_ATTR                                                               0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK                                                    0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT                                                           0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR                                                       (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000410)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK                                                             0xff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_POR                                                        0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_POR_RMSK                                                   0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ATTR                                                              0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK                                                         0xff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT                                                          0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR                                          (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000414)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK                                          0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_POR                                           0x7ffe0002
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_POR_RMSK                                      0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ATTR                                                 0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK                        0xfffe0000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT                              0x11
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK                         0x1fffc
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT                             0x2
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK                      0x2
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT                      0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK                       0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT                       0x0
-
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR                                                  (CE_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE      + 0x00000418)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK                                                         0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_POR                                                   0x00000000
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_POR_RMSK                                              0xffffffff
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ATTR                                                         0x3
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN          \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR, HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(m)      \
-        in_dword_masked(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR, m)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(v)      \
-        out_dword(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR,v)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(m,v) \
-        out_dword_masked_ns(HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR,m,v,HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN)
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK                                  0x1
-#define HWIO_CE_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT                                  0x0
-
-#endif /* __MSMHWIOREG_H__ */

+ 59 - 9
hw/qcn9000/phyrx_rssi_legacy.h

@@ -30,7 +30,7 @@
 //	3-18	struct receive_rssi_info pre_rssi_info_details;
 //	19-34	struct receive_rssi_info preamble_rssi_info_details;
 //	35	pre_rssi_comb[7:0], rssi_comb[15:8], normalized_pre_rssi_comb[23:16], normalized_rssi_comb[31:24]
-//	36	rssi_comb_ppdu[7:0], rssi_db_to_dbm_offset[15:8], reserved_36a[31:16]
+//	36	rssi_comb_ppdu[7:0], rssi_db_to_dbm_offset[15:8], rssi_for_spatial_reuse[23:16], rssi_for_trigger_resp[31:24]
 //
 // ################ END SUMMARY #################
 
@@ -53,7 +53,8 @@ struct phyrx_rssi_legacy {
                       normalized_rssi_comb            :  8; //[31:24]
              uint32_t rssi_comb_ppdu                  :  8, //[7:0]
                       rssi_db_to_dbm_offset           :  8, //[15:8]
-                      reserved_36a                    : 16; //[31:16]
+                      rssi_for_spatial_reuse          :  8, //[23:16]
+                      rssi_for_trigger_resp           :  8; //[31:24]
 };
 
 /*
@@ -433,9 +434,43 @@ rssi_db_to_dbm_offset
 			
 			<legal all>
 
-reserved_36a
+rssi_for_spatial_reuse
 			
-			<legal 0>
+			<legal all>
+
+rssi_for_trigger_resp
+			
+			RSSI to be used by PDG for transmit (power) selection
+			during trigger response, reported as an 8-bit signed value
+			
+			
+			
+			The resolution can be: 
+			
+			1dB or 0.5dB. This is statically configured within the
+			PHY and MAC
+			
+			
+			
+			In case of 1dB, the Range is:
+			
+			 -128dB to 127dB
+			
+			
+			
+			In case of 0.5dB, the Range is:
+			
+			 -64dB to 63.5dB
+			
+			
+			
+			As per 802.11ax draft 3.3 subsubclauses 28.3.14.2, for
+			trigger response, the received power should be measured from
+			the non-HE portion of the preamble of the PPDU containing
+			the trigger, normalized to 20 MHz, averaged over the
+			antennas over which the average pathloss is being computed.
+			
+			<legal all>
 */
 
 
@@ -2250,13 +2285,28 @@ reserved_36a
 #define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_LSB               8
 #define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_MASK              0x0000ff00
 
-/* Description		PHYRX_RSSI_LEGACY_36_RESERVED_36A
+/* Description		PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE
 			
-			<legal 0>
+			RSSI to be used by HWSCH for transmit (power) selection
+			during an SR opportunity, reported as an 8-bit signed value
+			
+			<legal all>
+*/
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_OFFSET           0x00000090
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_LSB              16
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_MASK             0x00ff0000
+
+/* Description		PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP
+			
+			RSSI to be used by PDG for transmit (power) selection
+			during trigger response, reported as an 8-bit signed value
+			
+			
+			<legal all>
 */
-#define PHYRX_RSSI_LEGACY_36_RESERVED_36A_OFFSET                     0x00000090
-#define PHYRX_RSSI_LEGACY_36_RESERVED_36A_LSB                        16
-#define PHYRX_RSSI_LEGACY_36_RESERVED_36A_MASK                       0xffff0000
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_OFFSET            0x00000090
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_LSB               24
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_MASK              0xff000000
 
 
 #endif // _PHYRX_RSSI_LEGACY_H_

+ 109 - 15
hw/qcn9000/reo_destination_ring.h

@@ -31,8 +31,8 @@
 //	4-5	struct rx_msdu_desc_info rx_msdu_desc_info_details;
 //	6	rx_reo_queue_desc_addr_31_0[31:0]
 //	7	rx_reo_queue_desc_addr_39_32[7:0], reo_dest_buffer_type[8], reo_push_reason[10:9], reo_error_code[15:11], receive_queue_number[31:16]
-//	8	soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], mpdu_fragment_number[16:13], reserved_8a[31:17]
-//	9	reserved_9a[31:0]
+//	8	soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], mpdu_fragment_number[16:13], captured_msdu_data_size[20:17], sw_exception[21], reserved_8a[31:22]
+//	9	reo_destination_struct_signature[31:0]
 //	10	reserved_10a[31:0]
 //	11	reserved_11a[31:0]
 //	12	reserved_12a[31:0]
@@ -58,8 +58,10 @@ struct reo_destination_ring {
                       reorder_opcode                  :  4, //[4:1]
                       reorder_slot_index              :  8, //[12:5]
                       mpdu_fragment_number            :  4, //[16:13]
-                      reserved_8a                     : 15; //[31:17]
-             uint32_t reserved_9a                     : 32; //[31:0]
+                      captured_msdu_data_size         :  4, //[20:17]
+                      sw_exception                    :  1, //[21]
+                      reserved_8a                     : 10; //[31:22]
+             uint32_t reo_destination_struct_signature: 32; //[31:0]
              uint32_t reserved_10a                    : 32; //[31:0]
              uint32_t reserved_11a                    : 32; //[31:0]
              uint32_t reserved_12a                    : 32; //[31:0]
@@ -218,6 +220,9 @@ reo_error_code
 
 receive_queue_number
 			
+			This field in NOT valid (should be set to 0), when
+			SW_exception is set.
+			
 			This field indicates the REO MPDU reorder queue ID from
 			which this frame originated. This field is populated from a
 			field with the same name in the RX_REO_QUEUE descriptor.
@@ -226,6 +231,9 @@ receive_queue_number
 
 soft_reorder_info_valid
 			
+			This field in NOT valid (should be set to 0), when
+			SW_exception is set.
+			
 			When set, REO has been instructed to not perform the
 			actual re-ordering of frames for this queue, but just to
 			insert the reorder opcodes
@@ -306,15 +314,50 @@ mpdu_fragment_number
 			
 			
 			
+			<legal all>
+
+captured_msdu_data_size
+			
+			The number of following REO_DESTINATION STRUCTs that
+			have been replaced with msdu_data extracted from the
+			msdu_buffer and copied into the ring for easy FW/SW access.
+			
+			Note that it is possible that these STRUCTs wrap around
+			the end of the ring.
+			
+			Feature supported only in HastingsPrime
+			
+			<legal 0-4>
+
+sw_exception
+			
+			This field has the same setting as the SW_exception
+			field in the corresponding REO_entrance_ring descriptor.
+			
+			When set, the REO entrance descriptor is generated by
+			FW, and the MPDU was processed in the following way:
+			
+			- NO re-order function is needed.
+			
+			- MPDU delinking is determined by the setting of
+			Entrance ring field: SW_excection_mpdu_delink
+			
+			- Destination ring selection is based on the setting of
+			
+			Feature supported only in HastingsPrime
+			
 			<legal all>
 
 reserved_8a
 			
 			<legal 0>
 
-reserved_9a
+reo_destination_struct_signature
 			
-			<legal 0>
+			Set to value 0x8888_88888 when msdu capture mode is
+			enabled for this ring (supported only in HastingsPrime)
+			
+			<legal 0, 2290649224 >
 
 reserved_10a
 			
@@ -919,10 +962,12 @@ looping_count
 			the REO2FW ring
 			
 			<enum 7 reo_destination_sw5> Reo will push the frame
-			into the REO2SW5 ring 
+			into the REO2SW5 ring (REO remaps this in chips without
+			REO2SW5 ring, e.g. Pine) 
 			
 			<enum 8 reo_destination_sw6> Reo will push the frame
-			into the REO2SW6 ring 
+			into the REO2SW6 ring (REO remaps this in chips without
+			REO2SW6 ring, e.g. Pine)
 			
 			 <enum 9 reo_destination_9> REO remaps this <enum 10
 			reo_destination_10> REO remaps this 
@@ -1229,6 +1274,9 @@ looping_count
 
 /* Description		REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER
 			
+			This field in NOT valid (should be set to 0), when
+			SW_exception is set.
+			
 			This field indicates the REO MPDU reorder queue ID from
 			which this frame originated. This field is populated from a
 			field with the same name in the RX_REO_QUEUE descriptor.
@@ -1241,6 +1289,9 @@ looping_count
 
 /* Description		REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID
 			
+			This field in NOT valid (should be set to 0), when
+			SW_exception is set.
+			
 			When set, REO has been instructed to not perform the
 			actual re-ordering of frames for this queue, but just to
 			insert the reorder opcodes
@@ -1339,21 +1390,64 @@ looping_count
 #define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_LSB              13
 #define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_MASK             0x0001e000
 
+/* Description		REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE
+			
+			The number of following REO_DESTINATION STRUCTs that
+			have been replaced with msdu_data extracted from the
+			msdu_buffer and copied into the ring for easy FW/SW access.
+			
+			Note that it is possible that these STRUCTs wrap around
+			the end of the ring.
+			
+			Feature supported only in HastingsPrime
+			
+			<legal 0-4>
+*/
+#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_OFFSET        0x00000020
+#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_LSB           17
+#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_MASK          0x001e0000
+
+/* Description		REO_DESTINATION_RING_8_SW_EXCEPTION
+			
+			This field has the same setting as the SW_exception
+			field in the corresponding REO_entrance_ring descriptor.
+			
+			When set, the REO entrance descriptor is generated by
+			FW, and the MPDU was processed in the following way:
+			
+			- NO re-order function is needed.
+			
+			- MPDU delinking is determined by the setting of
+			Entrance ring field: SW_excection_mpdu_delink
+			
+			- Destination ring selection is based on the setting of
+			
+			Feature supported only in HastingsPrime
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_8_SW_EXCEPTION_OFFSET                   0x00000020
+#define REO_DESTINATION_RING_8_SW_EXCEPTION_LSB                      21
+#define REO_DESTINATION_RING_8_SW_EXCEPTION_MASK                     0x00200000
+
 /* Description		REO_DESTINATION_RING_8_RESERVED_8A
 			
 			<legal 0>
 */
 #define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET                    0x00000020
-#define REO_DESTINATION_RING_8_RESERVED_8A_LSB                       17
-#define REO_DESTINATION_RING_8_RESERVED_8A_MASK                      0xfffe0000
+#define REO_DESTINATION_RING_8_RESERVED_8A_LSB                       22
+#define REO_DESTINATION_RING_8_RESERVED_8A_MASK                      0xffc00000
 
-/* Description		REO_DESTINATION_RING_9_RESERVED_9A
+/* Description		REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE
 			
-			<legal 0>
+			Set to value 0x8888_88888 when msdu capture mode is
+			enabled for this ring (supported only in HastingsPrime)
+			
+			<legal 0, 2290649224 >
 */
-#define REO_DESTINATION_RING_9_RESERVED_9A_OFFSET                    0x00000024
-#define REO_DESTINATION_RING_9_RESERVED_9A_LSB                       0
-#define REO_DESTINATION_RING_9_RESERVED_9A_MASK                      0xffffffff
+#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x00000024
+#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_LSB  0
+#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0xffffffff
 
 /* Description		REO_DESTINATION_RING_10_RESERVED_10A
 			

+ 357 - 12
hw/qcn9000/reo_entrance_ring.h

@@ -27,8 +27,8 @@
 //	0-3	struct rx_mpdu_details reo_level_mpdu_frame_info;
 //	4	rx_reo_queue_desc_addr_31_0[31:0]
 //	5	rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28]
-//	6	rxdma_push_reason[1:0], rxdma_error_code[6:2], mpdu_fragment_number[10:7], reserved_6a[31:11]
-//	7	reserved_7a[19:0], ring_id[27:20], looping_count[31:28]
+//	6	rxdma_push_reason[1:0], rxdma_error_code[6:2], mpdu_fragment_number[10:7], sw_exception[11], sw_exception_mpdu_delink[12], sw_exception_destination_ring_valid[13], sw_exception_destination_ring[18:14], reserved_6a[31:19]
+//	7	phy_ppdu_id[15:0], reserved_7a[19:16], ring_id[27:20], looping_count[31:28]
 //
 // ################ END SUMMARY #################
 
@@ -45,8 +45,13 @@ struct reo_entrance_ring {
              uint32_t rxdma_push_reason               :  2, //[1:0]
                       rxdma_error_code                :  5, //[6:2]
                       mpdu_fragment_number            :  4, //[10:7]
-                      reserved_6a                     : 21; //[31:11]
-             uint32_t reserved_7a                     : 20, //[19:0]
+                      sw_exception                    :  1, //[11]
+                      sw_exception_mpdu_delink        :  1, //[12]
+                      sw_exception_destination_ring_valid:  1, //[13]
+                      sw_exception_destination_ring   :  5, //[18:14]
+                      reserved_6a                     : 13; //[31:19]
+             uint32_t phy_ppdu_id                     : 16, //[15:0]
+                      reserved_7a                     :  4, //[19:16]
                       ring_id                         :  8, //[27:20]
                       looping_count                   :  4; //[31:28]
 };
@@ -133,10 +138,12 @@ reo_destination_indication
 			the REO2FW ring
 			
 			<enum 7 reo_destination_sw5> Reo will push the frame
-			into the REO2SW5 ring
+			into the REO2SW5 ring (REO remaps this in chips without
+			REO2SW5 ring, e.g. Pine)
 			
 			<enum 8 reo_destination_sw6> Reo will push the frame
-			into the REO2SW6 ring 
+			into the REO2SW6 ring (REO remaps this in chips without
+			REO2SW6 ring, e.g. Pine)
 			
 			 <enum 9 reo_destination_9> REO remaps this <enum 10
 			reo_destination_10> REO remaps this 
@@ -328,12 +335,170 @@ mpdu_fragment_number
 			
 			
 			
+			<legal all>
+
+sw_exception
+			
+			When not set, REO is performing all its default MPDU
+			processing operations,
+			
+			When set, this REO entrance descriptor is generated by
+			FW, and should be processed as an exception. This implies: 
+			
+			NO re-order function is needed.
+			
+			MPDU delinking is determined by the setting of field
+			SW_excection_mpdu_delink
+			
+			Destination ring selection is based on the setting of
+			the field SW_exception_destination_ring_valid
+			
+			In the destination ring descriptor set bit:
+			SW_exception_entry
+			
+			Feature supported only in HastingsPrime
+			
+			<legal all>
+
+sw_exception_mpdu_delink
+			
+			Field only valid when SW_exception is set.
+			
+			1'b0: REO should NOT delink the MPDU, and thus pass this
+			MPDU on to the destination ring as is. This implies that in
+			the REO_DESTINATION_RING struct field
+			Buf_or_link_desc_addr_info should point to an MSDU link
+			descriptor
+			
+			1'b1: REO should perform the normal MPDU delink into
+			MSDU operations.
+			
+			Feature supported only in HastingsPrime
+			
+			<legal all>
+
+sw_exception_destination_ring_valid
+			
+			Field only valid when SW_exception is set.
+			
+			1'b0: REO shall push the MPDU (or delinked MPDU based on
+			the setting of SW_exception_mpdu_delink) to the destination
+			ring according to field reo_destination_indication.
+			
+			1'b1: REO shall push the MPDU (or delinked MPDU based on
+			the setting of SW_exception_mpdu_delink) to the destination
+			ring according to field SW_exception_destination_ring.
+			
+			Feature supported only in HastingsPrime
+			
+			<legal all>
+
+sw_exception_destination_ring
+			
+			Field only valid when fields SW_exception and
+			SW_exception_destination_ring_valid are set.
+			
+			The ID of the ring where REO shall push this frame.
+			
+			<enum 0 reo_destination_tcl> Reo will push the frame
+			into the REO2TCL ring
+			
+			<enum 1 reo_destination_sw1> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 2 reo_destination_sw2> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 3 reo_destination_sw3> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 4 reo_destination_sw4> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 5 reo_destination_release> Reo will push the frame
+			into the REO_release ring
+			
+			<enum 6 reo_destination_fw> Reo will push the frame into
+			the REO2FW ring
+			
+			<enum 7 reo_destination_sw5> REO remaps this
+			
+			<enum 8 reo_destination_sw6> REO remaps this 
+			
+			<enum 9 reo_destination_9> REO remaps this
+			
+			<enum 10 reo_destination_10> REO remaps this 
+			
+			<enum 11 reo_destination_11> REO remaps this 
+			
+			<enum 12 reo_destination_12> REO remaps this <enum 13
+			reo_destination_13> REO remaps this 
+			
+			<enum 14 reo_destination_14> REO remaps this 
+			
+			<enum 15 reo_destination_15> REO remaps this 
+			
+			<enum 16 reo_destination_16> REO remaps this 
+			
+			<enum 17 reo_destination_17> REO remaps this 
+			
+			<enum 18 reo_destination_18> REO remaps this 
+			
+			<enum 19 reo_destination_19> REO remaps this 
+			
+			<enum 20 reo_destination_20> REO remaps this 
+			
+			<enum 21 reo_destination_21> REO remaps this 
+			
+			<enum 22 reo_destination_22> REO remaps this 
+			
+			<enum 23 reo_destination_23> REO remaps this 
+			
+			<enum 24 reo_destination_24> REO remaps this 
+			
+			<enum 25 reo_destination_25> REO remaps this 
+			
+			<enum 26 reo_destination_26> REO remaps this 
+			
+			<enum 27 reo_destination_27> REO remaps this 
+			
+			<enum 28 reo_destination_28> REO remaps this 
+			
+			<enum 29 reo_destination_29> REO remaps this 
+			
+			<enum 30 reo_destination_30> REO remaps this 
+			
+			<enum 31 reo_destination_31> REO remaps this 
+			
+			
+			
+			Feature supported only in HastingsPrime
+			
 			<legal all>
 
 reserved_6a
 			
 			<legal 0>
 
+phy_ppdu_id
+			
+			A PPDU counter value that PHY increments for every PPDU
+			received
+			
+			The counter value wraps around. Pine RXDMA can be
+			configured to copy this from the RX_PPDU_START TLV for every
+			output descriptor.
+			
+			
+			
+			This field is ignored by REO.
+			
+			
+			
+			Feature supported only in Pine
+			
+			<legal all>
+
 reserved_7a
 			
 			<legal 0>
@@ -877,10 +1042,12 @@ looping_count
 			the REO2FW ring
 			
 			<enum 7 reo_destination_sw5> Reo will push the frame
-			into the REO2SW5 ring
+			into the REO2SW5 ring (REO remaps this in chips without
+			REO2SW5 ring, e.g. Pine)
 			
 			<enum 8 reo_destination_sw6> Reo will push the frame
-			into the REO2SW6 ring 
+			into the REO2SW6 ring (REO remaps this in chips without
+			REO2SW6 ring, e.g. Pine)
 			
 			 <enum 9 reo_destination_9> REO remaps this <enum 10
 			reo_destination_10> REO remaps this 
@@ -1098,21 +1265,199 @@ looping_count
 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_LSB                 7
 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_MASK                0x00000780
 
+/* Description		REO_ENTRANCE_RING_6_SW_EXCEPTION
+			
+			When not set, REO is performing all its default MPDU
+			processing operations,
+			
+			When set, this REO entrance descriptor is generated by
+			FW, and should be processed as an exception. This implies: 
+			
+			NO re-order function is needed.
+			
+			MPDU delinking is determined by the setting of field
+			SW_excection_mpdu_delink
+			
+			Destination ring selection is based on the setting of
+			the field SW_exception_destination_ring_valid
+			
+			In the destination ring descriptor set bit:
+			SW_exception_entry
+			
+			Feature supported only in HastingsPrime
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_OFFSET                      0x00000018
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_LSB                         11
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MASK                        0x00000800
+
+/* Description		REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK
+			
+			Field only valid when SW_exception is set.
+			
+			1'b0: REO should NOT delink the MPDU, and thus pass this
+			MPDU on to the destination ring as is. This implies that in
+			the REO_DESTINATION_RING struct field
+			Buf_or_link_desc_addr_info should point to an MSDU link
+			descriptor
+			
+			1'b1: REO should perform the normal MPDU delink into
+			MSDU operations.
+			
+			Feature supported only in HastingsPrime
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_OFFSET          0x00000018
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_LSB             12
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_MASK            0x00001000
+
+/* Description		REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID
+			
+			Field only valid when SW_exception is set.
+			
+			1'b0: REO shall push the MPDU (or delinked MPDU based on
+			the setting of SW_exception_mpdu_delink) to the destination
+			ring according to field reo_destination_indication.
+			
+			1'b1: REO shall push the MPDU (or delinked MPDU based on
+			the setting of SW_exception_mpdu_delink) to the destination
+			ring according to field SW_exception_destination_ring.
+			
+			Feature supported only in HastingsPrime
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_LSB  13
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000
+
+/* Description		REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING
+			
+			Field only valid when fields SW_exception and
+			SW_exception_destination_ring_valid are set.
+			
+			The ID of the ring where REO shall push this frame.
+			
+			<enum 0 reo_destination_tcl> Reo will push the frame
+			into the REO2TCL ring
+			
+			<enum 1 reo_destination_sw1> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 2 reo_destination_sw2> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 3 reo_destination_sw3> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 4 reo_destination_sw4> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 5 reo_destination_release> Reo will push the frame
+			into the REO_release ring
+			
+			<enum 6 reo_destination_fw> Reo will push the frame into
+			the REO2FW ring
+			
+			<enum 7 reo_destination_sw5> REO remaps this
+			
+			<enum 8 reo_destination_sw6> REO remaps this 
+			
+			<enum 9 reo_destination_9> REO remaps this
+			
+			<enum 10 reo_destination_10> REO remaps this 
+			
+			<enum 11 reo_destination_11> REO remaps this 
+			
+			<enum 12 reo_destination_12> REO remaps this <enum 13
+			reo_destination_13> REO remaps this 
+			
+			<enum 14 reo_destination_14> REO remaps this 
+			
+			<enum 15 reo_destination_15> REO remaps this 
+			
+			<enum 16 reo_destination_16> REO remaps this 
+			
+			<enum 17 reo_destination_17> REO remaps this 
+			
+			<enum 18 reo_destination_18> REO remaps this 
+			
+			<enum 19 reo_destination_19> REO remaps this 
+			
+			<enum 20 reo_destination_20> REO remaps this 
+			
+			<enum 21 reo_destination_21> REO remaps this 
+			
+			<enum 22 reo_destination_22> REO remaps this 
+			
+			<enum 23 reo_destination_23> REO remaps this 
+			
+			<enum 24 reo_destination_24> REO remaps this 
+			
+			<enum 25 reo_destination_25> REO remaps this 
+			
+			<enum 26 reo_destination_26> REO remaps this 
+			
+			<enum 27 reo_destination_27> REO remaps this 
+			
+			<enum 28 reo_destination_28> REO remaps this 
+			
+			<enum 29 reo_destination_29> REO remaps this 
+			
+			<enum 30 reo_destination_30> REO remaps this 
+			
+			<enum 31 reo_destination_31> REO remaps this 
+			
+			
+			
+			Feature supported only in HastingsPrime
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_OFFSET     0x00000018
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_LSB        14
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_MASK       0x0007c000
+
 /* Description		REO_ENTRANCE_RING_6_RESERVED_6A
 			
 			<legal 0>
 */
 #define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET                       0x00000018
-#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB                          11
-#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK                         0xfffff800
+#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB                          19
+#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK                         0xfff80000
+
+/* Description		REO_ENTRANCE_RING_7_PHY_PPDU_ID
+			
+			A PPDU counter value that PHY increments for every PPDU
+			received
+			
+			The counter value wraps around. Pine RXDMA can be
+			configured to copy this from the RX_PPDU_START TLV for every
+			output descriptor.
+			
+			
+			
+			This field is ignored by REO.
+			
+			
+			
+			Feature supported only in Pine
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_OFFSET                       0x0000001c
+#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_LSB                          0
+#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_MASK                         0x0000ffff
 
 /* Description		REO_ENTRANCE_RING_7_RESERVED_7A
 			
 			<legal 0>
 */
 #define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET                       0x0000001c
-#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB                          0
-#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK                         0x000fffff
+#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB                          16
+#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK                         0x000f0000
 
 /* Description		REO_ENTRANCE_RING_7_RING_ID
 			

+ 197 - 53
hw/qcn9000/reo_reg_seq_hwioreg.h

@@ -15,10 +15,7 @@
  */
 
 ///////////////////////////////////////////////////////////////////////////////////////////////
-//
-///////////////////////////////////////////////////////////////////////////////////////////////
-//
-// reo_reg_seq_hwioreg.h : automatically generated by Autoseq  3.8 3/6/2019 
+// reo_reg_seq_hwioreg.h : automatically generated by Autoseq  3.8 7/1/2019 
 // User Name:pbechana
 //
 // !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
@@ -8028,10 +8025,129 @@
 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK     0x0000ffff
 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT            0x0
 
+//// Register REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 ////
+
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x)        (x+0x00000670)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x)        (x+0x00000670)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK           0xffffffff
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_SHFT                    0
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)          \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, mask)   \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, val)    \
+	out_dword( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK     0xffffffff
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT            0x0
+
+//// Register REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 ////
+
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x)        (x+0x00000674)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x)        (x+0x00000674)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK           0xffffffff
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_SHFT                    0
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)          \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, mask)   \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, val)    \
+	out_dword( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK     0xffffffff
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT            0x0
+
+//// Register REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 ////
+
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x)        (x+0x00000678)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x)        (x+0x00000678)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK           0xffffffff
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_SHFT                    0
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)          \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, mask)   \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, val)    \
+	out_dword( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK     0xffffffff
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT            0x0
+
+//// Register REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 ////
+
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x)        (x+0x0000067c)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x)        (x+0x0000067c)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK           0xffffffff
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_SHFT                    0
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)          \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, mask)   \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, val)    \
+	out_dword( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK     0xffffffff
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT            0x0
+
+//// Register REO_R0_GXI_GXI_AXI_OUTSANDING_CTL ////
+
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x)               (x+0x00000680)
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x)               (x+0x00000680)
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK                  0x00009f9f
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_SHFT                           0
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK)
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK        0x00008000
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT               0xf
+
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK       0x00001f00
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT              0x8
+
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK        0x00000080
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT               0x7
+
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK       0x0000001f
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT              0x0
+
 //// Register REO_R0_CACHE_CTL_CONFIG ////
 
-#define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x)                         (x+0x00000670)
-#define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x)                         (x+0x00000670)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x)                         (x+0x00000684)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x)                         (x+0x00000684)
 #define HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK                            0xffffffff
 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SHFT                                     0
 #define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)                           \
@@ -8079,9 +8195,9 @@
 
 //// Register REO_R0_CACHE_CTL_CONTROL ////
 
-#define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x)                        (x+0x00000674)
-#define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x)                        (x+0x00000674)
-#define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK                           0x00000001
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x)                        (x+0x00000688)
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x)                        (x+0x00000688)
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK                           0x00000003
 #define HWIO_REO_R0_CACHE_CTL_CONTROL_SHFT                                    0
 #define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)                          \
 	in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK)
@@ -8096,13 +8212,16 @@
 		HWIO_INTFREE();\
 	} while (0) 
 
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_BMSK 0x00000002
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_SHFT        0x1
+
 #define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK               0x00000001
 #define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT                      0x0
 
 //// Register REO_R0_CACHE_CTL_CONFIG_SET ////
 
-#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x)                     (x+0x00000678)
-#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_PHYS(x)                     (x+0x00000678)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x)                     (x+0x0000068c)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_PHYS(x)                     (x+0x0000068c)
 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK                        0x01ffffff
 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_SHFT                                 0
 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x)                       \
@@ -8129,8 +8248,8 @@
 
 //// Register REO_R0_CACHE_CTL_SET_SIZE ////
 
-#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x)                       (x+0x0000067c)
-#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_PHYS(x)                       (x+0x0000067c)
+#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x)                       (x+0x00000690)
+#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_PHYS(x)                       (x+0x00000690)
 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK                          0x000001ff
 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SHFT                                   0
 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x)                         \
@@ -8151,8 +8270,8 @@
 
 //// Register REO_R0_CLK_GATE_CTRL ////
 
-#define HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x)                            (x+0x00000680)
-#define HWIO_REO_R0_CLK_GATE_CTRL_PHYS(x)                            (x+0x00000680)
+#define HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x)                            (x+0x00000694)
+#define HWIO_REO_R0_CLK_GATE_CTRL_PHYS(x)                            (x+0x00000694)
 #define HWIO_REO_R0_CLK_GATE_CTRL_RMSK                               0x0007ffff
 #define HWIO_REO_R0_CLK_GATE_CTRL_SHFT                                        0
 #define HWIO_REO_R0_CLK_GATE_CTRL_IN(x)                              \
@@ -8200,8 +8319,8 @@
 
 //// Register REO_R0_EVENTMASK_IX_0 ////
 
-#define HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x)                           (x+0x00000684)
-#define HWIO_REO_R0_EVENTMASK_IX_0_PHYS(x)                           (x+0x00000684)
+#define HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x)                           (x+0x00000698)
+#define HWIO_REO_R0_EVENTMASK_IX_0_PHYS(x)                           (x+0x00000698)
 #define HWIO_REO_R0_EVENTMASK_IX_0_RMSK                              0xffffffff
 #define HWIO_REO_R0_EVENTMASK_IX_0_SHFT                                       0
 #define HWIO_REO_R0_EVENTMASK_IX_0_IN(x)                             \
@@ -8222,8 +8341,8 @@
 
 //// Register REO_R0_EVENTMASK_IX_1 ////
 
-#define HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x)                           (x+0x00000688)
-#define HWIO_REO_R0_EVENTMASK_IX_1_PHYS(x)                           (x+0x00000688)
+#define HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x)                           (x+0x0000069c)
+#define HWIO_REO_R0_EVENTMASK_IX_1_PHYS(x)                           (x+0x0000069c)
 #define HWIO_REO_R0_EVENTMASK_IX_1_RMSK                              0xffffffff
 #define HWIO_REO_R0_EVENTMASK_IX_1_SHFT                                       0
 #define HWIO_REO_R0_EVENTMASK_IX_1_IN(x)                             \
@@ -8244,8 +8363,8 @@
 
 //// Register REO_R0_EVENTMASK_IX_2 ////
 
-#define HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x)                           (x+0x0000068c)
-#define HWIO_REO_R0_EVENTMASK_IX_2_PHYS(x)                           (x+0x0000068c)
+#define HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x)                           (x+0x000006a0)
+#define HWIO_REO_R0_EVENTMASK_IX_2_PHYS(x)                           (x+0x000006a0)
 #define HWIO_REO_R0_EVENTMASK_IX_2_RMSK                              0xffffffff
 #define HWIO_REO_R0_EVENTMASK_IX_2_SHFT                                       0
 #define HWIO_REO_R0_EVENTMASK_IX_2_IN(x)                             \
@@ -8266,8 +8385,8 @@
 
 //// Register REO_R0_EVENTMASK_IX_3 ////
 
-#define HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x)                           (x+0x00000690)
-#define HWIO_REO_R0_EVENTMASK_IX_3_PHYS(x)                           (x+0x00000690)
+#define HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x)                           (x+0x000006a4)
+#define HWIO_REO_R0_EVENTMASK_IX_3_PHYS(x)                           (x+0x000006a4)
 #define HWIO_REO_R0_EVENTMASK_IX_3_RMSK                              0xffffffff
 #define HWIO_REO_R0_EVENTMASK_IX_3_SHFT                                       0
 #define HWIO_REO_R0_EVENTMASK_IX_3_IN(x)                             \
@@ -8627,10 +8746,35 @@
 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_BMSK      0xffffffff
 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_SHFT             0x0
 
+//// Register REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x)       (x+0x00002038)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_PHYS(x)       (x+0x00002038)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK          0x000fffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SHFT                   0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x)         \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_INM(x, mask)  \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), mask) 
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUT(x, val)   \
+	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_BMSK     0x000ffc00
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_SHFT            0xa
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_BMSK     0x000003ff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_SHFT            0x0
+
 //// Register REO_R1_CACHE_CTL_END_OF_TEST_CHECK ////
 
-#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x)              (x+0x00002038)
-#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x)              (x+0x00002038)
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x)              (x+0x0000203c)
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x)              (x+0x0000203c)
 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK                 0x00000001
 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_SHFT                          0
 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)                \
@@ -8651,8 +8795,8 @@
 
 //// Register REO_R1_END_OF_TEST_CHECK ////
 
-#define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x)                        (x+0x0000203c)
-#define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x)                        (x+0x0000203c)
+#define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x)                        (x+0x00002040)
+#define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x)                        (x+0x00002040)
 #define HWIO_REO_R1_END_OF_TEST_CHECK_RMSK                           0x00000001
 #define HWIO_REO_R1_END_OF_TEST_CHECK_SHFT                                    0
 #define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)                          \
@@ -8673,8 +8817,8 @@
 
 //// Register REO_R1_SM_ALL_IDLE ////
 
-#define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x)                              (x+0x00002040)
-#define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x)                              (x+0x00002040)
+#define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x)                              (x+0x00002044)
+#define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x)                              (x+0x00002044)
 #define HWIO_REO_R1_SM_ALL_IDLE_RMSK                                 0x00000007
 #define HWIO_REO_R1_SM_ALL_IDLE_SHFT                                          0
 #define HWIO_REO_R1_SM_ALL_IDLE_IN(x)                                \
@@ -8701,8 +8845,8 @@
 
 //// Register REO_R1_TESTBUS_CTRL ////
 
-#define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x)                             (x+0x00002044)
-#define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x)                             (x+0x00002044)
+#define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x)                             (x+0x00002048)
+#define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x)                             (x+0x00002048)
 #define HWIO_REO_R1_TESTBUS_CTRL_RMSK                                0x0000007f
 #define HWIO_REO_R1_TESTBUS_CTRL_SHFT                                         0
 #define HWIO_REO_R1_TESTBUS_CTRL_IN(x)                               \
@@ -8723,8 +8867,8 @@
 
 //// Register REO_R1_TESTBUS_LOWER ////
 
-#define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x)                            (x+0x00002048)
-#define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x)                            (x+0x00002048)
+#define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x)                            (x+0x0000204c)
+#define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x)                            (x+0x0000204c)
 #define HWIO_REO_R1_TESTBUS_LOWER_RMSK                               0xffffffff
 #define HWIO_REO_R1_TESTBUS_LOWER_SHFT                                        0
 #define HWIO_REO_R1_TESTBUS_LOWER_IN(x)                              \
@@ -8745,8 +8889,8 @@
 
 //// Register REO_R1_TESTBUS_HIGHER ////
 
-#define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x)                           (x+0x0000204c)
-#define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x)                           (x+0x0000204c)
+#define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x)                           (x+0x00002050)
+#define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x)                           (x+0x00002050)
 #define HWIO_REO_R1_TESTBUS_HIGHER_RMSK                              0x000000ff
 #define HWIO_REO_R1_TESTBUS_HIGHER_SHFT                                       0
 #define HWIO_REO_R1_TESTBUS_HIGHER_IN(x)                             \
@@ -8767,8 +8911,8 @@
 
 //// Register REO_R1_SM_STATES_IX_0 ////
 
-#define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x)                           (x+0x00002050)
-#define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x)                           (x+0x00002050)
+#define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x)                           (x+0x00002054)
+#define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x)                           (x+0x00002054)
 #define HWIO_REO_R1_SM_STATES_IX_0_RMSK                              0xffffffff
 #define HWIO_REO_R1_SM_STATES_IX_0_SHFT                                       0
 #define HWIO_REO_R1_SM_STATES_IX_0_IN(x)                             \
@@ -8789,8 +8933,8 @@
 
 //// Register REO_R1_SM_STATES_IX_1 ////
 
-#define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x)                           (x+0x00002054)
-#define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x)                           (x+0x00002054)
+#define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x)                           (x+0x00002058)
+#define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x)                           (x+0x00002058)
 #define HWIO_REO_R1_SM_STATES_IX_1_RMSK                              0xffffffff
 #define HWIO_REO_R1_SM_STATES_IX_1_SHFT                                       0
 #define HWIO_REO_R1_SM_STATES_IX_1_IN(x)                             \
@@ -8811,8 +8955,8 @@
 
 //// Register REO_R1_SM_STATES_IX_2 ////
 
-#define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x)                           (x+0x00002058)
-#define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x)                           (x+0x00002058)
+#define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x)                           (x+0x0000205c)
+#define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x)                           (x+0x0000205c)
 #define HWIO_REO_R1_SM_STATES_IX_2_RMSK                              0xffffffff
 #define HWIO_REO_R1_SM_STATES_IX_2_SHFT                                       0
 #define HWIO_REO_R1_SM_STATES_IX_2_IN(x)                             \
@@ -8833,8 +8977,8 @@
 
 //// Register REO_R1_SM_STATES_IX_3 ////
 
-#define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x)                           (x+0x0000205c)
-#define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x)                           (x+0x0000205c)
+#define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x)                           (x+0x00002060)
+#define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x)                           (x+0x00002060)
 #define HWIO_REO_R1_SM_STATES_IX_3_RMSK                              0xffffffff
 #define HWIO_REO_R1_SM_STATES_IX_3_SHFT                                       0
 #define HWIO_REO_R1_SM_STATES_IX_3_IN(x)                             \
@@ -8855,8 +8999,8 @@
 
 //// Register REO_R1_SM_STATES_IX_4 ////
 
-#define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x)                           (x+0x00002060)
-#define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x)                           (x+0x00002060)
+#define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x)                           (x+0x00002064)
+#define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x)                           (x+0x00002064)
 #define HWIO_REO_R1_SM_STATES_IX_4_RMSK                              0xffffffff
 #define HWIO_REO_R1_SM_STATES_IX_4_SHFT                                       0
 #define HWIO_REO_R1_SM_STATES_IX_4_IN(x)                             \
@@ -8877,8 +9021,8 @@
 
 //// Register REO_R1_SM_STATES_IX_5 ////
 
-#define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x)                           (x+0x00002064)
-#define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x)                           (x+0x00002064)
+#define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x)                           (x+0x00002068)
+#define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x)                           (x+0x00002068)
 #define HWIO_REO_R1_SM_STATES_IX_5_RMSK                              0xffffffff
 #define HWIO_REO_R1_SM_STATES_IX_5_SHFT                                       0
 #define HWIO_REO_R1_SM_STATES_IX_5_IN(x)                             \
@@ -8899,8 +9043,8 @@
 
 //// Register REO_R1_SM_STATES_IX_6 ////
 
-#define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x)                           (x+0x00002068)
-#define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x)                           (x+0x00002068)
+#define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x)                           (x+0x0000206c)
+#define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x)                           (x+0x0000206c)
 #define HWIO_REO_R1_SM_STATES_IX_6_RMSK                              0xffffffff
 #define HWIO_REO_R1_SM_STATES_IX_6_SHFT                                       0
 #define HWIO_REO_R1_SM_STATES_IX_6_IN(x)                             \
@@ -8921,8 +9065,8 @@
 
 //// Register REO_R1_IDLE_STATES_IX_0 ////
 
-#define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x)                         (x+0x0000206c)
-#define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x)                         (x+0x0000206c)
+#define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x)                         (x+0x00002070)
+#define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x)                         (x+0x00002070)
 #define HWIO_REO_R1_IDLE_STATES_IX_0_RMSK                            0xffffffff
 #define HWIO_REO_R1_IDLE_STATES_IX_0_SHFT                                     0
 #define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x)                           \
@@ -8943,8 +9087,8 @@
 
 //// Register REO_R1_INVALID_APB_ACCESS ////
 
-#define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x)                       (x+0x00002070)
-#define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x)                       (x+0x00002070)
+#define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x)                       (x+0x00002074)
+#define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x)                       (x+0x00002074)
 #define HWIO_REO_R1_INVALID_APB_ACCESS_RMSK                          0x0007ffff
 #define HWIO_REO_R1_INVALID_APB_ACCESS_SHFT                                   0
 #define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)                         \

+ 71 - 227
hw/qcn9000/rfa_from_wsi_seq_hwiobase.h

@@ -16,9 +16,7 @@
 
 ///////////////////////////////////////////////////////////////////////////////////////////////
 //
-///////////////////////////////////////////////////////////////////////////////////////////////
-//
-// rfa_from_wsi_seq_hwiobase.h : automatically generated by Autoseq  3.1 1/17/2019 
+// rfa_from_wsi_seq_hwiobase.h : automatically generated by Autoseq  3.8 7/1/2019 
 // User Name:pbechana
 //
 // !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
@@ -39,17 +37,6 @@
 // Instance Relative Offsets from Block rfa_from_wsi
 ///////////////////////////////////////////////////////////////////////////////////////////////
 
-#define SEQ_RFA_FROM_WSI_AO_SYSCTRL_OFFSET                           0x00001000
-#define SEQ_RFA_FROM_WSI_AO_TLMM_OFFSET                              0x00001400
-#define SEQ_RFA_FROM_WSI_AO_OVERRIDE_REG_OFFSET                      0x00001800
-#define SEQ_RFA_FROM_WSI_CM_TLMM_OFFSET                              0x00002000
-#define SEQ_RFA_FROM_WSI_CM_TRC_OFFSET                               0x00002200
-#define SEQ_RFA_FROM_WSI_HZ_COEX_LTE_REG_OFFSET                      0x00007000
-#define SEQ_RFA_FROM_WSI_PMU_OFFSET                                  0x0000b000
-#define SEQ_RFA_FROM_WSI_BT_SECURITY_CONTROL_OFFSET                  0x0000c000
-#define SEQ_RFA_FROM_WSI_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x0000eb00
-#define SEQ_RFA_FROM_WSI_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x0000c000
-#define SEQ_RFA_FROM_WSI_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x00010000
 #define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET                              0x00014000
 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET                          0x00014000
 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET                     0x00014240
@@ -58,9 +45,6 @@
 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET                  0x00014400
 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET                      0x00014480
 #define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET                       0x00014800
-#define SEQ_RFA_FROM_WSI_RFA_CMN_BTFMPLL_OFFSET                      0x00014c00
-#define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_OFFSET                        0x00015000
-#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_TOP_CLKGEN_OFFSET                0x00015400
 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET                 0x00016000
 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET               0x00016040
 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET               0x00016100
@@ -73,117 +57,44 @@
 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET               0x00016900
 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET                 0x00016940
 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET               0x00016980
-#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET                 0x000169c0
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET                 0x00016a00
 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_LO_OFFSET                 0x00016a80
-#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_BS_OFFSET                 0x00017000
-#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_CLBS_OFFSET               0x00017040
-#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_BIST_OFFSET               0x00017100
-#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_PC_OFFSET                 0x00017140
-#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_KVCO_OFFSET               0x00017180
-#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_AC_OFFSET                 0x000171c0
-#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_LO_OFFSET                 0x00017280
 #define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET               0x00017c00
-#define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET                               0x0001c000
-#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TOP_OFFSET                        0x0001c000
-#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET          0x0001e800
-#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_OFFSET                        0x0001e980
-#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET         0x0001e9c0
-#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_MISC_OFFSET                   0x0001eac0
-#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TX_OFFSET                         0x0001ec00
-#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RX_CH0_OFFSET                     0x0001f000
-#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RX_CH1_OFFSET                     0x0001f200
-#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET                   0x0001fc00
-#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET                 0x0001fc40
-#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET                   0x0001fc80
-#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET                   0x0001fcc0
+#define SEQ_RFA_FROM_WSI_RFA_PMU_OFFSET                              0x0001a000
+#define SEQ_RFA_FROM_WSI_RFA_PMU_PMU_OFFSET                          0x0001a000
 #define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET                               0x00020000
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH0_OFFSET                  0x00020000
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_2G_CH0_OFFSET                0x00020400
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_2G_CH0_OFFSET                0x00020800
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH0_OFFSET                0x00021000
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET                0x00021300
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH0_OFFSET                 0x00022000
-#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_2G_CH0_OFFSET               0x00022400
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_2G_CH0_OFFSET                 0x00022580
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET  0x000225c0
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET            0x000226c0
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_2G_CH0_OFFSET        0x00022734
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_2G_CH0_OFFSET                 0x00022740
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH0_OFFSET 0x00022800
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH0_OFFSET  0x00022840
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH0_OFFSET 0x00022880
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH0_OFFSET  0x000228c0
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH0_OFFSET     0x00022900
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_2G_CH0_OFFSET        0x0002299c
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH0_OFFSET                 0x00024000
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH0_OFFSET                  0x00028000
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_5G_CH0_OFFSET                0x00028400
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_5G_CH0_OFFSET                0x00028800
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH0_OFFSET                0x00029000
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET                0x00029300
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH0_OFFSET                 0x0002a000
-#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_5G_CH0_OFFSET               0x0002a400
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_5G_CH0_OFFSET                 0x0002a580
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET  0x0002a5c0
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET            0x0002a6c0
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_5G_CH0_OFFSET        0x0002a734
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_5G_CH0_OFFSET                 0x0002a740
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH0_OFFSET 0x0002a800
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH0_OFFSET  0x0002a840
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH0_OFFSET 0x0002a880
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH0_OFFSET  0x0002a8c0
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH0_OFFSET     0x0002a900
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_5G_CH0_OFFSET        0x0002a99c
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH0_OFFSET                 0x0002c000
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH1_OFFSET                  0x00030000
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_2G_CH1_OFFSET                0x00030400
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_2G_CH1_OFFSET                0x00030800
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH1_OFFSET                0x00031000
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH1_OFFSET                0x00031300
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH1_OFFSET                 0x00032000
-#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_2G_CH1_OFFSET               0x00032400
-#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_OFFSET                      0x00032500
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_2G_CH1_OFFSET                 0x00032580
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET  0x000325c0
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET            0x000326c0
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_2G_CH1_OFFSET        0x00032734
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_2G_CH1_OFFSET                 0x00032740
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH1_OFFSET 0x00032800
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH1_OFFSET  0x00032840
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH1_OFFSET 0x00032880
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET  0x000328c0
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET     0x00032900
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET        0x0003299c
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_CAL_CORE_OFFSET                   0x00032c00
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH1_OFFSET                 0x00034000
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH1_OFFSET                  0x00038000
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_5G_CH1_OFFSET                0x00038400
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_5G_CH1_OFFSET                0x00038800
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH1_OFFSET                0x00039000
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH1_OFFSET                0x00039300
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH1_OFFSET                 0x0003a000
-#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_5G_CH1_OFFSET               0x0003a400
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_5G_CH1_OFFSET                 0x0003a580
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET  0x0003a5c0
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET            0x0003a6c0
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_5G_CH1_OFFSET        0x0003a734
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_5G_CH1_OFFSET                 0x0003a740
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH1_OFFSET 0x0003a800
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH1_OFFSET  0x0003a840
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH1_OFFSET 0x0003a880
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH1_OFFSET  0x0003a8c0
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH1_OFFSET     0x0003a900
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_5G_CH1_OFFSET        0x0003a99c
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH1_OFFSET                 0x0003c000
-
-
-///////////////////////////////////////////////////////////////////////////////////////////////
-// Instance Relative Offsets from Block security_control_bt
-///////////////////////////////////////////////////////////////////////////////////////////////
-
-#define SEQ_SECURITY_CONTROL_BT_BT_SECURITY_CONTROL_CORE_OFFSET      0x00002b00
-#define SEQ_SECURITY_CONTROL_BT_BT_QFPROM_RAW_FUSE_OFFSET            0x00000000
-#define SEQ_SECURITY_CONTROL_BT_BT_QFPROM_CORR_FUSE_OFFSET           0x00004000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH0_OFFSET                     0x00020000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET                   0x00020400
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET                   0x00020800
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH0_OFFSET                   0x00021000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH0_OFFSET                   0x00021300
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH0_OFFSET                 0x00021600
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH0_OFFSET                     0x00021640
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH0_OFFSET                    0x00022000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH1_OFFSET                     0x00028000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH1_OFFSET                   0x00028400
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH1_OFFSET                   0x00028800
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH1_OFFSET                   0x00029000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH1_OFFSET                   0x00029300
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH1_OFFSET                 0x00029600
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH1_OFFSET                     0x00029640
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH1_OFFSET                    0x0002a000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH2_OFFSET                     0x00030000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH2_OFFSET                   0x00030400
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH2_OFFSET                   0x00030800
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH2_OFFSET                   0x00031000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH2_OFFSET                   0x00031300
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH2_OFFSET                 0x00031600
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH2_OFFSET                     0x00031640
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH2_OFFSET                    0x00032000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH3_OFFSET                     0x00038000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH3_OFFSET                   0x00038400
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH3_OFFSET                   0x00038800
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH3_OFFSET                   0x00039000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH3_OFFSET                   0x00039300
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH3_OFFSET                 0x00039600
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH3_OFFSET                     0x00039640
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH3_OFFSET                    0x0003a000
 
 
 ///////////////////////////////////////////////////////////////////////////////////////////////
@@ -197,9 +108,6 @@
 #define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET                               0x00000400
 #define SEQ_RFA_CMN_RFA_OTP_OFFSET                                   0x00000480
 #define SEQ_RFA_CMN_CLKGEN_OFFSET                                    0x00000800
-#define SEQ_RFA_CMN_BTFMPLL_OFFSET                                   0x00000c00
-#define SEQ_RFA_CMN_BBPLL_OFFSET                                     0x00001000
-#define SEQ_RFA_CMN_WL_TOP_CLKGEN_OFFSET                             0x00001400
 #define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET                              0x00002000
 #define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET                            0x00002040
 #define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET                            0x00002100
@@ -212,118 +120,54 @@
 #define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET                            0x00002900
 #define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET                              0x00002940
 #define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET                            0x00002980
-#define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET                              0x000029c0
+#define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET                              0x00002a00
 #define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET                              0x00002a80
-#define SEQ_RFA_CMN_WL_SYNTH2_BS_OFFSET                              0x00003000
-#define SEQ_RFA_CMN_WL_SYNTH2_CLBS_OFFSET                            0x00003040
-#define SEQ_RFA_CMN_WL_SYNTH2_BIST_OFFSET                            0x00003100
-#define SEQ_RFA_CMN_WL_SYNTH2_PC_OFFSET                              0x00003140
-#define SEQ_RFA_CMN_WL_SYNTH2_KVCO_OFFSET                            0x00003180
-#define SEQ_RFA_CMN_WL_SYNTH2_AC_OFFSET                              0x000031c0
-#define SEQ_RFA_CMN_WL_SYNTH2_LO_OFFSET                              0x00003280
 #define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET                            0x00003c00
 
 
 ///////////////////////////////////////////////////////////////////////////////////////////////
-// Instance Relative Offsets from Block rfa_bt
+// Instance Relative Offsets from Block rfa_pmu
 ///////////////////////////////////////////////////////////////////////////////////////////////
 
-#define SEQ_RFA_BT_BT_TOP_OFFSET                                     0x00000000
-#define SEQ_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET                       0x00002800
-#define SEQ_RFA_BT_BT_DAC_OFFSET                                     0x00002980
-#define SEQ_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET                      0x000029c0
-#define SEQ_RFA_BT_BT_DAC_MISC_OFFSET                                0x00002ac0
-#define SEQ_RFA_BT_BT_TX_OFFSET                                      0x00002c00
-#define SEQ_RFA_BT_BT_RX_CH0_OFFSET                                  0x00003000
-#define SEQ_RFA_BT_BT_RX_CH1_OFFSET                                  0x00003200
-#define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET                                0x00003c00
-#define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET                              0x00003c40
-#define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET                                0x00003c80
-#define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET                                0x00003cc0
+#define SEQ_RFA_PMU_PMU_OFFSET                                       0x00000000
 
 
 ///////////////////////////////////////////////////////////////////////////////////////////////
 // Instance Relative Offsets from Block rfa_wl
 ///////////////////////////////////////////////////////////////////////////////////////////////
 
-#define SEQ_RFA_WL_WL_MC_2G_CH0_OFFSET                               0x00000000
-#define SEQ_RFA_WL_WL_RXBB_2G_CH0_OFFSET                             0x00000400
-#define SEQ_RFA_WL_WL_TXBB_2G_CH0_OFFSET                             0x00000800
-#define SEQ_RFA_WL_WL_RXFE_2G_CH0_OFFSET                             0x00001000
-#define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET                             0x00001300
-#define SEQ_RFA_WL_WL_TPC_2G_CH0_OFFSET                              0x00002000
-#define SEQ_RFA_WL_RBIST_TX_2G_CH0_OFFSET                            0x00002400
-#define SEQ_RFA_WL_WL_DAC_2G_CH0_OFFSET                              0x00002580
-#define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET               0x000025c0
-#define SEQ_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET                         0x000026c0
-#define SEQ_RFA_WL_WL_DAC_BBCLKGEN_2G_CH0_OFFSET                     0x00002734
-#define SEQ_RFA_WL_WL_ADC_2G_CH0_OFFSET                              0x00002740
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH0_OFFSET              0x00002800
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH0_OFFSET               0x00002840
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH0_OFFSET              0x00002880
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH0_OFFSET               0x000028c0
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH0_OFFSET                  0x00002900
-#define SEQ_RFA_WL_WL_ADC_BBCLKGEN_2G_CH0_OFFSET                     0x0000299c
-#define SEQ_RFA_WL_WL_MEM_2G_CH0_OFFSET                              0x00004000
-#define SEQ_RFA_WL_WL_MC_5G_CH0_OFFSET                               0x00008000
-#define SEQ_RFA_WL_WL_RXBB_5G_CH0_OFFSET                             0x00008400
-#define SEQ_RFA_WL_WL_TXBB_5G_CH0_OFFSET                             0x00008800
-#define SEQ_RFA_WL_WL_RXFE_5G_CH0_OFFSET                             0x00009000
-#define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET                             0x00009300
-#define SEQ_RFA_WL_WL_TPC_5G_CH0_OFFSET                              0x0000a000
-#define SEQ_RFA_WL_RBIST_TX_5G_CH0_OFFSET                            0x0000a400
-#define SEQ_RFA_WL_WL_DAC_5G_CH0_OFFSET                              0x0000a580
-#define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET               0x0000a5c0
-#define SEQ_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET                         0x0000a6c0
-#define SEQ_RFA_WL_WL_DAC_BBCLKGEN_5G_CH0_OFFSET                     0x0000a734
-#define SEQ_RFA_WL_WL_ADC_5G_CH0_OFFSET                              0x0000a740
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH0_OFFSET              0x0000a800
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH0_OFFSET               0x0000a840
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH0_OFFSET              0x0000a880
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH0_OFFSET               0x0000a8c0
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH0_OFFSET                  0x0000a900
-#define SEQ_RFA_WL_WL_ADC_BBCLKGEN_5G_CH0_OFFSET                     0x0000a99c
-#define SEQ_RFA_WL_WL_MEM_5G_CH0_OFFSET                              0x0000c000
-#define SEQ_RFA_WL_WL_MC_2G_CH1_OFFSET                               0x00010000
-#define SEQ_RFA_WL_WL_RXBB_2G_CH1_OFFSET                             0x00010400
-#define SEQ_RFA_WL_WL_TXBB_2G_CH1_OFFSET                             0x00010800
-#define SEQ_RFA_WL_WL_RXFE_2G_CH1_OFFSET                             0x00011000
-#define SEQ_RFA_WL_WL_TXFE_2G_CH1_OFFSET                             0x00011300
-#define SEQ_RFA_WL_WL_TPC_2G_CH1_OFFSET                              0x00012000
-#define SEQ_RFA_WL_RBIST_TX_2G_CH1_OFFSET                            0x00012400
-#define SEQ_RFA_WL_RBIST_RX_OFFSET                                   0x00012500
-#define SEQ_RFA_WL_WL_DAC_2G_CH1_OFFSET                              0x00012580
-#define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET               0x000125c0
-#define SEQ_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET                         0x000126c0
-#define SEQ_RFA_WL_WL_DAC_BBCLKGEN_2G_CH1_OFFSET                     0x00012734
-#define SEQ_RFA_WL_WL_ADC_2G_CH1_OFFSET                              0x00012740
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_2G_CH1_OFFSET              0x00012800
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_2G_CH1_OFFSET               0x00012840
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_2G_CH1_OFFSET              0x00012880
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET               0x000128c0
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET                  0x00012900
-#define SEQ_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET                     0x0001299c
-#define SEQ_RFA_WL_WL_CAL_CORE_OFFSET                                0x00012c00
-#define SEQ_RFA_WL_WL_MEM_2G_CH1_OFFSET                              0x00014000
-#define SEQ_RFA_WL_WL_MC_5G_CH1_OFFSET                               0x00018000
-#define SEQ_RFA_WL_WL_RXBB_5G_CH1_OFFSET                             0x00018400
-#define SEQ_RFA_WL_WL_TXBB_5G_CH1_OFFSET                             0x00018800
-#define SEQ_RFA_WL_WL_RXFE_5G_CH1_OFFSET                             0x00019000
-#define SEQ_RFA_WL_WL_TXFE_5G_CH1_OFFSET                             0x00019300
-#define SEQ_RFA_WL_WL_TPC_5G_CH1_OFFSET                              0x0001a000
-#define SEQ_RFA_WL_RBIST_TX_5G_CH1_OFFSET                            0x0001a400
-#define SEQ_RFA_WL_WL_DAC_5G_CH1_OFFSET                              0x0001a580
-#define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET               0x0001a5c0
-#define SEQ_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET                         0x0001a6c0
-#define SEQ_RFA_WL_WL_DAC_BBCLKGEN_5G_CH1_OFFSET                     0x0001a734
-#define SEQ_RFA_WL_WL_ADC_5G_CH1_OFFSET                              0x0001a740
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_5G_CH1_OFFSET              0x0001a800
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_5G_CH1_OFFSET               0x0001a840
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_5G_CH1_OFFSET              0x0001a880
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_5G_CH1_OFFSET               0x0001a8c0
-#define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_5G_CH1_OFFSET                  0x0001a900
-#define SEQ_RFA_WL_WL_ADC_BBCLKGEN_5G_CH1_OFFSET                     0x0001a99c
-#define SEQ_RFA_WL_WL_MEM_5G_CH1_OFFSET                              0x0001c000
+#define SEQ_RFA_WL_WL_MC_CH0_OFFSET                                  0x00000000
+#define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET                                0x00000400
+#define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET                                0x00000800
+#define SEQ_RFA_WL_WL_RXFE_CH0_OFFSET                                0x00001000
+#define SEQ_RFA_WL_WL_TXFE_CH0_OFFSET                                0x00001300
+#define SEQ_RFA_WL_WL_LO_PAL_CH0_OFFSET                              0x00001600
+#define SEQ_RFA_WL_WL_LO_CH0_OFFSET                                  0x00001640
+#define SEQ_RFA_WL_WL_TPC_CH0_OFFSET                                 0x00002000
+#define SEQ_RFA_WL_WL_MC_CH1_OFFSET                                  0x00008000
+#define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET                                0x00008400
+#define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET                                0x00008800
+#define SEQ_RFA_WL_WL_RXFE_CH1_OFFSET                                0x00009000
+#define SEQ_RFA_WL_WL_TXFE_CH1_OFFSET                                0x00009300
+#define SEQ_RFA_WL_WL_LO_PAL_CH1_OFFSET                              0x00009600
+#define SEQ_RFA_WL_WL_LO_CH1_OFFSET                                  0x00009640
+#define SEQ_RFA_WL_WL_TPC_CH1_OFFSET                                 0x0000a000
+#define SEQ_RFA_WL_WL_MC_CH2_OFFSET                                  0x00010000
+#define SEQ_RFA_WL_WL_RXBB_CH2_OFFSET                                0x00010400
+#define SEQ_RFA_WL_WL_TXBB_CH2_OFFSET                                0x00010800
+#define SEQ_RFA_WL_WL_RXFE_CH2_OFFSET                                0x00011000
+#define SEQ_RFA_WL_WL_TXFE_CH2_OFFSET                                0x00011300
+#define SEQ_RFA_WL_WL_LO_PAL_CH2_OFFSET                              0x00011600
+#define SEQ_RFA_WL_WL_LO_CH2_OFFSET                                  0x00011640
+#define SEQ_RFA_WL_WL_TPC_CH2_OFFSET                                 0x00012000
+#define SEQ_RFA_WL_WL_MC_CH3_OFFSET                                  0x00018000
+#define SEQ_RFA_WL_WL_RXBB_CH3_OFFSET                                0x00018400
+#define SEQ_RFA_WL_WL_TXBB_CH3_OFFSET                                0x00018800
+#define SEQ_RFA_WL_WL_RXFE_CH3_OFFSET                                0x00019000
+#define SEQ_RFA_WL_WL_TXFE_CH3_OFFSET                                0x00019300
+#define SEQ_RFA_WL_WL_LO_PAL_CH3_OFFSET                              0x00019600
+#define SEQ_RFA_WL_WL_LO_CH3_OFFSET                                  0x00019640
+#define SEQ_RFA_WL_WL_TPC_CH3_OFFSET                                 0x0001a000
 
 
 #endif

+ 786 - 0
hw/qcn9000/rx_flow_search_entry.h

@@ -0,0 +1,786 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_FLOW_SEARCH_ENTRY_H_
+#define _RX_FLOW_SEARCH_ENTRY_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	src_ip_127_96[31:0]
+//	1	src_ip_95_64[31:0]
+//	2	src_ip_63_32[31:0]
+//	3	src_ip_31_0[31:0]
+//	4	dest_ip_127_96[31:0]
+//	5	dest_ip_95_64[31:0]
+//	6	dest_ip_63_32[31:0]
+//	7	dest_ip_31_0[31:0]
+//	8	src_port[15:0], dest_port[31:16]
+//	9	l4_protocol[7:0], valid[8], reserved_9[23:9], reo_destination_indication[28:24], msdu_drop[29], reo_destination_handler[31:30]
+//	10	metadata[31:0]
+//	11	aggregation_count[6:0], lro_eligible[7], msdu_count[31:8]
+//	12	msdu_byte_count[31:0]
+//	13	timestamp[31:0]
+//	14	cumulative_l4_checksum[15:0], cumulative_ip_length[31:16]
+//	15	tcp_sequence_number[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16
+
+struct rx_flow_search_entry {
+             uint32_t src_ip_127_96                   : 32; //[31:0]
+             uint32_t src_ip_95_64                    : 32; //[31:0]
+             uint32_t src_ip_63_32                    : 32; //[31:0]
+             uint32_t src_ip_31_0                     : 32; //[31:0]
+             uint32_t dest_ip_127_96                  : 32; //[31:0]
+             uint32_t dest_ip_95_64                   : 32; //[31:0]
+             uint32_t dest_ip_63_32                   : 32; //[31:0]
+             uint32_t dest_ip_31_0                    : 32; //[31:0]
+             uint32_t src_port                        : 16, //[15:0]
+                      dest_port                       : 16; //[31:16]
+             uint32_t l4_protocol                     :  8, //[7:0]
+                      valid                           :  1, //[8]
+                      reserved_9                      : 15, //[23:9]
+                      reo_destination_indication      :  5, //[28:24]
+                      msdu_drop                       :  1, //[29]
+                      reo_destination_handler         :  2; //[31:30]
+             uint32_t metadata                        : 32; //[31:0]
+             uint32_t aggregation_count               :  7, //[6:0]
+                      lro_eligible                    :  1, //[7]
+                      msdu_count                      : 24; //[31:8]
+             uint32_t msdu_byte_count                 : 32; //[31:0]
+             uint32_t timestamp                       : 32; //[31:0]
+             uint32_t cumulative_l4_checksum          : 16, //[15:0]
+                      cumulative_ip_length            : 16; //[31:16]
+             uint32_t tcp_sequence_number             : 32; //[31:0]
+};
+
+/*
+
+src_ip_127_96
+			
+			Uppermost 32 bits of source IPv6 address or prefix as
+			per Common Parser register field IP_DA_SA_PREFIX (with the
+			first byte in the MSB and the last byte in the LSB, i.e.
+			requiring a byte-swap for little-endian SW w.r.t. the byte
+			order in an IPv6 packet)
+			
+			<legal all>
+
+src_ip_95_64
+			
+			Next 32 bits of source IPv6 address or prefix (requiring
+			a byte-swap for little-endian SW) <legal all>
+
+src_ip_63_32
+			
+			Next 32 bits of source IPv6 address or lowest 32 bits of
+			prefix (requiring a byte-swap for little-endian SW)
+			
+			<legal all>
+
+src_ip_31_0
+			
+			Lowest 32 bits of source IPv6 address, or source IPv4
+			address (requiring a byte-swap for little-endian SW w.r.t.
+			the byte order in an IPv6 or IPv4 packet)
+			
+			<legal all>
+
+dest_ip_127_96
+			
+			Uppermost 32 bits of destination IPv6 address or prefix
+			as per Common Parser register field IP_DA_SA_PREFIX (with
+			the first byte in the MSB and the last byte in the LSB, i.e.
+			requiring a byte-swap for little-endian SW w.r.t. the byte
+			order as in an IPv6 packet)
+			
+			<legal all>
+
+dest_ip_95_64
+			
+			Next 32 bits of destination IPv6 address or prefix
+			(requiring a byte-swap for little-endian SW)
+			
+			<legal all>
+
+dest_ip_63_32
+			
+			Next 32 bits of destination IPv6 address or lowest 32
+			bits of prefix (requiring a byte-swap for little-endian SW)
+			
+			<legal all>
+
+dest_ip_31_0
+			
+			Lowest 32 bits of destination IPv6 address, or
+			destination IPv4 address (requiring a byte-swap for
+			little-endian SW w.r.t. the byte order in an IPv6 or IPv4
+			packet)
+			
+			<legal all>
+
+src_port
+			
+			LSB of SPI in case of ESP/AH
+			
+			else source port in case of TCP/UDP without IPsec,
+			
+			else zeros in case of ICMP (with the first/third byte in
+			the MSB and the second/fourth byte in the LSB, i.e.
+			requiring a byte-swap for little-endian SW w.r.t. the byte
+			order as in an IPv6 or IPv4 packet)  <legal all>
+
+dest_port
+			
+			MSB of SPI in case of ESP/AH
+			
+			else destination port in case of TCP/UDP without IPsec,
+			
+			else zeros in case of ICMP (with the first byte in the
+			MSB and the second byte in the LSB, i.e. requiring a
+			byte-swap for little-endian SW w.r.t. the byte order as in
+			an IPv6 or IPv4 packet)
+			
+			<legal all>
+
+l4_protocol
+			
+			IPsec or L4 protocol
+			
+			
+			
+			<enum 1 ICMPV4>
+			
+			<enum 6 TCP>
+			
+			<enum 17 UDP>
+			
+			<enum 50 ESP>
+			
+			<enum 51 AH>
+			
+			<enum 58 ICMPV6>
+			
+			<legal 1, 6, 17, 50, 51, 58>
+
+valid
+			
+			Indicates validity of entry
+			
+			<legal all>
+
+reserved_9
+			
+			<legal 0>
+
+reo_destination_indication
+			
+			The ID of the REO exit ring where the MSDU frame shall
+			push after (MPDU level) reordering has finished.
+			
+			
+			
+			<enum 0 reo_destination_tcl> Reo will push the frame
+			into the REO2TCL ring
+			
+			<enum 1 reo_destination_sw1> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 2 reo_destination_sw2> Reo will push the frame
+			into the REO2SW2 ring
+			
+			<enum 3 reo_destination_sw3> Reo will push the frame
+			into the REO2SW3 ring
+			
+			<enum 4 reo_destination_sw4> Reo will push the frame
+			into the REO2SW4 ring
+			
+			<enum 5 reo_destination_release> Reo will push the frame
+			into the REO_release ring
+			
+			<enum 6 reo_destination_fw> Reo will push the frame into
+			the REO2FW ring
+			
+			<enum 7 reo_destination_sw5> Reo will push the frame
+			into the REO2SW5 ring (REO remaps this in chips without
+			REO2SW5 ring, e.g. Pine)
+			
+			<enum 8 reo_destination_sw6> Reo will push the frame
+			into the REO2SW6 ring (REO remaps this in chips without
+			REO2SW6 ring, e.g. Pine) 
+			
+			<enum 9 reo_destination_9> REO remaps this <enum 10
+			reo_destination_10> REO remaps this 
+			
+			<enum 11 reo_destination_11> REO remaps this 
+			
+			<enum 12 reo_destination_12> REO remaps this <enum 13
+			reo_destination_13> REO remaps this 
+			
+			<enum 14 reo_destination_14> REO remaps this 
+			
+			<enum 15 reo_destination_15> REO remaps this 
+			
+			<enum 16 reo_destination_16> REO remaps this 
+			
+			<enum 17 reo_destination_17> REO remaps this 
+			
+			<enum 18 reo_destination_18> REO remaps this 
+			
+			<enum 19 reo_destination_19> REO remaps this 
+			
+			<enum 20 reo_destination_20> REO remaps this 
+			
+			<enum 21 reo_destination_21> REO remaps this 
+			
+			<enum 22 reo_destination_22> REO remaps this 
+			
+			<enum 23 reo_destination_23> REO remaps this 
+			
+			<enum 24 reo_destination_24> REO remaps this 
+			
+			<enum 25 reo_destination_25> REO remaps this 
+			
+			<enum 26 reo_destination_26> REO remaps this 
+			
+			<enum 27 reo_destination_27> REO remaps this 
+			
+			<enum 28 reo_destination_28> REO remaps this 
+			
+			<enum 29 reo_destination_29> REO remaps this 
+			
+			<enum 30 reo_destination_30> REO remaps this 
+			
+			<enum 31 reo_destination_31> REO remaps this 
+			
+			
+			
+			<legal all>
+
+msdu_drop
+			
+			Overriding indication to REO to forward to REO release
+			ring
+			
+			<legal all>
+
+reo_destination_handler
+			
+			Indicates how to decide the REO destination indication
+			
+			<enum 0 RXFT_USE_FT> Follow this entry
+			
+			<enum 1 RXFT_USE_ASPT> Use address search+peer table
+			entry
+			
+			<enum 2 RXFT_USE_FT2> Follow this entry
+			
+			<enum 3 RXFT_USE_CCE> Use CCE super-rule
+			
+			<legal all>
+
+metadata
+			
+			Value to be passed to SW if this flow search entry
+			matches
+			
+			<legal all>
+
+aggregation_count
+			
+			FISA: Number'of MSDU's aggregated so far
+			
+			
+			
+			Set to zero in chips not supporting FISA, e.g. Pine
+			
+			<legal all>
+
+lro_eligible
+			
+			FISA: To indicate whether the previous MSDU for this
+			flow is eligible for LRO/FISA
+			
+			
+			
+			Set to zero in chips not supporting FISA, e.g. Pine
+			
+			<legal all>
+
+msdu_count
+			
+			Number of Rx MSDUs matching this flow
+			
+			<legal all>
+
+msdu_byte_count
+			
+			Number of bytes in Rx MSDUs matching this flow
+			
+			<legal all>
+
+timestamp
+			
+			Time of last reception (as measured at Rx OLE) matching
+			this flow
+			
+			<legal all>
+
+cumulative_l4_checksum
+			
+			FISA: checksum 'or MSDU's that is part of this flow
+			aggregated so far
+			
+			
+			
+			Set to zero in chips not supporting FISA, e.g. Pine
+			
+			<legal all>
+
+cumulative_ip_length
+			
+			FISA: Total MSDU length that is part of this flow
+			aggregated so far
+			
+			
+			
+			Set to zero in chips not supporting FISA, e.g. Pine
+			
+			<legal all>
+
+tcp_sequence_number
+			
+			FISA: TCP Sequence number of the last packet in this
+			flow to detect sequence number jump
+			
+			
+			
+			Set to zero in chips not supporting FISA, e.g. Pine
+			
+			<legal all>
+*/
+
+
+/* Description		RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96
+			
+			Uppermost 32 bits of source IPv6 address or prefix as
+			per Common Parser register field IP_DA_SA_PREFIX (with the
+			first byte in the MSB and the last byte in the LSB, i.e.
+			requiring a byte-swap for little-endian SW w.r.t. the byte
+			order in an IPv6 packet)
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_OFFSET                  0x00000000
+#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_LSB                     0
+#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_MASK                    0xffffffff
+
+/* Description		RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64
+			
+			Next 32 bits of source IPv6 address or prefix (requiring
+			a byte-swap for little-endian SW) <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_OFFSET                   0x00000004
+#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_LSB                      0
+#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_MASK                     0xffffffff
+
+/* Description		RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32
+			
+			Next 32 bits of source IPv6 address or lowest 32 bits of
+			prefix (requiring a byte-swap for little-endian SW)
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_OFFSET                   0x00000008
+#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_LSB                      0
+#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_MASK                     0xffffffff
+
+/* Description		RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0
+			
+			Lowest 32 bits of source IPv6 address, or source IPv4
+			address (requiring a byte-swap for little-endian SW w.r.t.
+			the byte order in an IPv6 or IPv4 packet)
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_OFFSET                    0x0000000c
+#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_LSB                       0
+#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_MASK                      0xffffffff
+
+/* Description		RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96
+			
+			Uppermost 32 bits of destination IPv6 address or prefix
+			as per Common Parser register field IP_DA_SA_PREFIX (with
+			the first byte in the MSB and the last byte in the LSB, i.e.
+			requiring a byte-swap for little-endian SW w.r.t. the byte
+			order as in an IPv6 packet)
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_OFFSET                 0x00000010
+#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_LSB                    0
+#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_MASK                   0xffffffff
+
+/* Description		RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64
+			
+			Next 32 bits of destination IPv6 address or prefix
+			(requiring a byte-swap for little-endian SW)
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_OFFSET                  0x00000014
+#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_LSB                     0
+#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_MASK                    0xffffffff
+
+/* Description		RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32
+			
+			Next 32 bits of destination IPv6 address or lowest 32
+			bits of prefix (requiring a byte-swap for little-endian SW)
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_OFFSET                  0x00000018
+#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_LSB                     0
+#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_MASK                    0xffffffff
+
+/* Description		RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0
+			
+			Lowest 32 bits of destination IPv6 address, or
+			destination IPv4 address (requiring a byte-swap for
+			little-endian SW w.r.t. the byte order in an IPv6 or IPv4
+			packet)
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_OFFSET                   0x0000001c
+#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_LSB                      0
+#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_MASK                     0xffffffff
+
+/* Description		RX_FLOW_SEARCH_ENTRY_8_SRC_PORT
+			
+			LSB of SPI in case of ESP/AH
+			
+			else source port in case of TCP/UDP without IPsec,
+			
+			else zeros in case of ICMP (with the first/third byte in
+			the MSB and the second/fourth byte in the LSB, i.e.
+			requiring a byte-swap for little-endian SW w.r.t. the byte
+			order as in an IPv6 or IPv4 packet)  <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_OFFSET                       0x00000020
+#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_LSB                          0
+#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_MASK                         0x0000ffff
+
+/* Description		RX_FLOW_SEARCH_ENTRY_8_DEST_PORT
+			
+			MSB of SPI in case of ESP/AH
+			
+			else destination port in case of TCP/UDP without IPsec,
+			
+			else zeros in case of ICMP (with the first byte in the
+			MSB and the second byte in the LSB, i.e. requiring a
+			byte-swap for little-endian SW w.r.t. the byte order as in
+			an IPv6 or IPv4 packet)
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_OFFSET                      0x00000020
+#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_LSB                         16
+#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_MASK                        0xffff0000
+
+/* Description		RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL
+			
+			IPsec or L4 protocol
+			
+			
+			
+			<enum 1 ICMPV4>
+			
+			<enum 6 TCP>
+			
+			<enum 17 UDP>
+			
+			<enum 50 ESP>
+			
+			<enum 51 AH>
+			
+			<enum 58 ICMPV6>
+			
+			<legal 1, 6, 17, 50, 51, 58>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_OFFSET                    0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_LSB                       0
+#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_MASK                      0x000000ff
+
+/* Description		RX_FLOW_SEARCH_ENTRY_9_VALID
+			
+			Indicates validity of entry
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_VALID_OFFSET                          0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_VALID_LSB                             8
+#define RX_FLOW_SEARCH_ENTRY_9_VALID_MASK                            0x00000100
+
+/* Description		RX_FLOW_SEARCH_ENTRY_9_RESERVED_9
+			
+			<legal 0>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_OFFSET                     0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_LSB                        9
+#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_MASK                       0x00fffe00
+
+/* Description		RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION
+			
+			The ID of the REO exit ring where the MSDU frame shall
+			push after (MPDU level) reordering has finished.
+			
+			
+			
+			<enum 0 reo_destination_tcl> Reo will push the frame
+			into the REO2TCL ring
+			
+			<enum 1 reo_destination_sw1> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 2 reo_destination_sw2> Reo will push the frame
+			into the REO2SW2 ring
+			
+			<enum 3 reo_destination_sw3> Reo will push the frame
+			into the REO2SW3 ring
+			
+			<enum 4 reo_destination_sw4> Reo will push the frame
+			into the REO2SW4 ring
+			
+			<enum 5 reo_destination_release> Reo will push the frame
+			into the REO_release ring
+			
+			<enum 6 reo_destination_fw> Reo will push the frame into
+			the REO2FW ring
+			
+			<enum 7 reo_destination_sw5> Reo will push the frame
+			into the REO2SW5 ring (REO remaps this in chips without
+			REO2SW5 ring, e.g. Pine)
+			
+			<enum 8 reo_destination_sw6> Reo will push the frame
+			into the REO2SW6 ring (REO remaps this in chips without
+			REO2SW6 ring, e.g. Pine) 
+			
+			<enum 9 reo_destination_9> REO remaps this <enum 10
+			reo_destination_10> REO remaps this 
+			
+			<enum 11 reo_destination_11> REO remaps this 
+			
+			<enum 12 reo_destination_12> REO remaps this <enum 13
+			reo_destination_13> REO remaps this 
+			
+			<enum 14 reo_destination_14> REO remaps this 
+			
+			<enum 15 reo_destination_15> REO remaps this 
+			
+			<enum 16 reo_destination_16> REO remaps this 
+			
+			<enum 17 reo_destination_17> REO remaps this 
+			
+			<enum 18 reo_destination_18> REO remaps this 
+			
+			<enum 19 reo_destination_19> REO remaps this 
+			
+			<enum 20 reo_destination_20> REO remaps this 
+			
+			<enum 21 reo_destination_21> REO remaps this 
+			
+			<enum 22 reo_destination_22> REO remaps this 
+			
+			<enum 23 reo_destination_23> REO remaps this 
+			
+			<enum 24 reo_destination_24> REO remaps this 
+			
+			<enum 25 reo_destination_25> REO remaps this 
+			
+			<enum 26 reo_destination_26> REO remaps this 
+			
+			<enum 27 reo_destination_27> REO remaps this 
+			
+			<enum 28 reo_destination_28> REO remaps this 
+			
+			<enum 29 reo_destination_29> REO remaps this 
+			
+			<enum 30 reo_destination_30> REO remaps this 
+			
+			<enum 31 reo_destination_31> REO remaps this 
+			
+			
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_OFFSET     0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_LSB        24
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_MASK       0x1f000000
+
+/* Description		RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP
+			
+			Overriding indication to REO to forward to REO release
+			ring
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_OFFSET                      0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_LSB                         29
+#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_MASK                        0x20000000
+
+/* Description		RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER
+			
+			Indicates how to decide the REO destination indication
+			
+			<enum 0 RXFT_USE_FT> Follow this entry
+			
+			<enum 1 RXFT_USE_ASPT> Use address search+peer table
+			entry
+			
+			<enum 2 RXFT_USE_FT2> Follow this entry
+			
+			<enum 3 RXFT_USE_CCE> Use CCE super-rule
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_OFFSET        0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_LSB           30
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_MASK          0xc0000000
+
+/* Description		RX_FLOW_SEARCH_ENTRY_10_METADATA
+			
+			Value to be passed to SW if this flow search entry
+			matches
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_10_METADATA_OFFSET                      0x00000028
+#define RX_FLOW_SEARCH_ENTRY_10_METADATA_LSB                         0
+#define RX_FLOW_SEARCH_ENTRY_10_METADATA_MASK                        0xffffffff
+
+/* Description		RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT
+			
+			FISA: Number'of MSDU's aggregated so far
+			
+			
+			
+			Set to zero in chips not supporting FISA, e.g. Pine
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_OFFSET             0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_LSB                0
+#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_MASK               0x0000007f
+
+/* Description		RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE
+			
+			FISA: To indicate whether the previous MSDU for this
+			flow is eligible for LRO/FISA
+			
+			
+			
+			Set to zero in chips not supporting FISA, e.g. Pine
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_OFFSET                  0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_LSB                     7
+#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_MASK                    0x00000080
+
+/* Description		RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT
+			
+			Number of Rx MSDUs matching this flow
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_OFFSET                    0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_LSB                       8
+#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_MASK                      0xffffff00
+
+/* Description		RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT
+			
+			Number of bytes in Rx MSDUs matching this flow
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_OFFSET               0x00000030
+#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_LSB                  0
+#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_MASK                 0xffffffff
+
+/* Description		RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP
+			
+			Time of last reception (as measured at Rx OLE) matching
+			this flow
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_OFFSET                     0x00000034
+#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_LSB                        0
+#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_MASK                       0xffffffff
+
+/* Description		RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM
+			
+			FISA: checksum 'or MSDU's that is part of this flow
+			aggregated so far
+			
+			
+			
+			Set to zero in chips not supporting FISA, e.g. Pine
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_OFFSET        0x00000038
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_LSB           0
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_MASK          0x0000ffff
+
+/* Description		RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH
+			
+			FISA: Total MSDU length that is part of this flow
+			aggregated so far
+			
+			
+			
+			Set to zero in chips not supporting FISA, e.g. Pine
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_OFFSET          0x00000038
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_LSB             16
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_MASK            0xffff0000
+
+/* Description		RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER
+			
+			FISA: TCP Sequence number of the last packet in this
+			flow to detect sequence number jump
+			
+			
+			
+			Set to zero in chips not supporting FISA, e.g. Pine
+			
+			<legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_OFFSET           0x0000003c
+#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_LSB              0
+#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_MASK             0xffffffff
+
+
+#endif // _RX_FLOW_SEARCH_ENTRY_H_

File diff suppressed because it is too large
+ 404 - 403
hw/qcn9000/rx_mpdu_info.h


File diff suppressed because it is too large
+ 645 - 644
hw/qcn9000/rx_mpdu_start.h


+ 4 - 2
hw/qcn9000/rx_msdu_details.h

@@ -363,10 +363,12 @@ struct rx_msdu_desc_info rx_msdu_desc_info_details
 			the REO2FW ring
 			
 			<enum 7 reo_destination_sw5> Reo will push the frame
-			into the REO2SW5 ring 
+			into the REO2SW5 ring (REO remaps this in chips without
+			REO2SW5 ring, e.g. Pine) 
 			
 			<enum 8 reo_destination_sw6> Reo will push the frame
-			into the REO2SW6 ring 
+			into the REO2SW6 ring (REO remaps this in chips without
+			REO2SW6 ring, e.g. Pine)
 			
 			 <enum 9 reo_destination_9> REO remaps this <enum 10
 			reo_destination_10> REO remaps this 

File diff suppressed because it is too large
+ 378 - 403
hw/qcn9000/rx_msdu_end.h


+ 74 - 11
hw/qcn9000/rx_msdu_start.h

@@ -31,10 +31,11 @@
 //	5	user_rssi[7:0], pkt_type[11:8], stbc[12], sgi[14:13], rate_mcs[18:15], receive_bandwidth[20:19], reception_type[23:21], mimo_ss_bitmap[31:24]
 //	6	ppdu_start_timestamp[31:0]
 //	7	sw_phy_meta_data[31:0]
+//	8	vlan_ctag_ci[15:0], vlan_stag_ci[31:16]
 //
 // ################ END SUMMARY #################
 
-#define NUM_OF_DWORDS_RX_MSDU_START 8
+#define NUM_OF_DWORDS_RX_MSDU_START 9
 
 struct rx_msdu_start {
              uint32_t rxpcu_mpdu_filter_in_category   :  2, //[1:0]
@@ -75,6 +76,8 @@ struct rx_msdu_start {
                       mimo_ss_bitmap                  :  8; //[31:24]
              uint32_t ppdu_start_timestamp            : 32; //[31:0]
              uint32_t sw_phy_meta_data                : 32; //[31:0]
+             uint32_t vlan_ctag_ci                    : 16, //[15:0]
+                      vlan_stag_ci                    : 16; //[31:16]
 };
 
 /*
@@ -360,10 +363,20 @@ ip4_protocol_ip6_next_header
 
 toeplitz_hash_2_or_4
 			
-			Controlled by RxOLE register - If register bit set to 0,
-			Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest
-			addresses; otherwise, toeplitz hash is computed over 4-tuple
-			IPv4 or IPv6 src/dest addresses and src/dest ports
+			Controlled by multiple RxOLE registers for TCP/UDP over
+			IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple IPv4
+			or IPv6 src/dest addresses is reported; or, Toeplitz hash
+			computed over 4-tuple IPv4 or IPv6 src/dest addresses and
+			src/dest ports is reported. The Flow_id_toeplitz hash can
+			also be reported here. Usually the hash reported here is the
+			one used for hash-based REO routing (see
+			use_flow_id_toeplitz_clfy in 'RXPT_CLASSIFY_INFO').
+			
+			
+			
+			In Pine, optionally the 3-tuple Toeplitz hash over IPv4
+			or IPv6 src/dest addresses and L4 protocol can be reported
+			here. (Unsupported in HastingsPrime)
 
 flow_id_toeplitz
 			
@@ -376,7 +389,13 @@ flow_id_toeplitz
 			In case of IPSec - Toeplitz hash of 4-tuple 
 			
 			{IP source address, IP destination address, SPI, L4
-			protocol} 
+			protocol}
+			
+			
+			
+			In Pine, optionally the 3-tuple Toeplitz hash over IPv4
+			or IPv6 src/dest addresses and L4 protocol can be reported
+			here. (Unsupported in HastingsPrime)
 			
 			
 			
@@ -528,6 +547,16 @@ sw_phy_meta_data
 			on.
 			
 			<legal all>
+
+vlan_ctag_ci
+			
+			2 bytes of C-VLAN Tag Control Information from
+			WHO_L2_LLC
+
+vlan_stag_ci
+			
+			2 bytes of S-VLAN Tag Control Information from
+			WHO_L2_LLC in case of double VLAN
 */
 
 
@@ -916,10 +945,20 @@ sw_phy_meta_data
 
 /* Description		RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4
 			
-			Controlled by RxOLE register - If register bit set to 0,
-			Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest
-			addresses; otherwise, toeplitz hash is computed over 4-tuple
-			IPv4 or IPv6 src/dest addresses and src/dest ports
+			Controlled by multiple RxOLE registers for TCP/UDP over
+			IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple IPv4
+			or IPv6 src/dest addresses is reported; or, Toeplitz hash
+			computed over 4-tuple IPv4 or IPv6 src/dest addresses and
+			src/dest ports is reported. The Flow_id_toeplitz hash can
+			also be reported here. Usually the hash reported here is the
+			one used for hash-based REO routing (see
+			use_flow_id_toeplitz_clfy in 'RXPT_CLASSIFY_INFO').
+			
+			
+			
+			In Pine, optionally the 3-tuple Toeplitz hash over IPv4
+			or IPv6 src/dest addresses and L4 protocol can be reported
+			here. (Unsupported in HastingsPrime)
 */
 #define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_OFFSET                  0x0000000c
 #define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_LSB                     0
@@ -936,7 +975,13 @@ sw_phy_meta_data
 			In case of IPSec - Toeplitz hash of 4-tuple 
 			
 			{IP source address, IP destination address, SPI, L4
-			protocol} 
+			protocol}
+			
+			
+			
+			In Pine, optionally the 3-tuple Toeplitz hash over IPv4
+			or IPv6 src/dest addresses and L4 protocol can be reported
+			here. (Unsupported in HastingsPrime)
 			
 			
 			
@@ -1133,5 +1178,23 @@ sw_phy_meta_data
 #define RX_MSDU_START_7_SW_PHY_META_DATA_LSB                         0
 #define RX_MSDU_START_7_SW_PHY_META_DATA_MASK                        0xffffffff
 
+/* Description		RX_MSDU_START_8_VLAN_CTAG_CI
+			
+			2 bytes of C-VLAN Tag Control Information from
+			WHO_L2_LLC
+*/
+#define RX_MSDU_START_8_VLAN_CTAG_CI_OFFSET                          0x00000020
+#define RX_MSDU_START_8_VLAN_CTAG_CI_LSB                             0
+#define RX_MSDU_START_8_VLAN_CTAG_CI_MASK                            0x0000ffff
+
+/* Description		RX_MSDU_START_8_VLAN_STAG_CI
+			
+			2 bytes of S-VLAN Tag Control Information from
+			WHO_L2_LLC in case of double VLAN
+*/
+#define RX_MSDU_START_8_VLAN_STAG_CI_OFFSET                          0x00000020
+#define RX_MSDU_START_8_VLAN_STAG_CI_LSB                             16
+#define RX_MSDU_START_8_VLAN_STAG_CI_MASK                            0xffff0000
+
 
 #endif // _RX_MSDU_START_H_

+ 47 - 17
hw/qcn9000/rxpt_classify_info.h

@@ -23,7 +23,7 @@
 // ################ START SUMMARY #################
 //
 //	Dword	Fields
-//	0	reo_destination_indication[4:0], reserved_0a[6:5], use_flow_id_toeplitz_clfy[7], pkt_selection_fp_ucast_data[8], pkt_selection_fp_mcast_data[9], pkt_selection_fp_1000[10], rxdma0_source_ring_selection[12:11], rxdma0_destination_ring_selection[14:13], reserved_0b[31:15]
+//	0	reo_destination_indication[4:0], lmac_peer_id_msb[6:5], use_flow_id_toeplitz_clfy[7], pkt_selection_fp_ucast_data[8], pkt_selection_fp_mcast_data[9], pkt_selection_fp_1000[10], rxdma0_source_ring_selection[12:11], rxdma0_destination_ring_selection[14:13], reserved_0b[31:15]
 //
 // ################ END SUMMARY #################
 
@@ -31,7 +31,7 @@
 
 struct rxpt_classify_info {
              uint32_t reo_destination_indication      :  5, //[4:0]
-                      reserved_0a                     :  2, //[6:5]
+                      lmac_peer_id_msb                :  2, //[6:5]
                       use_flow_id_toeplitz_clfy       :  1, //[7]
                       pkt_selection_fp_ucast_data     :  1, //[8]
                       pkt_selection_fp_mcast_data     :  1, //[9]
@@ -72,10 +72,12 @@ reo_destination_indication
 			the REO2FW ring
 			
 			<enum 7 reo_destination_sw5> Reo will push the frame
-			into the REO2SW5 ring 
+			into the REO2SW5 ring (REO remaps this in chips without
+			REO2SW5 ring, e.g. Pine)
 			
 			<enum 8 reo_destination_sw6> Reo will push the frame
-			into the REO2SW6 ring 
+			into the REO2SW6 ring (REO remaps this in chips without
+			REO2SW6 ring, e.g. Pine)
 			
 			<enum 9 reo_destination_9> REO remaps this <enum 10
 			reo_destination_10> REO remaps this 
@@ -125,15 +127,28 @@ reo_destination_indication
 			
 			<legal all>
 
-reserved_0a
+lmac_peer_id_msb
+			
+			If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb
+			is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1,
+			hash[3:0]} using the chosen Toeplitz hash from Common Parser
+			if flow search fails.
+			
+			If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb
+			's not 2'b00, Rx OLE uses a REO desination indication of
+			{lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash
+			from Common Parser if flow search fails.
+			
+			This LMAC/peer-based routing is not supported in
+			Hastings80 and HastingsPrime.
 			
 			<legal 0>
 
 use_flow_id_toeplitz_clfy
 			
-			Indication to Rx OLE to enable classification based on
-			the chosen Toeplitz hash from Common Parser, in case flow
-			search fails
+			Indication to Rx OLE to enable REO destination routing
+			based on the chosen Toeplitz hash from Common Parser, in
+			case flow search fails
 			
 			<legal all>
 
@@ -274,10 +289,12 @@ reserved_0b
 			the REO2FW ring
 			
 			<enum 7 reo_destination_sw5> Reo will push the frame
-			into the REO2SW5 ring 
+			into the REO2SW5 ring (REO remaps this in chips without
+			REO2SW5 ring, e.g. Pine)
 			
 			<enum 8 reo_destination_sw6> Reo will push the frame
-			into the REO2SW6 ring 
+			into the REO2SW6 ring (REO remaps this in chips without
+			REO2SW6 ring, e.g. Pine)
 			
 			<enum 9 reo_destination_9> REO remaps this <enum 10
 			reo_destination_10> REO remaps this 
@@ -331,19 +348,32 @@ reserved_0b
 #define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_LSB          0
 #define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_MASK         0x0000001f
 
-/* Description		RXPT_CLASSIFY_INFO_0_RESERVED_0A
+/* Description		RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB
+			
+			If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb
+			is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1,
+			hash[3:0]} using the chosen Toeplitz hash from Common Parser
+			if flow search fails.
+			
+			If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb
+			's not 2'b00, Rx OLE uses a REO desination indication of
+			{lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash
+			from Common Parser if flow search fails.
+			
+			This LMAC/peer-based routing is not supported in
+			Hastings80 and HastingsPrime.
 			
 			<legal 0>
 */
-#define RXPT_CLASSIFY_INFO_0_RESERVED_0A_OFFSET                      0x00000000
-#define RXPT_CLASSIFY_INFO_0_RESERVED_0A_LSB                         5
-#define RXPT_CLASSIFY_INFO_0_RESERVED_0A_MASK                        0x00000060
+#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_OFFSET                 0x00000000
+#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_LSB                    5
+#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_MASK                   0x00000060
 
 /* Description		RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY
 			
-			Indication to Rx OLE to enable classification based on
-			the chosen Toeplitz hash from Common Parser, in case flow
-			search fails
+			Indication to Rx OLE to enable REO destination routing
+			based on the chosen Toeplitz hash from Common Parser, in
+			case flow search fails
 			
 			<legal all>
 */

+ 14 - 2
hw/qcn9000/sw_xml_headers.h

@@ -35,6 +35,7 @@
 #include "l_sig_a_info.h"
 #include "l_sig_b_info.h"
 #include "mactx_abort_request_info.h"
+#include "mactx_prefetch_cv_bulk_user.h"
 #include "mimo_control_info.h"
 #include "mimo_control_info_l1.h"
 #include "no_ack_report.h"
@@ -76,6 +77,7 @@
 #include "rxpt_classify_info.h"
 #include "scheduler_cmd.h"
 #include "service_info.h"
+#include "sw_monitor_ring.h"
 #include "sw_peer_info.h"
 #include "tcl_cce_classify_info.h"
 #include "tcl_cce_info.h"
@@ -154,10 +156,12 @@
 #include "mactx_mu_uplink_common_punc.h"
 #include "mactx_other_transmit_info_dl_ofdma_tx.h"
 #include "mactx_other_transmit_info_emuphy_setup.h"
+#include "mactx_other_transmit_info_sch_details.h"
 #include "mactx_phy_desc.h"
 #include "mactx_phy_nap.h"
 #include "mactx_pre_phy_desc.h"
 #include "mactx_prefetch_cv.h"
+#include "mactx_prefetch_cv_bulk.h"
 #include "mactx_prefetch_cv_common.h"
 #include "mactx_user_desc_common.h"
 #include "mactx_vht_sig_a.h"
@@ -186,6 +190,9 @@
 #include "phyrx_ht_sig.h"
 #include "phyrx_l_sig_a.h"
 #include "phyrx_l_sig_b.h"
+#include "phyrx_other_receive_info_108p_evm_details.h"
+#include "phyrx_other_receive_info_evm_details.h"
+#include "phyrx_other_receive_info_mu_rssi_common.h"
 #include "phyrx_pkt_end.h"
 #include "phyrx_rssi_ht.h"
 #include "phyrx_rssi_legacy.h"
@@ -219,7 +226,6 @@
 #include "response_end_status.h"
 #include "response_start_status.h"
 #include "rx_frame_bitmap_req.h"
-#include "rx_frameless_bar_details.h"
 #include "rx_pm_info.h"
 #include "rx_ppdu_ack_report.h"
 #include "rx_ppdu_end_status_done.h"
@@ -240,6 +246,8 @@
 #include "scheduler_rx_sifs_response_trigger_status.h"
 #include "scheduler_selfgen_response_status.h"
 #include "scheduler_sw_msg_status.h"
+#include "snoop_ppdu_end.h"
+#include "snoop_ppdu_start.h"
 #include "srp_info.h"
 #include "tcl_data_cmd.h"
 #include "tcl_gse_cmd.h"
@@ -313,7 +321,7 @@
 #include "phyrx_common_user_info.h"
 #include "phyrx_he_sig_b2_mu.h"
 #include "phyrx_he_sig_b2_ofdma.h"
-#include "phyrx_other_receive_info_evm_details.h"
+#include "phyrx_other_receive_info_mu_rssi_user.h"
 #include "phyrx_other_receive_info_ru_details.h"
 #include "phyrx_user_info.h"
 #include "phyrx_vht_sig_b_mu160.h"
@@ -322,6 +330,7 @@
 #include "phyrx_vht_sig_b_mu80.h"
 #include "rx_attention.h"
 #include "rx_frame_bitmap_ack.h"
+#include "rx_frameless_bar_details.h"
 #include "rx_header.h"
 #include "rx_mpdu_end.h"
 #include "rx_mpdu_pcu_start.h"
@@ -334,6 +343,9 @@
 #include "rx_ppdu_start_user_info.h"
 #include "rxpcu_user_setup.h"
 #include "rxpcu_user_setup_ext.h"
+#include "snoop_mpdu_usr_dbg_info.h"
+#include "snoop_mpdu_usr_stat_info.h"
+#include "snoop_msdu_usr_dbg_info.h"
 #include "tqm_acked_mpdu.h"
 #include "tqm_update_tx_mpdu_count.h"
 #include "tx_11ah_setup.h"

+ 14 - 4
hw/qcn9000/tlv_tag_def.h

@@ -14,10 +14,6 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-/**
- * Generated file ... Do not hand edit ...
- */
-
 #ifndef _TLV_TAG_DEF_
 #define _TLV_TAG_DEF_
 
@@ -492,6 +488,20 @@ typedef enum {
   WIFISCHEDULER_SW_MSG_STATUS_E            = 466 /* 0x1d2 */,
   WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E  = 467 /* 0x1d3 */,
   WIFIRXPCU_SETUP_COMPLETE_E               = 468 /* 0x1d4 */,
+  WIFISNOOP_PPDU_START_E                   = 469 /* 0x1d5 */,
+  WIFISNOOP_MPDU_USR_DBG_INFO_E            = 470 /* 0x1d6 */,
+  WIFISNOOP_MSDU_USR_DBG_INFO_E            = 471 /* 0x1d7 */,
+  WIFISNOOP_MSDU_USR_DATA_E                = 472 /* 0x1d8 */,
+  WIFISNOOP_MPDU_USR_STAT_INFO_E           = 473 /* 0x1d9 */,
+  WIFISNOOP_PPDU_END_E                     = 474 /* 0x1da */,
+  WIFISNOOP_SPARE_E                        = 475 /* 0x1db */,
+  WIFIMACTX_PREFETCH_CV_BULK_E             = 476 /* 0x1dc */,
+  WIFIMACTX_PREFETCH_CV_BULK_USER_E        = 477 /* 0x1dd */,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 478 /* 0x1de */,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 479 /* 0x1df */,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 480 /* 0x1e0 */,
+  WIFISW_MONITOR_RING_E                    = 481 /* 0x1e1 */,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 482 /* 0x1e2 */,
   WIFITLV_BASE_E                           = 511 /* 0x1ff */
 
 } tlv_tag_def__e; ///< tlv_tag_def Enum Type

File diff suppressed because it is too large
+ 275 - 167
hw/qcn9000/wbm_reg_seq_hwioreg.h


+ 70 - 9
hw/qcn9000/wbm_release_ring.h

@@ -27,7 +27,7 @@
 //	Dword	Fields
 //	0-1	struct buffer_addr_info released_buff_or_desc_addr_info;
 //	2	release_source_module[2:0], bm_action[5:3], buffer_or_desc_type[8:6], first_msdu_index[12:9], tqm_release_reason[16:13], rxdma_push_reason[18:17], rxdma_error_code[23:19], reo_push_reason[25:24], reo_error_code[30:26], wbm_internal_error[31]
-//	3	tqm_status_number[23:0], transmit_count[30:24], reserved_3a[31]
+//	3	tqm_status_number[23:0], transmit_count[30:24], msdu_continuation[31]
 //	4	ack_frame_rssi[7:0], sw_release_details_valid[8], first_msdu[9], last_msdu[10], msdu_part_of_amsdu[11], fw_tx_notify_frame[12], buffer_timestamp[31:13]
 //	5-6	struct tx_rate_stats_info tx_rate_stats;
 //	7	sw_peer_id[15:0], tid[19:16], ring_id[27:20], looping_count[31:28]
@@ -50,7 +50,7 @@ struct wbm_release_ring {
                       wbm_internal_error              :  1; //[31]
              uint32_t tqm_status_number               : 24, //[23:0]
                       transmit_count                  :  7, //[30:24]
-                      reserved_3a                     :  1; //[31]
+                      msdu_continuation               :  1; //[31]
              uint32_t ack_frame_rssi                  :  8, //[7:0]
                       sw_release_details_valid        :  1, //[8]
                       first_msdu                      :  1, //[9]
@@ -80,6 +80,15 @@ struct buffer_addr_info released_buff_or_desc_addr_info
 			descriptor, WBM will look at the 'owner' of the released
 			buffer/descriptor and forward it to SW/FW is WBM is not the
 			owner.
+			
+			
+			
+			In case of TQM releasing Tx MSDU link descriptors with
+			Tqm_release_reason set to 'tqm_fw_reason3,' HastingsPrime
+			WBM can optionally release the MSDU buffers pointed to by
+			the MSDU link descriptors to FW and override the
+			tx_rate_stats field, for FW reinjection of these MSDUs.
+			This is not supported in Pine.
 
 release_source_module
 			
@@ -276,6 +285,15 @@ tqm_release_reason
 			
 			
 			<legal 0-8>
+			
+			
+			
+			In case of TQM releasing Tx MSDU link descriptors with
+			Tqm_release_reason set to 'tqm_fw_reason3,' HastingsPrime
+			WBM can optionally release the MSDU buffers pointed to by
+			the MSDU link descriptors to FW and override the
+			tx_rate_stats field, for FW reinjection of these MSDUs.
+			This is not supported in Pine.
 
 rxdma_push_reason
 			
@@ -493,9 +511,13 @@ transmit_count
 			
 			The number of times this frame has been transmitted
 
-reserved_3a
+msdu_continuation
 			
-			<legal 0>
+			requests MSDU_continuation reporting for Rx
+			MSDUs in Pine and HastingsPrime for which
+			SW_release_details_valid may not be set.
+			
+			<legal all>
 
 ack_frame_rssi
 			
@@ -554,6 +576,10 @@ first_msdu
 			
 			
 			
+			extends this to Rx MSDUs in Pine and
+			HastingsPrime for which SW_release_details_valid may not be
+			set.
+			
 			<legal all>
 
 last_msdu
@@ -573,6 +599,10 @@ last_msdu
 			
 			
 			
+			extends this to Rx MSDUs in Pine and
+			HastingsPrime for which SW_release_details_valid may not be
+			set.
+			
 			<legal all>
 
 msdu_part_of_amsdu
@@ -638,6 +668,16 @@ struct tx_rate_stats_info tx_rate_stats
 			
 			
 			Details for command execution tracking purposes. 
+			
+			
+			
+			In case of TQM releasing Tx MSDU link descriptors with
+			Tqm_release_reason set to 'tqm_fw_reason3,' HastingsPrime
+			WBM can optionally release the MSDU buffers pointed to by
+			the MSDU link descriptors to FW and override the
+			tx_rate_stats field with words 2 and 3 of the
+			'TX_MSDU_DETAILS' structure, for FW reinjection of these
+			MSDUs. This is not supported in Pine.
 
 sw_peer_id
 			
@@ -1153,6 +1193,15 @@ looping_count
 			
 			
 			<legal 0-8>
+			
+			
+			
+			In case of TQM releasing Tx MSDU link descriptors with
+			Tqm_release_reason set to 'tqm_fw_reason3,' HastingsPrime
+			WBM can optionally release the MSDU buffers pointed to by
+			the MSDU link descriptors to FW and override the
+			tx_rate_stats field, for FW reinjection of these MSDUs.
+			This is not supported in Pine.
 */
 #define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET                 0x00000008
 #define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB                    13
@@ -1402,13 +1451,17 @@ looping_count
 #define WBM_RELEASE_RING_3_TRANSMIT_COUNT_LSB                        24
 #define WBM_RELEASE_RING_3_TRANSMIT_COUNT_MASK                       0x7f000000
 
-/* Description		WBM_RELEASE_RING_3_RESERVED_3A
+/* Description		WBM_RELEASE_RING_3_MSDU_CONTINUATION
 			
-			<legal 0>
+			requests MSDU_continuation reporting for Rx
+			MSDUs in Pine and HastingsPrime for which
+			SW_release_details_valid may not be set.
+			
+			<legal all>
 */
-#define WBM_RELEASE_RING_3_RESERVED_3A_OFFSET                        0x0000000c
-#define WBM_RELEASE_RING_3_RESERVED_3A_LSB                           31
-#define WBM_RELEASE_RING_3_RESERVED_3A_MASK                          0x80000000
+#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET                  0x0000000c
+#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB                     31
+#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK                    0x80000000
 
 /* Description		WBM_RELEASE_RING_4_ACK_FRAME_RSSI
 			
@@ -1475,6 +1528,10 @@ looping_count
 			
 			
 			
+			extends this to Rx MSDUs in Pine and
+			HastingsPrime for which SW_release_details_valid may not be
+			set.
+			
 			<legal all>
 */
 #define WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET                         0x00000010
@@ -1498,6 +1555,10 @@ looping_count
 			
 			
 			
+			extends this to Rx MSDUs in Pine and
+			HastingsPrime for which SW_release_details_valid may not be
+			set.
+			
 			<legal all>
 */
 #define WBM_RELEASE_RING_4_LAST_MSDU_OFFSET                          0x00000010

+ 400 - 169
hw/qcn9000/wcss_seq_hwiobase.h

@@ -14,17 +14,6 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-///////////////////////////////////////////////////////////////////////////////////////////////
-//
-///////////////////////////////////////////////////////////////////////////////////////////////
-//
-// wcss_seq_hwiobase.h : automatically generated by Autoseq  3.8 3/6/2019 
-// User Name:pbechana
-//
-// !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
-//
-///////////////////////////////////////////////////////////////////////////////////////////////
-
 #ifndef __WCSS_SEQ_BASE_H__
 #define __WCSS_SEQ_BASE_H__
 
@@ -34,7 +23,7 @@
 	#include "msmhwio.h"
 #endif
 
-#include "rfa_from_wsi_seq_hwiobase.h"
+
 #include "wcss_seq_hwiobase_ext.h"
 #define SOC_WCSS_BASE_ADDR 0x00000000
 ///////////////////////////////////////////////////////////////////////////////////////////////
@@ -66,6 +55,65 @@
 #define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET                      0x00480000
 #define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET                       0x004b0000
 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_1_REG_MAP_OFFSET                 0x00500000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_OFFSET                          0x005c0000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET                  0x005d4000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET              0x005d4000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET         0x005d4240
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET         0x005d42c0
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET           0x005d4300
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET      0x005d4400
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET          0x005d4480
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET           0x005d4800
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET     0x005d6000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET   0x005d6040
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET   0x005d6100
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET     0x005d6140
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET   0x005d6180
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET     0x005d61c0
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET     0x005d6280
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET     0x005d6800
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET   0x005d6840
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET   0x005d6900
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET     0x005d6940
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET   0x005d6980
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET     0x005d6a00
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET     0x005d6a80
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET   0x005d7c00
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_PMU_OFFSET                  0x005da000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_PMU_PMU_OFFSET              0x005da000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET                   0x005e0000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET         0x005e0000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET       0x005e0400
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET       0x005e0800
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET       0x005e1000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET       0x005e1300
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH0_OFFSET     0x005e1600
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH0_OFFSET         0x005e1640
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET        0x005e2000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET         0x005e8000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET       0x005e8400
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET       0x005e8800
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET       0x005e9000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET       0x005e9300
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH1_OFFSET     0x005e9600
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH1_OFFSET         0x005e9640
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET        0x005ea000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET         0x005f0000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET       0x005f0400
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET       0x005f0800
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH2_OFFSET       0x005f1000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH2_OFFSET       0x005f1300
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH2_OFFSET     0x005f1600
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH2_OFFSET         0x005f1640
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET        0x005f2000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET         0x005f8000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET       0x005f8400
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET       0x005f8800
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH3_OFFSET       0x005f9000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH3_OFFSET       0x005f9300
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH3_OFFSET     0x005f9600
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH3_OFFSET         0x005f9640
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET        0x005fa000
 #define SEQ_WCSS_UMAC_OFFSET                                         0x00a00000
 #define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET                             0x00a20000
 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET                 0x00a20000
@@ -108,66 +156,68 @@
 #define SEQ_WCSS_PMM_TOP_OFFSET                                      0x00b70000
 #define SEQ_WCSS_WL_MSIP_OFFSET                                      0x00b80000
 #define SEQ_WCSS_WL_MSIP_RBIST_TX_CH0_OFFSET                         0x00b80000
-#define SEQ_WCSS_WL_MSIP_WL_DAC_CH0_OFFSET                           0x00b80180
-#define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH0_OFFSET            0x00b801c0
-#define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH0_OFFSET                      0x00b802c0
-#define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET                  0x00b8033c
-#define SEQ_WCSS_WL_MSIP_WL_ADC_CH0_OFFSET                           0x00b80340
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET           0x00b80400
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET            0x00b80440
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET           0x00b80480
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET            0x00b804c0
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH0_OFFSET               0x00b80500
-#define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET                  0x00b8059c
+#define SEQ_WCSS_WL_MSIP_WL_DAC_CH0_OFFSET                           0x00b80080
+#define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH0_OFFSET            0x00b800c0
+#define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH0_OFFSET                      0x00b80340
+#define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET                  0x00b803bc
+#define SEQ_WCSS_WL_MSIP_WL_ADC_CH0_OFFSET                           0x00b80400
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET           0x00b80800
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET            0x00b80840
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET           0x00b80880
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET            0x00b808c0
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH0_OFFSET               0x00b80900
+#define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET                  0x00b8099c
 #define SEQ_WCSS_WL_MSIP_RBIST_TX_CH1_OFFSET                         0x00b81000
-#define SEQ_WCSS_WL_MSIP_WL_DAC_CH1_OFFSET                           0x00b81180
-#define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH1_OFFSET            0x00b811c0
-#define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH1_OFFSET                      0x00b812c0
-#define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH1_OFFSET                  0x00b8133c
-#define SEQ_WCSS_WL_MSIP_WL_ADC_CH1_OFFSET                           0x00b81340
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET           0x00b81400
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET            0x00b81440
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET           0x00b81480
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET            0x00b814c0
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH1_OFFSET               0x00b81500
-#define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH1_OFFSET                  0x00b8159c
+#define SEQ_WCSS_WL_MSIP_WL_DAC_CH1_OFFSET                           0x00b81080
+#define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH1_OFFSET            0x00b810c0
+#define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH1_OFFSET                      0x00b81340
+#define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH1_OFFSET                  0x00b813bc
+#define SEQ_WCSS_WL_MSIP_WL_ADC_CH1_OFFSET                           0x00b81400
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET           0x00b81800
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET            0x00b81840
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET           0x00b81880
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET            0x00b818c0
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH1_OFFSET               0x00b81900
+#define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH1_OFFSET                  0x00b8199c
 #define SEQ_WCSS_WL_MSIP_RBIST_TX_CH2_OFFSET                         0x00b82000
-#define SEQ_WCSS_WL_MSIP_WL_DAC_CH2_OFFSET                           0x00b82180
-#define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH2_OFFSET            0x00b821c0
-#define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH2_OFFSET                      0x00b822c0
-#define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH2_OFFSET                  0x00b8233c
-#define SEQ_WCSS_WL_MSIP_WL_ADC_CH2_OFFSET                           0x00b82340
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH2_OFFSET           0x00b82400
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH2_OFFSET            0x00b82440
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH2_OFFSET           0x00b82480
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH2_OFFSET            0x00b824c0
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH2_OFFSET               0x00b82500
-#define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH2_OFFSET                  0x00b8259c
+#define SEQ_WCSS_WL_MSIP_WL_DAC_CH2_OFFSET                           0x00b82080
+#define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH2_OFFSET            0x00b820c0
+#define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH2_OFFSET                      0x00b82340
+#define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH2_OFFSET                  0x00b823bc
+#define SEQ_WCSS_WL_MSIP_WL_ADC_CH2_OFFSET                           0x00b82400
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH2_OFFSET           0x00b82800
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH2_OFFSET            0x00b82840
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH2_OFFSET           0x00b82880
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH2_OFFSET            0x00b828c0
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH2_OFFSET               0x00b82900
+#define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH2_OFFSET                  0x00b8299c
 #define SEQ_WCSS_WL_MSIP_RBIST_TX_CH3_OFFSET                         0x00b83000
-#define SEQ_WCSS_WL_MSIP_WL_DAC_CH3_OFFSET                           0x00b83180
-#define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH3_OFFSET            0x00b831c0
-#define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH3_OFFSET                      0x00b832c0
-#define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH3_OFFSET                  0x00b8333c
-#define SEQ_WCSS_WL_MSIP_WL_ADC_CH3_OFFSET                           0x00b83340
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH3_OFFSET           0x00b83400
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH3_OFFSET            0x00b83440
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH3_OFFSET           0x00b83480
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH3_OFFSET            0x00b834c0
-#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH3_OFFSET               0x00b83500
-#define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH3_OFFSET                  0x00b8359c
+#define SEQ_WCSS_WL_MSIP_WL_DAC_CH3_OFFSET                           0x00b83080
+#define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH3_OFFSET            0x00b830c0
+#define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH3_OFFSET                      0x00b83340
+#define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH3_OFFSET                  0x00b833bc
+#define SEQ_WCSS_WL_MSIP_WL_ADC_CH3_OFFSET                           0x00b83400
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH3_OFFSET           0x00b83800
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH3_OFFSET            0x00b83840
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH3_OFFSET           0x00b83880
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH3_OFFSET            0x00b838c0
+#define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH3_OFFSET               0x00b83900
+#define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH3_OFFSET                  0x00b8399c
 #define SEQ_WCSS_WL_MSIP_MSIP_TMUX_OFFSET                            0x00b8d000
 #define SEQ_WCSS_WL_MSIP_MSIP_OTP_OFFSET                             0x00b8d080
-#define SEQ_WCSS_WL_MSIP_MSIP_LDO_CTRL_OFFSET                        0x00b8d0a0
-#define SEQ_WCSS_WL_MSIP_WL_ICIC_OFFSET                              0x00b8d340
-#define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_I_EVEN_OFFSET              0x00b8d400
-#define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_I_ODD_OFFSET               0x00b8d440
-#define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_Q_EVEN_OFFSET              0x00b8d480
-#define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_Q_ODD_OFFSET               0x00b8d4c0
-#define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_RO_OFFSET                  0x00b8d500
-#define SEQ_WCSS_WL_MSIP_WL_ICIC_BBCLKGEN_OFFSET                     0x00b8d59c
+#define SEQ_WCSS_WL_MSIP_MSIP_LDO_CTRL_OFFSET                        0x00b8d0b4
+#define SEQ_WCSS_WL_MSIP_MSIP_CLKGEN_OFFSET                          0x00b8d100
+#define SEQ_WCSS_WL_MSIP_WL_ICIC_OFFSET                              0x00b8d400
+#define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_I_EVEN_OFFSET              0x00b8d800
+#define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_I_ODD_OFFSET               0x00b8d840
+#define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_Q_EVEN_OFFSET              0x00b8d880
+#define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_Q_ODD_OFFSET               0x00b8d8c0
+#define SEQ_WCSS_WL_MSIP_WL_ICIC_POSTPROC_RO_OFFSET                  0x00b8d900
+#define SEQ_WCSS_WL_MSIP_WL_ICIC_BBCLKGEN_OFFSET                     0x00b8d99c
+#define SEQ_WCSS_WL_MSIP_WL_ICIC_CTRL_OFFSET                         0x00b8d9a4
 #define SEQ_WCSS_WL_MSIP_MSIP_BIAS_OFFSET                            0x00b8e000
 #define SEQ_WCSS_WL_MSIP_BBPLL_OFFSET                                0x00b8f000
-#define SEQ_WCSS_WL_MSIP_WL_TOP_CLKGEN_OFFSET                        0x00b8f800
+#define SEQ_WCSS_WL_MSIP_WL_TOP_CLKGEN_OFFSET                        0x00b8f100
 #define SEQ_WCSS_WL_MSIP_MSIP_DRM_REG_OFFSET                         0x00b8fc00
 #define SEQ_WCSS_DBG_OFFSET                                          0x00b90000
 #define SEQ_WCSS_DBG_WCSS_DBG_DAPROM_OFFSET                          0x00b90000
@@ -176,35 +226,52 @@
 #define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET                    0x00b94000
 #define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET                     0x00b95000
 #define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET                    0x00b96000
-#define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET                    0x00ba0000
-#define SEQ_WCSS_DBG_TPDM_OFFSET                                     0x00ba1000
-#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00ba1280
-#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00ba1000
-#define SEQ_WCSS_DBG_TPDA_OFFSET                                     0x00ba2000
-#define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET                      0x00ba3000
-#define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET                       0x00ba4000
-#define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET               0x00ba6000
-#define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET                        0x00ba8000
-#define SEQ_WCSS_DBG_TRCCNTRS_OFFSET                                 0x00ba9000
-#define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET                            0x00bb0000
-#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_OFFSET                            0x00bc0000
-#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET                   0x00bc0000
-#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET     0x00bc4000
-#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET         0x00bc5000
-#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET            0x00bc6000
-#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_ITM_OFFSET                        0x00bc8000
-#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_DWT_OFFSET                        0x00bc9000
-#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FPB_OFFSET                        0x00bca000
-#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_SCS_OFFSET                        0x00bcb000
-#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3_ETM_OFFSET                     0x00bcc000
-#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET        0x00bcd000
-#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET             0x00bce000
-#define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET                              0x00c01000
+#define SEQ_WCSS_DBG_EVENT_MACEVENT_OFFSET                           0x00bb0000
+#define SEQ_WCSS_DBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET              0x00bb1000
+#define SEQ_WCSS_DBG_TLV_MACTLV_OFFSET                               0x00bb2000
+#define SEQ_WCSS_DBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET                0x00bb3000
+#define SEQ_WCSS_DBG_TBUS_MACTBUS_OFFSET                             0x00bb4000
+#define SEQ_WCSS_DBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET               0x00bb5000
+#define SEQ_WCSS_DBG_CTIMAC_QC_CTI_12T_8CH_OFFSET                    0x00bb6000
+#define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET                    0x00bb8000
+#define SEQ_WCSS_DBG_TPDM_OFFSET                                     0x00bb9000
+#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00bb9280
+#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00bb9000
+#define SEQ_WCSS_DBG_TPDA_OFFSET                                     0x00bba000
+#define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET                      0x00bbb000
+#define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET                       0x00bbc000
+#define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET               0x00bbe000
+#define SEQ_WCSS_DBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET               0x00bbf000
+#define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET                        0x00bc0000
+#define SEQ_WCSS_DBG_TRCCNTRS_OFFSET                                 0x00bc1000
+#define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_OFFSET                    0x00bc2000
+#define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc2280
+#define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc2000
+#define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_OFFSET                   0x00bc3000
+#define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc3280
+#define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc3000
+#define SEQ_WCSS_DBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET                  0x00bc4000
+#define SEQ_WCSS_DBG_CTITGU_QC_CTI_4T_8CH_OFFSET                     0x00bc5000
+#define SEQ_WCSS_DBG_PHYADMUX_ATB_DEMUX_OFFSET                       0x00bc6000
+#define SEQ_WCSS_DBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET               0x00bc8000
+#define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET                            0x00bd0000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_OFFSET                            0x00be0000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET                   0x00be0000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET     0x00be4000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET         0x00be5000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET            0x00be6000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_ITM_OFFSET                        0x00be8000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_DWT_OFFSET                        0x00be9000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FPB_OFFSET                        0x00bea000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_SCS_OFFSET                        0x00beb000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3_ETM_OFFSET                     0x00bec000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET        0x00bed000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET             0x00bee000
+#define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET                              0x00c31000
 #define SEQ_WCSS_RET_AHB_OFFSET                                      0x00c90000
 #define SEQ_WCSS_WAHB_TSLV_OFFSET                                    0x00ca0000
 #define SEQ_WCSS_CC_OFFSET                                           0x00cb0000
 #define SEQ_WCSS_UMAC_ACMT_OFFSET                                    0x00cc0000
-
 #define SEQ_WCSS_Q6SS_WLAN_OFFSET                                    0x00d00000
 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_OFFSET                         0x00d00000
 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET       0x00d00000
@@ -219,6 +286,7 @@
 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00db0000
 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00db0000
 
+
 ///////////////////////////////////////////////////////////////////////////////////////////////
 // Instance Relative Offsets from Block wfax_top
 ///////////////////////////////////////////////////////////////////////////////////////////////
@@ -244,8 +312,143 @@
 #define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET                       0x00180000
 #define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET                        0x001b0000
 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_1_REG_MAP_OFFSET                  0x00200000
-#define SEQ_WFAX_TOP_RFA_REG_MAP_OFFSET                              0x002c0000
-#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET                      SEQ_WFAX_TOP_RFA_REG_MAP_OFFSET
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET                      0x002c0000 
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block rfa_from_wsi
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET                              0x00014000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET                          0x00014000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET                     0x00014240
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET                     0x000142c0
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET                       0x00014300
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET                  0x00014400
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET                      0x00014480
+#define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET                       0x00014800
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET                 0x00016000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET               0x00016040
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET               0x00016100
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET                 0x00016140
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET               0x00016180
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET                 0x000161c0
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_LO_OFFSET                 0x00016280
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BS_OFFSET                 0x00016800
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_CLBS_OFFSET               0x00016840
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET               0x00016900
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET                 0x00016940
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET               0x00016980
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET                 0x00016a00
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_LO_OFFSET                 0x00016a80
+#define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET               0x00017c00
+#define SEQ_RFA_FROM_WSI_RFA_PMU_OFFSET                              0x0001a000
+#define SEQ_RFA_FROM_WSI_RFA_PMU_PMU_OFFSET                          0x0001a000
+#define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET                               0x00020000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH0_OFFSET                     0x00020000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET                   0x00020400
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET                   0x00020800
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH0_OFFSET                   0x00021000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH0_OFFSET                   0x00021300
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH0_OFFSET                 0x00021600
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH0_OFFSET                     0x00021640
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH0_OFFSET                    0x00022000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH1_OFFSET                     0x00028000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH1_OFFSET                   0x00028400
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH1_OFFSET                   0x00028800
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH1_OFFSET                   0x00029000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH1_OFFSET                   0x00029300
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH1_OFFSET                 0x00029600
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH1_OFFSET                     0x00029640
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH1_OFFSET                    0x0002a000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH2_OFFSET                     0x00030000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH2_OFFSET                   0x00030400
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH2_OFFSET                   0x00030800
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH2_OFFSET                   0x00031000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH2_OFFSET                   0x00031300
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH2_OFFSET                 0x00031600
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH2_OFFSET                     0x00031640
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH2_OFFSET                    0x00032000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH3_OFFSET                     0x00038000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH3_OFFSET                   0x00038400
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH3_OFFSET                   0x00038800
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH3_OFFSET                   0x00039000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH3_OFFSET                   0x00039300
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH3_OFFSET                 0x00039600
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH3_OFFSET                     0x00039640
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH3_OFFSET                    0x0003a000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block rfa_cmn
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_RFA_CMN_AON_OFFSET                                       0x00000000
+#define SEQ_RFA_CMN_AON_XFEM_OFFSET                                  0x00000240
+#define SEQ_RFA_CMN_AON_COEX_OFFSET                                  0x000002c0
+#define SEQ_RFA_CMN_RFFE_M_OFFSET                                    0x00000300
+#define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET                               0x00000400
+#define SEQ_RFA_CMN_RFA_OTP_OFFSET                                   0x00000480
+#define SEQ_RFA_CMN_CLKGEN_OFFSET                                    0x00000800
+#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET                              0x00002000
+#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET                            0x00002040
+#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET                            0x00002100
+#define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET                              0x00002140
+#define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET                            0x00002180
+#define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET                              0x000021c0
+#define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET                              0x00002280
+#define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET                              0x00002800
+#define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET                            0x00002840
+#define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET                            0x00002900
+#define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET                              0x00002940
+#define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET                            0x00002980
+#define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET                              0x00002a00
+#define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET                              0x00002a80
+#define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET                            0x00003c00
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block rfa_pmu
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_RFA_PMU_PMU_OFFSET                                       0x00000000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block rfa_wl
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_RFA_WL_WL_MC_CH0_OFFSET                                  0x00000000
+#define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET                                0x00000400
+#define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET                                0x00000800
+#define SEQ_RFA_WL_WL_RXFE_CH0_OFFSET                                0x00001000
+#define SEQ_RFA_WL_WL_TXFE_CH0_OFFSET                                0x00001300
+#define SEQ_RFA_WL_WL_LO_PAL_CH0_OFFSET                              0x00001600
+#define SEQ_RFA_WL_WL_LO_CH0_OFFSET                                  0x00001640
+#define SEQ_RFA_WL_WL_TPC_CH0_OFFSET                                 0x00002000
+#define SEQ_RFA_WL_WL_MC_CH1_OFFSET                                  0x00008000
+#define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET                                0x00008400
+#define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET                                0x00008800
+#define SEQ_RFA_WL_WL_RXFE_CH1_OFFSET                                0x00009000
+#define SEQ_RFA_WL_WL_TXFE_CH1_OFFSET                                0x00009300
+#define SEQ_RFA_WL_WL_LO_PAL_CH1_OFFSET                              0x00009600
+#define SEQ_RFA_WL_WL_LO_CH1_OFFSET                                  0x00009640
+#define SEQ_RFA_WL_WL_TPC_CH1_OFFSET                                 0x0000a000
+#define SEQ_RFA_WL_WL_MC_CH2_OFFSET                                  0x00010000
+#define SEQ_RFA_WL_WL_RXBB_CH2_OFFSET                                0x00010400
+#define SEQ_RFA_WL_WL_TXBB_CH2_OFFSET                                0x00010800
+#define SEQ_RFA_WL_WL_RXFE_CH2_OFFSET                                0x00011000
+#define SEQ_RFA_WL_WL_TXFE_CH2_OFFSET                                0x00011300
+#define SEQ_RFA_WL_WL_LO_PAL_CH2_OFFSET                              0x00011600
+#define SEQ_RFA_WL_WL_LO_CH2_OFFSET                                  0x00011640
+#define SEQ_RFA_WL_WL_TPC_CH2_OFFSET                                 0x00012000
+#define SEQ_RFA_WL_WL_MC_CH3_OFFSET                                  0x00018000
+#define SEQ_RFA_WL_WL_RXBB_CH3_OFFSET                                0x00018400
+#define SEQ_RFA_WL_WL_TXBB_CH3_OFFSET                                0x00018800
+#define SEQ_RFA_WL_WL_RXFE_CH3_OFFSET                                0x00019000
+#define SEQ_RFA_WL_WL_TXFE_CH3_OFFSET                                0x00019300
+#define SEQ_RFA_WL_WL_LO_PAL_CH3_OFFSET                              0x00019600
+#define SEQ_RFA_WL_WL_LO_CH3_OFFSET                                  0x00019640
+#define SEQ_RFA_WL_WL_TPC_CH3_OFFSET                                 0x0001a000
 
 
 ///////////////////////////////////////////////////////////////////////////////////////////////
@@ -310,66 +513,68 @@
 ///////////////////////////////////////////////////////////////////////////////////////////////
 
 #define SEQ_MSIP_RBIST_TX_CH0_OFFSET                                 0x00000000
-#define SEQ_MSIP_WL_DAC_CH0_OFFSET                                   0x00000180
-#define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH0_OFFSET                    0x000001c0
-#define SEQ_MSIP_WL_DAC_MISC_CH0_OFFSET                              0x000002c0
-#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET                          0x0000033c
-#define SEQ_MSIP_WL_ADC_CH0_OFFSET                                   0x00000340
-#define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET                   0x00000400
-#define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET                    0x00000440
-#define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET                   0x00000480
-#define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET                    0x000004c0
-#define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH0_OFFSET                       0x00000500
-#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET                          0x0000059c
+#define SEQ_MSIP_WL_DAC_CH0_OFFSET                                   0x00000080
+#define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH0_OFFSET                    0x000000c0
+#define SEQ_MSIP_WL_DAC_MISC_CH0_OFFSET                              0x00000340
+#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET                          0x000003bc
+#define SEQ_MSIP_WL_ADC_CH0_OFFSET                                   0x00000400
+#define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET                   0x00000800
+#define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET                    0x00000840
+#define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET                   0x00000880
+#define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET                    0x000008c0
+#define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH0_OFFSET                       0x00000900
+#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET                          0x0000099c
 #define SEQ_MSIP_RBIST_TX_CH1_OFFSET                                 0x00001000
-#define SEQ_MSIP_WL_DAC_CH1_OFFSET                                   0x00001180
-#define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH1_OFFSET                    0x000011c0
-#define SEQ_MSIP_WL_DAC_MISC_CH1_OFFSET                              0x000012c0
-#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH1_OFFSET                          0x0000133c
-#define SEQ_MSIP_WL_ADC_CH1_OFFSET                                   0x00001340
-#define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET                   0x00001400
-#define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET                    0x00001440
-#define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET                   0x00001480
-#define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET                    0x000014c0
-#define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH1_OFFSET                       0x00001500
-#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH1_OFFSET                          0x0000159c
+#define SEQ_MSIP_WL_DAC_CH1_OFFSET                                   0x00001080
+#define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH1_OFFSET                    0x000010c0
+#define SEQ_MSIP_WL_DAC_MISC_CH1_OFFSET                              0x00001340
+#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH1_OFFSET                          0x000013bc
+#define SEQ_MSIP_WL_ADC_CH1_OFFSET                                   0x00001400
+#define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET                   0x00001800
+#define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET                    0x00001840
+#define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET                   0x00001880
+#define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET                    0x000018c0
+#define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH1_OFFSET                       0x00001900
+#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH1_OFFSET                          0x0000199c
 #define SEQ_MSIP_RBIST_TX_CH2_OFFSET                                 0x00002000
-#define SEQ_MSIP_WL_DAC_CH2_OFFSET                                   0x00002180
-#define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH2_OFFSET                    0x000021c0
-#define SEQ_MSIP_WL_DAC_MISC_CH2_OFFSET                              0x000022c0
-#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH2_OFFSET                          0x0000233c
-#define SEQ_MSIP_WL_ADC_CH2_OFFSET                                   0x00002340
-#define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH2_OFFSET                   0x00002400
-#define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH2_OFFSET                    0x00002440
-#define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH2_OFFSET                   0x00002480
-#define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH2_OFFSET                    0x000024c0
-#define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH2_OFFSET                       0x00002500
-#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH2_OFFSET                          0x0000259c
+#define SEQ_MSIP_WL_DAC_CH2_OFFSET                                   0x00002080
+#define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH2_OFFSET                    0x000020c0
+#define SEQ_MSIP_WL_DAC_MISC_CH2_OFFSET                              0x00002340
+#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH2_OFFSET                          0x000023bc
+#define SEQ_MSIP_WL_ADC_CH2_OFFSET                                   0x00002400
+#define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH2_OFFSET                   0x00002800
+#define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH2_OFFSET                    0x00002840
+#define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH2_OFFSET                   0x00002880
+#define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH2_OFFSET                    0x000028c0
+#define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH2_OFFSET                       0x00002900
+#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH2_OFFSET                          0x0000299c
 #define SEQ_MSIP_RBIST_TX_CH3_OFFSET                                 0x00003000
-#define SEQ_MSIP_WL_DAC_CH3_OFFSET                                   0x00003180
-#define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH3_OFFSET                    0x000031c0
-#define SEQ_MSIP_WL_DAC_MISC_CH3_OFFSET                              0x000032c0
-#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH3_OFFSET                          0x0000333c
-#define SEQ_MSIP_WL_ADC_CH3_OFFSET                                   0x00003340
-#define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH3_OFFSET                   0x00003400
-#define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH3_OFFSET                    0x00003440
-#define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH3_OFFSET                   0x00003480
-#define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH3_OFFSET                    0x000034c0
-#define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH3_OFFSET                       0x00003500
-#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH3_OFFSET                          0x0000359c
+#define SEQ_MSIP_WL_DAC_CH3_OFFSET                                   0x00003080
+#define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH3_OFFSET                    0x000030c0
+#define SEQ_MSIP_WL_DAC_MISC_CH3_OFFSET                              0x00003340
+#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH3_OFFSET                          0x000033bc
+#define SEQ_MSIP_WL_ADC_CH3_OFFSET                                   0x00003400
+#define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH3_OFFSET                   0x00003800
+#define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH3_OFFSET                    0x00003840
+#define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH3_OFFSET                   0x00003880
+#define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH3_OFFSET                    0x000038c0
+#define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH3_OFFSET                       0x00003900
+#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH3_OFFSET                          0x0000399c
 #define SEQ_MSIP_MSIP_TMUX_OFFSET                                    0x0000d000
 #define SEQ_MSIP_MSIP_OTP_OFFSET                                     0x0000d080
-#define SEQ_MSIP_MSIP_LDO_CTRL_OFFSET                                0x0000d0a0
-#define SEQ_MSIP_WL_ICIC_OFFSET                                      0x0000d340
-#define SEQ_MSIP_WL_ICIC_POSTPROC_I_EVEN_OFFSET                      0x0000d400
-#define SEQ_MSIP_WL_ICIC_POSTPROC_I_ODD_OFFSET                       0x0000d440
-#define SEQ_MSIP_WL_ICIC_POSTPROC_Q_EVEN_OFFSET                      0x0000d480
-#define SEQ_MSIP_WL_ICIC_POSTPROC_Q_ODD_OFFSET                       0x0000d4c0
-#define SEQ_MSIP_WL_ICIC_POSTPROC_RO_OFFSET                          0x0000d500
-#define SEQ_MSIP_WL_ICIC_BBCLKGEN_OFFSET                             0x0000d59c
+#define SEQ_MSIP_MSIP_LDO_CTRL_OFFSET                                0x0000d0b4
+#define SEQ_MSIP_MSIP_CLKGEN_OFFSET                                  0x0000d100
+#define SEQ_MSIP_WL_ICIC_OFFSET                                      0x0000d400
+#define SEQ_MSIP_WL_ICIC_POSTPROC_I_EVEN_OFFSET                      0x0000d800
+#define SEQ_MSIP_WL_ICIC_POSTPROC_I_ODD_OFFSET                       0x0000d840
+#define SEQ_MSIP_WL_ICIC_POSTPROC_Q_EVEN_OFFSET                      0x0000d880
+#define SEQ_MSIP_WL_ICIC_POSTPROC_Q_ODD_OFFSET                       0x0000d8c0
+#define SEQ_MSIP_WL_ICIC_POSTPROC_RO_OFFSET                          0x0000d900
+#define SEQ_MSIP_WL_ICIC_BBCLKGEN_OFFSET                             0x0000d99c
+#define SEQ_MSIP_WL_ICIC_CTRL_OFFSET                                 0x0000d9a4
 #define SEQ_MSIP_MSIP_BIAS_OFFSET                                    0x0000e000
 #define SEQ_MSIP_BBPLL_OFFSET                                        0x0000f000
-#define SEQ_MSIP_WL_TOP_CLKGEN_OFFSET                                0x0000f800
+#define SEQ_MSIP_WL_TOP_CLKGEN_OFFSET                                0x0000f100
 #define SEQ_MSIP_MSIP_DRM_REG_OFFSET                                 0x0000fc00
 
 
@@ -383,30 +588,48 @@
 #define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET                     0x00004000
 #define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET                      0x00005000
 #define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET                     0x00006000
-#define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET                     0x00010000
-#define SEQ_WCSSDBG_TPDM_OFFSET                                      0x00011000
-#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00011280
-#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00011000
-#define SEQ_WCSSDBG_TPDA_OFFSET                                      0x00012000
-#define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET                       0x00013000
-#define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET                        0x00014000
-#define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET                0x00016000
-#define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET                         0x00018000
-#define SEQ_WCSSDBG_TRCCNTRS_OFFSET                                  0x00019000
-#define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET                             0x00020000
-#define SEQ_WCSSDBG_PHYA_PHYA_DBG_OFFSET                             0x00030000
-#define SEQ_WCSSDBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET                    0x00030000
-#define SEQ_WCSSDBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET      0x00034000
-#define SEQ_WCSSDBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET          0x00035000
-#define SEQ_WCSSDBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET             0x00036000
-#define SEQ_WCSSDBG_PHYA_PHYA_DBG_ITM_OFFSET                         0x00038000
-#define SEQ_WCSSDBG_PHYA_PHYA_DBG_DWT_OFFSET                         0x00039000
-#define SEQ_WCSSDBG_PHYA_PHYA_DBG_FPB_OFFSET                         0x0003a000
-#define SEQ_WCSSDBG_PHYA_PHYA_DBG_SCS_OFFSET                         0x0003b000
-#define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3_ETM_OFFSET                      0x0003c000
-#define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET         0x0003d000
-#define SEQ_WCSSDBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET              0x0003e000
-#define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET                               0x00071000
+#define SEQ_WCSSDBG_EVENT_MACEVENT_OFFSET                            0x00020000
+#define SEQ_WCSSDBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET               0x00021000
+#define SEQ_WCSSDBG_TLV_MACTLV_OFFSET                                0x00022000
+#define SEQ_WCSSDBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET                 0x00023000
+#define SEQ_WCSSDBG_TBUS_MACTBUS_OFFSET                              0x00024000
+#define SEQ_WCSSDBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET                0x00025000
+#define SEQ_WCSSDBG_CTIMAC_QC_CTI_12T_8CH_OFFSET                     0x00026000
+#define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET                     0x00028000
+#define SEQ_WCSSDBG_TPDM_OFFSET                                      0x00029000
+#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00029280
+#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00029000
+#define SEQ_WCSSDBG_TPDA_OFFSET                                      0x0002a000
+#define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET                       0x0002b000
+#define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET                        0x0002c000
+#define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET                0x0002e000
+#define SEQ_WCSSDBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET                0x0002f000
+#define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET                         0x00030000
+#define SEQ_WCSSDBG_TRCCNTRS_OFFSET                                  0x00031000
+#define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_OFFSET                     0x00032000
+#define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00032280
+#define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00032000
+#define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_OFFSET                    0x00033000
+#define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00033280
+#define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00033000
+#define SEQ_WCSSDBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET                   0x00034000
+#define SEQ_WCSSDBG_CTITGU_QC_CTI_4T_8CH_OFFSET                      0x00035000
+#define SEQ_WCSSDBG_PHYADMUX_ATB_DEMUX_OFFSET                        0x00036000
+#define SEQ_WCSSDBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET                0x00038000
+#define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET                             0x00040000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_OFFSET                             0x00050000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET                    0x00050000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET      0x00054000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET          0x00055000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET             0x00056000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_ITM_OFFSET                         0x00058000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_DWT_OFFSET                         0x00059000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_FPB_OFFSET                         0x0005a000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_SCS_OFFSET                         0x0005b000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3_ETM_OFFSET                      0x0005c000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET         0x0005d000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET              0x0005e000
+#define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET                               0x000a1000
 
 
 ///////////////////////////////////////////////////////////////////////////////////////////////
@@ -417,6 +640,14 @@
 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000
 
 
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block tpdm_atb128_cmb64
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET           0x00000280
+#define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET           0x00000000
+
+
 ///////////////////////////////////////////////////////////////////////////////////////////////
 // Instance Relative Offsets from Block phya_dbg
 ///////////////////////////////////////////////////////////////////////////////////////////////

+ 1 - 1
hw/qcn9000/wcss_version.h

@@ -14,4 +14,4 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-#define WCSS_VERSION 30
+#define WCSS_VERSION 1051

+ 89 - 65
hw/qcn9000/wfss_ce_reg_seq_hwioreg.h

@@ -24,7 +24,7 @@
   @brief Auto-generated HWIO interface include file.
 
   Reference chip release:
-    QCN90xx (Pine) [PINE_TOP_P2_R14_2019_05_17]
+    QCN90xx (Pine) [PINE_TOP_P3_R34_2019_08_30_JSON]
  
   This file contains HWIO register definitions for the following modules:
     CE_.*
@@ -67,7 +67,7 @@
 /*----------------------------------------------------------------------------
  * MODULE: WFSS_CE_0_CHANNEL_SRC_REG
  *--------------------------------------------------------------------------*/
-#include "msmhwioreg.h"
+#define CE_WFSS_CE_REG_BASE 0x1B80000
 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x1B80000
 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x1B81000
 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x1B82000
@@ -15041,9 +15041,33 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK                                          0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT                                                 0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x)                                                                 ((x) + 0x0000004c)
-#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_PHYS(x)                                                                 ((x) + 0x0000004c)
-#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OFFS                                                                    (0x0000004c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_ADDR(x)                                                    ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_PHYS(x)                                                    ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_OFFS                                                       (0x0000004c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_RMSK                                                           0x9f9f
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_POR                                                        0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_POR_RMSK                                                   0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_ATTR                                                              0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_IN(x)      \
+        in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_INM(x, m)      \
+        in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_OUT(x, v)      \
+        out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_OUTM(x,m,v) \
+        out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK                                                 0x8000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT                                                    0xf
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK                                                0x1f00
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT                                                   0x8
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK                                                   0x80
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT                                                    0x7
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK                                                  0x1f
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT                                                   0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x)                                                                 ((x) + 0x00000050)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_PHYS(x)                                                                 ((x) + 0x00000050)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OFFS                                                                    (0x00000050)
 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK                                                                     0x1ffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_POR                                                                     0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_POR_RMSK                                                                0xffffffff
@@ -15063,9 +15087,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK                                                             0xfff
 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT                                                               0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x)                                                                 ((x) + 0x00000050)
-#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_PHYS(x)                                                                 ((x) + 0x00000050)
-#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OFFS                                                                    (0x00000050)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x)                                                                 ((x) + 0x00000054)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_PHYS(x)                                                                 ((x) + 0x00000054)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OFFS                                                                    (0x00000054)
 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK                                                                         0xfff
 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_POR                                                                     0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_POR_RMSK                                                                0xffffffff
@@ -15081,9 +15105,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK                                                             0xfff
 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT                                                               0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x)                                                                  ((x) + 0x00000054)
-#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_PHYS(x)                                                                  ((x) + 0x00000054)
-#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OFFS                                                                     (0x00000054)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x)                                                                  ((x) + 0x00000058)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_PHYS(x)                                                                  ((x) + 0x00000058)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OFFS                                                                     (0x00000058)
 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK                                                                       0xffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_POR                                                                      0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_POR_RMSK                                                                 0xffffffff
@@ -15101,9 +15125,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK                                                                      0xfff
 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT                                                                        0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x)                                                               ((x) + 0x00000058)
-#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_PHYS(x)                                                               ((x) + 0x00000058)
-#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OFFS                                                                  (0x00000058)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x)                                                               ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_PHYS(x)                                                               ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OFFS                                                                  (0x0000005c)
 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK                                                                   0x1ffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_POR                                                                   0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_POR_RMSK                                                              0xffffffff
@@ -15123,9 +15147,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK                                                           0xfff
 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT                                                             0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x)                                                               ((x) + 0x0000005c)
-#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_PHYS(x)                                                               ((x) + 0x0000005c)
-#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OFFS                                                                  (0x0000005c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x)                                                               ((x) + 0x00000060)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_PHYS(x)                                                               ((x) + 0x00000060)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OFFS                                                                  (0x00000060)
 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK                                                                       0xfff
 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_POR                                                                   0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_POR_RMSK                                                              0xffffffff
@@ -15141,9 +15165,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK                                                           0xfff
 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT                                                             0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x)                                                      ((x) + 0x00000060)
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_PHYS(x)                                                      ((x) + 0x00000060)
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OFFS                                                         (0x00000060)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x)                                                      ((x) + 0x00000064)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_PHYS(x)                                                      ((x) + 0x00000064)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OFFS                                                         (0x00000064)
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK                                                         0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_POR                                                          0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_POR_RMSK                                                     0xffffffff
@@ -15159,9 +15183,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK                                                  0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT                                                         0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x)                                                      ((x) + 0x00000064)
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_PHYS(x)                                                      ((x) + 0x00000064)
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OFFS                                                         (0x00000064)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x)                                                      ((x) + 0x00000068)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_PHYS(x)                                                      ((x) + 0x00000068)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OFFS                                                         (0x00000068)
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK                                                         0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_POR                                                          0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_POR_RMSK                                                     0xffffffff
@@ -15177,9 +15201,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK                                                  0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT                                                         0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x)                                                      ((x) + 0x00000068)
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_PHYS(x)                                                      ((x) + 0x00000068)
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OFFS                                                         (0x00000068)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x)                                                      ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_PHYS(x)                                                      ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OFFS                                                         (0x0000006c)
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK                                                                0x1
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_POR                                                          0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_POR_RMSK                                                     0xffffffff
@@ -15195,9 +15219,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_BMSK                                                         0x1
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_SHFT                                                         0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x)                                                           ((x) + 0x0000006c)
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_PHYS(x)                                                           ((x) + 0x0000006c)
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OFFS                                                              (0x0000006c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x)                                                           ((x) + 0x00000070)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_PHYS(x)                                                           ((x) + 0x00000070)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OFFS                                                              (0x00000070)
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK                                                              0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POR                                                               0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POR_RMSK                                                          0xffffffff
@@ -15213,9 +15237,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_BMSK                                                       0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_SHFT                                                              0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x)                                                           ((x) + 0x00000070)
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_PHYS(x)                                                           ((x) + 0x00000070)
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OFFS                                                              (0x00000070)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x)                                                           ((x) + 0x00000074)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_PHYS(x)                                                           ((x) + 0x00000074)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OFFS                                                              (0x00000074)
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK                                                              0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POR                                                               0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POR_RMSK                                                          0xffffffff
@@ -15231,9 +15255,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_BMSK                                                       0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_SHFT                                                              0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x)                                                           ((x) + 0x00000074)
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_PHYS(x)                                                           ((x) + 0x00000074)
-#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OFFS                                                              (0x00000074)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x)                                                           ((x) + 0x00000078)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_PHYS(x)                                                           ((x) + 0x00000078)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OFFS                                                              (0x00000078)
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK                                                                     0x1
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POR                                                               0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POR_RMSK                                                          0xffffffff
@@ -15249,9 +15273,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_BMSK                                                              0x1
 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_SHFT                                                              0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x)                                                               ((x) + 0x00000078)
-#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_PHYS(x)                                                               ((x) + 0x00000078)
-#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OFFS                                                                  (0x00000078)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x)                                                               ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_PHYS(x)                                                               ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OFFS                                                                  (0x0000007c)
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK                                                                  0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_POR                                                                   0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_POR_RMSK                                                              0xffffffff
@@ -15263,9 +15287,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK                                                            0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT                                                                   0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x)                                                               ((x) + 0x0000007c)
-#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_PHYS(x)                                                               ((x) + 0x0000007c)
-#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OFFS                                                                  (0x0000007c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x)                                                               ((x) + 0x00000080)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_PHYS(x)                                                               ((x) + 0x00000080)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OFFS                                                                  (0x00000080)
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK                                                                  0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_POR                                                                   0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_POR_RMSK                                                              0xffffffff
@@ -15277,9 +15301,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK                                                            0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT                                                                   0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x)                                                               ((x) + 0x00000080)
-#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_PHYS(x)                                                               ((x) + 0x00000080)
-#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OFFS                                                                  (0x00000080)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x)                                                               ((x) + 0x00000084)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_PHYS(x)                                                               ((x) + 0x00000084)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OFFS                                                                  (0x00000084)
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK                                                                  0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_POR                                                                   0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_POR_RMSK                                                              0xffffffff
@@ -15291,9 +15315,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK                                                            0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT                                                                   0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x)                                                               ((x) + 0x00000084)
-#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_PHYS(x)                                                               ((x) + 0x00000084)
-#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OFFS                                                                  (0x00000084)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x)                                                               ((x) + 0x00000088)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_PHYS(x)                                                               ((x) + 0x00000088)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OFFS                                                                  (0x00000088)
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK                                                                  0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_POR                                                                   0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_POR_RMSK                                                              0xffffffff
@@ -15305,9 +15329,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK                                                            0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT                                                                   0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x)                                                            ((x) + 0x00000088)
-#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_PHYS(x)                                                            ((x) + 0x00000088)
-#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OFFS                                                               (0x00000088)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x)                                                            ((x) + 0x0000008c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_PHYS(x)                                                            ((x) + 0x0000008c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OFFS                                                               (0x0000008c)
 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK                                                               0xfffdffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_POR                                                                0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_POR_RMSK                                                           0xffffffff
@@ -15333,9 +15357,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_BMSK                                                       0xfff
 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_SHFT                                                         0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x)                                                            ((x) + 0x0000008c)
-#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_PHYS(x)                                                            ((x) + 0x0000008c)
-#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OFFS                                                               (0x0000008c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x)                                                            ((x) + 0x00000090)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_PHYS(x)                                                            ((x) + 0x00000090)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OFFS                                                               (0x00000090)
 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK                                                                 0xffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_POR                                                                0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_POR_RMSK                                                           0xffffffff
@@ -15353,9 +15377,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_BMSK                                                       0xfff
 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_SHFT                                                         0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x)                                                            ((x) + 0x00000090)
-#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_PHYS(x)                                                            ((x) + 0x00000090)
-#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OFFS                                                               (0x00000090)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x)                                                            ((x) + 0x00000094)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_PHYS(x)                                                            ((x) + 0x00000094)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OFFS                                                               (0x00000094)
 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK                                                                   0x1fff
 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_POR                                                                0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_POR_RMSK                                                           0xffffffff
@@ -15373,9 +15397,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_BMSK                                                       0xfff
 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_SHFT                                                         0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x)                                                               ((x) + 0x00000094)
-#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_PHYS(x)                                                               ((x) + 0x00000094)
-#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OFFS                                                                  (0x00000094)
+#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x)                                                               ((x) + 0x00000098)
+#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_PHYS(x)                                                               ((x) + 0x00000098)
+#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OFFS                                                                  (0x00000098)
 #define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK                                                                       0xfff
 #define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_POR                                                                   0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_POR_RMSK                                                              0xffffffff
@@ -15391,9 +15415,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_BMSK                                                              0xfff
 #define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_SHFT                                                                0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR(x)                                                      ((x) + 0x00000098)
-#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_PHYS(x)                                                      ((x) + 0x00000098)
-#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_OFFS                                                         (0x00000098)
+#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR(x)                                                      ((x) + 0x0000009c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_PHYS(x)                                                      ((x) + 0x0000009c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_OFFS                                                         (0x0000009c)
 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK                                                         0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_POR                                                          0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_POR_RMSK                                                     0xffffffff
@@ -15405,9 +15429,9 @@
 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_BMSK                                                   0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_SHFT                                                          0x0
 
-#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x)                                                           ((x) + 0x0000009c)
-#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_PHYS(x)                                                           ((x) + 0x0000009c)
-#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OFFS                                                              (0x0000009c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x)                                                           ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_PHYS(x)                                                           ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OFFS                                                              (0x000000a0)
 #define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK                                                              0xffffffff
 #define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_POR                                                               0x00000000
 #define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_POR_RMSK                                                          0xffffffff

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