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msm: eva: reset AXI and CTRL clocks

Avoid pending transaction after EVA is power off. The transactions
may be introduced by PDX FIFO CX side pointer not reset after EVA power
collapsed. PMU can turn on AXI clock on CX side. It may trigger spurious
DDR transactions that are abnormal, in our case, the write transaction
has header, but not data.

Change-Id: I1374aa5ddf64ecc56c6c806cf096bed2761fd9a7
Signed-off-by: George Shen <[email protected]>
George Shen 3 years ago
parent
commit
d20d1298e2
2 changed files with 20 additions and 8 deletions
  1. 19 7
      msm/eva/cvp_hfi.c
  2. 1 1
      msm/eva/msm_cvp_resources.h

+ 19 - 7
msm/eva/cvp_hfi.c

@@ -3072,7 +3072,8 @@ static int __handle_reset_clk(struct msm_cvp_platform_resources *res,
 			goto failed_to_reset;
 			goto failed_to_reset;
 		}
 		}
 
 
-		if (pwr_state != rst_info.required_state)
+		if (pwr_state != CVP_POWER_IGNORED &&
+			pwr_state != rst_info.required_state)
 			break;
 			break;
 
 
 		rc = reset_control_assert(rst);
 		rc = reset_control_assert(rst);
@@ -3083,7 +3084,8 @@ static int __handle_reset_clk(struct msm_cvp_platform_resources *res,
 			goto failed_to_reset;
 			goto failed_to_reset;
 		}
 		}
 
 
-		if (pwr_state != rst_info.required_state)
+		if (pwr_state != CVP_POWER_IGNORED &&
+			pwr_state != rst_info.required_state)
 			break;
 			break;
 
 
 		rc = reset_control_deassert(rst);
 		rc = reset_control_deassert(rst);
@@ -3117,6 +3119,8 @@ static int reset_ahb2axi_bridge(struct iris_hfi_device *device)
 	else
 	else
 		s = CVP_POWER_OFF;
 		s = CVP_POWER_OFF;
 
 
+	s = CVP_POWER_IGNORED;
+
 	for (i = 0; i < device->res->reset_set.count; i++) {
 	for (i = 0; i < device->res->reset_set.count; i++) {
 		rc = __handle_reset_clk(device->res, i, ASSERT, s);
 		rc = __handle_reset_clk(device->res, i, ASSERT, s);
 		if (rc) {
 		if (rc) {
@@ -3124,10 +3128,12 @@ static int reset_ahb2axi_bridge(struct iris_hfi_device *device)
 				"failed to assert reset clocks\n");
 				"failed to assert reset clocks\n");
 			goto failed_to_reset;
 			goto failed_to_reset;
 		}
 		}
+	}
 
 
-		/* wait for deassert */
-		usleep_range(1000, 1050);
+	/* wait for deassert */
+	usleep_range(1000, 1050);
 
 
+	for (i = 0; i < device->res->reset_set.count; i++) {
 		rc = __handle_reset_clk(device->res, i, DEASSERT, s);
 		rc = __handle_reset_clk(device->res, i, DEASSERT, s);
 		if (rc) {
 		if (rc) {
 			dprintk(CVP_ERR,
 			dprintk(CVP_ERR,
@@ -3902,6 +3908,7 @@ static int __power_off_controller(struct iris_hfi_device *device)
 {
 {
 	u32 lpi_status, reg_status = 0, count = 0, max_count = 1000;
 	u32 lpi_status, reg_status = 0, count = 0, max_count = 1000;
 	u32 sbm_ln0_low;
 	u32 sbm_ln0_low;
+	int rc;
 
 
 	/* HPG 6.2.2 Step 1  */
 	/* HPG 6.2.2 Step 1  */
 	__write_register(device, CVP_CPU_CS_X2RPMh, 0x3);
 	__write_register(device, CVP_CPU_CS_X2RPMh, 0x3);
@@ -3988,12 +3995,17 @@ static int __power_off_controller(struct iris_hfi_device *device)
 	/* HPG 6.2.2 Step 5 */
 	/* HPG 6.2.2 Step 5 */
 	msm_cvp_disable_unprepare_clk(device, "cvp_clk");
 	msm_cvp_disable_unprepare_clk(device, "cvp_clk");
 
 
-	/* HPG 6.2.2 Step 6 */
-	__disable_regulator(device, "cvp");
-
 	/* HPG 6.2.2 Step 7 */
 	/* HPG 6.2.2 Step 7 */
 	msm_cvp_disable_unprepare_clk(device, "gcc_video_axi1");
 	msm_cvp_disable_unprepare_clk(device, "gcc_video_axi1");
 
 
+	/* Added to avoid pending transaction after power off */
+	rc = call_iris_op(device, reset_ahb2axi_bridge, device);
+	if (rc)
+		dprintk(CVP_ERR, "Off: Failed to reset ahb2axi: %d\n", rc);
+
+	/* HPG 6.2.2 Step 6 */
+	__disable_regulator(device, "cvp");
+
 	return 0;
 	return 0;
 }
 }
 
 

+ 1 - 1
msm/eva/msm_cvp_resources.h

@@ -88,7 +88,7 @@ enum power_state {
 	CVP_POWER_INIT,
 	CVP_POWER_INIT,
 	CVP_POWER_ON,
 	CVP_POWER_ON,
 	CVP_POWER_OFF,
 	CVP_POWER_OFF,
-	CVP_POWER_INVALID,
+	CVP_POWER_IGNORED,
 };
 };
 
 
 struct reset_info {
 struct reset_info {