Merge "msm: camera: isp: Fix PPI index based on the phy selection" into camera-kernel.lnx.5.0

drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c

@@ -162,9 +162,7 @@ static int cam_csid_ppi_init_hw(void *hw_priv, void *init_args,
 {
 	int i, rc = 0;
 	uint32_t num_lanes;
-	uint32_t lanes[CAM_CSID_PPI_HW_MAX] = {0, 0, 0, 0};
 	uint32_t cphy;
-	bool dl0, dl1;
 	uint32_t ppi_cfg_val = 0;
 	struct cam_csid_ppi_hw                *ppi_hw;
 	struct cam_hw_info                    *ppi_hw_info;
@@ -179,7 +177,6 @@ static int cam_csid_ppi_init_hw(void *hw_priv, void *init_args,
 		goto end;
 	}
 
-	dl0 = dl1 = false;
 	ppi_hw_info = (struct cam_hw_info *)hw_priv;
 	ppi_hw      = (struct cam_csid_ppi_hw *)ppi_hw_info->core_info;
 	ppi_reg     = ppi_hw->ppi_info->ppi_reg;
@@ -194,31 +191,16 @@ static int cam_csid_ppi_init_hw(void *hw_priv, void *init_args,
 	CAM_DBG(CAM_ISP, "lane_cfg  0x%x | num_lanes  0x%x | lane_type 0x%x",
 		ppi_cfg.lane_cfg, num_lanes, cphy);
 
-	for (i = 0; i < num_lanes; i++) {
-		lanes[i] = ppi_cfg.lane_cfg & (0x3 << (4 * i));
-		(lanes[i] < 2) ? (dl0 = true) : (dl1 = true);
-		CAM_DBG(CAM_ISP, "lanes[%d] %d", i, lanes[i]);
-	}
-
-	if (num_lanes) {
-		if (cphy) {
-			for (i = 0; i < num_lanes; i++) {
-				ppi_cfg_val |= PPI_CFG_CPHY_DLX_SEL(lanes[i]);
-				ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(lanes[i]);
-			}
-		} else {
-			if (dl0)
-				ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(0);
-			if (dl1)
-				ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(1);
-		}
+	if (cphy) {
+		ppi_cfg_val |= PPI_CFG_CPHY_DLX_SEL(0);
+		ppi_cfg_val |= PPI_CFG_CPHY_DLX_SEL(1);
 	} else {
-		CAM_ERR(CAM_ISP,
-			"Number of lanes to enable is cannot be zero");
-		rc = -1;
-		goto end;
+		ppi_cfg_val = 0;
 	}
 
+	for (i = 0; i < CAM_CSID_PPI_LANES_MAX; i++)
+		ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(i);
+
 	CAM_DBG(CAM_ISP, "ppi_cfg_val 0x%x", ppi_cfg_val);
 	soc_info = &ppi_hw->hw_info->soc_info;
 	cam_io_w_mb(ppi_cfg_val, soc_info->reg_map[0].mem_base +

drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CAM_CSID_PPI_HW_H_
@@ -25,7 +25,7 @@
 /*
  * Select the PHY (CPHY set '1' or DPHY set '0')
  */
-#define PPI_CFG_CPHY_DLX_SEL(X)            ((X < 2) ? BIT(X) : 0)
+#define PPI_CFG_CPHY_DLX_SEL(X)            BIT(X)
 
 #define PPI_CFG_CPHY_DLX_EN(X)             BIT(4+X)
 

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h

@@ -144,6 +144,7 @@ static struct cam_tfe_csid_csi2_rx_reg_offset
 	.csid_csi2_rx_irq_set_addr                    = 0x2c,
 
 	/*CSI2 rx control */
+	.phy_sel_base                                 = 1,
 	.csid_csi2_rx_cfg0_addr                       = 0x100,
 	.csid_csi2_rx_cfg1_addr                       = 0x104,
 	.csid_csi2_rx_capture_ctrl_addr               = 0x108,

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid640.h

@@ -182,6 +182,7 @@ static struct cam_tfe_csid_csi2_rx_reg_offset
 	.csid_csi2_rx_irq_set_addr                    = 0x2c,
 
 	/*CSI2 rx control */
+	.phy_sel_base                                 = 1,
 	.csid_csi2_rx_cfg0_addr                       = 0x100,
 	.csid_csi2_rx_cfg1_addr                       = 0x104,
 	.csid_csi2_rx_capture_ctrl_addr               = 0x108,

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c

@@ -1022,8 +1022,14 @@ static int cam_tfe_csid_enable_csi2(
 
 	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
 		csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr);
+	/*
+	 * There is one to one mapping for ppi index with phy index
+	 * we do not always update phy sel equal to phy number,for some
+	 * targets "phy_sel = phy_num + 1", and for some targets it is
+	 * "phy_sel = phy_num", ppi_index should be updated accordingly
+	 */
+	ppi_index = csid_hw->csi2_rx_cfg.phy_sel - csid_reg->csi2_reg->phy_sel_base;
 
-	ppi_index = csid_hw->csi2_rx_cfg.phy_sel;
 	if (csid_hw->ppi_hw_intf[ppi_index] && csid_hw->ppi_enable) {
 		ppi_lane_cfg.lane_type = csid_hw->csi2_rx_cfg.lane_type;
 		ppi_lane_cfg.lane_num  = csid_hw->csi2_rx_cfg.lane_num;
@@ -1067,7 +1073,7 @@ static int cam_tfe_csid_disable_csi2(
 	cam_io_w_mb(0, soc_info->reg_map[0].mem_base +
 		csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr);
 
-	ppi_index = csid_hw->csi2_rx_cfg.phy_sel;
+	ppi_index = csid_hw->csi2_rx_cfg.phy_sel - csid_reg->csi2_reg->phy_sel_base;
 	if (csid_hw->ppi_hw_intf[ppi_index] && csid_hw->ppi_enable) {
 		/* De-Initialize the PPI bridge */
 		CAM_DBG(CAM_ISP, "ppi_index to de-init %d\n", ppi_index);

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h

@@ -217,6 +217,7 @@ struct cam_tfe_csid_csi2_rx_reg_offset {
 
 	/*configurations */
 	uint32_t phy_tpg_base_id;
+	uint32_t phy_sel_base;
 	uint32_t csi2_rst_srb_all;
 	uint32_t csi2_rst_done_shift_val;
 	uint32_t csi2_irq_mask_all;