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@@ -162,9 +162,7 @@ static int cam_csid_ppi_init_hw(void *hw_priv, void *init_args,
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{
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int i, rc = 0;
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uint32_t num_lanes;
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- uint32_t lanes[CAM_CSID_PPI_HW_MAX] = {0, 0, 0, 0};
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uint32_t cphy;
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- bool dl0, dl1;
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uint32_t ppi_cfg_val = 0;
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struct cam_csid_ppi_hw *ppi_hw;
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struct cam_hw_info *ppi_hw_info;
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@@ -179,7 +177,6 @@ static int cam_csid_ppi_init_hw(void *hw_priv, void *init_args,
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goto end;
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}
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- dl0 = dl1 = false;
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ppi_hw_info = (struct cam_hw_info *)hw_priv;
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ppi_hw = (struct cam_csid_ppi_hw *)ppi_hw_info->core_info;
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ppi_reg = ppi_hw->ppi_info->ppi_reg;
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@@ -194,31 +191,16 @@ static int cam_csid_ppi_init_hw(void *hw_priv, void *init_args,
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CAM_DBG(CAM_ISP, "lane_cfg 0x%x | num_lanes 0x%x | lane_type 0x%x",
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ppi_cfg.lane_cfg, num_lanes, cphy);
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- for (i = 0; i < num_lanes; i++) {
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- lanes[i] = ppi_cfg.lane_cfg & (0x3 << (4 * i));
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- (lanes[i] < 2) ? (dl0 = true) : (dl1 = true);
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- CAM_DBG(CAM_ISP, "lanes[%d] %d", i, lanes[i]);
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- }
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-
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- if (num_lanes) {
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- if (cphy) {
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- for (i = 0; i < num_lanes; i++) {
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- ppi_cfg_val |= PPI_CFG_CPHY_DLX_SEL(lanes[i]);
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- ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(lanes[i]);
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- }
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- } else {
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- if (dl0)
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- ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(0);
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- if (dl1)
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- ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(1);
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- }
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+ if (cphy) {
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+ ppi_cfg_val |= PPI_CFG_CPHY_DLX_SEL(0);
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+ ppi_cfg_val |= PPI_CFG_CPHY_DLX_SEL(1);
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} else {
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- CAM_ERR(CAM_ISP,
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- "Number of lanes to enable is cannot be zero");
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- rc = -1;
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- goto end;
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+ ppi_cfg_val = 0;
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}
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+ for (i = 0; i < CAM_CSID_PPI_LANES_MAX; i++)
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+ ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(i);
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+
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CAM_DBG(CAM_ISP, "ppi_cfg_val 0x%x", ppi_cfg_val);
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soc_info = &ppi_hw->hw_info->soc_info;
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cam_io_w_mb(ppi_cfg_val, soc_info->reg_map[0].mem_base +
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