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@@ -297,7 +297,7 @@ static int __disable_regulator_iris3(struct msm_vidc_core *core,
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rc = __acquire_regulator(core, rinfo);
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if (rc) {
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d_vpr_e("%s: failed to acquire %s, rc = %d\n",
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- rinfo->name, rc);
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+ __func__, rinfo->name, rc);
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/* Bring attention to this issue */
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WARN_ON(true);
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return rc;
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@@ -307,7 +307,7 @@ static int __disable_regulator_iris3(struct msm_vidc_core *core,
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rc = regulator_disable(rinfo->regulator);
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if (rc) {
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d_vpr_e("%s: failed to disable %s, rc = %d\n",
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- rinfo->name, rc);
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+ __func__, rinfo->name, rc);
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return rc;
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}
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d_vpr_h("%s: disabled regulator %s\n", __func__, rinfo->name);
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@@ -575,10 +575,10 @@ static int __power_off_iris3_controller(struct msm_vidc_core *core)
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if (rc)
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d_vpr_h("%s: debug bridge release failed\n", __func__);
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- /* power down process */
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- rc = __disable_regulator_iris3(core, "iris-ctl");
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+ /* Turn off MVP MVS0C core clock */
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+ rc = __disable_unprepare_clock_iris3(core, "core_clk");
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if (rc) {
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- d_vpr_e("%s: disable regulator iris-ctl failed\n", __func__);
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+ d_vpr_e("%s: disable unprepare core_clk failed\n", __func__);
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rc = 0;
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}
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@@ -589,17 +589,16 @@ static int __power_off_iris3_controller(struct msm_vidc_core *core)
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rc = 0;
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}
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- /* Turn off MVP MVS0C core clock */
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- rc = __disable_unprepare_clock_iris3(core, "core_clk");
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+ rc = call_venus_op(core, reset_ahb2axi_bridge, core);
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if (rc) {
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- d_vpr_e("%s: disable unprepare core_clk failed\n", __func__);
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+ d_vpr_e("%s: reset ahb2axi bridge failed\n", __func__);
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rc = 0;
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}
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- /* Turn off MVP MVS0 SRC clock */
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- rc = __disable_unprepare_clock_iris3(core, "video_cc_mvs0_clk_src");
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+ /* power down process */
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+ rc = __disable_regulator_iris3(core, "iris-ctl");
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if (rc) {
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- d_vpr_e("%s: disable unprepare video_cc_mvs0_clk_src failed\n", __func__);
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+ d_vpr_e("%s: disable regulator iris-ctl failed\n", __func__);
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rc = 0;
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}
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@@ -618,6 +617,14 @@ static int __power_off_iris3(struct msm_vidc_core *core)
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if (!core->power_enabled)
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return 0;
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+ /**
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+ * Reset video_cc_mvs0_clk_src value to resolve MMRM high video
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+ * clock projection issue.
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+ */
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+ rc = __set_clocks(core, 0);
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+ if (rc)
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+ d_vpr_e("%s: resetting clocks failed\n", __func__);
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+
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if (__power_off_iris3_hardware(core))
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d_vpr_e("%s: failed to power off hardware\n", __func__);
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@@ -656,14 +663,8 @@ static int __power_on_iris3_controller(struct msm_vidc_core *core)
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if (rc)
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goto fail_clk_controller;
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- rc = __prepare_enable_clock_iris3(core, "video_cc_mvs0_clk_src");
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- if (rc)
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- goto fail_clk_src;
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-
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return 0;
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-fail_clk_src:
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- __disable_unprepare_clock_iris3(core, "core_clk");
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fail_clk_controller:
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__disable_unprepare_clock_iris3(core, "gcc_video_axi0");
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fail_clk_axi:
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@@ -1059,12 +1060,8 @@ int msm_vidc_decide_work_route_iris3(struct msm_vidc_inst* inst)
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CODED_FRAMES_INTERLACE)
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work_route = MSM_VIDC_PIPE_1;
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} else if (is_encode_session(inst)) {
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- u32 slice_mode, width, height;
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- struct v4l2_format* f;
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+ u32 slice_mode;
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- f = &inst->fmts[INPUT_PORT];
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- height = f->fmt.pix_mp.height;
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- width = f->fmt.pix_mp.width;
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slice_mode = inst->capabilities->cap[SLICE_MODE].value;
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/*TODO Pipe=1 for legacy CBR*/
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