Merge "video: driver: Update power down sequence"
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ca802f423a
@@ -273,6 +273,11 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
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{0},
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NULL, msm_vidc_set_u32},
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{TS_REORDER, DEC, H264|HEVC,
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V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE,
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1, V4L2_MPEG_MSM_VIDC_DISABLE,
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V4L2_CID_MPEG_VIDC_TS_REORDER},
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{HFLIP, ENC, CODECS_ALL,
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V4L2_MPEG_MSM_VIDC_DISABLE,
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V4L2_MPEG_MSM_VIDC_ENABLE,
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@@ -401,8 +406,8 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
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{0},
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{LTR_COUNT, IR_RANDOM, TIME_DELTA_BASED_RC, I_FRAME_QP,
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P_FRAME_QP, B_FRAME_QP, ENH_LAYER_COUNT, BIT_RATE,
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CONTENT_ADAPTIVE_CODING, BITRATE_BOOST, MIN_QUALITY,
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VBV_DELAY, PEAK_BITRATE,SLICE_MODE, META_ROI_INFO,
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META_ROI_INFO, MIN_QUALITY, BITRATE_BOOST, VBV_DELAY,
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PEAK_BITRATE, SLICE_MODE, CONTENT_ADAPTIVE_CODING,
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BLUR_TYPES, LOWLATENCY_MODE},
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msm_vidc_adjust_bitrate_mode, msm_vidc_set_u32_enum},
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@@ -419,13 +424,12 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
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{0},
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{LTR_COUNT, IR_RANDOM, TIME_DELTA_BASED_RC, I_FRAME_QP,
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P_FRAME_QP, B_FRAME_QP, CONSTANT_QUALITY, ENH_LAYER_COUNT,
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CONTENT_ADAPTIVE_CODING, BIT_RATE,
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BITRATE_BOOST, MIN_QUALITY, VBV_DELAY,
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PEAK_BITRATE, SLICE_MODE, META_ROI_INFO, BLUR_TYPES,
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LOWLATENCY_MODE},
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BIT_RATE, META_ROI_INFO, MIN_QUALITY, BITRATE_BOOST, VBV_DELAY,
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PEAK_BITRATE, SLICE_MODE, CONTENT_ADAPTIVE_CODING,
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BLUR_TYPES, LOWLATENCY_MODE},
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msm_vidc_adjust_bitrate_mode, msm_vidc_set_u32_enum},
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{LOSSLESS, ENC, HEVC|HEIC,
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{LOSSLESS, ENC, HEVC,
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V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE,
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1, V4L2_MPEG_MSM_VIDC_DISABLE,
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V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU},
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@@ -531,7 +535,7 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
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1, V4L2_MPEG_MSM_VIDC_DISABLE,
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V4L2_CID_MPEG_VIDC_LOWLATENCY_REQUEST,
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HFI_PROP_SEQ_CHANGE_AT_SYNC_FRAME,
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CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED},
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CAP_FLAG_INPUT_PORT},
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{LTR_COUNT, ENC, H264|HEVC,
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0, 2, 1, 0,
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@@ -614,8 +614,7 @@ static int msm_vidc_input_min_count_iris3(struct msm_vidc_inst* inst)
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HFI_IRIS3_ENC_MIN_INPUT_BUF_COUNT(input_min_count,
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total_hb_layer);
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} else {
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i_vpr_e(inst, "%s: invalid domain\n",
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__func__, inst->domain);
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i_vpr_e(inst, "%s: invalid domain %d\n", __func__, inst->domain);
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return 0;
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}
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@@ -297,7 +297,7 @@ static int __disable_regulator_iris3(struct msm_vidc_core *core,
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rc = __acquire_regulator(core, rinfo);
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if (rc) {
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d_vpr_e("%s: failed to acquire %s, rc = %d\n",
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rinfo->name, rc);
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__func__, rinfo->name, rc);
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/* Bring attention to this issue */
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WARN_ON(true);
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return rc;
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@@ -307,7 +307,7 @@ static int __disable_regulator_iris3(struct msm_vidc_core *core,
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rc = regulator_disable(rinfo->regulator);
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if (rc) {
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d_vpr_e("%s: failed to disable %s, rc = %d\n",
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rinfo->name, rc);
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__func__, rinfo->name, rc);
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return rc;
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}
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d_vpr_h("%s: disabled regulator %s\n", __func__, rinfo->name);
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@@ -575,10 +575,10 @@ static int __power_off_iris3_controller(struct msm_vidc_core *core)
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if (rc)
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d_vpr_h("%s: debug bridge release failed\n", __func__);
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/* power down process */
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rc = __disable_regulator_iris3(core, "iris-ctl");
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/* Turn off MVP MVS0C core clock */
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rc = __disable_unprepare_clock_iris3(core, "core_clk");
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if (rc) {
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d_vpr_e("%s: disable regulator iris-ctl failed\n", __func__);
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d_vpr_e("%s: disable unprepare core_clk failed\n", __func__);
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rc = 0;
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}
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@@ -589,17 +589,16 @@ static int __power_off_iris3_controller(struct msm_vidc_core *core)
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rc = 0;
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}
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/* Turn off MVP MVS0C core clock */
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rc = __disable_unprepare_clock_iris3(core, "core_clk");
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rc = call_venus_op(core, reset_ahb2axi_bridge, core);
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if (rc) {
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d_vpr_e("%s: disable unprepare core_clk failed\n", __func__);
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d_vpr_e("%s: reset ahb2axi bridge failed\n", __func__);
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rc = 0;
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}
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/* Turn off MVP MVS0 SRC clock */
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rc = __disable_unprepare_clock_iris3(core, "video_cc_mvs0_clk_src");
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/* power down process */
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rc = __disable_regulator_iris3(core, "iris-ctl");
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if (rc) {
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d_vpr_e("%s: disable unprepare video_cc_mvs0_clk_src failed\n", __func__);
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d_vpr_e("%s: disable regulator iris-ctl failed\n", __func__);
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rc = 0;
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}
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@@ -618,6 +617,14 @@ static int __power_off_iris3(struct msm_vidc_core *core)
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if (!core->power_enabled)
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return 0;
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/**
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* Reset video_cc_mvs0_clk_src value to resolve MMRM high video
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* clock projection issue.
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*/
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rc = __set_clocks(core, 0);
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if (rc)
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d_vpr_e("%s: resetting clocks failed\n", __func__);
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if (__power_off_iris3_hardware(core))
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d_vpr_e("%s: failed to power off hardware\n", __func__);
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@@ -656,14 +663,8 @@ static int __power_on_iris3_controller(struct msm_vidc_core *core)
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if (rc)
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goto fail_clk_controller;
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rc = __prepare_enable_clock_iris3(core, "video_cc_mvs0_clk_src");
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if (rc)
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goto fail_clk_src;
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return 0;
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fail_clk_src:
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__disable_unprepare_clock_iris3(core, "core_clk");
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fail_clk_controller:
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__disable_unprepare_clock_iris3(core, "gcc_video_axi0");
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fail_clk_axi:
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@@ -1059,12 +1060,8 @@ int msm_vidc_decide_work_route_iris3(struct msm_vidc_inst* inst)
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CODED_FRAMES_INTERLACE)
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work_route = MSM_VIDC_PIPE_1;
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} else if (is_encode_session(inst)) {
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u32 slice_mode, width, height;
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struct v4l2_format* f;
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u32 slice_mode;
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f = &inst->fmts[INPUT_PORT];
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height = f->fmt.pix_mp.height;
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width = f->fmt.pix_mp.width;
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slice_mode = inst->capabilities->cap[SLICE_MODE].value;
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/*TODO Pipe=1 for legacy CBR*/
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@@ -15,7 +15,6 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
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{
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u64 freq = 0;
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struct msm_vidc_core* core;
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struct msm_vidc_power* power;
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u64 vsp_cycles = 0, vpp_cycles = 0, fw_cycles = 0;
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u64 fw_vpp_cycles = 0, bitrate = 0;
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u32 vpp_cycles_per_mb;
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@@ -31,7 +30,6 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
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return freq;
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}
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power = &inst->power;
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core = inst->core;
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if (!core->dt) {
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d_vpr_e("%s: invalid params\n", __func__);
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