From 000a10db5697df77705dbdeb1a4c512df15ccdb9 Mon Sep 17 00:00:00 2001 From: Chinmay Sawarkar Date: Thu, 3 Feb 2022 15:26:13 -0800 Subject: [PATCH 1/3] video: driver: Port fixes from iris2 to iris3 1. Change format specifier and API clean-up 2. Remove HEIC from Lossless Encoding 3. add support for timestamp reorder 4. alter bitrate_mode child adjust sequence 5. disable dynamic low latency Change-Id: I57d8150bac123cdfd8a0d14a2422246b87b4abfa Signed-off-by: Chinmay Sawarkar --- driver/platform/kalama/src/msm_vidc_kalama.c | 20 +++++++++++-------- .../variant/iris3/src/msm_vidc_buffer_iris3.c | 3 +-- driver/variant/iris3/src/msm_vidc_iris3.c | 10 +++------- .../variant/iris3/src/msm_vidc_power_iris3.c | 2 -- 4 files changed, 16 insertions(+), 19 deletions(-) diff --git a/driver/platform/kalama/src/msm_vidc_kalama.c b/driver/platform/kalama/src/msm_vidc_kalama.c index ab8af3551b..16104365da 100644 --- a/driver/platform/kalama/src/msm_vidc_kalama.c +++ b/driver/platform/kalama/src/msm_vidc_kalama.c @@ -273,6 +273,11 @@ static struct msm_platform_inst_capability instance_data_kalama[] = { {0}, NULL, msm_vidc_set_u32}, + {TS_REORDER, DEC, H264|HEVC, + V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE, + 1, V4L2_MPEG_MSM_VIDC_DISABLE, + V4L2_CID_MPEG_VIDC_TS_REORDER}, + {HFLIP, ENC, CODECS_ALL, V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE, @@ -401,8 +406,8 @@ static struct msm_platform_inst_capability instance_data_kalama[] = { {0}, {LTR_COUNT, IR_RANDOM, TIME_DELTA_BASED_RC, I_FRAME_QP, P_FRAME_QP, B_FRAME_QP, ENH_LAYER_COUNT, BIT_RATE, - CONTENT_ADAPTIVE_CODING, BITRATE_BOOST, MIN_QUALITY, - VBV_DELAY, PEAK_BITRATE,SLICE_MODE, META_ROI_INFO, + META_ROI_INFO, MIN_QUALITY, BITRATE_BOOST, VBV_DELAY, + PEAK_BITRATE, SLICE_MODE, CONTENT_ADAPTIVE_CODING, BLUR_TYPES, LOWLATENCY_MODE}, msm_vidc_adjust_bitrate_mode, msm_vidc_set_u32_enum}, @@ -419,13 +424,12 @@ static struct msm_platform_inst_capability instance_data_kalama[] = { {0}, {LTR_COUNT, IR_RANDOM, TIME_DELTA_BASED_RC, I_FRAME_QP, P_FRAME_QP, B_FRAME_QP, CONSTANT_QUALITY, ENH_LAYER_COUNT, - CONTENT_ADAPTIVE_CODING, BIT_RATE, - BITRATE_BOOST, MIN_QUALITY, VBV_DELAY, - PEAK_BITRATE, SLICE_MODE, META_ROI_INFO, BLUR_TYPES, - LOWLATENCY_MODE}, + BIT_RATE, META_ROI_INFO, MIN_QUALITY, BITRATE_BOOST, VBV_DELAY, + PEAK_BITRATE, SLICE_MODE, CONTENT_ADAPTIVE_CODING, + BLUR_TYPES, LOWLATENCY_MODE}, msm_vidc_adjust_bitrate_mode, msm_vidc_set_u32_enum}, - {LOSSLESS, ENC, HEVC|HEIC, + {LOSSLESS, ENC, HEVC, V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE, 1, V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU}, @@ -531,7 +535,7 @@ static struct msm_platform_inst_capability instance_data_kalama[] = { 1, V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_CID_MPEG_VIDC_LOWLATENCY_REQUEST, HFI_PROP_SEQ_CHANGE_AT_SYNC_FRAME, - CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED}, + CAP_FLAG_INPUT_PORT}, {LTR_COUNT, ENC, H264|HEVC, 0, 2, 1, 0, diff --git a/driver/variant/iris3/src/msm_vidc_buffer_iris3.c b/driver/variant/iris3/src/msm_vidc_buffer_iris3.c index 66b77c8005..8cf777da6f 100644 --- a/driver/variant/iris3/src/msm_vidc_buffer_iris3.c +++ b/driver/variant/iris3/src/msm_vidc_buffer_iris3.c @@ -614,8 +614,7 @@ static int msm_vidc_input_min_count_iris3(struct msm_vidc_inst* inst) HFI_IRIS3_ENC_MIN_INPUT_BUF_COUNT(input_min_count, total_hb_layer); } else { - i_vpr_e(inst, "%s: invalid domain\n", - __func__, inst->domain); + i_vpr_e(inst, "%s: invalid domain %d\n", __func__, inst->domain); return 0; } diff --git a/driver/variant/iris3/src/msm_vidc_iris3.c b/driver/variant/iris3/src/msm_vidc_iris3.c index 1ce11804b7..2aa9a1979b 100644 --- a/driver/variant/iris3/src/msm_vidc_iris3.c +++ b/driver/variant/iris3/src/msm_vidc_iris3.c @@ -297,7 +297,7 @@ static int __disable_regulator_iris3(struct msm_vidc_core *core, rc = __acquire_regulator(core, rinfo); if (rc) { d_vpr_e("%s: failed to acquire %s, rc = %d\n", - rinfo->name, rc); + __func__, rinfo->name, rc); /* Bring attention to this issue */ WARN_ON(true); return rc; @@ -307,7 +307,7 @@ static int __disable_regulator_iris3(struct msm_vidc_core *core, rc = regulator_disable(rinfo->regulator); if (rc) { d_vpr_e("%s: failed to disable %s, rc = %d\n", - rinfo->name, rc); + __func__, rinfo->name, rc); return rc; } d_vpr_h("%s: disabled regulator %s\n", __func__, rinfo->name); @@ -1059,12 +1059,8 @@ int msm_vidc_decide_work_route_iris3(struct msm_vidc_inst* inst) CODED_FRAMES_INTERLACE) work_route = MSM_VIDC_PIPE_1; } else if (is_encode_session(inst)) { - u32 slice_mode, width, height; - struct v4l2_format* f; + u32 slice_mode; - f = &inst->fmts[INPUT_PORT]; - height = f->fmt.pix_mp.height; - width = f->fmt.pix_mp.width; slice_mode = inst->capabilities->cap[SLICE_MODE].value; /*TODO Pipe=1 for legacy CBR*/ diff --git a/driver/variant/iris3/src/msm_vidc_power_iris3.c b/driver/variant/iris3/src/msm_vidc_power_iris3.c index a3ab8c8d9f..0653e5fe09 100644 --- a/driver/variant/iris3/src/msm_vidc_power_iris3.c +++ b/driver/variant/iris3/src/msm_vidc_power_iris3.c @@ -15,7 +15,6 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size) { u64 freq = 0; struct msm_vidc_core* core; - struct msm_vidc_power* power; u64 vsp_cycles = 0, vpp_cycles = 0, fw_cycles = 0; u64 fw_vpp_cycles = 0, bitrate = 0; u32 vpp_cycles_per_mb; @@ -31,7 +30,6 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size) return freq; } - power = &inst->power; core = inst->core; if (!core->dt) { d_vpr_e("%s: invalid params\n", __func__); From 784cc63c21d9826a70ae21036f656eb8f83956e6 Mon Sep 17 00:00:00 2001 From: Chinmay Sawarkar Date: Wed, 2 Feb 2022 13:06:35 -0800 Subject: [PATCH 2/3] video: driver: reset video_cc_mvs0_clk_src clock_rate Reset video_cc_mvs0_clk_src value to resolve MMRM high video clock projection issue. Change-Id: Ieb937dfdc7d48e1a95a0052a32189d00eeac70cf Signed-off-by: Chinmay Sawarkar --- driver/variant/iris3/src/msm_vidc_iris3.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/driver/variant/iris3/src/msm_vidc_iris3.c b/driver/variant/iris3/src/msm_vidc_iris3.c index 2aa9a1979b..94c79f28a4 100644 --- a/driver/variant/iris3/src/msm_vidc_iris3.c +++ b/driver/variant/iris3/src/msm_vidc_iris3.c @@ -618,6 +618,14 @@ static int __power_off_iris3(struct msm_vidc_core *core) if (!core->power_enabled) return 0; + /** + * Reset video_cc_mvs0_clk_src value to resolve MMRM high video + * clock projection issue. + */ + rc = __set_clocks(core, 0); + if (rc) + d_vpr_e("%s: resetting clocks failed\n", __func__); + if (__power_off_iris3_hardware(core)) d_vpr_e("%s: failed to power off hardware\n", __func__); From f7c4e2fe65bdf285d266666f786ccad2d163c615 Mon Sep 17 00:00:00 2001 From: Chinmay Sawarkar Date: Fri, 4 Feb 2022 15:53:23 -0800 Subject: [PATCH 3/3] video: driver: Update power down sequence Copy fixes in power down sequence from Iris2 to Iris3. Change-Id: I0ec94dbe064e10b6c4172b206561d8951c00a26b Signed-off-by: Chinmay Sawarkar --- driver/variant/iris3/src/msm_vidc_iris3.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/driver/variant/iris3/src/msm_vidc_iris3.c b/driver/variant/iris3/src/msm_vidc_iris3.c index 94c79f28a4..76169626bf 100644 --- a/driver/variant/iris3/src/msm_vidc_iris3.c +++ b/driver/variant/iris3/src/msm_vidc_iris3.c @@ -575,10 +575,10 @@ static int __power_off_iris3_controller(struct msm_vidc_core *core) if (rc) d_vpr_h("%s: debug bridge release failed\n", __func__); - /* power down process */ - rc = __disable_regulator_iris3(core, "iris-ctl"); + /* Turn off MVP MVS0C core clock */ + rc = __disable_unprepare_clock_iris3(core, "core_clk"); if (rc) { - d_vpr_e("%s: disable regulator iris-ctl failed\n", __func__); + d_vpr_e("%s: disable unprepare core_clk failed\n", __func__); rc = 0; } @@ -589,17 +589,16 @@ static int __power_off_iris3_controller(struct msm_vidc_core *core) rc = 0; } - /* Turn off MVP MVS0C core clock */ - rc = __disable_unprepare_clock_iris3(core, "core_clk"); + rc = call_venus_op(core, reset_ahb2axi_bridge, core); if (rc) { - d_vpr_e("%s: disable unprepare core_clk failed\n", __func__); + d_vpr_e("%s: reset ahb2axi bridge failed\n", __func__); rc = 0; } - /* Turn off MVP MVS0 SRC clock */ - rc = __disable_unprepare_clock_iris3(core, "video_cc_mvs0_clk_src"); + /* power down process */ + rc = __disable_regulator_iris3(core, "iris-ctl"); if (rc) { - d_vpr_e("%s: disable unprepare video_cc_mvs0_clk_src failed\n", __func__); + d_vpr_e("%s: disable regulator iris-ctl failed\n", __func__); rc = 0; } @@ -664,14 +663,8 @@ static int __power_on_iris3_controller(struct msm_vidc_core *core) if (rc) goto fail_clk_controller; - rc = __prepare_enable_clock_iris3(core, "video_cc_mvs0_clk_src"); - if (rc) - goto fail_clk_src; - return 0; -fail_clk_src: - __disable_unprepare_clock_iris3(core, "core_clk"); fail_clk_controller: __disable_unprepare_clock_iris3(core, "gcc_video_axi0"); fail_clk_axi: