samsung-sm8650/android_kernel_samsung_sm8650-modules
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qcacmn: Cleanup target reg table

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Remove unused fields in target reg table.

Change-Id: Ic183f7a27ffd5d4542dfe1c3eccb11825539c70f
Acked-by: Venkateswara Swamy Bandaru <vbandaru@codeaurora.org>
CRs-Fixed: 1042915
This commit is contained in:
Venkateswara Swamy Bandaru
2016-09-20 20:23:50 +05:30
parent 127461b4e7
commit c5de4d9fd7
2 changed files with 1 additions and 110 deletions
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50
hif/inc/reg_struct.h
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@@ -100,8 +100,6 @@ struct targetdef_s {
uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK;
uint32_t d_ANALOG_INTF_BASE_ADDRESS;
uint32_t d_WLAN_MAC_BASE_ADDRESS;
uint32_t d_CE0_BASE_ADDRESS;
uint32_t d_CE1_BASE_ADDRESS;
uint32_t d_FW_INDICATOR_ADDRESS;
uint32_t d_FW_CPU_PLL_CONFIG;
uint32_t d_DRAM_BASE_ADDRESS;
@@ -128,55 +126,8 @@ struct targetdef_s {
uint32_t d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB;
uint32_t d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB;
/* copy_engine.c */
uint32_t d_DST_WR_INDEX_ADDRESS;
uint32_t d_SRC_WATERMARK_ADDRESS;
uint32_t d_SRC_WATERMARK_LOW_MASK;
uint32_t d_SRC_WATERMARK_HIGH_MASK;
uint32_t d_DST_WATERMARK_LOW_MASK;
uint32_t d_DST_WATERMARK_HIGH_MASK;
uint32_t d_CURRENT_SRRI_ADDRESS;
uint32_t d_CURRENT_DRRI_ADDRESS;
uint32_t d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK;
uint32_t d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK;
uint32_t d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK;
uint32_t d_HOST_IS_DST_RING_LOW_WATERMARK_MASK;
uint32_t d_HOST_IS_ADDRESS;
uint32_t d_HOST_IS_COPY_COMPLETE_MASK;
uint32_t d_CE_CMD_ADDRESS;
uint32_t d_CE_CMD_HALT_MASK;
uint32_t d_CE_WRAPPER_BASE_ADDRESS;
uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS;
uint32_t d_HOST_IE_ADDRESS;
uint32_t d_HOST_IE_COPY_COMPLETE_MASK;
uint32_t d_SR_BA_ADDRESS;
uint32_t d_SR_SIZE_ADDRESS;
uint32_t d_CE_CTRL1_ADDRESS;
uint32_t d_CE_CTRL1_DMAX_LENGTH_MASK;
uint32_t d_DR_BA_ADDRESS;
uint32_t d_DR_SIZE_ADDRESS;
uint32_t d_MISC_IE_ADDRESS;
uint32_t d_MISC_IS_AXI_ERR_MASK;
uint32_t d_MISC_IS_DST_ADDR_ERR_MASK;
uint32_t d_MISC_IS_SRC_LEN_ERR_MASK;
uint32_t d_MISC_IS_DST_MAX_LEN_VIO_MASK;
uint32_t d_MISC_IS_DST_RING_OVERFLOW_MASK;
uint32_t d_MISC_IS_SRC_RING_OVERFLOW_MASK;
uint32_t d_SRC_WATERMARK_LOW_LSB;
uint32_t d_SRC_WATERMARK_HIGH_LSB;
uint32_t d_DST_WATERMARK_LOW_LSB;
uint32_t d_DST_WATERMARK_HIGH_LSB;
uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK;
uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB;
uint32_t d_CE_CTRL1_DMAX_LENGTH_LSB;
uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK;
uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK;
uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB;
uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB;
uint32_t d_CE_CMD_HALT_STATUS_MASK;
uint32_t d_CE_CMD_HALT_STATUS_LSB;
uint32_t d_SR_WR_INDEX_ADDRESS;
uint32_t d_DST_WATERMARK_ADDRESS;
/* htt_rx.c */
uint32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK;
uint32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB;
@@ -298,7 +249,6 @@ struct targetdef_s {
uint32_t d_FW_AXI_MSI_ADDR;
uint32_t d_FW_AXI_MSI_DATA;
uint32_t d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS;
uint32_t d_FPGA_VERSION_ADDRESS;
/* chip id end */