diff --git a/hif/inc/reg_struct.h b/hif/inc/reg_struct.h index 7e05857c9b..d1f8c799ef 100644 --- a/hif/inc/reg_struct.h +++ b/hif/inc/reg_struct.h @@ -100,8 +100,6 @@ struct targetdef_s { uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK; uint32_t d_ANALOG_INTF_BASE_ADDRESS; uint32_t d_WLAN_MAC_BASE_ADDRESS; - uint32_t d_CE0_BASE_ADDRESS; - uint32_t d_CE1_BASE_ADDRESS; uint32_t d_FW_INDICATOR_ADDRESS; uint32_t d_FW_CPU_PLL_CONFIG; uint32_t d_DRAM_BASE_ADDRESS; @@ -128,55 +126,8 @@ struct targetdef_s { uint32_t d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB; uint32_t d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB; /* copy_engine.c */ - uint32_t d_DST_WR_INDEX_ADDRESS; - uint32_t d_SRC_WATERMARK_ADDRESS; - uint32_t d_SRC_WATERMARK_LOW_MASK; - uint32_t d_SRC_WATERMARK_HIGH_MASK; - uint32_t d_DST_WATERMARK_LOW_MASK; - uint32_t d_DST_WATERMARK_HIGH_MASK; - uint32_t d_CURRENT_SRRI_ADDRESS; - uint32_t d_CURRENT_DRRI_ADDRESS; - uint32_t d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK; - uint32_t d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK; - uint32_t d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK; - uint32_t d_HOST_IS_DST_RING_LOW_WATERMARK_MASK; - uint32_t d_HOST_IS_ADDRESS; - uint32_t d_HOST_IS_COPY_COMPLETE_MASK; - uint32_t d_CE_CMD_ADDRESS; - uint32_t d_CE_CMD_HALT_MASK; - uint32_t d_CE_WRAPPER_BASE_ADDRESS; - uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS; - uint32_t d_HOST_IE_ADDRESS; - uint32_t d_HOST_IE_COPY_COMPLETE_MASK; - uint32_t d_SR_BA_ADDRESS; - uint32_t d_SR_SIZE_ADDRESS; - uint32_t d_CE_CTRL1_ADDRESS; - uint32_t d_CE_CTRL1_DMAX_LENGTH_MASK; - uint32_t d_DR_BA_ADDRESS; - uint32_t d_DR_SIZE_ADDRESS; - uint32_t d_MISC_IE_ADDRESS; - uint32_t d_MISC_IS_AXI_ERR_MASK; - uint32_t d_MISC_IS_DST_ADDR_ERR_MASK; - uint32_t d_MISC_IS_SRC_LEN_ERR_MASK; - uint32_t d_MISC_IS_DST_MAX_LEN_VIO_MASK; - uint32_t d_MISC_IS_DST_RING_OVERFLOW_MASK; - uint32_t d_MISC_IS_SRC_RING_OVERFLOW_MASK; - uint32_t d_SRC_WATERMARK_LOW_LSB; - uint32_t d_SRC_WATERMARK_HIGH_LSB; - uint32_t d_DST_WATERMARK_LOW_LSB; - uint32_t d_DST_WATERMARK_HIGH_LSB; - uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK; - uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB; - uint32_t d_CE_CTRL1_DMAX_LENGTH_LSB; - uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK; - uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK; - uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB; - uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB; - uint32_t d_CE_CMD_HALT_STATUS_MASK; - uint32_t d_CE_CMD_HALT_STATUS_LSB; uint32_t d_SR_WR_INDEX_ADDRESS; uint32_t d_DST_WATERMARK_ADDRESS; - /* htt_rx.c */ uint32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK; uint32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB; @@ -298,7 +249,6 @@ struct targetdef_s { uint32_t d_FW_AXI_MSI_ADDR; uint32_t d_FW_AXI_MSI_DATA; uint32_t d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS; - uint32_t d_FPGA_VERSION_ADDRESS; /* chip id end */ diff --git a/hif/inc/target_reg_init.h b/hif/inc/target_reg_init.h index a776678d90..4948785d83 100644 --- a/hif/inc/target_reg_init.h +++ b/hif/inc/target_reg_init.h @@ -244,8 +244,6 @@ static struct targetdef_s my_target_def = { .d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK = CLOCK_GPIO_BT_CLK_OUT_EN_MASK, .d_ANALOG_INTF_BASE_ADDRESS = ANALOG_INTF_BASE_ADDRESS, .d_WLAN_MAC_BASE_ADDRESS = WLAN_MAC_BASE_ADDRESS, - .d_CE0_BASE_ADDRESS = CE0_BASE_ADDRESS, - .d_CE1_BASE_ADDRESS = CE1_BASE_ADDRESS, .d_FW_INDICATOR_ADDRESS = FW_INDICATOR_ADDRESS, .d_FW_CPU_PLL_CONFIG = FW_CPU_PLL_CONFIG, .d_DRAM_BASE_ADDRESS = DRAM_BASE_ADDRESS, @@ -280,65 +278,9 @@ static struct targetdef_s my_target_def = { .d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB = MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB, /* copy_engine.c */ - .d_DST_WR_INDEX_ADDRESS = DST_WR_INDEX_ADDRESS, - .d_SRC_WATERMARK_ADDRESS = SRC_WATERMARK_ADDRESS, - .d_SRC_WATERMARK_LOW_MASK = SRC_WATERMARK_LOW_MASK, - .d_SRC_WATERMARK_HIGH_MASK = SRC_WATERMARK_HIGH_MASK, - .d_DST_WATERMARK_LOW_MASK = DST_WATERMARK_LOW_MASK, - .d_DST_WATERMARK_HIGH_MASK = DST_WATERMARK_HIGH_MASK, - .d_CURRENT_SRRI_ADDRESS = CURRENT_SRRI_ADDRESS, - .d_CURRENT_DRRI_ADDRESS = CURRENT_DRRI_ADDRESS, - .d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK - = HOST_IS_SRC_RING_HIGH_WATERMARK_MASK, - .d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK - = HOST_IS_SRC_RING_LOW_WATERMARK_MASK, - .d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK - = HOST_IS_DST_RING_HIGH_WATERMARK_MASK, - .d_HOST_IS_DST_RING_LOW_WATERMARK_MASK - = HOST_IS_DST_RING_LOW_WATERMARK_MASK, - .d_HOST_IS_ADDRESS = HOST_IS_ADDRESS, - .d_HOST_IS_COPY_COMPLETE_MASK = HOST_IS_COPY_COMPLETE_MASK, - .d_CE_CMD_ADDRESS = CE_CMD_ADDRESS, - .d_CE_CMD_HALT_MASK = CE_CMD_HALT_MASK, - .d_CE_WRAPPER_BASE_ADDRESS = CE_WRAPPER_BASE_ADDRESS, - .d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS - = CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS, - .d_HOST_IE_ADDRESS = HOST_IE_ADDRESS, - .d_HOST_IE_COPY_COMPLETE_MASK = HOST_IE_COPY_COMPLETE_MASK, - .d_SR_BA_ADDRESS = SR_BA_ADDRESS, - .d_SR_SIZE_ADDRESS = SR_SIZE_ADDRESS, - .d_CE_CTRL1_ADDRESS = CE_CTRL1_ADDRESS, - .d_CE_CTRL1_DMAX_LENGTH_MASK = CE_CTRL1_DMAX_LENGTH_MASK, - .d_DR_BA_ADDRESS = DR_BA_ADDRESS, - .d_DR_SIZE_ADDRESS = DR_SIZE_ADDRESS, - .d_MISC_IE_ADDRESS = MISC_IE_ADDRESS, - .d_MISC_IS_AXI_ERR_MASK = MISC_IS_AXI_ERR_MASK, - .d_MISC_IS_DST_ADDR_ERR_MASK = MISC_IS_DST_ADDR_ERR_MASK, - .d_MISC_IS_SRC_LEN_ERR_MASK = MISC_IS_SRC_LEN_ERR_MASK, - .d_MISC_IS_DST_MAX_LEN_VIO_MASK = MISC_IS_DST_MAX_LEN_VIO_MASK, - .d_MISC_IS_DST_RING_OVERFLOW_MASK = MISC_IS_DST_RING_OVERFLOW_MASK, - .d_MISC_IS_SRC_RING_OVERFLOW_MASK = MISC_IS_SRC_RING_OVERFLOW_MASK, - .d_SRC_WATERMARK_LOW_LSB = SRC_WATERMARK_LOW_LSB, - .d_SRC_WATERMARK_HIGH_LSB = SRC_WATERMARK_HIGH_LSB, - .d_DST_WATERMARK_LOW_LSB = DST_WATERMARK_LOW_LSB, - .d_DST_WATERMARK_HIGH_LSB = DST_WATERMARK_HIGH_LSB, - .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK - = CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK, - .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB - = CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB, - .d_CE_CTRL1_DMAX_LENGTH_LSB = CE_CTRL1_DMAX_LENGTH_LSB, - .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK - = CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK, - .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK - = CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK, - .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB - = CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB, - .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB - = CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB, - .d_CE_CMD_HALT_STATUS_MASK = CE_CMD_HALT_STATUS_MASK, - .d_CE_CMD_HALT_STATUS_LSB = CE_CMD_HALT_STATUS_LSB, .d_SR_WR_INDEX_ADDRESS = SR_WR_INDEX_ADDRESS, .d_DST_WATERMARK_ADDRESS = DST_WATERMARK_ADDRESS, + .d_PCIE_INTR_CAUSE_ADDRESS = PCIE_INTR_CAUSE_ADDRESS, .d_SOC_RESET_CONTROL_ADDRESS = SOC_RESET_CONTROL_ADDRESS, .d_SOC_RESET_CONTROL_CE_RST_MASK = SOC_RESET_CONTROL_CE_RST_MASK, @@ -362,7 +304,6 @@ static struct targetdef_s my_target_def = { .d_FW_AXI_MSI_ADDR = FW_AXI_MSI_ADDR, .d_FW_AXI_MSI_DATA = FW_AXI_MSI_DATA, .d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS = WLAN_SUBSYSTEM_CORE_ID_ADDRESS, - .d_FPGA_VERSION_ADDRESS = FPGA_VERSION_ADDRESS, .d_WIFICMN_INT_STATUS_ADDRESS = WIFICMN_INT_STATUS_ADDRESS, };