icnss2: pass fw capability to wlan host driver

Pass he_channel_width_cap, phy_qam_cap and rd_card_chain_cap
to wlan host driver as part of soc info.

Change-Id: I471de0df5452c960662955aad20cf1b1f6c8845e
CRs-Fixed: 3533554

icnss2/debug.c

@@ -315,6 +315,12 @@ static int icnss_stats_show_capability(struct seq_file *s,
 			   priv->fw_version_info.fw_build_timestamp);
 		seq_printf(s, "Firmware Build ID: %s\n",
 			   priv->fw_build_id);
+		seq_printf(s, "RD card chain cap: %d\n",
+			   priv->rd_card_chain_cap);
+		seq_printf(s, "PHY HE channel width cap: %d\n",
+			   priv->phy_he_channel_width_cap);
+		seq_printf(s, "PHY QAM cap: %d\n",
+			   priv->phy_qam_cap);
 	}
 
 	return 0;

icnss2/main.c

@@ -3356,6 +3356,9 @@ int icnss_get_soc_info(struct device *dev, struct icnss_soc_info *info)
 		WLFW_MAX_TIMESTAMP_LEN + 1);
 	strlcpy(info->fw_build_id, priv->fw_build_id,
 	        ICNSS_WLFW_MAX_BUILD_ID_LEN + 1);
+	info->rd_card_chain_cap = priv->rd_card_chain_cap;
+	info->phy_he_channel_width_cap = priv->phy_he_channel_width_cap;
+	info->phy_qam_cap = priv->phy_qam_cap;
 
 	return 0;
 }

icnss2/main.h

@@ -513,6 +513,9 @@ struct icnss_priv {
 	struct timer_list recovery_timer;
 	struct timer_list wpss_ssr_timer;
 	bool wpss_self_recovery_enabled;
+	enum icnss_rd_card_chain_cap rd_card_chain_cap;
+	enum icnss_phy_he_channel_width_cap phy_he_channel_width_cap;
+	enum icnss_phy_qam_cap phy_qam_cap;
 };
 
 struct icnss_reg_info {

icnss2/qmi.c

@@ -784,15 +784,24 @@ int wlfw_cap_send_sync_msg(struct icnss_priv *priv)
 		strlcpy(priv->fw_build_id, resp->fw_build_id,
 			QMI_WLFW_MAX_BUILD_ID_LEN_V01 + 1);
 
-	if (resp->rd_card_chain_cap_valid &&
-	    resp->rd_card_chain_cap == WLFW_RD_CARD_CHAIN_CAP_1x1_V01)
-		priv->is_chain1_supported = false;
+	if (resp->rd_card_chain_cap_valid) {
+		priv->rd_card_chain_cap = (enum icnss_rd_card_chain_cap)resp->rd_card_chain_cap;
+		if (resp->rd_card_chain_cap == WLFW_RD_CARD_CHAIN_CAP_1x1_V01)
+			priv->is_chain1_supported = false;
+	}
 
 	if (resp->foundry_name_valid)
 		priv->foundry_name = resp->foundry_name[0];
 	else if (resp->chip_info_valid && priv->chip_info.chip_id == UMC_CHIP_ID)
 		priv->foundry_name = 'u';
 
+	if (resp->he_channel_width_cap_valid)
+		priv->phy_he_channel_width_cap =
+			(enum icnss_phy_he_channel_width_cap)resp->he_channel_width_cap;
+
+	if (resp->phy_qam_cap_valid)
+		priv->phy_qam_cap = (enum icnss_phy_qam_cap)resp->phy_qam_cap;
+
 	icnss_pr_dbg("Capability, chip_id: 0x%x, chip_family: 0x%x, board_id: 0x%x, soc_id: 0x%x",
 		     priv->chip_info.chip_id, priv->chip_info.chip_family,
 		     priv->board_id, priv->soc_id);
@@ -802,6 +811,10 @@ int wlfw_cap_send_sync_msg(struct icnss_priv *priv)
 		     priv->fw_version_info.fw_build_timestamp,
 		     priv->fw_build_id);
 
+	icnss_pr_dbg("RD card chain cap: %d, PHY HE channel width cap: %d, PHY QAM cap: %d",
+		     priv->rd_card_chain_cap, priv->phy_he_channel_width_cap,
+		     priv->phy_qam_cap);
+
 	kfree(resp);
 	kfree(req);
 	return 0;

inc/icnss2.h

@@ -131,6 +131,27 @@ enum icnss_driver_mode {
 	ICNSS_CALIBRATION,
 };
 
+enum icnss_rd_card_chain_cap {
+	ICNSS_RD_CARD_CHAIN_CAP_UNSPECIFIED,
+	ICNSS_RD_CARD_CHAIN_CAP_1x1,
+	ICNSS_RD_CARD_CHAIN_CAP_2x2,
+	ICNSS_RD_CARD_CHAIN_CAP_MAX_VAL,
+};
+
+enum icnss_phy_he_channel_width_cap {
+	ICNSS_PHY_HE_CHANNEL_WIDTH_CAP_UNSPECIFIED,
+	ICNSS_PHY_HE_CHANNEL_WIDTH_CAP_80MHZ,
+	ICNSS_PHY_HE_CHANNEL_WIDTH_CAP_160MHZ,
+	ICNSS_PHY_HE_CHANNEL_WIDTH_CAP_MAX_VAL,
+};
+
+enum icnss_phy_qam_cap {
+	ICNSS_PHY_QAM_CAP_UNSPECIFIED,
+	ICNSS_PHY_QAM_CAP_1K,
+	ICNSS_PHY_QAM_CAP_4K,
+	ICNSS_PHY_QAM_CAP_MAX_VAL,
+};
+
 struct icnss_soc_info {
 	void __iomem *v_addr;
 	phys_addr_t p_addr;
@@ -141,6 +162,9 @@ struct icnss_soc_info {
 	uint32_t fw_version;
 	char fw_build_timestamp[ICNSS_MAX_TIMESTAMP_LEN + 1];
 	char fw_build_id[ICNSS_WLFW_MAX_BUILD_ID_LEN + 1];
+	enum icnss_rd_card_chain_cap rd_card_chain_cap;
+	enum icnss_phy_he_channel_width_cap phy_he_channel_width_cap;
+	enum icnss_phy_qam_cap phy_qam_cap;
 };
 
 #define icnss_register_driver(ops)		\