qcacmn: Add support for Regtable convergence
Add regtable definitions for chipsets AR6004,AR6320,AR900B,
AR9888,IPQ4019,QCA9888,QCA9984
Change-Id: Ic018a1396aa36f61ead6d8607feda4711e2a2b07
Acked-by: Venkateswara Swamy Bandaru <vbandaru@codeaurora.org>
CRs-Fixed: 1009050
Dieser Commit ist enthalten in:
Houston Hoffman
committet von
Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
Ursprung
9348186afb
Commit
c3c6bc1e5c
@@ -30,254 +30,6 @@
|
||||
|
||||
#define MISSING 0
|
||||
|
||||
struct targetdef_s {
|
||||
uint32_t d_RTC_SOC_BASE_ADDRESS;
|
||||
uint32_t d_RTC_WMAC_BASE_ADDRESS;
|
||||
uint32_t d_SYSTEM_SLEEP_OFFSET;
|
||||
uint32_t d_WLAN_SYSTEM_SLEEP_OFFSET;
|
||||
uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_LSB;
|
||||
uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_MASK;
|
||||
uint32_t d_CLOCK_CONTROL_OFFSET;
|
||||
uint32_t d_CLOCK_CONTROL_SI0_CLK_MASK;
|
||||
uint32_t d_RESET_CONTROL_OFFSET;
|
||||
uint32_t d_RESET_CONTROL_MBOX_RST_MASK;
|
||||
uint32_t d_RESET_CONTROL_SI0_RST_MASK;
|
||||
uint32_t d_WLAN_RESET_CONTROL_OFFSET;
|
||||
uint32_t d_WLAN_RESET_CONTROL_COLD_RST_MASK;
|
||||
uint32_t d_WLAN_RESET_CONTROL_WARM_RST_MASK;
|
||||
uint32_t d_GPIO_BASE_ADDRESS;
|
||||
uint32_t d_GPIO_PIN0_OFFSET;
|
||||
uint32_t d_GPIO_PIN1_OFFSET;
|
||||
uint32_t d_GPIO_PIN0_CONFIG_MASK;
|
||||
uint32_t d_GPIO_PIN1_CONFIG_MASK;
|
||||
uint32_t d_SI_CONFIG_BIDIR_OD_DATA_LSB;
|
||||
uint32_t d_SI_CONFIG_BIDIR_OD_DATA_MASK;
|
||||
uint32_t d_SI_CONFIG_I2C_LSB;
|
||||
uint32_t d_SI_CONFIG_I2C_MASK;
|
||||
uint32_t d_SI_CONFIG_POS_SAMPLE_LSB;
|
||||
uint32_t d_SI_CONFIG_POS_SAMPLE_MASK;
|
||||
uint32_t d_SI_CONFIG_INACTIVE_CLK_LSB;
|
||||
uint32_t d_SI_CONFIG_INACTIVE_CLK_MASK;
|
||||
uint32_t d_SI_CONFIG_INACTIVE_DATA_LSB;
|
||||
uint32_t d_SI_CONFIG_INACTIVE_DATA_MASK;
|
||||
uint32_t d_SI_CONFIG_DIVIDER_LSB;
|
||||
uint32_t d_SI_CONFIG_DIVIDER_MASK;
|
||||
uint32_t d_SI_BASE_ADDRESS;
|
||||
uint32_t d_SI_CONFIG_OFFSET;
|
||||
uint32_t d_SI_TX_DATA0_OFFSET;
|
||||
uint32_t d_SI_TX_DATA1_OFFSET;
|
||||
uint32_t d_SI_RX_DATA0_OFFSET;
|
||||
uint32_t d_SI_RX_DATA1_OFFSET;
|
||||
uint32_t d_SI_CS_OFFSET;
|
||||
uint32_t d_SI_CS_DONE_ERR_MASK;
|
||||
uint32_t d_SI_CS_DONE_INT_MASK;
|
||||
uint32_t d_SI_CS_START_LSB;
|
||||
uint32_t d_SI_CS_START_MASK;
|
||||
uint32_t d_SI_CS_RX_CNT_LSB;
|
||||
uint32_t d_SI_CS_RX_CNT_MASK;
|
||||
uint32_t d_SI_CS_TX_CNT_LSB;
|
||||
uint32_t d_SI_CS_TX_CNT_MASK;
|
||||
uint32_t d_BOARD_DATA_SZ;
|
||||
uint32_t d_BOARD_EXT_DATA_SZ;
|
||||
uint32_t d_MBOX_BASE_ADDRESS;
|
||||
uint32_t d_LOCAL_SCRATCH_OFFSET;
|
||||
uint32_t d_CPU_CLOCK_OFFSET;
|
||||
uint32_t d_LPO_CAL_OFFSET;
|
||||
uint32_t d_GPIO_PIN10_OFFSET;
|
||||
uint32_t d_GPIO_PIN11_OFFSET;
|
||||
uint32_t d_GPIO_PIN12_OFFSET;
|
||||
uint32_t d_GPIO_PIN13_OFFSET;
|
||||
uint32_t d_CLOCK_GPIO_OFFSET;
|
||||
uint32_t d_CPU_CLOCK_STANDARD_LSB;
|
||||
uint32_t d_CPU_CLOCK_STANDARD_MASK;
|
||||
uint32_t d_LPO_CAL_ENABLE_LSB;
|
||||
uint32_t d_LPO_CAL_ENABLE_MASK;
|
||||
uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB;
|
||||
uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK;
|
||||
uint32_t d_ANALOG_INTF_BASE_ADDRESS;
|
||||
uint32_t d_WLAN_MAC_BASE_ADDRESS;
|
||||
uint32_t d_FW_INDICATOR_ADDRESS;
|
||||
uint32_t d_DRAM_BASE_ADDRESS;
|
||||
uint32_t d_SOC_CORE_BASE_ADDRESS;
|
||||
uint32_t d_CORE_CTRL_ADDRESS;
|
||||
uint32_t d_CE_COUNT;
|
||||
uint32_t d_MSI_NUM_REQUEST;
|
||||
uint32_t d_MSI_ASSIGN_FW;
|
||||
uint32_t d_MSI_ASSIGN_CE_INITIAL;
|
||||
uint32_t d_PCIE_INTR_ENABLE_ADDRESS;
|
||||
uint32_t d_PCIE_INTR_CLR_ADDRESS;
|
||||
uint32_t d_PCIE_INTR_FIRMWARE_MASK;
|
||||
uint32_t d_PCIE_INTR_CE_MASK_ALL;
|
||||
uint32_t d_CORE_CTRL_CPU_INTR_MASK;
|
||||
uint32_t d_SR_WR_INDEX_ADDRESS;
|
||||
uint32_t d_DST_WATERMARK_ADDRESS;
|
||||
|
||||
/* htt_rx.c */
|
||||
uint32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK;
|
||||
uint32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB;
|
||||
uint32_t d_RX_MPDU_START_0_RETRY_LSB;
|
||||
uint32_t d_RX_MPDU_START_0_RETRY_MASK;
|
||||
uint32_t d_RX_MPDU_START_0_SEQ_NUM_MASK;
|
||||
uint32_t d_RX_MPDU_START_0_SEQ_NUM_LSB;
|
||||
uint32_t d_RX_MPDU_START_2_PN_47_32_LSB;
|
||||
uint32_t d_RX_MPDU_START_2_PN_47_32_MASK;
|
||||
uint32_t d_RX_MPDU_START_2_TID_LSB;
|
||||
uint32_t d_RX_MPDU_START_2_TID_MASK;
|
||||
uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK;
|
||||
uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB;
|
||||
uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_MASK;
|
||||
uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_LSB;
|
||||
uint32_t d_RX_MSDU_END_4_LAST_MSDU_MASK;
|
||||
uint32_t d_RX_MSDU_END_4_LAST_MSDU_LSB;
|
||||
uint32_t d_RX_ATTENTION_0_MCAST_BCAST_MASK;
|
||||
uint32_t d_RX_ATTENTION_0_MCAST_BCAST_LSB;
|
||||
uint32_t d_RX_ATTENTION_0_FRAGMENT_MASK;
|
||||
uint32_t d_RX_ATTENTION_0_FRAGMENT_LSB;
|
||||
uint32_t d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK;
|
||||
uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK;
|
||||
uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB;
|
||||
uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_MASK;
|
||||
uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_LSB;
|
||||
uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET;
|
||||
uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_MASK;
|
||||
uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_LSB;
|
||||
uint32_t d_RX_MPDU_START_0_ENCRYPTED_MASK;
|
||||
uint32_t d_RX_MPDU_START_0_ENCRYPTED_LSB;
|
||||
uint32_t d_RX_ATTENTION_0_MORE_DATA_MASK;
|
||||
uint32_t d_RX_ATTENTION_0_MSDU_DONE_MASK;
|
||||
uint32_t d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK;
|
||||
/* end */
|
||||
|
||||
/* PLL start */
|
||||
uint32_t d_EFUSE_OFFSET;
|
||||
uint32_t d_EFUSE_XTAL_SEL_MSB;
|
||||
uint32_t d_EFUSE_XTAL_SEL_LSB;
|
||||
uint32_t d_EFUSE_XTAL_SEL_MASK;
|
||||
uint32_t d_BB_PLL_CONFIG_OFFSET;
|
||||
uint32_t d_BB_PLL_CONFIG_OUTDIV_MSB;
|
||||
uint32_t d_BB_PLL_CONFIG_OUTDIV_LSB;
|
||||
uint32_t d_BB_PLL_CONFIG_OUTDIV_MASK;
|
||||
uint32_t d_BB_PLL_CONFIG_FRAC_MSB;
|
||||
uint32_t d_BB_PLL_CONFIG_FRAC_LSB;
|
||||
uint32_t d_BB_PLL_CONFIG_FRAC_MASK;
|
||||
uint32_t d_WLAN_PLL_SETTLE_TIME_MSB;
|
||||
uint32_t d_WLAN_PLL_SETTLE_TIME_LSB;
|
||||
uint32_t d_WLAN_PLL_SETTLE_TIME_MASK;
|
||||
uint32_t d_WLAN_PLL_SETTLE_OFFSET;
|
||||
uint32_t d_WLAN_PLL_SETTLE_SW_MASK;
|
||||
uint32_t d_WLAN_PLL_SETTLE_RSTMASK;
|
||||
uint32_t d_WLAN_PLL_SETTLE_RESET;
|
||||
uint32_t d_WLAN_PLL_CONTROL_NOPWD_MSB;
|
||||
uint32_t d_WLAN_PLL_CONTROL_NOPWD_LSB;
|
||||
uint32_t d_WLAN_PLL_CONTROL_NOPWD_MASK;
|
||||
uint32_t d_WLAN_PLL_CONTROL_BYPASS_MSB;
|
||||
uint32_t d_WLAN_PLL_CONTROL_BYPASS_LSB;
|
||||
uint32_t d_WLAN_PLL_CONTROL_BYPASS_MASK;
|
||||
uint32_t d_WLAN_PLL_CONTROL_BYPASS_RESET;
|
||||
uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MSB;
|
||||
uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_LSB;
|
||||
uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MASK;
|
||||
uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_RESET;
|
||||
uint32_t d_WLAN_PLL_CONTROL_REFDIV_MSB;
|
||||
uint32_t d_WLAN_PLL_CONTROL_REFDIV_LSB;
|
||||
uint32_t d_WLAN_PLL_CONTROL_REFDIV_MASK;
|
||||
uint32_t d_WLAN_PLL_CONTROL_REFDIV_RESET;
|
||||
uint32_t d_WLAN_PLL_CONTROL_DIV_MSB;
|
||||
uint32_t d_WLAN_PLL_CONTROL_DIV_LSB;
|
||||
uint32_t d_WLAN_PLL_CONTROL_DIV_MASK;
|
||||
uint32_t d_WLAN_PLL_CONTROL_DIV_RESET;
|
||||
uint32_t d_WLAN_PLL_CONTROL_OFFSET;
|
||||
uint32_t d_WLAN_PLL_CONTROL_SW_MASK;
|
||||
uint32_t d_WLAN_PLL_CONTROL_RSTMASK;
|
||||
uint32_t d_WLAN_PLL_CONTROL_RESET;
|
||||
uint32_t d_SOC_CORE_CLK_CTRL_OFFSET;
|
||||
uint32_t d_SOC_CORE_CLK_CTRL_DIV_MSB;
|
||||
uint32_t d_SOC_CORE_CLK_CTRL_DIV_LSB;
|
||||
uint32_t d_SOC_CORE_CLK_CTRL_DIV_MASK;
|
||||
uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MSB;
|
||||
uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_LSB;
|
||||
uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MASK;
|
||||
uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_RESET;
|
||||
uint32_t d_RTC_SYNC_STATUS_OFFSET;
|
||||
uint32_t d_SOC_CPU_CLOCK_OFFSET;
|
||||
uint32_t d_SOC_CPU_CLOCK_STANDARD_MSB;
|
||||
uint32_t d_SOC_CPU_CLOCK_STANDARD_LSB;
|
||||
uint32_t d_SOC_CPU_CLOCK_STANDARD_MASK;
|
||||
/* PLL end */
|
||||
|
||||
uint32_t d_SOC_POWER_REG_OFFSET;
|
||||
uint32_t d_PCIE_INTR_CAUSE_ADDRESS;
|
||||
uint32_t d_SOC_RESET_CONTROL_ADDRESS;
|
||||
uint32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK;
|
||||
uint32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB;
|
||||
uint32_t d_SOC_RESET_CONTROL_CE_RST_MASK;
|
||||
uint32_t d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK;
|
||||
uint32_t d_CPU_INTR_ADDRESS;
|
||||
uint32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS;
|
||||
uint32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK;
|
||||
|
||||
/* chip id start */
|
||||
uint32_t d_SOC_CHIP_ID_ADDRESS;
|
||||
uint32_t d_SOC_CHIP_ID_VERSION_MASK;
|
||||
uint32_t d_SOC_CHIP_ID_VERSION_LSB;
|
||||
uint32_t d_SOC_CHIP_ID_REVISION_MASK;
|
||||
uint32_t d_SOC_CHIP_ID_REVISION_LSB;
|
||||
/* chip id end */
|
||||
|
||||
uint32_t d_A_SOC_CORE_SCRATCH_0_ADDRESS;
|
||||
uint32_t d_A_SOC_CORE_SCRATCH_1_ADDRESS;
|
||||
uint32_t d_A_SOC_CORE_SCRATCH_2_ADDRESS;
|
||||
uint32_t d_A_SOC_CORE_SCRATCH_3_ADDRESS;
|
||||
uint32_t d_A_SOC_CORE_SCRATCH_4_ADDRESS;
|
||||
uint32_t d_A_SOC_CORE_SCRATCH_5_ADDRESS;
|
||||
uint32_t d_A_SOC_CORE_SCRATCH_6_ADDRESS;
|
||||
uint32_t d_A_SOC_CORE_SCRATCH_7_ADDRESS;
|
||||
uint32_t d_A_SOC_CORE_SPARE_0_REGISTER;
|
||||
uint32_t d_PCIE_INTR_FIRMWARE_ROUTE_MASK;
|
||||
uint32_t d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1;
|
||||
uint32_t d_A_SOC_CORE_SPARE_1_REGISTER;
|
||||
uint32_t d_A_SOC_CORE_PCIE_INTR_CLR_GRP1;
|
||||
uint32_t d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1;
|
||||
uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_0;
|
||||
uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_1;
|
||||
uint32_t d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA;
|
||||
uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_2;
|
||||
uint32_t d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK;
|
||||
|
||||
uint32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET;
|
||||
uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB;
|
||||
uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB;
|
||||
uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK;
|
||||
uint32_t d_WLAN_DEBUG_CONTROL_OFFSET;
|
||||
uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB;
|
||||
uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB;
|
||||
uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK;
|
||||
uint32_t d_WLAN_DEBUG_OUT_OFFSET;
|
||||
uint32_t d_WLAN_DEBUG_OUT_DATA_MSB;
|
||||
uint32_t d_WLAN_DEBUG_OUT_DATA_LSB;
|
||||
uint32_t d_WLAN_DEBUG_OUT_DATA_MASK;
|
||||
uint32_t d_AMBA_DEBUG_BUS_OFFSET;
|
||||
uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB;
|
||||
uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB;
|
||||
uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK;
|
||||
uint32_t d_AMBA_DEBUG_BUS_SEL_MSB;
|
||||
uint32_t d_AMBA_DEBUG_BUS_SEL_LSB;
|
||||
uint32_t d_AMBA_DEBUG_BUS_SEL_MASK;
|
||||
|
||||
#ifdef QCA_WIFI_3_0_ADRASTEA
|
||||
uint32_t d_Q6_ENABLE_REGISTER_0;
|
||||
uint32_t d_Q6_ENABLE_REGISTER_1;
|
||||
uint32_t d_Q6_CAUSE_REGISTER_0;
|
||||
uint32_t d_Q6_CAUSE_REGISTER_1;
|
||||
uint32_t d_Q6_CLEAR_REGISTER_0;
|
||||
uint32_t d_Q6_CLEAR_REGISTER_1;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BYPASS_QMI
|
||||
uint32_t d_BYPASS_QMI_TEMP_REGISTER;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK \
|
||||
(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK)
|
||||
#define A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 \
|
||||
@@ -457,6 +209,7 @@ struct targetdef_s {
|
||||
#define SOC_POWER_REG_OFFSET (scn->targetdef->d_SOC_POWER_REG_OFFSET)
|
||||
/* end */
|
||||
|
||||
#ifndef CONFIG_WIN
|
||||
/* htt_rx.c */
|
||||
#define RX_MSDU_END_4_FIRST_MSDU_MASK \
|
||||
(pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_MASK)
|
||||
@@ -525,6 +278,7 @@ struct targetdef_s {
|
||||
#define RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK \
|
||||
(pdev->targetdef->d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK)
|
||||
/* end */
|
||||
#endif
|
||||
|
||||
/* copy_engine.c */
|
||||
/* end */
|
||||
@@ -609,6 +363,64 @@ struct targetdef_s {
|
||||
(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK)
|
||||
/* PLL end */
|
||||
|
||||
#define FW_CPU_PLL_CONFIG \
|
||||
(sc->targetdef->d_FW_CPU_PLL_CONFIG)
|
||||
|
||||
#define WIFICMN_PCIE_BAR_REG_ADDRESS \
|
||||
(sc->targetdef->d_WIFICMN_PCIE_BAR_REG_ADDRESS)
|
||||
|
||||
/* htt tx */
|
||||
#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK \
|
||||
(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK)
|
||||
#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK \
|
||||
(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK)
|
||||
#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK \
|
||||
(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK)
|
||||
#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK \
|
||||
(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK)
|
||||
#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB \
|
||||
(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB)
|
||||
#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB \
|
||||
(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB)
|
||||
#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB \
|
||||
(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB)
|
||||
#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB \
|
||||
(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB)
|
||||
|
||||
#define CE_CMD_ADDRESS \
|
||||
(scn->targetdef->d_CE_CMD_ADDRESS)
|
||||
#define CE_CMD_HALT_MASK \
|
||||
(scn->targetdef->d_CE_CMD_HALT_MASK)
|
||||
#define CE_CMD_HALT_STATUS_MASK \
|
||||
(scn->targetdef->d_CE_CMD_HALT_STATUS_MASK)
|
||||
#define CE_CMD_HALT_STATUS_LSB \
|
||||
(scn->targetdef->d_CE_CMD_HALT_STATUS_LSB)
|
||||
|
||||
#define SI_CONFIG_ERR_INT_MASK \
|
||||
(scn->targetdef->d_SI_CONFIG_ERR_INT_MASK)
|
||||
#define SI_CONFIG_ERR_INT_LSB \
|
||||
(scn->targetdef->d_SI_CONFIG_ERR_INT_LSB)
|
||||
#define GPIO_ENABLE_W1TS_LOW_ADDRESS \
|
||||
(scn->targetdef->d_GPIO_ENABLE_W1TS_LOW_ADDRESS)
|
||||
#define GPIO_PIN0_CONFIG_LSB \
|
||||
(scn->targetdef->d_GPIO_PIN0_CONFIG_LSB)
|
||||
#define GPIO_PIN0_PAD_PULL_LSB \
|
||||
(scn->targetdef->d_GPIO_PIN0_PAD_PULL_LSB)
|
||||
#define GPIO_PIN0_PAD_PULL_MASK \
|
||||
(scn->targetdef->d_GPIO_PIN0_PAD_PULL_MASK)
|
||||
|
||||
#define SOC_CHIP_ID_REVISION_MSB \
|
||||
(scn->targetdef->d_SOC_CHIP_ID_REVISION_MSB)
|
||||
|
||||
#define FW_AXI_MSI_ADDR \
|
||||
(scn->targetdef->d_FW_AXI_MSI_ADDR)
|
||||
#define FW_AXI_MSI_DATA \
|
||||
(scn->targetdef->d_FW_AXI_MSI_DATA)
|
||||
#define WLAN_SUBSYSTEM_CORE_ID_ADDRESS \
|
||||
(scn->targetdef->d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS)
|
||||
#define FPGA_VERSION_ADDRESS \
|
||||
(scn->targetdef->d_FPGA_VERSION_ADDRESS)
|
||||
|
||||
/* SET macros */
|
||||
#define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \
|
||||
(((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \
|
||||
@@ -687,6 +499,13 @@ struct targetdef_s {
|
||||
#define SOC_CPU_CLOCK_STANDARD_SET(x) \
|
||||
(((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK)
|
||||
/* PLL end */
|
||||
#define WLAN_GPIO_PIN0_CONFIG_SET(x) \
|
||||
(((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK)
|
||||
#define WLAN_GPIO_PIN0_PAD_PULL_SET(x) \
|
||||
(((x) << GPIO_PIN0_PAD_PULL_LSB) & GPIO_PIN0_PAD_PULL_MASK)
|
||||
#define SI_CONFIG_ERR_INT_SET(x) \
|
||||
(((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
|
||||
|
||||
|
||||
#ifdef QCA_WIFI_3_0_ADRASTEA
|
||||
#define Q6_ENABLE_REGISTER_0 \
|
||||
@@ -708,73 +527,6 @@ struct targetdef_s {
|
||||
(scn->targetdef->d_BYPASS_QMI_TEMP_REGISTER)
|
||||
#endif
|
||||
|
||||
struct hostdef_s {
|
||||
uint32_t d_INT_STATUS_ENABLE_ERROR_LSB;
|
||||
uint32_t d_INT_STATUS_ENABLE_ERROR_MASK;
|
||||
uint32_t d_INT_STATUS_ENABLE_CPU_LSB;
|
||||
uint32_t d_INT_STATUS_ENABLE_CPU_MASK;
|
||||
uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB;
|
||||
uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK;
|
||||
uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB;
|
||||
uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK;
|
||||
uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB;
|
||||
uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK;
|
||||
uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB;
|
||||
uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK;
|
||||
uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB;
|
||||
uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK;
|
||||
uint32_t d_INT_STATUS_ENABLE_ADDRESS;
|
||||
uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB;
|
||||
uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK;
|
||||
uint32_t d_HOST_INT_STATUS_ADDRESS;
|
||||
uint32_t d_CPU_INT_STATUS_ADDRESS;
|
||||
uint32_t d_ERROR_INT_STATUS_ADDRESS;
|
||||
uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK;
|
||||
uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB;
|
||||
uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK;
|
||||
uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB;
|
||||
uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK;
|
||||
uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB;
|
||||
uint32_t d_COUNT_DEC_ADDRESS;
|
||||
uint32_t d_HOST_INT_STATUS_CPU_MASK;
|
||||
uint32_t d_HOST_INT_STATUS_CPU_LSB;
|
||||
uint32_t d_HOST_INT_STATUS_ERROR_MASK;
|
||||
uint32_t d_HOST_INT_STATUS_ERROR_LSB;
|
||||
uint32_t d_HOST_INT_STATUS_COUNTER_MASK;
|
||||
uint32_t d_HOST_INT_STATUS_COUNTER_LSB;
|
||||
uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS;
|
||||
uint32_t d_WINDOW_DATA_ADDRESS;
|
||||
uint32_t d_WINDOW_READ_ADDR_ADDRESS;
|
||||
uint32_t d_WINDOW_WRITE_ADDR_ADDRESS;
|
||||
uint32_t d_SOC_GLOBAL_RESET_ADDRESS;
|
||||
uint32_t d_RTC_STATE_ADDRESS;
|
||||
uint32_t d_RTC_STATE_COLD_RESET_MASK;
|
||||
uint32_t d_PCIE_LOCAL_BASE_ADDRESS;
|
||||
uint32_t d_PCIE_SOC_WAKE_RESET;
|
||||
uint32_t d_PCIE_SOC_WAKE_ADDRESS;
|
||||
uint32_t d_PCIE_SOC_WAKE_V_MASK;
|
||||
uint32_t d_RTC_STATE_V_MASK;
|
||||
uint32_t d_RTC_STATE_V_LSB;
|
||||
uint32_t d_FW_IND_EVENT_PENDING;
|
||||
uint32_t d_FW_IND_INITIALIZED;
|
||||
uint32_t d_FW_IND_HELPER;
|
||||
uint32_t d_RTC_STATE_V_ON;
|
||||
#if defined(SDIO_3_0)
|
||||
uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK;
|
||||
uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB;
|
||||
#endif
|
||||
uint32_t d_PCIE_SOC_RDY_STATUS_ADDRESS;
|
||||
uint32_t d_PCIE_SOC_RDY_STATUS_BAR_MASK;
|
||||
uint32_t d_SOC_PCIE_BASE_ADDRESS;
|
||||
uint32_t d_MSI_MAGIC_ADR_ADDRESS;
|
||||
uint32_t d_MSI_MAGIC_ADDRESS;
|
||||
uint32_t d_HOST_CE_COUNT;
|
||||
uint32_t d_ENABLE_MSI;
|
||||
uint32_t d_MUX_ID_MASK;
|
||||
uint32_t d_TRANSACTION_ID_MASK;
|
||||
uint32_t d_DESC_DATA_FLAG_MASK;
|
||||
uint32_t d_A_SOC_PCIE_PCIE_BAR0_START;
|
||||
};
|
||||
#define A_SOC_PCIE_PCIE_BAR0_START (scn->hostdef->d_A_SOC_PCIE_PCIE_BAR0_START)
|
||||
#define DESC_DATA_FLAG_MASK (scn->hostdef->d_DESC_DATA_FLAG_MASK)
|
||||
#define MUX_ID_MASK (scn->hostdef->d_MUX_ID_MASK)
|
||||
@@ -854,6 +606,9 @@ struct hostdef_s {
|
||||
#define FW_IND_INITIALIZED (scn->hostdef->d_FW_IND_INITIALIZED)
|
||||
#define FW_IND_HELPER (scn->hostdef->d_FW_IND_HELPER)
|
||||
#define RTC_STATE_V_ON (scn->hostdef->d_RTC_STATE_V_ON)
|
||||
|
||||
#define FW_IND_HOST_READY (scn->hostdef->d_FW_IND_HOST_READY)
|
||||
|
||||
#if defined(SDIO_3_0)
|
||||
#define HOST_INT_STATUS_MBOX_DATA_MASK \
|
||||
(scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK)
|
||||
@@ -985,55 +740,4 @@ struct hif_softc;
|
||||
void target_register_tbl_attach(struct hif_softc *scn, u32 target_type);
|
||||
void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type);
|
||||
|
||||
struct host_shadow_regs_s {
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_0;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_1;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_2;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_3;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_4;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_5;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_6;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_7;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_8;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_9;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_10;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_11;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_12;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_13;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_14;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_15;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_16;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_17;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_18;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_19;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_20;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_21;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_22;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_VALUE_23;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_0;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_1;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_2;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_3;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_4;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_5;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_6;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_7;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_8;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_9;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_10;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_11;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_12;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_13;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_14;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_15;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_16;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_17;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_18;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_19;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_20;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_21;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_22;
|
||||
uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_23;
|
||||
};
|
||||
|
||||
#endif /* _REGTABLE_PCIE_H_ */
|
||||
|
||||
In neuem Issue referenzieren
Einen Benutzer sperren