diff --git a/hif/inc/hif.h b/hif/inc/hif.h index 331a977e13..7277c86c82 100644 --- a/hif/inc/hif.h +++ b/hif/inc/hif.h @@ -54,7 +54,7 @@ typedef void *hif_handle_t; #define HIF_TYPE_AR6320 7 #define HIF_TYPE_AR6320V2 8 /* For attaching Peregrine 2.0 board host_reg_tbl only */ -#define HIF_TYPE_AR9888V2 8 +#define HIF_TYPE_AR9888V2 9 #define HIF_TYPE_ADRASTEA 10 #define HIF_TYPE_AR900B 11 #define HIF_TYPE_QCA9984 12 @@ -73,17 +73,17 @@ typedef void *hif_handle_t; #define TARGET_TYPE_AR6320 8 #define TARGET_TYPE_AR900B 9 /* For attach Peregrine 2.0 board target_reg_tbl only */ -#define TARGET_TYPE_AR9888V2 10 +#define TARGET_TYPE_AR9888V2 13 /* For attach Rome1.0 target_reg_tbl only*/ -#define TARGET_TYPE_AR6320V1 11 +#define TARGET_TYPE_AR6320V1 14 /* For Rome2.0/2.1 target_reg_tbl ID*/ -#define TARGET_TYPE_AR6320V2 12 +#define TARGET_TYPE_AR6320V2 15 /* For Rome3.0 target_reg_tbl ID*/ -#define TARGET_TYPE_AR6320V3 13 +#define TARGET_TYPE_AR6320V3 16 /* For Tufello1.0 target_reg_tbl ID*/ -#define TARGET_TYPE_QCA9377V1 14 +#define TARGET_TYPE_QCA9377V1 17 /* For Adrastea target */ -#define TARGET_TYPE_ADRASTEA 16 +#define TARGET_TYPE_ADRASTEA 19 struct CE_state; #define CE_COUNT_MAX 12 diff --git a/hif/inc/host_reg_init.h b/hif/inc/host_reg_init.h new file mode 100644 index 0000000000..f154192c9f --- /dev/null +++ b/hif/inc/host_reg_init.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HOST_REG_INIT_H +#define HOST_REG_INIT_H + +#include "reg_struct.h" +#include "targaddrs.h" + +#if defined(MY_HOST_DEF) + +#if !defined(FW_IND_HOST_READY) +#define FW_IND_HOST_READY 0 +#endif + +#if !defined(PCIE_LOCAL_BASE_ADDRESS) +#define PCIE_LOCAL_BASE_ADDRESS 0 +#define PCIE_SOC_WAKE_RESET 0 +#define PCIE_SOC_WAKE_ADDRESS 0 +#define PCIE_SOC_WAKE_V_MASK 0 +#define RTC_STATE_ADDRESS 0 +#define RTC_STATE_COLD_RESET_MASK 0 +#define RTC_STATE_V_MASK 0 +#define RTC_STATE_V_LSB 0 +#define RTC_STATE_V_ON 0 +#define SOC_GLOBAL_RESET_ADDRESS 0 +#endif + +#if !defined(CE_COUNT) +#define CE_COUNT 0 +#endif + +#if !defined(TRANSACTION_ID_MASK) +#define TRANSACTION_ID_MASK 0xfff +#endif + +static struct hostdef_s my_host_def = { + .d_INT_STATUS_ENABLE_ERROR_LSB = INT_STATUS_ENABLE_ERROR_LSB, + .d_INT_STATUS_ENABLE_ERROR_MASK = INT_STATUS_ENABLE_ERROR_MASK, + .d_INT_STATUS_ENABLE_CPU_LSB = INT_STATUS_ENABLE_CPU_LSB, + .d_INT_STATUS_ENABLE_CPU_MASK = INT_STATUS_ENABLE_CPU_MASK, + .d_INT_STATUS_ENABLE_COUNTER_LSB = INT_STATUS_ENABLE_COUNTER_LSB, + .d_INT_STATUS_ENABLE_COUNTER_MASK = INT_STATUS_ENABLE_COUNTER_MASK, + .d_INT_STATUS_ENABLE_MBOX_DATA_LSB = INT_STATUS_ENABLE_MBOX_DATA_LSB, + .d_INT_STATUS_ENABLE_MBOX_DATA_MASK = INT_STATUS_ENABLE_MBOX_DATA_MASK, + .d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB + = ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB, + .d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK + = ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK, + .d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB + = ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB, + .d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK + = ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK, + .d_COUNTER_INT_STATUS_ENABLE_BIT_LSB + = COUNTER_INT_STATUS_ENABLE_BIT_LSB, + .d_COUNTER_INT_STATUS_ENABLE_BIT_MASK + = COUNTER_INT_STATUS_ENABLE_BIT_MASK, + .d_INT_STATUS_ENABLE_ADDRESS = INT_STATUS_ENABLE_ADDRESS, + .d_CPU_INT_STATUS_ENABLE_BIT_LSB = CPU_INT_STATUS_ENABLE_BIT_LSB, + .d_CPU_INT_STATUS_ENABLE_BIT_MASK = CPU_INT_STATUS_ENABLE_BIT_MASK, + .d_HOST_INT_STATUS_ADDRESS = HOST_INT_STATUS_ADDRESS, + .d_CPU_INT_STATUS_ADDRESS = CPU_INT_STATUS_ADDRESS, + .d_ERROR_INT_STATUS_ADDRESS = ERROR_INT_STATUS_ADDRESS, + .d_ERROR_INT_STATUS_WAKEUP_MASK = ERROR_INT_STATUS_WAKEUP_MASK, + .d_ERROR_INT_STATUS_WAKEUP_LSB = ERROR_INT_STATUS_WAKEUP_LSB, + .d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK + = ERROR_INT_STATUS_RX_UNDERFLOW_MASK, + .d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB + = ERROR_INT_STATUS_RX_UNDERFLOW_LSB, + .d_ERROR_INT_STATUS_TX_OVERFLOW_MASK + = ERROR_INT_STATUS_TX_OVERFLOW_MASK, + .d_ERROR_INT_STATUS_TX_OVERFLOW_LSB = ERROR_INT_STATUS_TX_OVERFLOW_LSB, + .d_COUNT_DEC_ADDRESS = COUNT_DEC_ADDRESS, + .d_HOST_INT_STATUS_CPU_MASK = HOST_INT_STATUS_CPU_MASK, + .d_HOST_INT_STATUS_CPU_LSB = HOST_INT_STATUS_CPU_LSB, + .d_HOST_INT_STATUS_ERROR_MASK = HOST_INT_STATUS_ERROR_MASK, + .d_HOST_INT_STATUS_ERROR_LSB = HOST_INT_STATUS_ERROR_LSB, + .d_HOST_INT_STATUS_COUNTER_MASK = HOST_INT_STATUS_COUNTER_MASK, + .d_HOST_INT_STATUS_COUNTER_LSB = HOST_INT_STATUS_COUNTER_LSB, + .d_RX_LOOKAHEAD_VALID_ADDRESS = RX_LOOKAHEAD_VALID_ADDRESS, + .d_WINDOW_DATA_ADDRESS = WINDOW_DATA_ADDRESS, + .d_WINDOW_READ_ADDR_ADDRESS = WINDOW_READ_ADDR_ADDRESS, + .d_WINDOW_WRITE_ADDR_ADDRESS = WINDOW_WRITE_ADDR_ADDRESS, + .d_SOC_GLOBAL_RESET_ADDRESS = SOC_GLOBAL_RESET_ADDRESS, + .d_RTC_STATE_ADDRESS = RTC_STATE_ADDRESS, + .d_RTC_STATE_COLD_RESET_MASK = RTC_STATE_COLD_RESET_MASK, + .d_PCIE_LOCAL_BASE_ADDRESS = PCIE_LOCAL_BASE_ADDRESS, + .d_PCIE_SOC_WAKE_RESET = PCIE_SOC_WAKE_RESET, + .d_PCIE_SOC_WAKE_ADDRESS = PCIE_SOC_WAKE_ADDRESS, + .d_PCIE_SOC_WAKE_V_MASK = PCIE_SOC_WAKE_V_MASK, + .d_RTC_STATE_V_MASK = RTC_STATE_V_MASK, + .d_RTC_STATE_V_LSB = RTC_STATE_V_LSB, + .d_FW_IND_EVENT_PENDING = FW_IND_EVENT_PENDING, + .d_FW_IND_INITIALIZED = FW_IND_INITIALIZED, + .d_RTC_STATE_V_ON = RTC_STATE_V_ON, +#if defined(SDIO_3_0) + .d_HOST_INT_STATUS_MBOX_DATA_MASK = HOST_INT_STATUS_MBOX_DATA_MASK, + .d_HOST_INT_STATUS_MBOX_DATA_LSB = HOST_INT_STATUS_MBOX_DATA_LSB, +#endif + .d_FW_IND_HOST_READY = FW_IND_HOST_READY, + .d_HOST_CE_COUNT = CE_COUNT, + .d_TRANSACTION_ID_MASK = TRANSACTION_ID_MASK, +}; + +struct hostdef_s *MY_HOST_DEF = &my_host_def; +#else /* MY_HOST_DEF */ +#endif /* MY_HOST_DEF */ + + + +#if defined(MY_HOST_SHADOW_REGS) +struct host_shadow_regs_s my_host_shadow_regs = { + .d_A_LOCAL_SHADOW_REG_VALUE_0 = A_LOCAL_SHADOW_REG_VALUE_0; + .d_A_LOCAL_SHADOW_REG_VALUE_1 = A_LOCAL_SHADOW_REG_VALUE_1; + .d_A_LOCAL_SHADOW_REG_VALUE_2 = A_LOCAL_SHADOW_REG_VALUE_2; + .d_A_LOCAL_SHADOW_REG_VALUE_3 = A_LOCAL_SHADOW_REG_VALUE_3; + .d_A_LOCAL_SHADOW_REG_VALUE_4 = A_LOCAL_SHADOW_REG_VALUE_4; + .d_A_LOCAL_SHADOW_REG_VALUE_5 = A_LOCAL_SHADOW_REG_VALUE_5; + .d_A_LOCAL_SHADOW_REG_VALUE_6 = A_LOCAL_SHADOW_REG_VALUE_6; + .d_A_LOCAL_SHADOW_REG_VALUE_7 = A_LOCAL_SHADOW_REG_VALUE_7; + .d_A_LOCAL_SHADOW_REG_VALUE_8 = A_LOCAL_SHADOW_REG_VALUE_8; + .d_A_LOCAL_SHADOW_REG_VALUE_9 = A_LOCAL_SHADOW_REG_VALUE_9; + .d_A_LOCAL_SHADOW_REG_VALUE_10 = A_LOCAL_SHADOW_REG_VALUE_10; + .d_A_LOCAL_SHADOW_REG_VALUE_11 = A_LOCAL_SHADOW_REG_VALUE_11; + .d_A_LOCAL_SHADOW_REG_VALUE_12 = A_LOCAL_SHADOW_REG_VALUE_12; + .d_A_LOCAL_SHADOW_REG_VALUE_13 = A_LOCAL_SHADOW_REG_VALUE_13; + .d_A_LOCAL_SHADOW_REG_VALUE_14 = A_LOCAL_SHADOW_REG_VALUE_14; + .d_A_LOCAL_SHADOW_REG_VALUE_15 = A_LOCAL_SHADOW_REG_VALUE_15; + .d_A_LOCAL_SHADOW_REG_VALUE_16 = A_LOCAL_SHADOW_REG_VALUE_16; + .d_A_LOCAL_SHADOW_REG_VALUE_17 = A_LOCAL_SHADOW_REG_VALUE_17; + .d_A_LOCAL_SHADOW_REG_VALUE_18 = A_LOCAL_SHADOW_REG_VALUE_18; + .d_A_LOCAL_SHADOW_REG_VALUE_19 = A_LOCAL_SHADOW_REG_VALUE_19; + .d_A_LOCAL_SHADOW_REG_VALUE_20 = A_LOCAL_SHADOW_REG_VALUE_20; + .d_A_LOCAL_SHADOW_REG_VALUE_21 = A_LOCAL_SHADOW_REG_VALUE_21; + .d_A_LOCAL_SHADOW_REG_VALUE_22 = A_LOCAL_SHADOW_REG_VALUE_22; + .d_A_LOCAL_SHADOW_REG_VALUE_23 = A_LOCAL_SHADOW_REG_VALUE_23; + .d_A_LOCAL_SHADOW_REG_ADDRESS_0 = A_LOCAL_SHADOW_REG_ADDRESS_0; + .d_A_LOCAL_SHADOW_REG_ADDRESS_1 = A_LOCAL_SHADOW_REG_ADDRESS_1; + .d_A_LOCAL_SHADOW_REG_ADDRESS_2 = A_LOCAL_SHADOW_REG_ADDRESS_2; + .d_A_LOCAL_SHADOW_REG_ADDRESS_3 = A_LOCAL_SHADOW_REG_ADDRESS_3; + .d_A_LOCAL_SHADOW_REG_ADDRESS_4 = A_LOCAL_SHADOW_REG_ADDRESS_4; + .d_A_LOCAL_SHADOW_REG_ADDRESS_5 = A_LOCAL_SHADOW_REG_ADDRESS_5; + .d_A_LOCAL_SHADOW_REG_ADDRESS_6 = A_LOCAL_SHADOW_REG_ADDRESS_6; + .d_A_LOCAL_SHADOW_REG_ADDRESS_7 = A_LOCAL_SHADOW_REG_ADDRESS_7; + .d_A_LOCAL_SHADOW_REG_ADDRESS_8 = A_LOCAL_SHADOW_REG_ADDRESS_8; + .d_A_LOCAL_SHADOW_REG_ADDRESS_9 = A_LOCAL_SHADOW_REG_ADDRESS_9; + .d_A_LOCAL_SHADOW_REG_ADDRESS_10 = A_LOCAL_SHADOW_REG_ADDRESS_10; + .d_A_LOCAL_SHADOW_REG_ADDRESS_11 = A_LOCAL_SHADOW_REG_ADDRESS_11; + .d_A_LOCAL_SHADOW_REG_ADDRESS_12 = A_LOCAL_SHADOW_REG_ADDRESS_12; + .d_A_LOCAL_SHADOW_REG_ADDRESS_13 = A_LOCAL_SHADOW_REG_ADDRESS_13; + .d_A_LOCAL_SHADOW_REG_ADDRESS_14 = A_LOCAL_SHADOW_REG_ADDRESS_14; + .d_A_LOCAL_SHADOW_REG_ADDRESS_15 = A_LOCAL_SHADOW_REG_ADDRESS_15; + .d_A_LOCAL_SHADOW_REG_ADDRESS_16 = A_LOCAL_SHADOW_REG_ADDRESS_16; + .d_A_LOCAL_SHADOW_REG_ADDRESS_17 = A_LOCAL_SHADOW_REG_ADDRESS_17; + .d_A_LOCAL_SHADOW_REG_ADDRESS_18 = A_LOCAL_SHADOW_REG_ADDRESS_18; + .d_A_LOCAL_SHADOW_REG_ADDRESS_19 = A_LOCAL_SHADOW_REG_ADDRESS_19; + .d_A_LOCAL_SHADOW_REG_ADDRESS_20 = A_LOCAL_SHADOW_REG_ADDRESS_20; + .d_A_LOCAL_SHADOW_REG_ADDRESS_21 = A_LOCAL_SHADOW_REG_ADDRESS_21; + .d_A_LOCAL_SHADOW_REG_ADDRESS_22 = A_LOCAL_SHADOW_REG_ADDRESS_22; + .d_A_LOCAL_SHADOW_REG_ADDRESS_23 = A_LOCAL_SHADOW_REG_ADDRESS_23; +}; + +struct hostdef_s *MY_HOST_SHADOW_REGS = &my_host_shadow_regs; +#else /* MY_HOST_SHADOW_REGS */ +#endif /* MY_HOST_SHADOW_REGS */ +#endif /* HOST_REG_INIT_H */ diff --git a/hif/inc/hostdef.h b/hif/inc/hostdef.h new file mode 100644 index 0000000000..b291bbfb14 --- /dev/null +++ b/hif/inc/hostdef.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HOSTDEFS_H_ +#define HOSTDEFS_H_ + +#include +#include +#include +#include "host_reg_init.h" + +extern struct hostdef_s *AR6002_HOSTdef; +extern struct hostdef_s *AR6003_HOSTdef; +extern struct hostdef_s *AR6004_HOSTdef; +extern struct hostdef_s *AR9888_HOSTdef; +extern struct hostdef_s *AR9888V2_HOSTdef; +extern struct hostdef_s *AR6320_HOSTdef; +extern struct hostdef_s *AR900B_HOSTdef; +extern struct hostdef_s *QCA9984_HOSTdef; +extern struct hostdef_s *QCA9888_HOSTdef; +#ifdef ATH_AHB +extern struct hostdef_s *IPQ4019_HOSTdef; +#endif + +#endif diff --git a/hif/inc/reg_struct.h b/hif/inc/reg_struct.h new file mode 100644 index 0000000000..8098f468c8 --- /dev/null +++ b/hif/inc/reg_struct.h @@ -0,0 +1,694 @@ +/* + * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef REG_STRUCT_H +#define REG_STRUCT_H + +struct targetdef_s { + uint32_t d_RTC_SOC_BASE_ADDRESS; + uint32_t d_RTC_WMAC_BASE_ADDRESS; + uint32_t d_SYSTEM_SLEEP_OFFSET; + uint32_t d_WLAN_SYSTEM_SLEEP_OFFSET; + uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_LSB; + uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_MASK; + uint32_t d_CLOCK_CONTROL_OFFSET; + uint32_t d_CLOCK_CONTROL_SI0_CLK_MASK; + uint32_t d_RESET_CONTROL_OFFSET; + uint32_t d_RESET_CONTROL_MBOX_RST_MASK; + uint32_t d_RESET_CONTROL_SI0_RST_MASK; + uint32_t d_WLAN_RESET_CONTROL_OFFSET; + uint32_t d_WLAN_RESET_CONTROL_COLD_RST_MASK; + uint32_t d_WLAN_RESET_CONTROL_WARM_RST_MASK; + uint32_t d_GPIO_BASE_ADDRESS; + uint32_t d_GPIO_PIN0_OFFSET; + uint32_t d_GPIO_PIN1_OFFSET; + uint32_t d_GPIO_PIN0_CONFIG_MASK; + uint32_t d_GPIO_PIN1_CONFIG_MASK; + uint32_t d_SI_CONFIG_BIDIR_OD_DATA_LSB; + uint32_t d_SI_CONFIG_BIDIR_OD_DATA_MASK; + uint32_t d_SI_CONFIG_I2C_LSB; + uint32_t d_SI_CONFIG_I2C_MASK; + uint32_t d_SI_CONFIG_POS_SAMPLE_LSB; + uint32_t d_SI_CONFIG_POS_SAMPLE_MASK; + uint32_t d_SI_CONFIG_INACTIVE_CLK_LSB; + uint32_t d_SI_CONFIG_INACTIVE_CLK_MASK; + uint32_t d_SI_CONFIG_INACTIVE_DATA_LSB; + uint32_t d_SI_CONFIG_INACTIVE_DATA_MASK; + uint32_t d_SI_CONFIG_DIVIDER_LSB; + uint32_t d_SI_CONFIG_DIVIDER_MASK; + uint32_t d_SI_BASE_ADDRESS; + uint32_t d_SI_CONFIG_OFFSET; + uint32_t d_SI_TX_DATA0_OFFSET; + uint32_t d_SI_TX_DATA1_OFFSET; + uint32_t d_SI_RX_DATA0_OFFSET; + uint32_t d_SI_RX_DATA1_OFFSET; + uint32_t d_SI_CS_OFFSET; + uint32_t d_SI_CS_DONE_ERR_MASK; + uint32_t d_SI_CS_DONE_INT_MASK; + uint32_t d_SI_CS_START_LSB; + uint32_t d_SI_CS_START_MASK; + uint32_t d_SI_CS_RX_CNT_LSB; + uint32_t d_SI_CS_RX_CNT_MASK; + uint32_t d_SI_CS_TX_CNT_LSB; + uint32_t d_SI_CS_TX_CNT_MASK; + uint32_t d_BOARD_DATA_SZ; + uint32_t d_BOARD_EXT_DATA_SZ; + uint32_t d_MBOX_BASE_ADDRESS; + uint32_t d_LOCAL_SCRATCH_OFFSET; + uint32_t d_CPU_CLOCK_OFFSET; + uint32_t d_LPO_CAL_OFFSET; + uint32_t d_GPIO_PIN10_OFFSET; + uint32_t d_GPIO_PIN11_OFFSET; + uint32_t d_GPIO_PIN12_OFFSET; + uint32_t d_GPIO_PIN13_OFFSET; + uint32_t d_CLOCK_GPIO_OFFSET; + uint32_t d_CPU_CLOCK_STANDARD_LSB; + uint32_t d_CPU_CLOCK_STANDARD_MASK; + uint32_t d_LPO_CAL_ENABLE_LSB; + uint32_t d_LPO_CAL_ENABLE_MASK; + uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB; + uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK; + uint32_t d_ANALOG_INTF_BASE_ADDRESS; + uint32_t d_WLAN_MAC_BASE_ADDRESS; + uint32_t d_CE0_BASE_ADDRESS; + uint32_t d_CE1_BASE_ADDRESS; + uint32_t d_FW_INDICATOR_ADDRESS; + uint32_t d_FW_CPU_PLL_CONFIG; + uint32_t d_DRAM_BASE_ADDRESS; + uint32_t d_SOC_CORE_BASE_ADDRESS; + uint32_t d_CORE_CTRL_ADDRESS; + uint32_t d_CE_COUNT; + uint32_t d_MSI_NUM_REQUEST; + uint32_t d_MSI_ASSIGN_FW; + uint32_t d_MSI_ASSIGN_CE_INITIAL; + uint32_t d_PCIE_INTR_ENABLE_ADDRESS; + uint32_t d_PCIE_INTR_CLR_ADDRESS; + uint32_t d_PCIE_INTR_FIRMWARE_MASK; + uint32_t d_PCIE_INTR_CE_MASK_ALL; + uint32_t d_CORE_CTRL_CPU_INTR_MASK; + uint32_t d_WIFICMN_PCIE_BAR_REG_ADDRESS; + /* htt_rx.c */ + /* htt tx */ + uint32_t d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK; + uint32_t d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK; + uint32_t d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK; + uint32_t d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK; + uint32_t d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB; + uint32_t d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB; + uint32_t d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB; + uint32_t d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB; + /* copy_engine.c */ + uint32_t d_DST_WR_INDEX_ADDRESS; + uint32_t d_SRC_WATERMARK_ADDRESS; + uint32_t d_SRC_WATERMARK_LOW_MASK; + uint32_t d_SRC_WATERMARK_HIGH_MASK; + uint32_t d_DST_WATERMARK_LOW_MASK; + uint32_t d_DST_WATERMARK_HIGH_MASK; + uint32_t d_CURRENT_SRRI_ADDRESS; + uint32_t d_CURRENT_DRRI_ADDRESS; + uint32_t d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK; + uint32_t d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK; + uint32_t d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK; + uint32_t d_HOST_IS_DST_RING_LOW_WATERMARK_MASK; + uint32_t d_HOST_IS_ADDRESS; + uint32_t d_HOST_IS_COPY_COMPLETE_MASK; + uint32_t d_CE_CMD_ADDRESS; + uint32_t d_CE_CMD_HALT_MASK; + uint32_t d_CE_WRAPPER_BASE_ADDRESS; + uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS; + uint32_t d_HOST_IE_ADDRESS; + uint32_t d_HOST_IE_COPY_COMPLETE_MASK; + uint32_t d_SR_BA_ADDRESS; + uint32_t d_SR_SIZE_ADDRESS; + uint32_t d_CE_CTRL1_ADDRESS; + uint32_t d_CE_CTRL1_DMAX_LENGTH_MASK; + uint32_t d_DR_BA_ADDRESS; + uint32_t d_DR_SIZE_ADDRESS; + uint32_t d_MISC_IE_ADDRESS; + uint32_t d_MISC_IS_AXI_ERR_MASK; + uint32_t d_MISC_IS_DST_ADDR_ERR_MASK; + uint32_t d_MISC_IS_SRC_LEN_ERR_MASK; + uint32_t d_MISC_IS_DST_MAX_LEN_VIO_MASK; + uint32_t d_MISC_IS_DST_RING_OVERFLOW_MASK; + uint32_t d_MISC_IS_SRC_RING_OVERFLOW_MASK; + uint32_t d_SRC_WATERMARK_LOW_LSB; + uint32_t d_SRC_WATERMARK_HIGH_LSB; + uint32_t d_DST_WATERMARK_LOW_LSB; + uint32_t d_DST_WATERMARK_HIGH_LSB; + uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK; + uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB; + uint32_t d_CE_CTRL1_DMAX_LENGTH_LSB; + uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK; + uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK; + uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB; + uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB; + uint32_t d_CE_CMD_HALT_STATUS_MASK; + uint32_t d_CE_CMD_HALT_STATUS_LSB; + uint32_t d_SR_WR_INDEX_ADDRESS; + uint32_t d_DST_WATERMARK_ADDRESS; + + /* htt_rx.c */ + uint32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK; + uint32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB; + uint32_t d_RX_MPDU_START_0_RETRY_LSB; + uint32_t d_RX_MPDU_START_0_RETRY_MASK; + uint32_t d_RX_MPDU_START_0_SEQ_NUM_MASK; + uint32_t d_RX_MPDU_START_0_SEQ_NUM_LSB; + uint32_t d_RX_MPDU_START_2_PN_47_32_LSB; + uint32_t d_RX_MPDU_START_2_PN_47_32_MASK; + uint32_t d_RX_MPDU_START_2_TID_LSB; + uint32_t d_RX_MPDU_START_2_TID_MASK; + uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK; + uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB; + uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_MASK; + uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_LSB; + uint32_t d_RX_MSDU_END_4_LAST_MSDU_MASK; + uint32_t d_RX_MSDU_END_4_LAST_MSDU_LSB; + uint32_t d_RX_ATTENTION_0_MCAST_BCAST_MASK; + uint32_t d_RX_ATTENTION_0_MCAST_BCAST_LSB; + uint32_t d_RX_ATTENTION_0_FRAGMENT_MASK; + uint32_t d_RX_ATTENTION_0_FRAGMENT_LSB; + uint32_t d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK; + uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK; + uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB; + uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_MASK; + uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_LSB; + uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET; + uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_MASK; + uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_LSB; + uint32_t d_RX_MPDU_START_0_ENCRYPTED_MASK; + uint32_t d_RX_MPDU_START_0_ENCRYPTED_LSB; + uint32_t d_RX_ATTENTION_0_MORE_DATA_MASK; + uint32_t d_RX_ATTENTION_0_MSDU_DONE_MASK; + uint32_t d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK; + /* end */ + + /* PLL start */ + uint32_t d_EFUSE_OFFSET; + uint32_t d_EFUSE_XTAL_SEL_MSB; + uint32_t d_EFUSE_XTAL_SEL_LSB; + uint32_t d_EFUSE_XTAL_SEL_MASK; + uint32_t d_BB_PLL_CONFIG_OFFSET; + uint32_t d_BB_PLL_CONFIG_OUTDIV_MSB; + uint32_t d_BB_PLL_CONFIG_OUTDIV_LSB; + uint32_t d_BB_PLL_CONFIG_OUTDIV_MASK; + uint32_t d_BB_PLL_CONFIG_FRAC_MSB; + uint32_t d_BB_PLL_CONFIG_FRAC_LSB; + uint32_t d_BB_PLL_CONFIG_FRAC_MASK; + uint32_t d_WLAN_PLL_SETTLE_TIME_MSB; + uint32_t d_WLAN_PLL_SETTLE_TIME_LSB; + uint32_t d_WLAN_PLL_SETTLE_TIME_MASK; + uint32_t d_WLAN_PLL_SETTLE_OFFSET; + uint32_t d_WLAN_PLL_SETTLE_SW_MASK; + uint32_t d_WLAN_PLL_SETTLE_RSTMASK; + uint32_t d_WLAN_PLL_SETTLE_RESET; + uint32_t d_WLAN_PLL_CONTROL_NOPWD_MSB; + uint32_t d_WLAN_PLL_CONTROL_NOPWD_LSB; + uint32_t d_WLAN_PLL_CONTROL_NOPWD_MASK; + uint32_t d_WLAN_PLL_CONTROL_BYPASS_MSB; + uint32_t d_WLAN_PLL_CONTROL_BYPASS_LSB; + uint32_t d_WLAN_PLL_CONTROL_BYPASS_MASK; + uint32_t d_WLAN_PLL_CONTROL_BYPASS_RESET; + uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MSB; + uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_LSB; + uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MASK; + uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_RESET; + uint32_t d_WLAN_PLL_CONTROL_REFDIV_MSB; + uint32_t d_WLAN_PLL_CONTROL_REFDIV_LSB; + uint32_t d_WLAN_PLL_CONTROL_REFDIV_MASK; + uint32_t d_WLAN_PLL_CONTROL_REFDIV_RESET; + uint32_t d_WLAN_PLL_CONTROL_DIV_MSB; + uint32_t d_WLAN_PLL_CONTROL_DIV_LSB; + uint32_t d_WLAN_PLL_CONTROL_DIV_MASK; + uint32_t d_WLAN_PLL_CONTROL_DIV_RESET; + uint32_t d_WLAN_PLL_CONTROL_OFFSET; + uint32_t d_WLAN_PLL_CONTROL_SW_MASK; + uint32_t d_WLAN_PLL_CONTROL_RSTMASK; + uint32_t d_WLAN_PLL_CONTROL_RESET; + uint32_t d_SOC_CORE_CLK_CTRL_OFFSET; + uint32_t d_SOC_CORE_CLK_CTRL_DIV_MSB; + uint32_t d_SOC_CORE_CLK_CTRL_DIV_LSB; + uint32_t d_SOC_CORE_CLK_CTRL_DIV_MASK; + uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MSB; + uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_LSB; + uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MASK; + uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_RESET; + uint32_t d_RTC_SYNC_STATUS_OFFSET; + uint32_t d_SOC_CPU_CLOCK_OFFSET; + uint32_t d_SOC_CPU_CLOCK_STANDARD_MSB; + uint32_t d_SOC_CPU_CLOCK_STANDARD_LSB; + uint32_t d_SOC_CPU_CLOCK_STANDARD_MASK; + /* PLL end */ + + uint32_t d_SOC_POWER_REG_OFFSET; + uint32_t d_PCIE_INTR_CAUSE_ADDRESS; + uint32_t d_SOC_RESET_CONTROL_ADDRESS; + uint32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK; + uint32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB; + uint32_t d_SOC_RESET_CONTROL_CE_RST_MASK; + uint32_t d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK; + uint32_t d_CPU_INTR_ADDRESS; + uint32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS; + uint32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK; + + /* chip id start */ + uint32_t d_SI_CONFIG_ERR_INT_MASK; + uint32_t d_SI_CONFIG_ERR_INT_LSB; + uint32_t d_GPIO_ENABLE_W1TS_LOW_ADDRESS; + uint32_t d_GPIO_PIN0_CONFIG_LSB; + uint32_t d_GPIO_PIN0_PAD_PULL_LSB; + uint32_t d_GPIO_PIN0_PAD_PULL_MASK; + + uint32_t d_SOC_CHIP_ID_ADDRESS; + uint32_t d_SOC_CHIP_ID_VERSION_MASK; + uint32_t d_SOC_CHIP_ID_VERSION_LSB; + uint32_t d_SOC_CHIP_ID_REVISION_MASK; + uint32_t d_SOC_CHIP_ID_REVISION_LSB; + uint32_t d_SOC_CHIP_ID_REVISION_MSB; + uint32_t d_FW_AXI_MSI_ADDR; + uint32_t d_FW_AXI_MSI_DATA; + uint32_t d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS; + uint32_t d_FPGA_VERSION_ADDRESS; + + /* chip id end */ + + uint32_t d_A_SOC_CORE_SCRATCH_0_ADDRESS; + uint32_t d_A_SOC_CORE_SCRATCH_1_ADDRESS; + uint32_t d_A_SOC_CORE_SCRATCH_2_ADDRESS; + uint32_t d_A_SOC_CORE_SCRATCH_3_ADDRESS; + uint32_t d_A_SOC_CORE_SCRATCH_4_ADDRESS; + uint32_t d_A_SOC_CORE_SCRATCH_5_ADDRESS; + uint32_t d_A_SOC_CORE_SCRATCH_6_ADDRESS; + uint32_t d_A_SOC_CORE_SCRATCH_7_ADDRESS; + uint32_t d_A_SOC_CORE_SPARE_0_REGISTER; + uint32_t d_PCIE_INTR_FIRMWARE_ROUTE_MASK; + uint32_t d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1; + uint32_t d_A_SOC_CORE_SPARE_1_REGISTER; + uint32_t d_A_SOC_CORE_PCIE_INTR_CLR_GRP1; + uint32_t d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1; + uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_0; + uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_1; + uint32_t d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA; + uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_2; + uint32_t d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK; + + uint32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET; + uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB; + uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB; + uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK; + uint32_t d_WLAN_DEBUG_CONTROL_OFFSET; + uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB; + uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB; + uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK; + uint32_t d_WLAN_DEBUG_OUT_OFFSET; + uint32_t d_WLAN_DEBUG_OUT_DATA_MSB; + uint32_t d_WLAN_DEBUG_OUT_DATA_LSB; + uint32_t d_WLAN_DEBUG_OUT_DATA_MASK; + uint32_t d_AMBA_DEBUG_BUS_OFFSET; + uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB; + uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB; + uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK; + uint32_t d_AMBA_DEBUG_BUS_SEL_MSB; + uint32_t d_AMBA_DEBUG_BUS_SEL_LSB; + uint32_t d_AMBA_DEBUG_BUS_SEL_MASK; + +#ifdef QCA_WIFI_3_0_ADRASTEA + uint32_t d_Q6_ENABLE_REGISTER_0; + uint32_t d_Q6_ENABLE_REGISTER_1; + uint32_t d_Q6_CAUSE_REGISTER_0; + uint32_t d_Q6_CAUSE_REGISTER_1; + uint32_t d_Q6_CLEAR_REGISTER_0; + uint32_t d_Q6_CLEAR_REGISTER_1; +#endif +#ifdef CONFIG_BYPASS_QMI + uint32_t d_BYPASS_QMI_TEMP_REGISTER; +#endif + uint32_t d_WIFICMN_INT_STATUS_ADDRESS; +}; + +struct hostdef_s { + uint32_t d_INT_STATUS_ENABLE_ERROR_LSB; + uint32_t d_INT_STATUS_ENABLE_ERROR_MASK; + uint32_t d_INT_STATUS_ENABLE_CPU_LSB; + uint32_t d_INT_STATUS_ENABLE_CPU_MASK; + uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB; + uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK; + uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB; + uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK; + uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB; + uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK; + uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB; + uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK; + uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB; + uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK; + uint32_t d_INT_STATUS_ENABLE_ADDRESS; + uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB; + uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK; + uint32_t d_HOST_INT_STATUS_ADDRESS; + uint32_t d_CPU_INT_STATUS_ADDRESS; + uint32_t d_ERROR_INT_STATUS_ADDRESS; + uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK; + uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB; + uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK; + uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB; + uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK; + uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB; + uint32_t d_COUNT_DEC_ADDRESS; + uint32_t d_HOST_INT_STATUS_CPU_MASK; + uint32_t d_HOST_INT_STATUS_CPU_LSB; + uint32_t d_HOST_INT_STATUS_ERROR_MASK; + uint32_t d_HOST_INT_STATUS_ERROR_LSB; + uint32_t d_HOST_INT_STATUS_COUNTER_MASK; + uint32_t d_HOST_INT_STATUS_COUNTER_LSB; + uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS; + uint32_t d_WINDOW_DATA_ADDRESS; + uint32_t d_WINDOW_READ_ADDR_ADDRESS; + uint32_t d_WINDOW_WRITE_ADDR_ADDRESS; + uint32_t d_SOC_GLOBAL_RESET_ADDRESS; + uint32_t d_RTC_STATE_ADDRESS; + uint32_t d_RTC_STATE_COLD_RESET_MASK; + uint32_t d_PCIE_LOCAL_BASE_ADDRESS; + uint32_t d_PCIE_SOC_WAKE_RESET; + uint32_t d_PCIE_SOC_WAKE_ADDRESS; + uint32_t d_PCIE_SOC_WAKE_V_MASK; + uint32_t d_RTC_STATE_V_MASK; + uint32_t d_RTC_STATE_V_LSB; + uint32_t d_FW_IND_EVENT_PENDING; + uint32_t d_FW_IND_INITIALIZED; + uint32_t d_FW_IND_HELPER; + uint32_t d_RTC_STATE_V_ON; +#if defined(SDIO_3_0) + uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK; + uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB; +#endif + uint32_t d_PCIE_SOC_RDY_STATUS_ADDRESS; + uint32_t d_PCIE_SOC_RDY_STATUS_BAR_MASK; + uint32_t d_SOC_PCIE_BASE_ADDRESS; + uint32_t d_MSI_MAGIC_ADR_ADDRESS; + uint32_t d_MSI_MAGIC_ADDRESS; + uint32_t d_HOST_CE_COUNT; + uint32_t d_ENABLE_MSI; + uint32_t d_MUX_ID_MASK; + uint32_t d_TRANSACTION_ID_MASK; + uint32_t d_DESC_DATA_FLAG_MASK; + uint32_t d_A_SOC_PCIE_PCIE_BAR0_START; + uint32_t d_FW_IND_HOST_READY; +}; + +struct host_shadow_regs_s { + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_0; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_1; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_2; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_3; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_4; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_5; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_6; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_7; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_8; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_9; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_10; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_11; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_12; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_13; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_14; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_15; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_16; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_17; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_18; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_19; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_20; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_21; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_22; + uint32_t d_A_LOCAL_SHADOW_REG_VALUE_23; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_0; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_1; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_2; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_3; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_4; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_5; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_6; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_7; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_8; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_9; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_10; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_11; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_12; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_13; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_14; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_15; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_16; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_17; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_18; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_19; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_20; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_21; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_22; + uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_23; +}; + + +/* + * @d_DST_WR_INDEX_ADDRESS: Destination ring write index + * + * @d_SRC_WATERMARK_ADDRESS: Source ring watermark + * + * @d_SRC_WATERMARK_LOW_MASK: Bits indicating low watermark from Source ring + * watermark + * + * @d_SRC_WATERMARK_HIGH_MASK: Bits indicating high watermark from Source ring + * watermark + * + * @d_DST_WATERMARK_LOW_MASK: Bits indicating low watermark from Destination + * ring watermark + * + * @d_DST_WATERMARK_HIGH_MASK: Bits indicating high watermark from Destination + * ring watermark + * + * @d_CURRENT_SRRI_ADDRESS: Current source ring read index.The Start Offset + * will be reflected after a CE transfer is completed. + * + * @d_CURRENT_DRRI_ADDRESS: Current Destination ring read index. The Start + * Offset will be reflected after a CE transfer + * is completed. + * + * @d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK: Source ring high watermark + * Interrupt Status + * + * @d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK: Source ring low watermark + * Interrupt Status + * + * @d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK: Destination ring high watermark + * Interrupt Status + * + * @d_HOST_IS_DST_RING_LOW_WATERMARK_MASK: Source ring low watermark + * Interrupt Status + * + * @d_HOST_IS_ADDRESS: Host Interrupt Status Register + * + * @d_MISC_IS_ADDRESS: Miscellaneous Interrupt Status Register + * + * @d_HOST_IS_COPY_COMPLETE_MASK: Bits indicating Copy complete interrupt + * status from the Host Interrupt Status + * register + * + * @d_CE_WRAPPER_BASE_ADDRESS: Copy Engine Wrapper Base Address + * + * @d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS: CE Wrapper summary for interrupts + * to host + * + * @d_CE_WRAPPER_INDEX_BASE_LOW: The LSB Base address to which source and + * destination read indices are written + * + * @d_CE_WRAPPER_INDEX_BASE_HIGH: The MSB Base address to which source and + * destination read indices are written + * + * @d_HOST_IE_ADDRESS: Host Line Interrupt Enable Register + * + * @d_HOST_IE_COPY_COMPLETE_MASK: Bits indicating Copy complete interrupt + * enable from the IE register + * + * @d_SR_BA_ADDRESS: LSB of Source Ring Base Address + * + * @d_SR_BA_ADDRESS_HIGH: MSB of Source Ring Base Address + * + * @d_SR_SIZE_ADDRESS: Source Ring size - number of entries and Start Offset + * + * @d_CE_CTRL1_ADDRESS: CE Control register + * + * @d_CE_CTRL1_DMAX_LENGTH_MASK: Destination buffer Max Length used for error + * check + * + * @d_DR_BA_ADDRESS: Destination Ring Base Address Low + * + * @d_DR_BA_ADDRESS_HIGH: Destination Ring Base Address High + * + * @d_DR_SIZE_ADDRESS: Destination Ring size - number of entries Start Offset + * + * @d_CE_CMD_REGISTER: Implements commands to all CE Halt Flush + * + * @d_CE_MSI_ADDRESS: CE MSI LOW Address register + * + * @d_CE_MSI_ADDRESS_HIGH: CE MSI High Address register + * + * @d_CE_MSI_DATA: CE MSI Data Register + * + * @d_CE_MSI_ENABLE_BIT: Bit in CTRL1 register indication the MSI enable + * + * @d_MISC_IE_ADDRESS: Miscellaneous Interrupt Enable Register + * + * @d_MISC_IS_AXI_ERR_MASK: + * Bit in Misc IS indicating AXI Timeout Interrupt status + * + * @d_MISC_IS_DST_ADDR_ERR_MASK: + * Bit in Misc IS indicating Destination Address Error + * + * @d_MISC_IS_SRC_LEN_ERR_MASK: Bit in Misc IS indicating Source Zero Length + * Error Interrupt status + * + * @d_MISC_IS_DST_MAX_LEN_VIO_MASK: Bit in Misc IS indicating Destination Max + * Length Violated Interrupt status + * + * @d_MISC_IS_DST_RING_OVERFLOW_MASK: Bit in Misc IS indicating Destination + * Ring Overflow Interrupt status + * + * @d_MISC_IS_SRC_RING_OVERFLOW_MASK: Bit in Misc IS indicating Source Ring + * Overflow Interrupt status + * + * @d_SRC_WATERMARK_LOW_LSB: Source Ring Low Watermark LSB + * + * @d_SRC_WATERMARK_HIGH_LSB: Source Ring Low Watermark MSB + * + * @d_DST_WATERMARK_LOW_LSB: Destination Ring Low Watermark LSB + * + * @d_DST_WATERMARK_HIGH_LSB: Destination Ring High Watermark LSB + * + * @d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK: + * Bits in d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDR + * indicating Copy engine miscellaneous interrupt summary + * + * @d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB: + * Bits in d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDR + * indicating Host interrupts summary + * + * @d_CE_CTRL1_DMAX_LENGTH_LSB: + * LSB of Destination buffer Max Length used for error check + * + * @d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK: + * Bits indicating Source ring Byte Swap enable. + * Treats source ring memory organisation as big-endian. + * + * @d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK: + * Bits indicating Destination ring byte swap enable. + * Treats destination ring memory organisation as big-endian + * + * @d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB: + * LSB of Source ring Byte Swap enable + * + * @d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB: + * LSB of Destination ring Byte Swap enable + * + * @d_CE_WRAPPER_DEBUG_OFFSET: Offset of CE OBS BUS Select register + * + * @d_CE_WRAPPER_DEBUG_SEL_MSB: + * MSB of Control register selecting inputs for trace/debug + * + * @d_CE_WRAPPER_DEBUG_SEL_LSB: + * LSB of Control register selecting inputs for trace/debug + * + * @d_CE_WRAPPER_DEBUG_SEL_MASK: + * Bit mask for trace/debug Control register + * + * @d_CE_DEBUG_OFFSET: Offset of Copy Engine FSM Debug Status + * + * @d_CE_DEBUG_SEL_MSB: MSB of Copy Engine FSM Debug Status + * + * @d_CE_DEBUG_SEL_LSB: LSB of Copy Engine FSM Debug Status + * + * @d_CE_DEBUG_SEL_MASK: Bits indicating Copy Engine FSM Debug Status + * + */ +struct ce_reg_def { + /* copy_engine.c */ + uint32_t d_DST_WR_INDEX_ADDRESS; + uint32_t d_SRC_WATERMARK_ADDRESS; + uint32_t d_SRC_WATERMARK_LOW_MASK; + uint32_t d_SRC_WATERMARK_HIGH_MASK; + uint32_t d_DST_WATERMARK_LOW_MASK; + uint32_t d_DST_WATERMARK_HIGH_MASK; + uint32_t d_CURRENT_SRRI_ADDRESS; + uint32_t d_CURRENT_DRRI_ADDRESS; + uint32_t d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK; + uint32_t d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK; + uint32_t d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK; + uint32_t d_HOST_IS_DST_RING_LOW_WATERMARK_MASK; + uint32_t d_HOST_IS_ADDRESS; + uint32_t d_MISC_IS_ADDRESS; + uint32_t d_HOST_IS_COPY_COMPLETE_MASK; + uint32_t d_CE_WRAPPER_BASE_ADDRESS; + uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS; + uint32_t d_CE_DDR_ADDRESS_FOR_RRI_LOW; + uint32_t d_CE_DDR_ADDRESS_FOR_RRI_HIGH; + uint32_t d_HOST_IE_ADDRESS; + uint32_t d_HOST_IE_COPY_COMPLETE_MASK; + uint32_t d_SR_BA_ADDRESS; + uint32_t d_SR_BA_ADDRESS_HIGH; + uint32_t d_SR_SIZE_ADDRESS; + uint32_t d_CE_CTRL1_ADDRESS; + uint32_t d_CE_CTRL1_DMAX_LENGTH_MASK; + uint32_t d_DR_BA_ADDRESS; + uint32_t d_DR_BA_ADDRESS_HIGH; + uint32_t d_DR_SIZE_ADDRESS; + uint32_t d_CE_CMD_REGISTER; + uint32_t d_CE_MSI_ADDRESS; + uint32_t d_CE_MSI_ADDRESS_HIGH; + uint32_t d_CE_MSI_DATA; + uint32_t d_CE_MSI_ENABLE_BIT; + uint32_t d_MISC_IE_ADDRESS; + uint32_t d_MISC_IS_AXI_ERR_MASK; + uint32_t d_MISC_IS_DST_ADDR_ERR_MASK; + uint32_t d_MISC_IS_SRC_LEN_ERR_MASK; + uint32_t d_MISC_IS_DST_MAX_LEN_VIO_MASK; + uint32_t d_MISC_IS_DST_RING_OVERFLOW_MASK; + uint32_t d_MISC_IS_SRC_RING_OVERFLOW_MASK; + uint32_t d_SRC_WATERMARK_LOW_LSB; + uint32_t d_SRC_WATERMARK_HIGH_LSB; + uint32_t d_DST_WATERMARK_LOW_LSB; + uint32_t d_DST_WATERMARK_HIGH_LSB; + uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK; + uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB; + uint32_t d_CE_CTRL1_DMAX_LENGTH_LSB; + uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK; + uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK; + uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB; + uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB; + uint32_t d_CE_CTRL1_IDX_UPD_EN_MASK; + uint32_t d_CE_WRAPPER_DEBUG_OFFSET; + uint32_t d_CE_WRAPPER_DEBUG_SEL_MSB; + uint32_t d_CE_WRAPPER_DEBUG_SEL_LSB; + uint32_t d_CE_WRAPPER_DEBUG_SEL_MASK; + uint32_t d_CE_DEBUG_OFFSET; + uint32_t d_CE_DEBUG_SEL_MSB; + uint32_t d_CE_DEBUG_SEL_LSB; + uint32_t d_CE_DEBUG_SEL_MASK; + uint32_t d_CE0_BASE_ADDRESS; + uint32_t d_CE1_BASE_ADDRESS; + uint32_t d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES; + uint32_t d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS; +}; + +#endif diff --git a/hif/inc/regtable.h b/hif/inc/regtable.h index 2aae9e8d89..a5340c05fb 100644 --- a/hif/inc/regtable.h +++ b/hif/inc/regtable.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -28,6 +28,6 @@ #ifndef _REGTABLE_H_ #define _REGTABLE_H_ +#include "reg_struct.h" #include "regtable_pcie.h" -#include "regtable_ce.h" #endif diff --git a/hif/inc/regtable_ce.h b/hif/inc/regtable_ce.h deleted file mode 100644 index 5261bac0b0..0000000000 --- a/hif/inc/regtable_ce.h +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Copyright (c) 2015 The Linux Foundation. All rights reserved. - * - * Previously licensed under the ISC license by Qualcomm Atheros, Inc. - * - * - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all - * copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL - * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE - * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL - * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR - * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ - -/* - * This file was originally distributed by Qualcomm Atheros, Inc. - * under proprietary terms before Copyright ownership was assigned - * to the Linux Foundation. - */ - -#ifndef _REGTABLE_CE_H_ -#define _REGTABLE_CE_H_ - -/* - * @d_DST_WR_INDEX_ADDRESS: Destination ring write index - * - * @d_SRC_WATERMARK_ADDRESS: Source ring watermark - * - * @d_SRC_WATERMARK_LOW_MASK: Bits indicating low watermark from Source ring - * watermark - * - * @d_SRC_WATERMARK_HIGH_MASK: Bits indicating high watermark from Source ring - * watermark - * - * @d_DST_WATERMARK_LOW_MASK: Bits indicating low watermark from Destination - * ring watermark - * - * @d_DST_WATERMARK_HIGH_MASK: Bits indicating high watermark from Destination - * ring watermark - * - * @d_CURRENT_SRRI_ADDRESS: Current source ring read index.The Start Offset - * will be reflected after a CE transfer is completed. - * - * @d_CURRENT_DRRI_ADDRESS: Current Destination ring read index. The Start - * Offset will be reflected after a CE transfer - * is completed. - * - * @d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK: Source ring high watermark - * Interrupt Status - * - * @d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK: Source ring low watermark - * Interrupt Status - * - * @d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK: Destination ring high watermark - * Interrupt Status - * - * @d_HOST_IS_DST_RING_LOW_WATERMARK_MASK: Source ring low watermark - * Interrupt Status - * - * @d_HOST_IS_ADDRESS: Host Interrupt Status Register - * - * @d_MISC_IS_ADDRESS: Miscellaneous Interrupt Status Register - * - * @d_HOST_IS_COPY_COMPLETE_MASK: Bits indicating Copy complete interrupt - * status from the Host Interrupt Status - * register - * - * @d_CE_WRAPPER_BASE_ADDRESS: Copy Engine Wrapper Base Address - * - * @d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS: CE Wrapper summary for interrupts - * to host - * - * @d_CE_WRAPPER_INDEX_BASE_LOW: The LSB Base address to which source and - * destination read indices are written - * - * @d_CE_WRAPPER_INDEX_BASE_HIGH: The MSB Base address to which source and - * destination read indices are written - * - * @d_HOST_IE_ADDRESS: Host Line Interrupt Enable Register - * - * @d_HOST_IE_COPY_COMPLETE_MASK: Bits indicating Copy complete interrupt - * enable from the IE register - * - * @d_SR_BA_ADDRESS: LSB of Source Ring Base Address - * - * @d_SR_BA_ADDRESS_HIGH: MSB of Source Ring Base Address - * - * @d_SR_SIZE_ADDRESS: Source Ring size - number of entries and Start Offset - * - * @d_CE_CTRL1_ADDRESS: CE Control register - * - * @d_CE_CTRL1_DMAX_LENGTH_MASK: Destination buffer Max Length used for error - * check - * - * @d_DR_BA_ADDRESS: Destination Ring Base Address Low - * - * @d_DR_BA_ADDRESS_HIGH: Destination Ring Base Address High - * - * @d_DR_SIZE_ADDRESS: Destination Ring size - number of entries Start Offset - * - * @d_CE_CMD_REGISTER: Implements commands to all CE Halt Flush - * - * @d_CE_MSI_ADDRESS: CE MSI LOW Address register - * - * @d_CE_MSI_ADDRESS_HIGH: CE MSI High Address register - * - * @d_CE_MSI_DATA: CE MSI Data Register - * - * @d_CE_MSI_ENABLE_BIT: Bit in CTRL1 register indication the MSI enable - * - * @d_MISC_IE_ADDRESS: Miscellaneous Interrupt Enable Register - * - * @d_MISC_IS_AXI_ERR_MASK: Bit in Misc IS indicating AXI Timeout Interrupt - * status - * - * @d_MISC_IS_DST_ADDR_ERR_MASK: Bit in Misc IS indicating Destination Address - * Error - * - * @d_MISC_IS_SRC_LEN_ERR_MASK: Bit in Misc IS indicating Source Zero Length - * Error Interrupt status - * - * @d_MISC_IS_DST_MAX_LEN_VIO_MASK: Bit in Misc IS indicating Destination Max - * Length Violated Interrupt status - * - * @d_MISC_IS_DST_RING_OVERFLOW_MASK: Bit in Misc IS indicating Destination - * Ring Overflow Interrupt status - * - * @d_MISC_IS_SRC_RING_OVERFLOW_MASK: Bit in Misc IS indicating Source Ring - * Overflow Interrupt status - * - * @d_SRC_WATERMARK_LOW_LSB: Source Ring Low Watermark LSB - * - * @d_SRC_WATERMARK_HIGH_LSB: Source Ring Low Watermark MSB - * - * @d_DST_WATERMARK_LOW_LSB: Destination Ring Low Watermark LSB - * - * @d_DST_WATERMARK_HIGH_LSB: Destination Ring High Watermark LSB - * - * - * @d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK: Bits in - * d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDR - * indicating Copy engine - * miscellaneous interrupt summary - * - * @d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB:Bits in - * d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDR - * indicating Host interrupts summary - * - * @d_CE_CTRL1_DMAX_LENGTH_LSB: LSB of Destination buffer Max Length used for - * error check - * - * @d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK: Bits indicating Source ring Byte Swap - * enable. Treats source ring memory - * organisation as big-endian - * - * @d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK: Bits indicating Destination ring - * byte swap enable. Treats destination - * ring memory organisation as big-endian - * - * @d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB: LSB of Source ring Byte Swap enable - * - * @d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB: LSB of Destination ring Byte Swap enable - * - * @d_CE_WRAPPER_DEBUG_OFFSET: Offset of CE OBS BUS Select register - * - * @d_CE_WRAPPER_DEBUG_SEL_MSB: MSB of Control register selecting inputs for - * trace/debug - * - * @d_CE_WRAPPER_DEBUG_SEL_LSB: LSB of Control register selecting inputs for - * trace/debug - * - * @d_CE_WRAPPER_DEBUG_SEL_MASK: Bits indicating Control register selecting - * inputs for trace/debug - * - * @d_CE_DEBUG_OFFSET: Offset of Copy Engine FSM Debug Status - * - * @d_CE_DEBUG_SEL_MSB: MSB of Copy Engine FSM Debug Status - * - * @d_CE_DEBUG_SEL_LSB: LSB of Copy Engine FSM Debug Status - * - * @d_CE_DEBUG_SEL_MASK: Bits indicating Copy Engine FSM Debug Status - * -*/ - -struct ce_reg_def { - /* copy_engine.c */ - uint32_t d_DST_WR_INDEX_ADDRESS; - uint32_t d_SRC_WATERMARK_ADDRESS; - uint32_t d_SRC_WATERMARK_LOW_MASK; - uint32_t d_SRC_WATERMARK_HIGH_MASK; - uint32_t d_DST_WATERMARK_LOW_MASK; - uint32_t d_DST_WATERMARK_HIGH_MASK; - uint32_t d_CURRENT_SRRI_ADDRESS; - uint32_t d_CURRENT_DRRI_ADDRESS; - uint32_t d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK; - uint32_t d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK; - uint32_t d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK; - uint32_t d_HOST_IS_DST_RING_LOW_WATERMARK_MASK; - uint32_t d_HOST_IS_ADDRESS; - uint32_t d_MISC_IS_ADDRESS; - uint32_t d_HOST_IS_COPY_COMPLETE_MASK; - uint32_t d_CE_WRAPPER_BASE_ADDRESS; - uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS; - uint32_t d_CE_DDR_ADDRESS_FOR_RRI_LOW; - uint32_t d_CE_DDR_ADDRESS_FOR_RRI_HIGH; - uint32_t d_HOST_IE_ADDRESS; - uint32_t d_HOST_IE_COPY_COMPLETE_MASK; - uint32_t d_SR_BA_ADDRESS; - uint32_t d_SR_BA_ADDRESS_HIGH; - uint32_t d_SR_SIZE_ADDRESS; - uint32_t d_CE_CTRL1_ADDRESS; - uint32_t d_CE_CTRL1_DMAX_LENGTH_MASK; - uint32_t d_DR_BA_ADDRESS; - uint32_t d_DR_BA_ADDRESS_HIGH; - uint32_t d_DR_SIZE_ADDRESS; - uint32_t d_CE_CMD_REGISTER; - uint32_t d_CE_MSI_ADDRESS; - uint32_t d_CE_MSI_ADDRESS_HIGH; - uint32_t d_CE_MSI_DATA; - uint32_t d_CE_MSI_ENABLE_BIT; - uint32_t d_MISC_IE_ADDRESS; - uint32_t d_MISC_IS_AXI_ERR_MASK; - uint32_t d_MISC_IS_DST_ADDR_ERR_MASK; - uint32_t d_MISC_IS_SRC_LEN_ERR_MASK; - uint32_t d_MISC_IS_DST_MAX_LEN_VIO_MASK; - uint32_t d_MISC_IS_DST_RING_OVERFLOW_MASK; - uint32_t d_MISC_IS_SRC_RING_OVERFLOW_MASK; - uint32_t d_SRC_WATERMARK_LOW_LSB; - uint32_t d_SRC_WATERMARK_HIGH_LSB; - uint32_t d_DST_WATERMARK_LOW_LSB; - uint32_t d_DST_WATERMARK_HIGH_LSB; - uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK; - uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB; - uint32_t d_CE_CTRL1_DMAX_LENGTH_LSB; - uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK; - uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK; - uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB; - uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB; - uint32_t d_CE_CTRL1_IDX_UPD_EN_MASK; - uint32_t d_CE_WRAPPER_DEBUG_OFFSET; - uint32_t d_CE_WRAPPER_DEBUG_SEL_MSB; - uint32_t d_CE_WRAPPER_DEBUG_SEL_LSB; - uint32_t d_CE_WRAPPER_DEBUG_SEL_MASK; - uint32_t d_CE_DEBUG_OFFSET; - uint32_t d_CE_DEBUG_SEL_MSB; - uint32_t d_CE_DEBUG_SEL_LSB; - uint32_t d_CE_DEBUG_SEL_MASK; - uint32_t d_CE0_BASE_ADDRESS; - uint32_t d_CE1_BASE_ADDRESS; - uint32_t d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES; - uint32_t d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS; -}; -#endif /* _REGTABLE_CE_H_ */ diff --git a/hif/inc/regtable_pcie.h b/hif/inc/regtable_pcie.h index faed8b7419..753271b75d 100644 --- a/hif/inc/regtable_pcie.h +++ b/hif/inc/regtable_pcie.h @@ -30,254 +30,6 @@ #define MISSING 0 -struct targetdef_s { - uint32_t d_RTC_SOC_BASE_ADDRESS; - uint32_t d_RTC_WMAC_BASE_ADDRESS; - uint32_t d_SYSTEM_SLEEP_OFFSET; - uint32_t d_WLAN_SYSTEM_SLEEP_OFFSET; - uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_LSB; - uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_MASK; - uint32_t d_CLOCK_CONTROL_OFFSET; - uint32_t d_CLOCK_CONTROL_SI0_CLK_MASK; - uint32_t d_RESET_CONTROL_OFFSET; - uint32_t d_RESET_CONTROL_MBOX_RST_MASK; - uint32_t d_RESET_CONTROL_SI0_RST_MASK; - uint32_t d_WLAN_RESET_CONTROL_OFFSET; - uint32_t d_WLAN_RESET_CONTROL_COLD_RST_MASK; - uint32_t d_WLAN_RESET_CONTROL_WARM_RST_MASK; - uint32_t d_GPIO_BASE_ADDRESS; - uint32_t d_GPIO_PIN0_OFFSET; - uint32_t d_GPIO_PIN1_OFFSET; - uint32_t d_GPIO_PIN0_CONFIG_MASK; - uint32_t d_GPIO_PIN1_CONFIG_MASK; - uint32_t d_SI_CONFIG_BIDIR_OD_DATA_LSB; - uint32_t d_SI_CONFIG_BIDIR_OD_DATA_MASK; - uint32_t d_SI_CONFIG_I2C_LSB; - uint32_t d_SI_CONFIG_I2C_MASK; - uint32_t d_SI_CONFIG_POS_SAMPLE_LSB; - uint32_t d_SI_CONFIG_POS_SAMPLE_MASK; - uint32_t d_SI_CONFIG_INACTIVE_CLK_LSB; - uint32_t d_SI_CONFIG_INACTIVE_CLK_MASK; - uint32_t d_SI_CONFIG_INACTIVE_DATA_LSB; - uint32_t d_SI_CONFIG_INACTIVE_DATA_MASK; - uint32_t d_SI_CONFIG_DIVIDER_LSB; - uint32_t d_SI_CONFIG_DIVIDER_MASK; - uint32_t d_SI_BASE_ADDRESS; - uint32_t d_SI_CONFIG_OFFSET; - uint32_t d_SI_TX_DATA0_OFFSET; - uint32_t d_SI_TX_DATA1_OFFSET; - uint32_t d_SI_RX_DATA0_OFFSET; - uint32_t d_SI_RX_DATA1_OFFSET; - uint32_t d_SI_CS_OFFSET; - uint32_t d_SI_CS_DONE_ERR_MASK; - uint32_t d_SI_CS_DONE_INT_MASK; - uint32_t d_SI_CS_START_LSB; - uint32_t d_SI_CS_START_MASK; - uint32_t d_SI_CS_RX_CNT_LSB; - uint32_t d_SI_CS_RX_CNT_MASK; - uint32_t d_SI_CS_TX_CNT_LSB; - uint32_t d_SI_CS_TX_CNT_MASK; - uint32_t d_BOARD_DATA_SZ; - uint32_t d_BOARD_EXT_DATA_SZ; - uint32_t d_MBOX_BASE_ADDRESS; - uint32_t d_LOCAL_SCRATCH_OFFSET; - uint32_t d_CPU_CLOCK_OFFSET; - uint32_t d_LPO_CAL_OFFSET; - uint32_t d_GPIO_PIN10_OFFSET; - uint32_t d_GPIO_PIN11_OFFSET; - uint32_t d_GPIO_PIN12_OFFSET; - uint32_t d_GPIO_PIN13_OFFSET; - uint32_t d_CLOCK_GPIO_OFFSET; - uint32_t d_CPU_CLOCK_STANDARD_LSB; - uint32_t d_CPU_CLOCK_STANDARD_MASK; - uint32_t d_LPO_CAL_ENABLE_LSB; - uint32_t d_LPO_CAL_ENABLE_MASK; - uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB; - uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK; - uint32_t d_ANALOG_INTF_BASE_ADDRESS; - uint32_t d_WLAN_MAC_BASE_ADDRESS; - uint32_t d_FW_INDICATOR_ADDRESS; - uint32_t d_DRAM_BASE_ADDRESS; - uint32_t d_SOC_CORE_BASE_ADDRESS; - uint32_t d_CORE_CTRL_ADDRESS; - uint32_t d_CE_COUNT; - uint32_t d_MSI_NUM_REQUEST; - uint32_t d_MSI_ASSIGN_FW; - uint32_t d_MSI_ASSIGN_CE_INITIAL; - uint32_t d_PCIE_INTR_ENABLE_ADDRESS; - uint32_t d_PCIE_INTR_CLR_ADDRESS; - uint32_t d_PCIE_INTR_FIRMWARE_MASK; - uint32_t d_PCIE_INTR_CE_MASK_ALL; - uint32_t d_CORE_CTRL_CPU_INTR_MASK; - uint32_t d_SR_WR_INDEX_ADDRESS; - uint32_t d_DST_WATERMARK_ADDRESS; - - /* htt_rx.c */ - uint32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK; - uint32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB; - uint32_t d_RX_MPDU_START_0_RETRY_LSB; - uint32_t d_RX_MPDU_START_0_RETRY_MASK; - uint32_t d_RX_MPDU_START_0_SEQ_NUM_MASK; - uint32_t d_RX_MPDU_START_0_SEQ_NUM_LSB; - uint32_t d_RX_MPDU_START_2_PN_47_32_LSB; - uint32_t d_RX_MPDU_START_2_PN_47_32_MASK; - uint32_t d_RX_MPDU_START_2_TID_LSB; - uint32_t d_RX_MPDU_START_2_TID_MASK; - uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK; - uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB; - uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_MASK; - uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_LSB; - uint32_t d_RX_MSDU_END_4_LAST_MSDU_MASK; - uint32_t d_RX_MSDU_END_4_LAST_MSDU_LSB; - uint32_t d_RX_ATTENTION_0_MCAST_BCAST_MASK; - uint32_t d_RX_ATTENTION_0_MCAST_BCAST_LSB; - uint32_t d_RX_ATTENTION_0_FRAGMENT_MASK; - uint32_t d_RX_ATTENTION_0_FRAGMENT_LSB; - uint32_t d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK; - uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK; - uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB; - uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_MASK; - uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_LSB; - uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET; - uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_MASK; - uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_LSB; - uint32_t d_RX_MPDU_START_0_ENCRYPTED_MASK; - uint32_t d_RX_MPDU_START_0_ENCRYPTED_LSB; - uint32_t d_RX_ATTENTION_0_MORE_DATA_MASK; - uint32_t d_RX_ATTENTION_0_MSDU_DONE_MASK; - uint32_t d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK; - /* end */ - - /* PLL start */ - uint32_t d_EFUSE_OFFSET; - uint32_t d_EFUSE_XTAL_SEL_MSB; - uint32_t d_EFUSE_XTAL_SEL_LSB; - uint32_t d_EFUSE_XTAL_SEL_MASK; - uint32_t d_BB_PLL_CONFIG_OFFSET; - uint32_t d_BB_PLL_CONFIG_OUTDIV_MSB; - uint32_t d_BB_PLL_CONFIG_OUTDIV_LSB; - uint32_t d_BB_PLL_CONFIG_OUTDIV_MASK; - uint32_t d_BB_PLL_CONFIG_FRAC_MSB; - uint32_t d_BB_PLL_CONFIG_FRAC_LSB; - uint32_t d_BB_PLL_CONFIG_FRAC_MASK; - uint32_t d_WLAN_PLL_SETTLE_TIME_MSB; - uint32_t d_WLAN_PLL_SETTLE_TIME_LSB; - uint32_t d_WLAN_PLL_SETTLE_TIME_MASK; - uint32_t d_WLAN_PLL_SETTLE_OFFSET; - uint32_t d_WLAN_PLL_SETTLE_SW_MASK; - uint32_t d_WLAN_PLL_SETTLE_RSTMASK; - uint32_t d_WLAN_PLL_SETTLE_RESET; - uint32_t d_WLAN_PLL_CONTROL_NOPWD_MSB; - uint32_t d_WLAN_PLL_CONTROL_NOPWD_LSB; - uint32_t d_WLAN_PLL_CONTROL_NOPWD_MASK; - uint32_t d_WLAN_PLL_CONTROL_BYPASS_MSB; - uint32_t d_WLAN_PLL_CONTROL_BYPASS_LSB; - uint32_t d_WLAN_PLL_CONTROL_BYPASS_MASK; - uint32_t d_WLAN_PLL_CONTROL_BYPASS_RESET; - uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MSB; - uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_LSB; - uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MASK; - uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_RESET; - uint32_t d_WLAN_PLL_CONTROL_REFDIV_MSB; - uint32_t d_WLAN_PLL_CONTROL_REFDIV_LSB; - uint32_t d_WLAN_PLL_CONTROL_REFDIV_MASK; - uint32_t d_WLAN_PLL_CONTROL_REFDIV_RESET; - uint32_t d_WLAN_PLL_CONTROL_DIV_MSB; - uint32_t d_WLAN_PLL_CONTROL_DIV_LSB; - uint32_t d_WLAN_PLL_CONTROL_DIV_MASK; - uint32_t d_WLAN_PLL_CONTROL_DIV_RESET; - uint32_t d_WLAN_PLL_CONTROL_OFFSET; - uint32_t d_WLAN_PLL_CONTROL_SW_MASK; - uint32_t d_WLAN_PLL_CONTROL_RSTMASK; - uint32_t d_WLAN_PLL_CONTROL_RESET; - uint32_t d_SOC_CORE_CLK_CTRL_OFFSET; - uint32_t d_SOC_CORE_CLK_CTRL_DIV_MSB; - uint32_t d_SOC_CORE_CLK_CTRL_DIV_LSB; - uint32_t d_SOC_CORE_CLK_CTRL_DIV_MASK; - uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MSB; - uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_LSB; - uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MASK; - uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_RESET; - uint32_t d_RTC_SYNC_STATUS_OFFSET; - uint32_t d_SOC_CPU_CLOCK_OFFSET; - uint32_t d_SOC_CPU_CLOCK_STANDARD_MSB; - uint32_t d_SOC_CPU_CLOCK_STANDARD_LSB; - uint32_t d_SOC_CPU_CLOCK_STANDARD_MASK; - /* PLL end */ - - uint32_t d_SOC_POWER_REG_OFFSET; - uint32_t d_PCIE_INTR_CAUSE_ADDRESS; - uint32_t d_SOC_RESET_CONTROL_ADDRESS; - uint32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK; - uint32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB; - uint32_t d_SOC_RESET_CONTROL_CE_RST_MASK; - uint32_t d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK; - uint32_t d_CPU_INTR_ADDRESS; - uint32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS; - uint32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK; - - /* chip id start */ - uint32_t d_SOC_CHIP_ID_ADDRESS; - uint32_t d_SOC_CHIP_ID_VERSION_MASK; - uint32_t d_SOC_CHIP_ID_VERSION_LSB; - uint32_t d_SOC_CHIP_ID_REVISION_MASK; - uint32_t d_SOC_CHIP_ID_REVISION_LSB; - /* chip id end */ - - uint32_t d_A_SOC_CORE_SCRATCH_0_ADDRESS; - uint32_t d_A_SOC_CORE_SCRATCH_1_ADDRESS; - uint32_t d_A_SOC_CORE_SCRATCH_2_ADDRESS; - uint32_t d_A_SOC_CORE_SCRATCH_3_ADDRESS; - uint32_t d_A_SOC_CORE_SCRATCH_4_ADDRESS; - uint32_t d_A_SOC_CORE_SCRATCH_5_ADDRESS; - uint32_t d_A_SOC_CORE_SCRATCH_6_ADDRESS; - uint32_t d_A_SOC_CORE_SCRATCH_7_ADDRESS; - uint32_t d_A_SOC_CORE_SPARE_0_REGISTER; - uint32_t d_PCIE_INTR_FIRMWARE_ROUTE_MASK; - uint32_t d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1; - uint32_t d_A_SOC_CORE_SPARE_1_REGISTER; - uint32_t d_A_SOC_CORE_PCIE_INTR_CLR_GRP1; - uint32_t d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1; - uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_0; - uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_1; - uint32_t d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA; - uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_2; - uint32_t d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK; - - uint32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET; - uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB; - uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB; - uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK; - uint32_t d_WLAN_DEBUG_CONTROL_OFFSET; - uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB; - uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB; - uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK; - uint32_t d_WLAN_DEBUG_OUT_OFFSET; - uint32_t d_WLAN_DEBUG_OUT_DATA_MSB; - uint32_t d_WLAN_DEBUG_OUT_DATA_LSB; - uint32_t d_WLAN_DEBUG_OUT_DATA_MASK; - uint32_t d_AMBA_DEBUG_BUS_OFFSET; - uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB; - uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB; - uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK; - uint32_t d_AMBA_DEBUG_BUS_SEL_MSB; - uint32_t d_AMBA_DEBUG_BUS_SEL_LSB; - uint32_t d_AMBA_DEBUG_BUS_SEL_MASK; - -#ifdef QCA_WIFI_3_0_ADRASTEA - uint32_t d_Q6_ENABLE_REGISTER_0; - uint32_t d_Q6_ENABLE_REGISTER_1; - uint32_t d_Q6_CAUSE_REGISTER_0; - uint32_t d_Q6_CAUSE_REGISTER_1; - uint32_t d_Q6_CLEAR_REGISTER_0; - uint32_t d_Q6_CLEAR_REGISTER_1; -#endif - -#ifdef CONFIG_BYPASS_QMI - uint32_t d_BYPASS_QMI_TEMP_REGISTER; -#endif -}; - #define A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK \ (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK) #define A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 \ @@ -457,6 +209,7 @@ struct targetdef_s { #define SOC_POWER_REG_OFFSET (scn->targetdef->d_SOC_POWER_REG_OFFSET) /* end */ +#ifndef CONFIG_WIN /* htt_rx.c */ #define RX_MSDU_END_4_FIRST_MSDU_MASK \ (pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_MASK) @@ -525,6 +278,7 @@ struct targetdef_s { #define RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK \ (pdev->targetdef->d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK) /* end */ +#endif /* copy_engine.c */ /* end */ @@ -609,6 +363,64 @@ struct targetdef_s { (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK) /* PLL end */ +#define FW_CPU_PLL_CONFIG \ + (sc->targetdef->d_FW_CPU_PLL_CONFIG) + +#define WIFICMN_PCIE_BAR_REG_ADDRESS \ + (sc->targetdef->d_WIFICMN_PCIE_BAR_REG_ADDRESS) + + /* htt tx */ +#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK \ + (pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK) +#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK \ + (pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK) +#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK \ + (pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK) +#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK \ + (pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK) +#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB \ + (pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB) +#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB \ + (pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB) +#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB \ + (pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB) +#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB \ + (pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB) + +#define CE_CMD_ADDRESS \ + (scn->targetdef->d_CE_CMD_ADDRESS) +#define CE_CMD_HALT_MASK \ + (scn->targetdef->d_CE_CMD_HALT_MASK) +#define CE_CMD_HALT_STATUS_MASK \ + (scn->targetdef->d_CE_CMD_HALT_STATUS_MASK) +#define CE_CMD_HALT_STATUS_LSB \ + (scn->targetdef->d_CE_CMD_HALT_STATUS_LSB) + +#define SI_CONFIG_ERR_INT_MASK \ + (scn->targetdef->d_SI_CONFIG_ERR_INT_MASK) +#define SI_CONFIG_ERR_INT_LSB \ + (scn->targetdef->d_SI_CONFIG_ERR_INT_LSB) +#define GPIO_ENABLE_W1TS_LOW_ADDRESS \ + (scn->targetdef->d_GPIO_ENABLE_W1TS_LOW_ADDRESS) +#define GPIO_PIN0_CONFIG_LSB \ + (scn->targetdef->d_GPIO_PIN0_CONFIG_LSB) +#define GPIO_PIN0_PAD_PULL_LSB \ + (scn->targetdef->d_GPIO_PIN0_PAD_PULL_LSB) +#define GPIO_PIN0_PAD_PULL_MASK \ + (scn->targetdef->d_GPIO_PIN0_PAD_PULL_MASK) + +#define SOC_CHIP_ID_REVISION_MSB \ + (scn->targetdef->d_SOC_CHIP_ID_REVISION_MSB) + +#define FW_AXI_MSI_ADDR \ + (scn->targetdef->d_FW_AXI_MSI_ADDR) +#define FW_AXI_MSI_DATA \ + (scn->targetdef->d_FW_AXI_MSI_DATA) +#define WLAN_SUBSYSTEM_CORE_ID_ADDRESS \ + (scn->targetdef->d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS) +#define FPGA_VERSION_ADDRESS \ + (scn->targetdef->d_FPGA_VERSION_ADDRESS) + /* SET macros */ #define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \ (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \ @@ -687,6 +499,13 @@ struct targetdef_s { #define SOC_CPU_CLOCK_STANDARD_SET(x) \ (((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK) /* PLL end */ +#define WLAN_GPIO_PIN0_CONFIG_SET(x) \ + (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK) +#define WLAN_GPIO_PIN0_PAD_PULL_SET(x) \ + (((x) << GPIO_PIN0_PAD_PULL_LSB) & GPIO_PIN0_PAD_PULL_MASK) +#define SI_CONFIG_ERR_INT_SET(x) \ + (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK) + #ifdef QCA_WIFI_3_0_ADRASTEA #define Q6_ENABLE_REGISTER_0 \ @@ -708,73 +527,6 @@ struct targetdef_s { (scn->targetdef->d_BYPASS_QMI_TEMP_REGISTER) #endif -struct hostdef_s { - uint32_t d_INT_STATUS_ENABLE_ERROR_LSB; - uint32_t d_INT_STATUS_ENABLE_ERROR_MASK; - uint32_t d_INT_STATUS_ENABLE_CPU_LSB; - uint32_t d_INT_STATUS_ENABLE_CPU_MASK; - uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB; - uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK; - uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB; - uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK; - uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB; - uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK; - uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB; - uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK; - uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB; - uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK; - uint32_t d_INT_STATUS_ENABLE_ADDRESS; - uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB; - uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK; - uint32_t d_HOST_INT_STATUS_ADDRESS; - uint32_t d_CPU_INT_STATUS_ADDRESS; - uint32_t d_ERROR_INT_STATUS_ADDRESS; - uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK; - uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB; - uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK; - uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB; - uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK; - uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB; - uint32_t d_COUNT_DEC_ADDRESS; - uint32_t d_HOST_INT_STATUS_CPU_MASK; - uint32_t d_HOST_INT_STATUS_CPU_LSB; - uint32_t d_HOST_INT_STATUS_ERROR_MASK; - uint32_t d_HOST_INT_STATUS_ERROR_LSB; - uint32_t d_HOST_INT_STATUS_COUNTER_MASK; - uint32_t d_HOST_INT_STATUS_COUNTER_LSB; - uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS; - uint32_t d_WINDOW_DATA_ADDRESS; - uint32_t d_WINDOW_READ_ADDR_ADDRESS; - uint32_t d_WINDOW_WRITE_ADDR_ADDRESS; - uint32_t d_SOC_GLOBAL_RESET_ADDRESS; - uint32_t d_RTC_STATE_ADDRESS; - uint32_t d_RTC_STATE_COLD_RESET_MASK; - uint32_t d_PCIE_LOCAL_BASE_ADDRESS; - uint32_t d_PCIE_SOC_WAKE_RESET; - uint32_t d_PCIE_SOC_WAKE_ADDRESS; - uint32_t d_PCIE_SOC_WAKE_V_MASK; - uint32_t d_RTC_STATE_V_MASK; - uint32_t d_RTC_STATE_V_LSB; - uint32_t d_FW_IND_EVENT_PENDING; - uint32_t d_FW_IND_INITIALIZED; - uint32_t d_FW_IND_HELPER; - uint32_t d_RTC_STATE_V_ON; -#if defined(SDIO_3_0) - uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK; - uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB; -#endif - uint32_t d_PCIE_SOC_RDY_STATUS_ADDRESS; - uint32_t d_PCIE_SOC_RDY_STATUS_BAR_MASK; - uint32_t d_SOC_PCIE_BASE_ADDRESS; - uint32_t d_MSI_MAGIC_ADR_ADDRESS; - uint32_t d_MSI_MAGIC_ADDRESS; - uint32_t d_HOST_CE_COUNT; - uint32_t d_ENABLE_MSI; - uint32_t d_MUX_ID_MASK; - uint32_t d_TRANSACTION_ID_MASK; - uint32_t d_DESC_DATA_FLAG_MASK; - uint32_t d_A_SOC_PCIE_PCIE_BAR0_START; -}; #define A_SOC_PCIE_PCIE_BAR0_START (scn->hostdef->d_A_SOC_PCIE_PCIE_BAR0_START) #define DESC_DATA_FLAG_MASK (scn->hostdef->d_DESC_DATA_FLAG_MASK) #define MUX_ID_MASK (scn->hostdef->d_MUX_ID_MASK) @@ -854,6 +606,9 @@ struct hostdef_s { #define FW_IND_INITIALIZED (scn->hostdef->d_FW_IND_INITIALIZED) #define FW_IND_HELPER (scn->hostdef->d_FW_IND_HELPER) #define RTC_STATE_V_ON (scn->hostdef->d_RTC_STATE_V_ON) + +#define FW_IND_HOST_READY (scn->hostdef->d_FW_IND_HOST_READY) + #if defined(SDIO_3_0) #define HOST_INT_STATUS_MBOX_DATA_MASK \ (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK) @@ -985,55 +740,4 @@ struct hif_softc; void target_register_tbl_attach(struct hif_softc *scn, u32 target_type); void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type); -struct host_shadow_regs_s { - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_0; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_1; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_2; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_3; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_4; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_5; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_6; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_7; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_8; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_9; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_10; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_11; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_12; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_13; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_14; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_15; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_16; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_17; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_18; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_19; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_20; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_21; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_22; - uint32_t d_A_LOCAL_SHADOW_REG_VALUE_23; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_0; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_1; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_2; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_3; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_4; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_5; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_6; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_7; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_8; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_9; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_10; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_11; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_12; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_13; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_14; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_15; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_16; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_17; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_18; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_19; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_20; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_21; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_22; - uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_23; -}; - #endif /* _REGTABLE_PCIE_H_ */ diff --git a/hif/inc/target_reg_init.h b/hif/inc/target_reg_init.h new file mode 100644 index 0000000000..d41caf1f7d --- /dev/null +++ b/hif/inc/target_reg_init.h @@ -0,0 +1,504 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef TARGET_REG_INIT_H +#define TARGET_REG_INIT_H +#include "reg_struct.h" +#include "targaddrs.h" +/*** WARNING : Add to the end of the TABLE! do not change the order ****/ +typedef struct targetdef_s TARGET_REGISTER_TABLE; + + + +#define ATH_UNSUPPORTED_REG_OFFSET 0xffffffff +#define ATH_SUPPORTED_BY_TARGET(reg_offset) \ + ((reg_offset) != ATH_UNSUPPORTED_REG_OFFSET) + +#if defined(MY_TARGET_DEF) + +/* Cross-platform compatibility */ +#if !defined(SOC_RESET_CONTROL_OFFSET) && defined(RESET_CONTROL_OFFSET) +#define SOC_RESET_CONTROL_OFFSET RESET_CONTROL_OFFSET +#endif + +#if !defined(CLOCK_GPIO_OFFSET) +#define CLOCK_GPIO_OFFSET ATH_UNSUPPORTED_REG_OFFSET +#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 +#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 +#endif + +#if !defined(WLAN_MAC_BASE_ADDRESS) +#define WLAN_MAC_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif + +#if !defined(CE0_BASE_ADDRESS) +#define CE0_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#define CE1_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#define CE_COUNT 0 +#endif + +#if !defined(MSI_NUM_REQUEST) +#define MSI_NUM_REQUEST 0 +#define MSI_ASSIGN_FW 0 +#define MSI_ASSIGN_CE_INITIAL 0 +#endif + +#if !defined(FW_INDICATOR_ADDRESS) +#define FW_INDICATOR_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif + +#if !defined(FW_CPU_PLL_CONFIG) +#define FW_CPU_PLL_CONFIG ATH_UNSUPPORTED_REG_OFFSET +#endif + +#if !defined(DRAM_BASE_ADDRESS) +#define DRAM_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif + +#if !defined(SOC_CORE_BASE_ADDRESS) +#define SOC_CORE_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif + +#if !defined(CPU_INTR_ADDRESS) +#define CPU_INTR_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif + +#if !defined(SOC_LF_TIMER_CONTROL0_ADDRESS) +#define SOC_LF_TIMER_CONTROL0_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK ATH_UNSUPPORTED_REG_OFFSET +#endif + +#if !defined(SOC_RESET_CONTROL_ADDRESS) +#define SOC_RESET_CONTROL_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#define SOC_RESET_CONTROL_CE_RST_MASK ATH_UNSUPPORTED_REG_OFFSET +#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK ATH_UNSUPPORTED_REG_OFFSET +#endif + +#if !defined(CORE_CTRL_ADDRESS) +#define CORE_CTRL_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#define CORE_CTRL_CPU_INTR_MASK 0 +#endif + +#if !defined(PCIE_INTR_ENABLE_ADDRESS) +#define PCIE_INTR_ENABLE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#define PCIE_INTR_CLR_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#define PCIE_INTR_FIRMWARE_MASK ATH_UNSUPPORTED_REG_OFFSET +#define PCIE_INTR_CE_MASK_ALL ATH_UNSUPPORTED_REG_OFFSET +#define PCIE_INTR_CAUSE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif + +#if !defined(WIFICMN_PCIE_BAR_REG_ADDRESS) +#define WIFICMN_PCIE_BAR_REG_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif + +#if !defined(WIFICMN_INT_STATUS_ADDRESS) +#define WIFICMN_INT_STATUS_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif + +#if !defined(FW_AXI_MSI_ADDR) +#define FW_AXI_MSI_ADDR ATH_UNSUPPORTED_REG_OFFSET +#endif + +#if !defined(FW_AXI_MSI_DATA) +#define FW_AXI_MSI_DATA ATH_UNSUPPORTED_REG_OFFSET +#endif + +#if !defined(WLAN_SUBSYSTEM_CORE_ID_ADDRESS) +#define WLAN_SUBSYSTEM_CORE_ID_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif + +#if !defined(FPGA_VERSION_ADDRESS) +#define FPGA_VERSION_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif + +#if !defined(SI_CONFIG_ADDRESS) +#define SI_CONFIG_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#define SI_CONFIG_BIDIR_OD_DATA_LSB 0 +#define SI_CONFIG_BIDIR_OD_DATA_MASK 0 +#define SI_CONFIG_I2C_LSB 0 +#define SI_CONFIG_I2C_MASK 0 +#define SI_CONFIG_POS_SAMPLE_LSB 0 +#define SI_CONFIG_POS_SAMPLE_MASK 0 +#define SI_CONFIG_INACTIVE_CLK_LSB 0 +#define SI_CONFIG_INACTIVE_CLK_MASK 0 +#define SI_CONFIG_INACTIVE_DATA_LSB 0 +#define SI_CONFIG_INACTIVE_DATA_MASK 0 +#define SI_CONFIG_DIVIDER_LSB 0 +#define SI_CONFIG_DIVIDER_MASK 0 +#define SI_CONFIG_OFFSET 0 +#define SI_TX_DATA0_OFFSET ATH_UNSUPPORTED_REG_OFFSET +#define SI_TX_DATA1_OFFSET ATH_UNSUPPORTED_REG_OFFSET +#define SI_RX_DATA0_OFFSET ATH_UNSUPPORTED_REG_OFFSET +#define SI_RX_DATA1_OFFSET ATH_UNSUPPORTED_REG_OFFSET +#define SI_CS_OFFSET ATH_UNSUPPORTED_REG_OFFSET +#define SI_CS_DONE_ERR_MASK 0 +#define SI_CS_DONE_INT_MASK 0 +#define SI_CS_START_LSB 0 +#define SI_CS_START_MASK 0 +#define SI_CS_RX_CNT_LSB 0 +#define SI_CS_RX_CNT_MASK 0 +#define SI_CS_TX_CNT_LSB 0 +#define SI_CS_TX_CNT_MASK 0 +#endif + +#ifndef SI_BASE_ADDRESS +#define SI_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif + +#ifndef WLAN_GPIO_PIN10_ADDRESS +#define WLAN_GPIO_PIN10_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif + +#ifndef WLAN_GPIO_PIN11_ADDRESS +#define WLAN_GPIO_PIN11_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif + +#ifndef WLAN_GPIO_PIN12_ADDRESS +#define WLAN_GPIO_PIN12_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif + +#ifndef WLAN_GPIO_PIN13_ADDRESS +#define WLAN_GPIO_PIN13_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif + +#ifndef WIFICMN_INT_STATUS_ADDRESS +#define WIFICMN_INT_STATUS_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif + +static struct targetdef_s my_target_def = { + .d_RTC_SOC_BASE_ADDRESS = RTC_SOC_BASE_ADDRESS, + .d_RTC_WMAC_BASE_ADDRESS = RTC_WMAC_BASE_ADDRESS, + .d_SYSTEM_SLEEP_OFFSET = WLAN_SYSTEM_SLEEP_OFFSET, + .d_WLAN_SYSTEM_SLEEP_OFFSET = WLAN_SYSTEM_SLEEP_OFFSET, + .d_WLAN_SYSTEM_SLEEP_DISABLE_LSB = WLAN_SYSTEM_SLEEP_DISABLE_LSB, + .d_WLAN_SYSTEM_SLEEP_DISABLE_MASK = WLAN_SYSTEM_SLEEP_DISABLE_MASK, + .d_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET, + .d_CLOCK_CONTROL_SI0_CLK_MASK = CLOCK_CONTROL_SI0_CLK_MASK, + .d_RESET_CONTROL_OFFSET = SOC_RESET_CONTROL_OFFSET, + .d_RESET_CONTROL_SI0_RST_MASK = RESET_CONTROL_SI0_RST_MASK, + .d_WLAN_RESET_CONTROL_OFFSET = WLAN_RESET_CONTROL_OFFSET, + .d_WLAN_RESET_CONTROL_COLD_RST_MASK = WLAN_RESET_CONTROL_COLD_RST_MASK, + .d_WLAN_RESET_CONTROL_WARM_RST_MASK = WLAN_RESET_CONTROL_WARM_RST_MASK, + .d_GPIO_BASE_ADDRESS = GPIO_BASE_ADDRESS, + .d_GPIO_PIN0_OFFSET = GPIO_PIN0_OFFSET, + .d_GPIO_PIN1_OFFSET = GPIO_PIN1_OFFSET, + .d_GPIO_PIN0_CONFIG_MASK = GPIO_PIN0_CONFIG_MASK, + .d_GPIO_PIN1_CONFIG_MASK = GPIO_PIN1_CONFIG_MASK, + .d_SI_CONFIG_BIDIR_OD_DATA_LSB = SI_CONFIG_BIDIR_OD_DATA_LSB, + .d_SI_CONFIG_BIDIR_OD_DATA_MASK = SI_CONFIG_BIDIR_OD_DATA_MASK, + .d_SI_CONFIG_I2C_LSB = SI_CONFIG_I2C_LSB, + .d_SI_CONFIG_I2C_MASK = SI_CONFIG_I2C_MASK, + .d_SI_CONFIG_POS_SAMPLE_LSB = SI_CONFIG_POS_SAMPLE_LSB, + .d_SI_CONFIG_POS_SAMPLE_MASK = SI_CONFIG_POS_SAMPLE_MASK, + .d_SI_CONFIG_INACTIVE_CLK_LSB = SI_CONFIG_INACTIVE_CLK_LSB, + .d_SI_CONFIG_INACTIVE_CLK_MASK = SI_CONFIG_INACTIVE_CLK_MASK, + .d_SI_CONFIG_INACTIVE_DATA_LSB = SI_CONFIG_INACTIVE_DATA_LSB, + .d_SI_CONFIG_INACTIVE_DATA_MASK = SI_CONFIG_INACTIVE_DATA_MASK, + .d_SI_CONFIG_DIVIDER_LSB = SI_CONFIG_DIVIDER_LSB, + .d_SI_CONFIG_DIVIDER_MASK = SI_CONFIG_DIVIDER_MASK, + .d_SI_BASE_ADDRESS = SI_BASE_ADDRESS, + .d_SI_CONFIG_OFFSET = SI_CONFIG_OFFSET, + .d_SI_TX_DATA0_OFFSET = SI_TX_DATA0_OFFSET, + .d_SI_TX_DATA1_OFFSET = SI_TX_DATA1_OFFSET, + .d_SI_RX_DATA0_OFFSET = SI_RX_DATA0_OFFSET, + .d_SI_RX_DATA1_OFFSET = SI_RX_DATA1_OFFSET, + .d_SI_CS_OFFSET = SI_CS_OFFSET, + .d_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK, + .d_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK, + .d_SI_CS_START_LSB = SI_CS_START_LSB, + .d_SI_CS_START_MASK = SI_CS_START_MASK, + .d_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB, + .d_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK, + .d_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB, + .d_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK, + .d_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ, + .d_BOARD_EXT_DATA_SZ = MY_TARGET_BOARD_EXT_DATA_SZ, + .d_MBOX_BASE_ADDRESS = MBOX_BASE_ADDRESS, + .d_LOCAL_SCRATCH_OFFSET = LOCAL_SCRATCH_OFFSET, + .d_CPU_CLOCK_OFFSET = CPU_CLOCK_OFFSET, + .d_GPIO_PIN10_OFFSET = GPIO_PIN10_OFFSET, + .d_GPIO_PIN11_OFFSET = GPIO_PIN11_OFFSET, + .d_GPIO_PIN12_OFFSET = GPIO_PIN12_OFFSET, + .d_GPIO_PIN13_OFFSET = GPIO_PIN13_OFFSET, + .d_CLOCK_GPIO_OFFSET = CLOCK_GPIO_OFFSET, + .d_CPU_CLOCK_STANDARD_LSB = CPU_CLOCK_STANDARD_LSB, + .d_CPU_CLOCK_STANDARD_MASK = CPU_CLOCK_STANDARD_MASK, + .d_LPO_CAL_ENABLE_LSB = LPO_CAL_ENABLE_LSB, + .d_LPO_CAL_ENABLE_MASK = LPO_CAL_ENABLE_MASK, + .d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = CLOCK_GPIO_BT_CLK_OUT_EN_LSB, + .d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK = CLOCK_GPIO_BT_CLK_OUT_EN_MASK, + .d_ANALOG_INTF_BASE_ADDRESS = ANALOG_INTF_BASE_ADDRESS, + .d_WLAN_MAC_BASE_ADDRESS = WLAN_MAC_BASE_ADDRESS, + .d_CE0_BASE_ADDRESS = CE0_BASE_ADDRESS, + .d_CE1_BASE_ADDRESS = CE1_BASE_ADDRESS, + .d_FW_INDICATOR_ADDRESS = FW_INDICATOR_ADDRESS, + .d_FW_CPU_PLL_CONFIG = FW_CPU_PLL_CONFIG, + .d_DRAM_BASE_ADDRESS = DRAM_BASE_ADDRESS, + .d_SOC_CORE_BASE_ADDRESS = SOC_CORE_BASE_ADDRESS, + .d_CORE_CTRL_ADDRESS = CORE_CTRL_ADDRESS, + .d_CE_COUNT = CE_COUNT, + .d_MSI_NUM_REQUEST = MSI_NUM_REQUEST, + .d_MSI_ASSIGN_FW = MSI_ASSIGN_FW, + .d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL, + .d_PCIE_INTR_ENABLE_ADDRESS = PCIE_INTR_ENABLE_ADDRESS, + .d_PCIE_INTR_CLR_ADDRESS = PCIE_INTR_CLR_ADDRESS, + .d_PCIE_INTR_FIRMWARE_MASK = PCIE_INTR_FIRMWARE_MASK, + .d_PCIE_INTR_CE_MASK_ALL = PCIE_INTR_CE_MASK_ALL, + .d_CORE_CTRL_CPU_INTR_MASK = CORE_CTRL_CPU_INTR_MASK, + .d_WIFICMN_PCIE_BAR_REG_ADDRESS = WIFICMN_PCIE_BAR_REG_ADDRESS, + /* htt_rx.c */ + /* htt tx */ + .d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK + = MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK, + .d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK + = MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK, + .d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK + = MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK, + .d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK + = MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK, + .d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB + = MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB, + .d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB + = MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB, + .d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB + = MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB, + .d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB + = MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB, + /* copy_engine.c */ + .d_DST_WR_INDEX_ADDRESS = DST_WR_INDEX_ADDRESS, + .d_SRC_WATERMARK_ADDRESS = SRC_WATERMARK_ADDRESS, + .d_SRC_WATERMARK_LOW_MASK = SRC_WATERMARK_LOW_MASK, + .d_SRC_WATERMARK_HIGH_MASK = SRC_WATERMARK_HIGH_MASK, + .d_DST_WATERMARK_LOW_MASK = DST_WATERMARK_LOW_MASK, + .d_DST_WATERMARK_HIGH_MASK = DST_WATERMARK_HIGH_MASK, + .d_CURRENT_SRRI_ADDRESS = CURRENT_SRRI_ADDRESS, + .d_CURRENT_DRRI_ADDRESS = CURRENT_DRRI_ADDRESS, + .d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK + = HOST_IS_SRC_RING_HIGH_WATERMARK_MASK, + .d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK + = HOST_IS_SRC_RING_LOW_WATERMARK_MASK, + .d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK + = HOST_IS_DST_RING_HIGH_WATERMARK_MASK, + .d_HOST_IS_DST_RING_LOW_WATERMARK_MASK + = HOST_IS_DST_RING_LOW_WATERMARK_MASK, + .d_HOST_IS_ADDRESS = HOST_IS_ADDRESS, + .d_HOST_IS_COPY_COMPLETE_MASK = HOST_IS_COPY_COMPLETE_MASK, + .d_CE_CMD_ADDRESS = CE_CMD_ADDRESS, + .d_CE_CMD_HALT_MASK = CE_CMD_HALT_MASK, + .d_CE_WRAPPER_BASE_ADDRESS = CE_WRAPPER_BASE_ADDRESS, + .d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS + = CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS, + .d_HOST_IE_ADDRESS = HOST_IE_ADDRESS, + .d_HOST_IE_COPY_COMPLETE_MASK = HOST_IE_COPY_COMPLETE_MASK, + .d_SR_BA_ADDRESS = SR_BA_ADDRESS, + .d_SR_SIZE_ADDRESS = SR_SIZE_ADDRESS, + .d_CE_CTRL1_ADDRESS = CE_CTRL1_ADDRESS, + .d_CE_CTRL1_DMAX_LENGTH_MASK = CE_CTRL1_DMAX_LENGTH_MASK, + .d_DR_BA_ADDRESS = DR_BA_ADDRESS, + .d_DR_SIZE_ADDRESS = DR_SIZE_ADDRESS, + .d_MISC_IE_ADDRESS = MISC_IE_ADDRESS, + .d_MISC_IS_AXI_ERR_MASK = MISC_IS_AXI_ERR_MASK, + .d_MISC_IS_DST_ADDR_ERR_MASK = MISC_IS_DST_ADDR_ERR_MASK, + .d_MISC_IS_SRC_LEN_ERR_MASK = MISC_IS_SRC_LEN_ERR_MASK, + .d_MISC_IS_DST_MAX_LEN_VIO_MASK = MISC_IS_DST_MAX_LEN_VIO_MASK, + .d_MISC_IS_DST_RING_OVERFLOW_MASK = MISC_IS_DST_RING_OVERFLOW_MASK, + .d_MISC_IS_SRC_RING_OVERFLOW_MASK = MISC_IS_SRC_RING_OVERFLOW_MASK, + .d_SRC_WATERMARK_LOW_LSB = SRC_WATERMARK_LOW_LSB, + .d_SRC_WATERMARK_HIGH_LSB = SRC_WATERMARK_HIGH_LSB, + .d_DST_WATERMARK_LOW_LSB = DST_WATERMARK_LOW_LSB, + .d_DST_WATERMARK_HIGH_LSB = DST_WATERMARK_HIGH_LSB, + .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK + = CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK, + .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB + = CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB, + .d_CE_CTRL1_DMAX_LENGTH_LSB = CE_CTRL1_DMAX_LENGTH_LSB, + .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK + = CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK, + .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK + = CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK, + .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB + = CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB, + .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB + = CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB, + .d_CE_CMD_HALT_STATUS_MASK = CE_CMD_HALT_STATUS_MASK, + .d_CE_CMD_HALT_STATUS_LSB = CE_CMD_HALT_STATUS_LSB, + .d_SR_WR_INDEX_ADDRESS = SR_WR_INDEX_ADDRESS, + .d_DST_WATERMARK_ADDRESS = DST_WATERMARK_ADDRESS, + .d_PCIE_INTR_CAUSE_ADDRESS = PCIE_INTR_CAUSE_ADDRESS, + .d_SOC_RESET_CONTROL_ADDRESS = SOC_RESET_CONTROL_ADDRESS, + .d_SOC_RESET_CONTROL_CE_RST_MASK = SOC_RESET_CONTROL_CE_RST_MASK, + .d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK + = SOC_RESET_CONTROL_CPU_WARM_RST_MASK, + .d_CPU_INTR_ADDRESS = CPU_INTR_ADDRESS, + .d_SOC_LF_TIMER_CONTROL0_ADDRESS = SOC_LF_TIMER_CONTROL0_ADDRESS, + .d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK + = SOC_LF_TIMER_CONTROL0_ENABLE_MASK, + .d_SI_CONFIG_ERR_INT_MASK = SI_CONFIG_ERR_INT_MASK, + .d_SI_CONFIG_ERR_INT_LSB = SI_CONFIG_ERR_INT_LSB, + .d_GPIO_ENABLE_W1TS_LOW_ADDRESS = GPIO_ENABLE_W1TS_LOW_ADDRESS, + .d_GPIO_PIN0_CONFIG_LSB = GPIO_PIN0_CONFIG_LSB, + .d_GPIO_PIN0_PAD_PULL_LSB = GPIO_PIN0_PAD_PULL_LSB, + .d_GPIO_PIN0_PAD_PULL_MASK = GPIO_PIN0_PAD_PULL_MASK, + .d_SOC_CHIP_ID_ADDRESS = SOC_CHIP_ID_ADDRESS, + .d_SOC_CHIP_ID_REVISION_MASK = SOC_CHIP_ID_REVISION_MASK, + .d_SOC_CHIP_ID_REVISION_LSB = SOC_CHIP_ID_REVISION_LSB, + .d_SOC_CHIP_ID_REVISION_MSB = SOC_CHIP_ID_REVISION_MSB, + .d_WIFICMN_PCIE_BAR_REG_ADDRESS = WIFICMN_PCIE_BAR_REG_ADDRESS, + .d_FW_AXI_MSI_ADDR = FW_AXI_MSI_ADDR, + .d_FW_AXI_MSI_DATA = FW_AXI_MSI_DATA, + .d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS = WLAN_SUBSYSTEM_CORE_ID_ADDRESS, + .d_FPGA_VERSION_ADDRESS = FPGA_VERSION_ADDRESS, + .d_WIFICMN_INT_STATUS_ADDRESS = WIFICMN_INT_STATUS_ADDRESS, +}; + +struct targetdef_s *MY_TARGET_DEF = &my_target_def; +#else +#endif + +#if defined(MY_CEREG_DEF) + +#if !defined(CE_DDR_ADDRESS_FOR_RRI_LOW) +#define CE_DDR_ADDRESS_FOR_RRI_LOW ATH_UNSUPPORTED_REG_OFFSET +#endif +#if !defined(CE_DDR_ADDRESS_FOR_RRI_HIGH) +#define CE_DDR_ADDRESS_FOR_RRI_HIGH ATH_UNSUPPORTED_REG_OFFSET +#endif +#if !defined(SR_BA_ADDRESS_HIGH) +#define SR_BA_ADDRESS_HIGH ATH_UNSUPPORTED_REG_OFFSET +#endif +#if !defined(DR_BA_ADDRESS_HIGH) +#define DR_BA_ADDRESS_HIGH ATH_UNSUPPORTED_REG_OFFSET +#endif +#if !defined(CE_CMD_REGISTER) +#define CE_CMD_REGISTER ATH_UNSUPPORTED_REG_OFFSET +#endif +#if !defined(CE_MSI_ADDRESS) +#define CE_MSI_ADDRESS ATH_UNSUPPORTED_REG_OFFSET +#endif +#if !defined(CE_MSI_ADDRESS_HIGH) +#define CE_MSI_ADDRESS_HIGH ATH_UNSUPPORTED_REG_OFFSET +#endif +#if !defined(CE_MSI_DATA) +#define CE_MSI_DATA ATH_UNSUPPORTED_REG_OFFSET +#endif +#if !defined(CE_MSI_ENABLE_BIT) +#define CE_MSI_ENABLE_BIT ATH_UNSUPPORTED_REG_OFFSET +#endif +#if !defined(CE_CTRL1_IDX_UPD_EN_MASK) +#define CE_CTRL1_IDX_UPD_EN_MASK ATH_UNSUPPORTED_REG_OFFSET +#endif +#if !defined(CE_WRAPPER_DEBUG_OFFSET) +#define CE_WRAPPER_DEBUG_OFFSET ATH_UNSUPPORTED_REG_OFFSET +#endif +#if !defined(CE_DEBUG_OFFSET) +#define CE_DEBUG_OFFSET ATH_UNSUPPORTED_REG_OFFSET +#endif +#if !defined(A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES) +#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES ATH_UNSUPPORTED_REG_OFFSET +#endif +#if !defined(A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS) +#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS ATH_UNSUPPORTED_REG_OFFSET +#endif + +static struct ce_reg_def my_ce_reg_def = { + /* copy_engine.c */ + .d_DST_WR_INDEX_ADDRESS = DST_WR_INDEX_ADDRESS, + .d_SRC_WATERMARK_ADDRESS = SRC_WATERMARK_ADDRESS, + .d_SRC_WATERMARK_LOW_MASK = SRC_WATERMARK_LOW_MASK, + .d_SRC_WATERMARK_HIGH_MASK = SRC_WATERMARK_HIGH_MASK, + .d_DST_WATERMARK_LOW_MASK = DST_WATERMARK_LOW_MASK, + .d_DST_WATERMARK_HIGH_MASK = DST_WATERMARK_HIGH_MASK, + .d_CURRENT_SRRI_ADDRESS = CURRENT_SRRI_ADDRESS, + .d_CURRENT_DRRI_ADDRESS = CURRENT_DRRI_ADDRESS, + .d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK + = HOST_IS_SRC_RING_HIGH_WATERMARK_MASK, + .d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK + = HOST_IS_SRC_RING_LOW_WATERMARK_MASK, + .d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK + = HOST_IS_DST_RING_HIGH_WATERMARK_MASK, + .d_HOST_IS_DST_RING_LOW_WATERMARK_MASK + = HOST_IS_DST_RING_LOW_WATERMARK_MASK, + .d_HOST_IS_ADDRESS = HOST_IS_ADDRESS, + .d_MISC_IS_ADDRESS = MISC_IS_ADDRESS, + .d_HOST_IS_COPY_COMPLETE_MASK = HOST_IS_COPY_COMPLETE_MASK, + .d_CE_WRAPPER_BASE_ADDRESS = CE_WRAPPER_BASE_ADDRESS, + .d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS + = CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS, + .d_CE_DDR_ADDRESS_FOR_RRI_LOW = CE_DDR_ADDRESS_FOR_RRI_LOW, + .d_CE_DDR_ADDRESS_FOR_RRI_HIGH = CE_DDR_ADDRESS_FOR_RRI_HIGH, + .d_HOST_IE_ADDRESS = HOST_IE_ADDRESS, + .d_HOST_IE_COPY_COMPLETE_MASK = HOST_IE_COPY_COMPLETE_MASK, + .d_SR_BA_ADDRESS = SR_BA_ADDRESS, + .d_SR_BA_ADDRESS_HIGH = SR_BA_ADDRESS_HIGH, + .d_SR_SIZE_ADDRESS = SR_SIZE_ADDRESS, + .d_CE_CTRL1_ADDRESS = CE_CTRL1_ADDRESS, + .d_CE_CTRL1_DMAX_LENGTH_MASK = CE_CTRL1_DMAX_LENGTH_MASK, + .d_DR_BA_ADDRESS = DR_BA_ADDRESS, + .d_DR_BA_ADDRESS_HIGH = DR_BA_ADDRESS_HIGH, + .d_DR_SIZE_ADDRESS = DR_SIZE_ADDRESS, + .d_CE_CMD_REGISTER = CE_CMD_REGISTER, + .d_CE_MSI_ADDRESS = CE_MSI_ADDRESS, + .d_CE_MSI_ADDRESS_HIGH = CE_MSI_ADDRESS_HIGH, + .d_CE_MSI_DATA = CE_MSI_DATA, + .d_CE_MSI_ENABLE_BIT = CE_MSI_ENABLE_BIT, + .d_MISC_IE_ADDRESS = MISC_IE_ADDRESS, + .d_MISC_IS_AXI_ERR_MASK = MISC_IS_AXI_ERR_MASK, + .d_MISC_IS_DST_ADDR_ERR_MASK = MISC_IS_DST_ADDR_ERR_MASK, + .d_MISC_IS_SRC_LEN_ERR_MASK = MISC_IS_SRC_LEN_ERR_MASK, + .d_MISC_IS_DST_MAX_LEN_VIO_MASK = MISC_IS_DST_MAX_LEN_VIO_MASK, + .d_MISC_IS_DST_RING_OVERFLOW_MASK = MISC_IS_DST_RING_OVERFLOW_MASK, + .d_MISC_IS_SRC_RING_OVERFLOW_MASK = MISC_IS_SRC_RING_OVERFLOW_MASK, + .d_SRC_WATERMARK_LOW_LSB = SRC_WATERMARK_LOW_LSB, + .d_SRC_WATERMARK_HIGH_LSB = SRC_WATERMARK_HIGH_LSB, + .d_DST_WATERMARK_LOW_LSB = DST_WATERMARK_LOW_LSB, + .d_DST_WATERMARK_HIGH_LSB = DST_WATERMARK_HIGH_LSB, + .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK + = CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK, + .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB + = CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB, + .d_CE_CTRL1_DMAX_LENGTH_LSB = CE_CTRL1_DMAX_LENGTH_LSB, + .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK + = CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK, + .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK + = CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK, + .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB + = CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB, + .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB + = CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB, + .d_CE_CTRL1_IDX_UPD_EN_MASK = CE_CTRL1_IDX_UPD_EN_MASK, + .d_CE_WRAPPER_DEBUG_OFFSET = CE_WRAPPER_DEBUG_OFFSET, + .d_CE_WRAPPER_DEBUG_SEL_MSB = CE_WRAPPER_DEBUG_SEL_MSB, + .d_CE_WRAPPER_DEBUG_SEL_LSB = CE_WRAPPER_DEBUG_SEL_LSB, + .d_CE_WRAPPER_DEBUG_SEL_MASK = CE_WRAPPER_DEBUG_SEL_MASK, + .d_CE_DEBUG_OFFSET = CE_DEBUG_OFFSET, + .d_CE_DEBUG_SEL_MSB = CE_DEBUG_SEL_MSB, + .d_CE_DEBUG_SEL_LSB = CE_DEBUG_SEL_LSB, + .d_CE_DEBUG_SEL_MASK = CE_DEBUG_SEL_MASK, + .d_CE0_BASE_ADDRESS = CE0_BASE_ADDRESS, + .d_CE1_BASE_ADDRESS = CE1_BASE_ADDRESS, + .d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES + = A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES, + .d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS + = A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS +}; + +struct ce_reg_def *MY_CEREG_DEF = &my_ce_reg_def; + +#else +#endif +#endif diff --git a/hif/inc/targetdef.h b/hif/inc/targetdef.h new file mode 100644 index 0000000000..0c99e0fe6f --- /dev/null +++ b/hif/inc/targetdef.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef TARGETDEFS_H_ +#define TARGETDEFS_H_ + +#include +#include +#include +#include "target_reg_init.h" + +extern struct targetdef_s *AR6002_TARGETdef; +extern struct targetdef_s *AR6003_TARGETdef; +extern struct targetdef_s *AR6004_TARGETdef; +extern struct targetdef_s *AR9888_TARGETdef; +extern struct targetdef_s *AR9888V2_TARGETdef; +extern struct targetdef_s *AR6320_TARGETdef; +extern struct targetdef_s *AR900B_TARGETdef; +extern struct targetdef_s *QCA9984_TARGETdef; +extern struct targetdef_s *QCA9888_TARGETdef; +#ifdef ATH_AHB +extern struct targetdef_s *IPQ4019_TARGETdef; +#endif + +extern struct ce_reg_def *AR6002_CE_TARGETdef; +extern struct ce_reg_def *AR6003_CE_TARGETdef; +extern struct ce_reg_def *AR6004_CE_TARGETdef; +extern struct ce_reg_def *AR9888_CE_TARGETdef; +extern struct ce_reg_def *AR9888V2_CE_TARGETdef; +extern struct ce_reg_def *AR6320_CE_TARGETdef; +extern struct ce_reg_def *AR900B_CE_TARGETdef; +extern struct ce_reg_def *QCA9984_CE_TARGETdef; +extern struct ce_reg_def *QCA9888_CE_TARGETdef; +#ifdef ATH_AHB +extern struct ce_reg_def *IPQ4019_CE_TARGETdef; +#endif + + +#endif diff --git a/hif/src/ar6004def.c b/hif/src/ar6004def.c new file mode 100644 index 0000000000..88bdcc5df2 --- /dev/null +++ b/hif/src/ar6004def.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2013,2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#if defined(AR6004_HEADERS_DEF) +#define AR6004 1 + +#define WLAN_HEADERS 1 +#include "common_drv.h" +#include "AR6004/hw/apb_map.h" +#include "AR6004/hw/gpio_reg.h" +#include "AR6004/hw/rtc_reg.h" +#include "AR6004/hw/si_reg.h" +#include "AR6004/hw/mbox_reg.h" +#include "AR6004/hw/mbox_wlan_host_reg.h" + +#define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET +#define SCRATCH_BASE_ADDRESS MBOX_BASE_ADDRESS + +#define MY_TARGET_DEF AR6004_TARGETdef +#define MY_HOST_DEF AR6004_HOSTdef +#define MY_CEREG_DEF AR6004_CE_TARGETdef +#define MY_TARGET_BOARD_DATA_SZ AR6004_BOARD_DATA_SZ +#define MY_TARGET_BOARD_EXT_DATA_SZ AR6004_BOARD_EXT_DATA_SZ +#include "targetdef.h" +#include "hostdef.h" +#else +#include "common_drv.h" +#include "targetdef.h" +#include "hostdef.h" +struct targetdef_s *AR6004_TARGETdef; +struct hostdef_s *AR6004_HOSTdef; +#endif /*AR6004_HEADERS_DEF */ diff --git a/hif/src/ar6320def.c b/hif/src/ar6320def.c new file mode 100644 index 0000000000..5440ecdecd --- /dev/null +++ b/hif/src/ar6320def.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2013,2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#if defined(AR6320_HEADERS_DEF) +#define AR6320 1 + +#define WLAN_HEADERS 1 +#include "common_drv.h" +#include "AR6320/hw/apb_map.h" +#include "AR6320/hw/gpio_reg.h" +#include "AR6320/hw/rtc_reg.h" +#include "AR6320/extra/hw/si_reg.h" +#include "AR6320/hw/mbox_reg.h" +#include "AR6320/extra/hw/ce_reg_csr.h" +#include "AR6320/hw/mbox_wlan_host_reg.h" +#include "soc_addrs.h" +#include "AR6320/extra/hw/soc_core_reg.h" +#include "AR6320/hw/pcie_local_reg.h" +#include "AR6320/hw/soc_pcie_reg.h" + +#ifndef SYSTEM_SLEEP_OFFSET +#define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET +#endif +#ifndef WLAN_SYSTEM_SLEEP_OFFSET +#define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET +#endif +#ifndef WLAN_RESET_CONTROL_OFFSET +#define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET +#endif +#ifndef RESET_CONTROL_SI0_RST_MASK +#define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK +#endif +#ifndef SI_BASE_ADDRESS +#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS +#endif +#ifndef PCIE_LOCAL_BASE_ADDRESS +/* TBDXXX: Eventually, this Base Address will be defined in HW header files */ +#define PCIE_LOCAL_BASE_ADDRESS 0x80000 +#endif +#ifndef RTC_STATE_V_ON +#define RTC_STATE_V_ON 3 +#endif + +#define MY_TARGET_DEF AR6320_TARGETdef +#define MY_HOST_DEF AR6320_HOSTdef +#define MY_CEREG_DEF AR6320_CE_TARGETdef +#define MY_TARGET_BOARD_DATA_SZ AR6320_BOARD_DATA_SZ +#define MY_TARGET_BOARD_EXT_DATA_SZ AR6320_BOARD_EXT_DATA_SZ +#define DRAM_BASE_ADDRESS TARG_DRAM_START +#include "targetdef.h" +#include "hostdef.h" +#else +#include "common_drv.h" +#include "targetdef.h" +#include "hostdef.h" +struct targetdef_s *AR6320_TARGETdef; +struct hostdef_s *AR6320_HOSTdef; +#endif /* AR6320_HEADERS_DEF */ diff --git a/hif/src/ar900Bdef.c b/hif/src/ar900Bdef.c new file mode 100644 index 0000000000..b5b65f7da9 --- /dev/null +++ b/hif/src/ar900Bdef.c @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2010,2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#if defined(AR900B_HEADERS_DEF) +#define AR900B 1 + +#define WLAN_HEADERS 1 +#include "common_drv.h" +#include "AR900B/soc_addrs.h" +#include "AR900B/extra/hw/apb_map.h" +#include "AR900B/hw/gpio_athr_wlan_reg.h" +#ifdef WLAN_HEADERS +#include "AR900B/extra/hw/wifi_top_reg_map.h" +#include "AR900B/hw/rtc_soc_reg.h" +#endif +#include "AR900B/hw/si_reg.h" +#include "AR900B/extra/hw/pcie_local_reg.h" +#include "AR900B/hw/ce_wrapper_reg_csr.h" +#if 0 +#include "hw/soc_core_reg.h" +#include "hw/soc_pcie_reg.h" +#include "hw/ce_reg_csr.h" +#endif + +#include "AR900B/extra/hw/soc_core_reg.h" +#include "AR900B/hw/soc_pcie_reg.h" +#include "AR900B/extra/hw/ce_reg_csr.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Base address is defined in pcie_local_reg.h. Macros which access the + * registers include the base address in their definition. + */ +#define PCIE_LOCAL_BASE_ADDRESS 0 + +#define FW_EVENT_PENDING_ADDRESS (WIFICMN_SCRATCH_3_ADDRESS) +#define DRAM_BASE_ADDRESS TARG_DRAM_START + +/* Backwards compatibility -- TBDXXX */ + +#define MISSING 0 + +#define WLAN_SYSTEM_SLEEP_DISABLE_LSB WIFI_SYSTEM_SLEEP_DISABLE_LSB +#define WLAN_SYSTEM_SLEEP_DISABLE_MASK WIFI_SYSTEM_SLEEP_DISABLE_MASK +#define WLAN_RESET_CONTROL_COLD_RST_MASK WIFI_RESET_CONTROL_MAC_COLD_RST_MASK +#define WLAN_RESET_CONTROL_WARM_RST_MASK WIFI_RESET_CONTROL_MAC_WARM_RST_MASK +#define SOC_CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_ADDRESS +#define SOC_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_ADDRESS +#define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_ADDRESS +#define SOC_LPO_CAL_OFFSET SOC_LPO_CAL_ADDRESS +#define SOC_RESET_CONTROL_CE_RST_MASK WIFI_RESET_CONTROL_CE_RESET_MASK +#define WLAN_SYSTEM_SLEEP_OFFSET WIFI_SYSTEM_SLEEP_ADDRESS +#define WLAN_RESET_CONTROL_OFFSET WIFI_RESET_CONTROL_ADDRESS +#define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET +#define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK +#define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK +#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS +#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS +#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS +#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK +#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK +#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS +#define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS +#define LOCAL_SCRATCH_OFFSET 0x18 +#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS +#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS +#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS +#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS +#define SI_CONFIG_OFFSET SI_CONFIG_ADDRESS +#define SI_TX_DATA0_OFFSET SI_TX_DATA0_ADDRESS +#define SI_TX_DATA1_OFFSET SI_TX_DATA1_ADDRESS +#define SI_RX_DATA0_OFFSET SI_RX_DATA0_ADDRESS +#define SI_RX_DATA1_OFFSET SI_RX_DATA1_ADDRESS +#define SI_CS_OFFSET SI_CS_ADDRESS +#define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB +#define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK +#define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB +#define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK +#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS +#define MBOX_BASE_ADDRESS MISSING +#define INT_STATUS_ENABLE_ERROR_LSB MISSING +#define INT_STATUS_ENABLE_ERROR_MASK MISSING +#define INT_STATUS_ENABLE_CPU_LSB MISSING +#define INT_STATUS_ENABLE_CPU_MASK MISSING +#define INT_STATUS_ENABLE_COUNTER_LSB MISSING +#define INT_STATUS_ENABLE_COUNTER_MASK MISSING +#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING +#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING +#define INT_STATUS_ENABLE_ADDRESS MISSING +#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING +#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING +#define HOST_INT_STATUS_ADDRESS MISSING +#define CPU_INT_STATUS_ADDRESS MISSING +#define ERROR_INT_STATUS_ADDRESS MISSING +#define ERROR_INT_STATUS_WAKEUP_MASK MISSING +#define ERROR_INT_STATUS_WAKEUP_LSB MISSING +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING +#define COUNT_DEC_ADDRESS MISSING +#define HOST_INT_STATUS_CPU_MASK MISSING +#define HOST_INT_STATUS_CPU_LSB MISSING +#define HOST_INT_STATUS_ERROR_MASK MISSING +#define HOST_INT_STATUS_ERROR_LSB MISSING +#define HOST_INT_STATUS_COUNTER_MASK MISSING +#define HOST_INT_STATUS_COUNTER_LSB MISSING +#define RX_LOOKAHEAD_VALID_ADDRESS MISSING +#define WINDOW_DATA_ADDRESS MISSING +#define WINDOW_READ_ADDR_ADDRESS MISSING +#define WINDOW_WRITE_ADDR_ADDRESS MISSING +/* MAC Descriptor */ +#define RX_PPDU_END_ANTENNA_OFFSET_DWORD (RX_PPDU_END_25_RX_ANTENNA_OFFSET >> 2) +/* GPIO Register */ +#define GPIO_ENABLE_W1TS_LOW_ADDRESS WLAN_GPIO_ENABLE_W1TS_LOW_ADDRESS +#define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB +#define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB +#define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK +/* CE descriptor */ +#define CE_SRC_DESC_SIZE_DWORD 2 +#define CE_DEST_DESC_SIZE_DWORD 2 +#define CE_SRC_DESC_SRC_PTR_OFFSET_DWORD 0 +#define CE_SRC_DESC_INFO_OFFSET_DWORD 1 +#define CE_DEST_DESC_DEST_PTR_OFFSET_DWORD 0 +#define CE_DEST_DESC_INFO_OFFSET_DWORD 1 +#if _BYTE_ORDER == _BIG_ENDIAN +#define CE_SRC_DESC_INFO_NBYTES_MASK 0xFFFF0000 +#define CE_SRC_DESC_INFO_NBYTES_SHIFT 16 +#define CE_SRC_DESC_INFO_GATHER_MASK 0x00008000 +#define CE_SRC_DESC_INFO_GATHER_SHIFT 15 +#define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00004000 +#define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 14 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK 0x00002000 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT 13 +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00001000 +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12 +#define CE_SRC_DESC_INFO_META_DATA_MASK 0x00000FFF +#define CE_SRC_DESC_INFO_META_DATA_SHIFT 0 +#else +#define CE_SRC_DESC_INFO_NBYTES_MASK 0x0000FFFF +#define CE_SRC_DESC_INFO_NBYTES_SHIFT 0 +#define CE_SRC_DESC_INFO_GATHER_MASK 0x00010000 +#define CE_SRC_DESC_INFO_GATHER_SHIFT 16 +#define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00020000 +#define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 17 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK 0x00040000 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT 18 +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00080000 +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19 +#define CE_SRC_DESC_INFO_META_DATA_MASK 0xFFF00000 +#define CE_SRC_DESC_INFO_META_DATA_SHIFT 20 +#endif +#if _BYTE_ORDER == _BIG_ENDIAN +#define CE_DEST_DESC_INFO_NBYTES_MASK 0xFFFF0000 +#define CE_DEST_DESC_INFO_NBYTES_SHIFT 16 +#define CE_DEST_DESC_INFO_GATHER_MASK 0x00008000 +#define CE_DEST_DESC_INFO_GATHER_SHIFT 15 +#define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00004000 +#define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 14 +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK 0x00002000 +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT 13 +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00001000 +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12 +#define CE_DEST_DESC_INFO_META_DATA_MASK 0x00000FFF +#define CE_DEST_DESC_INFO_META_DATA_SHIFT 0 +#else +#define CE_DEST_DESC_INFO_NBYTES_MASK 0x0000FFFF +#define CE_DEST_DESC_INFO_NBYTES_SHIFT 0 +#define CE_DEST_DESC_INFO_GATHER_MASK 0x00010000 +#define CE_DEST_DESC_INFO_GATHER_SHIFT 16 +#define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00020000 +#define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 17 +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK 0x00040000 +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT 18 +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00080000 +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19 +#define CE_DEST_DESC_INFO_META_DATA_MASK 0xFFF00000 +#define CE_DEST_DESC_INFO_META_DATA_SHIFT 20 +#endif + +#define MY_TARGET_DEF AR900B_TARGETdef +#define MY_HOST_DEF AR900B_HOSTdef +#define MY_CEREG_DEF AR900B_CE_TARGETdef +#define MY_TARGET_BOARD_DATA_SZ AR900B_BOARD_DATA_SZ +#define MY_TARGET_BOARD_EXT_DATA_SZ AR900B_BOARD_EXT_DATA_SZ +#include "targetdef.h" +#include "hostdef.h" +#else +#include "common_drv.h" +#include "targetdef.h" +#include "hostdef.h" +struct targetdef_s *AR900B_TARGETdef; +struct hostdef_s *AR900B_HOSTdef; +#endif /*AR900B_HEADERS_DEF */ diff --git a/hif/src/ar9888def.c b/hif/src/ar9888def.c new file mode 100644 index 0000000000..7336c52f17 --- /dev/null +++ b/hif/src/ar9888def.c @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2013,2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#if defined(AR9888_HEADERS_DEF) +#define AR9888 1 + +#define WLAN_HEADERS 1 +#include "common_drv.h" +#include "AR9888/v2/soc_addrs.h" +#include "AR9888/v2/hw/apb_athr_wlan_map.h" +#include "AR9888/v2/hw/gpio_athr_wlan_reg.h" +#include "AR9888/v2/hw/rtc_soc_reg.h" +#include "AR9888/v2/hw/rtc_wlan_reg.h" +#include "AR9888/v2/hw/si_reg.h" +#include "AR9888/v2/extra/hw/pcie_local_reg.h" + +#include "AR9888/v2/extra/hw/soc_core_reg.h" +#include "AR9888/v2/hw/soc_pcie_reg.h" +#include "AR9888/v2/extra/hw/ce_reg_csr.h" +#include "AR9888/v2/hw/ce_wrapper_reg_csr.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +/* TBDXXX: Eventually, this Base Address will be defined in HW header files */ +#define PCIE_LOCAL_BASE_ADDRESS 0x80000 + +#define FW_EVENT_PENDING_ADDRESS (SOC_CORE_BASE_ADDRESS+SCRATCH_3_ADDRESS) +#define DRAM_BASE_ADDRESS TARG_DRAM_START + +/* Backwards compatibility -- TBDXXX */ + +#define MISSING 0 + +#define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET +#define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET +#define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET +#define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET +#define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK +#define RESET_CONTROL_MBOX_RST_MASK MISSING +#define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK +#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS +#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS +#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS +#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK +#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK +#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS +#define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS +#define LOCAL_SCRATCH_OFFSET 0x18 +#define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET +#define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET +#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS +#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS +#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS +#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS +#define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB +#define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK +#define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB +#define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK +#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS +#define MBOX_BASE_ADDRESS MISSING +#define INT_STATUS_ENABLE_ERROR_LSB MISSING +#define INT_STATUS_ENABLE_ERROR_MASK MISSING +#define INT_STATUS_ENABLE_CPU_LSB MISSING +#define INT_STATUS_ENABLE_CPU_MASK MISSING +#define INT_STATUS_ENABLE_COUNTER_LSB MISSING +#define INT_STATUS_ENABLE_COUNTER_MASK MISSING +#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING +#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING +#define INT_STATUS_ENABLE_ADDRESS MISSING +#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING +#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING +#define HOST_INT_STATUS_ADDRESS MISSING +#define CPU_INT_STATUS_ADDRESS MISSING +#define ERROR_INT_STATUS_ADDRESS MISSING +#define ERROR_INT_STATUS_WAKEUP_MASK MISSING +#define ERROR_INT_STATUS_WAKEUP_LSB MISSING +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING +#define COUNT_DEC_ADDRESS MISSING +#define HOST_INT_STATUS_CPU_MASK MISSING +#define HOST_INT_STATUS_CPU_LSB MISSING +#define HOST_INT_STATUS_ERROR_MASK MISSING +#define HOST_INT_STATUS_ERROR_LSB MISSING +#define HOST_INT_STATUS_COUNTER_MASK MISSING +#define HOST_INT_STATUS_COUNTER_LSB MISSING +#define RX_LOOKAHEAD_VALID_ADDRESS MISSING +#define WINDOW_DATA_ADDRESS MISSING +#define WINDOW_READ_ADDR_ADDRESS MISSING +#define WINDOW_WRITE_ADDR_ADDRESS MISSING +/* MAC descriptor */ +#define RX_ATTENTION_0_PHY_DATA_TYPE_MASK MISSING +#define RX_MSDU_END_8_LRO_ELIGIBLE_MASK MISSING +#define RX_MSDU_END_8_LRO_ELIGIBLE_LSB MISSING +#define RX_MSDU_END_8_L3_HEADER_PADDING_LSB MISSING +#define RX_MSDU_END_8_L3_HEADER_PADDING_MASK MISSING +#define RX_PPDU_END_ANTENNA_OFFSET_DWORD (RX_PPDU_END_19_RX_ANTENNA_OFFSET >> 2) +#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING +#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING +#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING +#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING +#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB MISSING +#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB MISSING +#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB MISSING +#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB MISSING +/* GPIO Register */ + +#define GPIO_ENABLE_W1TS_LOW_ADDRESS WLAN_GPIO_ENABLE_W1TS_LOW_ADDRESS +#define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB +#define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB +#define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK +/* CE descriptor */ +#define CE_SRC_DESC_SIZE_DWORD 2 +#define CE_DEST_DESC_SIZE_DWORD 2 +#define CE_SRC_DESC_SRC_PTR_OFFSET_DWORD 0 +#define CE_SRC_DESC_INFO_OFFSET_DWORD 1 +#define CE_DEST_DESC_DEST_PTR_OFFSET_DWORD 0 +#define CE_DEST_DESC_INFO_OFFSET_DWORD 1 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK MISSING +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT MISSING +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK MISSING +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT MISSING +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK MISSING +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT MISSING +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK MISSING +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT MISSING +#if _BYTE_ORDER == _BIG_ENDIAN +#define CE_SRC_DESC_INFO_NBYTES_MASK 0xFFFF0000 +#define CE_SRC_DESC_INFO_NBYTES_SHIFT 16 +#define CE_SRC_DESC_INFO_GATHER_MASK 0x00008000 +#define CE_SRC_DESC_INFO_GATHER_SHIFT 15 +#define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00004000 +#define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 14 +#define CE_SRC_DESC_INFO_META_DATA_MASK 0x00003FFF +#define CE_SRC_DESC_INFO_META_DATA_SHIFT 0 +#else +#define CE_SRC_DESC_INFO_NBYTES_MASK 0x0000FFFF +#define CE_SRC_DESC_INFO_NBYTES_SHIFT 0 +#define CE_SRC_DESC_INFO_GATHER_MASK 0x00010000 +#define CE_SRC_DESC_INFO_GATHER_SHIFT 16 +#define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00020000 +#define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 17 +#define CE_SRC_DESC_INFO_META_DATA_MASK 0xFFFC0000 +#define CE_SRC_DESC_INFO_META_DATA_SHIFT 18 +#endif +#if _BYTE_ORDER == _BIG_ENDIAN +#define CE_DEST_DESC_INFO_NBYTES_MASK 0xFFFF0000 +#define CE_DEST_DESC_INFO_NBYTES_SHIFT 16 +#define CE_DEST_DESC_INFO_GATHER_MASK 0x00008000 +#define CE_DEST_DESC_INFO_GATHER_SHIFT 15 +#define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00004000 +#define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 14 +#define CE_DEST_DESC_INFO_META_DATA_MASK 0x00003FFF +#define CE_DEST_DESC_INFO_META_DATA_SHIFT 0 +#else +#define CE_DEST_DESC_INFO_NBYTES_MASK 0x0000FFFF +#define CE_DEST_DESC_INFO_NBYTES_SHIFT 0 +#define CE_DEST_DESC_INFO_GATHER_MASK 0x00010000 +#define CE_DEST_DESC_INFO_GATHER_SHIFT 16 +#define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00020000 +#define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 17 +#define CE_DEST_DESC_INFO_META_DATA_MASK 0xFFFC0000 +#define CE_DEST_DESC_INFO_META_DATA_SHIFT 18 +#endif + +#define MY_TARGET_DEF AR9888_TARGETdef +#define MY_HOST_DEF AR9888_HOSTdef +#define MY_CEREG_DEF AR9888_CE_TARGETdef +#define MY_TARGET_BOARD_DATA_SZ AR9888_BOARD_DATA_SZ +#define MY_TARGET_BOARD_EXT_DATA_SZ AR9888_BOARD_EXT_DATA_SZ +#include "targetdef.h" +#include "hostdef.h" +#else +#include "common_drv.h" +#include "targetdef.h" +#include "hostdef.h" +struct targetdef_s *AR9888_TARGETdef; +struct hostdef_s *AR9888_HOSTdef; +#endif /*AR9888_HEADERS_DEF */ diff --git a/hif/src/ipq4019def.c b/hif/src/ipq4019def.c new file mode 100644 index 0000000000..ef0e281c1d --- /dev/null +++ b/hif/src/ipq4019def.c @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#if defined(IPQ4019_HEADERS_DEF) +#define AR900B 1 + +#define WLAN_HEADERS 1 +#include "common_drv.h" +#include "IPQ4019/soc_addrs.h" +#include "IPQ4019/extra/hw/apb_map.h" +#ifdef WLAN_HEADERS +#include "IPQ4019/extra/hw/wifi_top_reg_map.h" +#include "IPQ4019/hw/rtc_soc_reg.h" +#endif +#include "IPQ4019/hw/ce_wrapper_reg_csr.h" + +#include "IPQ4019/extra/hw/soc_core_reg.h" +#include "IPQ4019/extra/hw/ce_reg_csr.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Base address is defined in pcie_local_reg.h. Macros which access the + * registers include the base address in their definition. + */ + +#define FW_EVENT_PENDING_ADDRESS (WIFICMN_SCRATCH_3_ADDRESS) +#define DRAM_BASE_ADDRESS TARG_DRAM_START + +/* Backwards compatibility -- TBDXXX */ + +#define MISSING 0 + +#define WLAN_SYSTEM_SLEEP_DISABLE_LSB WIFI_SYSTEM_SLEEP_DISABLE_LSB +#define WLAN_SYSTEM_SLEEP_DISABLE_MASK WIFI_SYSTEM_SLEEP_DISABLE_MASK +#define WLAN_RESET_CONTROL_COLD_RST_MASK WIFI_RESET_CONTROL_MAC_COLD_RST_MASK +#define WLAN_RESET_CONTROL_WARM_RST_MASK WIFI_RESET_CONTROL_MAC_WARM_RST_MASK +#define SOC_CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_ADDRESS +#define SOC_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_ADDRESS +#define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_ADDRESS +#define SOC_LPO_CAL_OFFSET SOC_LPO_CAL_ADDRESS +#define SOC_RESET_CONTROL_CE_RST_MASK WIFI_RESET_CONTROL_CE_RESET_MASK +#define WLAN_SYSTEM_SLEEP_OFFSET WIFI_SYSTEM_SLEEP_ADDRESS +#define WLAN_RESET_CONTROL_OFFSET WIFI_RESET_CONTROL_ADDRESS +#define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET +#define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK +#define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK +#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS +#define GPIO_PIN0_OFFSET MISSING +#define GPIO_PIN1_OFFSET MISSING +#define GPIO_PIN0_CONFIG_MASK MISSING +#define GPIO_PIN1_CONFIG_MASK MISSING +#define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS +#define LOCAL_SCRATCH_OFFSET 0x18 +#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS +#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS +#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS +#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS +/*TBD:dakota Check if these can be removed for dakota */ +#define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB +#define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK +#define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB +#define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK +#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS +#define MBOX_BASE_ADDRESS MISSING +#define INT_STATUS_ENABLE_ERROR_LSB MISSING +#define INT_STATUS_ENABLE_ERROR_MASK MISSING +#define INT_STATUS_ENABLE_CPU_LSB MISSING +#define INT_STATUS_ENABLE_CPU_MASK MISSING +#define INT_STATUS_ENABLE_COUNTER_LSB MISSING +#define INT_STATUS_ENABLE_COUNTER_MASK MISSING +#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING +#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING +#define INT_STATUS_ENABLE_ADDRESS MISSING +#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING +#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING +#define HOST_INT_STATUS_ADDRESS MISSING +#define CPU_INT_STATUS_ADDRESS MISSING +#define ERROR_INT_STATUS_ADDRESS MISSING +#define ERROR_INT_STATUS_WAKEUP_MASK MISSING +#define ERROR_INT_STATUS_WAKEUP_LSB MISSING +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING +#define COUNT_DEC_ADDRESS MISSING +#define HOST_INT_STATUS_CPU_MASK MISSING +#define HOST_INT_STATUS_CPU_LSB MISSING +#define HOST_INT_STATUS_ERROR_MASK MISSING +#define HOST_INT_STATUS_ERROR_LSB MISSING +#define HOST_INT_STATUS_COUNTER_MASK MISSING +#define HOST_INT_STATUS_COUNTER_LSB MISSING +#define RX_LOOKAHEAD_VALID_ADDRESS MISSING +#define WINDOW_DATA_ADDRESS MISSING +#define WINDOW_READ_ADDR_ADDRESS MISSING +#define WINDOW_WRITE_ADDR_ADDRESS MISSING +/* MAC Descriptor */ +#define RX_PPDU_END_ANTENNA_OFFSET_DWORD (RX_PPDU_END_25_RX_ANTENNA_OFFSET >> 2) +/* GPIO Register */ +#define GPIO_ENABLE_W1TS_LOW_ADDRESS MISSING +#define GPIO_PIN0_CONFIG_LSB MISSING +#define GPIO_PIN0_PAD_PULL_LSB MISSING +#define GPIO_PIN0_PAD_PULL_MASK MISSING +/* SI reg */ +#define SI_CONFIG_ERR_INT_MASK MISSING +#define SI_CONFIG_ERR_INT_LSB MISSING +/* CE descriptor */ +#define CE_SRC_DESC_SIZE_DWORD 2 +#define CE_DEST_DESC_SIZE_DWORD 2 +#define CE_SRC_DESC_SRC_PTR_OFFSET_DWORD 0 +#define CE_SRC_DESC_INFO_OFFSET_DWORD 1 +#define CE_DEST_DESC_DEST_PTR_OFFSET_DWORD 0 +#define CE_DEST_DESC_INFO_OFFSET_DWORD 1 +#if _BYTE_ORDER == _BIG_ENDIAN +#define CE_SRC_DESC_INFO_NBYTES_MASK 0xFFFF0000 +#define CE_SRC_DESC_INFO_NBYTES_SHIFT 16 +#define CE_SRC_DESC_INFO_GATHER_MASK 0x00008000 +#define CE_SRC_DESC_INFO_GATHER_SHIFT 15 +#define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00004000 +#define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 14 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK 0x00002000 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT 13 +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00001000 +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12 +#define CE_SRC_DESC_INFO_META_DATA_MASK 0x00000FFF +#define CE_SRC_DESC_INFO_META_DATA_SHIFT 0 +#else +#define CE_SRC_DESC_INFO_NBYTES_MASK 0x0000FFFF +#define CE_SRC_DESC_INFO_NBYTES_SHIFT 0 +#define CE_SRC_DESC_INFO_GATHER_MASK 0x00010000 +#define CE_SRC_DESC_INFO_GATHER_SHIFT 16 +#define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00020000 +#define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 17 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK 0x00040000 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT 18 +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00080000 +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19 +#define CE_SRC_DESC_INFO_META_DATA_MASK 0xFFF00000 +#define CE_SRC_DESC_INFO_META_DATA_SHIFT 20 +#endif +#if _BYTE_ORDER == _BIG_ENDIAN +#define CE_DEST_DESC_INFO_NBYTES_MASK 0xFFFF0000 +#define CE_DEST_DESC_INFO_NBYTES_SHIFT 16 +#define CE_DEST_DESC_INFO_GATHER_MASK 0x00008000 +#define CE_DEST_DESC_INFO_GATHER_SHIFT 15 +#define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00004000 +#define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 14 +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK 0x00002000 +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT 13 +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00001000 +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12 +#define CE_DEST_DESC_INFO_META_DATA_MASK 0x00000FFF +#define CE_DEST_DESC_INFO_META_DATA_SHIFT 0 +#else +#define CE_DEST_DESC_INFO_NBYTES_MASK 0x0000FFFF +#define CE_DEST_DESC_INFO_NBYTES_SHIFT 0 +#define CE_DEST_DESC_INFO_GATHER_MASK 0x00010000 +#define CE_DEST_DESC_INFO_GATHER_SHIFT 16 +#define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00020000 +#define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 17 +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK 0x00040000 +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT 18 +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00080000 +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19 +#define CE_DEST_DESC_INFO_META_DATA_MASK 0xFFF00000 +#define CE_DEST_DESC_INFO_META_DATA_SHIFT 20 +#endif + +#define MY_TARGET_DEF IPQ4019_TARGETdef +#define MY_HOST_DEF IPQ4019_HOSTdef +#define MY_CEREG_DEF IPQ4019_CE_TARGETdef +#define MY_TARGET_BOARD_DATA_SZ IPQ4019_BOARD_DATA_SZ +#define MY_TARGET_BOARD_EXT_DATA_SZ IPQ4019_BOARD_EXT_DATA_SZ +#include "targetdef.h" +#include "hostdef.h" +#else +#include "common_drv.h" +#include "targetdef.h" +#include "hostdef.h" +struct targetdef_s *IPQ4019_TARGETdef; +struct hostdef_s *IPQ4019_HOSTdef; +#endif /* IPQ4019_HEADERS_DEF */ diff --git a/hif/src/qca9888def.c b/hif/src/qca9888def.c new file mode 100644 index 0000000000..2c67094e39 --- /dev/null +++ b/hif/src/qca9888def.c @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2015,2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#if defined(QCA9888_HEADERS_DEF) +#define QCA9888 1 + +#define WLAN_HEADERS 1 +#include "common_drv.h" +#include "QCA9888/v2/soc_addrs.h" +#include "QCA9888/v2/extra/hw/apb_map.h" +#include "QCA9888/v2/hw/gpio_athr_wlan_reg.h" +#ifdef WLAN_HEADERS + +#include "QCA9888/v2/extra/hw/wifi_top_reg_map.h" +#include "QCA9888/v2/hw/rtc_soc_reg.h" + +#endif +#include "QCA9888/v2/hw/si_reg.h" +#include "QCA9888/v2/extra/hw/pcie_local_reg.h" +#include "QCA9888/v2/hw/ce_wrapper_reg_csr.h" + +#include "QCA9888/v2/extra/hw/soc_core_reg.h" +#include "QCA9888/v2/hw/soc_pcie_reg.h" +#include "QCA9888/v2/extra/hw/ce_reg_csr.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Base address is defined in pcie_local_reg.h. Macros which access the + * registers include the base address in their definition. + */ +#define PCIE_LOCAL_BASE_ADDRESS 0 + +#define FW_EVENT_PENDING_ADDRESS (WIFICMN_SCRATCH_3_ADDRESS) +#define DRAM_BASE_ADDRESS TARG_DRAM_START + +/* Backwards compatibility -- TBDXXX */ + +#define MISSING 0 + +#define WLAN_SYSTEM_SLEEP_DISABLE_LSB WIFI_SYSTEM_SLEEP_DISABLE_LSB +#define WLAN_SYSTEM_SLEEP_DISABLE_MASK WIFI_SYSTEM_SLEEP_DISABLE_MASK +#define WLAN_RESET_CONTROL_COLD_RST_MASK WIFI_RESET_CONTROL_MAC_COLD_RST_MASK +#define WLAN_RESET_CONTROL_WARM_RST_MASK WIFI_RESET_CONTROL_MAC_WARM_RST_MASK +#define SOC_CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_ADDRESS +#define SOC_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_ADDRESS +#define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_ADDRESS +#define SOC_LPO_CAL_OFFSET SOC_LPO_CAL_ADDRESS +#define SOC_RESET_CONTROL_CE_RST_MASK WIFI_RESET_CONTROL_CE_RESET_MASK +#define WLAN_SYSTEM_SLEEP_OFFSET WIFI_SYSTEM_SLEEP_ADDRESS +#define WLAN_RESET_CONTROL_OFFSET WIFI_RESET_CONTROL_ADDRESS +#define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET +#define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK +#define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK +#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS +#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS +#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS +#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK +#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK +#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS +#define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS +#define LOCAL_SCRATCH_OFFSET 0x18 +#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS +#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS +#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS +#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS +#define SI_CONFIG_OFFSET SI_CONFIG_ADDRESS +#define SI_TX_DATA0_OFFSET SI_TX_DATA0_ADDRESS +#define SI_TX_DATA1_OFFSET SI_TX_DATA1_ADDRESS +#define SI_RX_DATA0_OFFSET SI_RX_DATA0_ADDRESS +#define SI_RX_DATA1_OFFSET SI_RX_DATA1_ADDRESS +#define SI_CS_OFFSET SI_CS_ADDRESS +#define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB +#define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK +#define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB +#define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK +#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS +#define MBOX_BASE_ADDRESS MISSING +#define INT_STATUS_ENABLE_ERROR_LSB MISSING +#define INT_STATUS_ENABLE_ERROR_MASK MISSING +#define INT_STATUS_ENABLE_CPU_LSB MISSING +#define INT_STATUS_ENABLE_CPU_MASK MISSING +#define INT_STATUS_ENABLE_COUNTER_LSB MISSING +#define INT_STATUS_ENABLE_COUNTER_MASK MISSING +#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING +#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING +#define INT_STATUS_ENABLE_ADDRESS MISSING +#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING +#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING +#define HOST_INT_STATUS_ADDRESS MISSING +#define CPU_INT_STATUS_ADDRESS MISSING +#define ERROR_INT_STATUS_ADDRESS MISSING +#define ERROR_INT_STATUS_WAKEUP_MASK MISSING +#define ERROR_INT_STATUS_WAKEUP_LSB MISSING +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING +#define COUNT_DEC_ADDRESS MISSING +#define HOST_INT_STATUS_CPU_MASK MISSING +#define HOST_INT_STATUS_CPU_LSB MISSING +#define HOST_INT_STATUS_ERROR_MASK MISSING +#define HOST_INT_STATUS_ERROR_LSB MISSING +#define HOST_INT_STATUS_COUNTER_MASK MISSING +#define HOST_INT_STATUS_COUNTER_LSB MISSING +#define RX_LOOKAHEAD_VALID_ADDRESS MISSING +#define WINDOW_DATA_ADDRESS MISSING +#define WINDOW_READ_ADDR_ADDRESS MISSING +#define WINDOW_WRITE_ADDR_ADDRESS MISSING +/* MAC Descriptor */ +#define RX_PPDU_END_ANTENNA_OFFSET_DWORD (RX_PPDU_END_25_RX_ANTENNA_OFFSET >> 2) +/* GPIO Register */ +#define GPIO_ENABLE_W1TS_LOW_ADDRESS WLAN_GPIO_ENABLE_W1TS_LOW_ADDRESS +#define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB +#define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB +#define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK +/* CE descriptor */ +#define CE_SRC_DESC_SIZE_DWORD 2 +#define CE_DEST_DESC_SIZE_DWORD 2 +#define CE_SRC_DESC_SRC_PTR_OFFSET_DWORD 0 +#define CE_SRC_DESC_INFO_OFFSET_DWORD 1 +#define CE_DEST_DESC_DEST_PTR_OFFSET_DWORD 0 +#define CE_DEST_DESC_INFO_OFFSET_DWORD 1 +#if _BYTE_ORDER == _BIG_ENDIAN +#define CE_SRC_DESC_INFO_NBYTES_MASK 0xFFFF0000 +#define CE_SRC_DESC_INFO_NBYTES_SHIFT 16 +#define CE_SRC_DESC_INFO_GATHER_MASK 0x00008000 +#define CE_SRC_DESC_INFO_GATHER_SHIFT 15 +#define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00004000 +#define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 14 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK 0x00002000 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT 13 +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00001000 +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12 +#define CE_SRC_DESC_INFO_META_DATA_MASK 0x00000FFF +#define CE_SRC_DESC_INFO_META_DATA_SHIFT 0 +#else +#define CE_SRC_DESC_INFO_NBYTES_MASK 0x0000FFFF +#define CE_SRC_DESC_INFO_NBYTES_SHIFT 0 +#define CE_SRC_DESC_INFO_GATHER_MASK 0x00010000 +#define CE_SRC_DESC_INFO_GATHER_SHIFT 16 +#define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00020000 +#define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 17 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK 0x00040000 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT 18 +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00080000 +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19 +#define CE_SRC_DESC_INFO_META_DATA_MASK 0xFFF00000 +#define CE_SRC_DESC_INFO_META_DATA_SHIFT 20 +#endif +#if _BYTE_ORDER == _BIG_ENDIAN +#define CE_DEST_DESC_INFO_NBYTES_MASK 0xFFFF0000 +#define CE_DEST_DESC_INFO_NBYTES_SHIFT 16 +#define CE_DEST_DESC_INFO_GATHER_MASK 0x00008000 +#define CE_DEST_DESC_INFO_GATHER_SHIFT 15 +#define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00004000 +#define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 14 +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK 0x00002000 +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT 13 +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00001000 +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12 +#define CE_DEST_DESC_INFO_META_DATA_MASK 0x00000FFF +#define CE_DEST_DESC_INFO_META_DATA_SHIFT 0 +#else +#define CE_DEST_DESC_INFO_NBYTES_MASK 0x0000FFFF +#define CE_DEST_DESC_INFO_NBYTES_SHIFT 0 +#define CE_DEST_DESC_INFO_GATHER_MASK 0x00010000 +#define CE_DEST_DESC_INFO_GATHER_SHIFT 16 +#define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00020000 +#define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 17 +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK 0x00040000 +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT 18 +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00080000 +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19 +#define CE_DEST_DESC_INFO_META_DATA_MASK 0xFFF00000 +#define CE_DEST_DESC_INFO_META_DATA_SHIFT 20 +#endif + +#define MY_TARGET_DEF QCA9888_TARGETdef +#define MY_HOST_DEF QCA9888_HOSTdef +#define MY_CEREG_DEF QCA9888_CE_TARGETdef +#define MY_TARGET_BOARD_DATA_SZ QCA9888_BOARD_DATA_SZ +#define MY_TARGET_BOARD_EXT_DATA_SZ QCA9888_BOARD_EXT_DATA_SZ +#include "targetdef.h" +#include "hostdef.h" +#else +#include "common_drv.h" +#include "targetdef.h" +#include "hostdef.h" +struct targetdef_s *QCA9888_TARGETdef; +struct hostdef_s *QCA9888_HOSTdef; +#endif /* QCA9888_HEADERS_DEF */ diff --git a/hif/src/qca9984def.c b/hif/src/qca9984def.c new file mode 100644 index 0000000000..61d09c75e8 --- /dev/null +++ b/hif/src/qca9984def.c @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2015,2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#if defined(QCA9984_HEADERS_DEF) +#define QCA9984 1 + +#define WLAN_HEADERS 1 +#include "common_drv.h" +#include "QCA9984/soc_addrs.h" +#include "QCA9984/extra/hw/apb_map.h" +#include "QCA9984/hw/gpio_athr_wlan_reg.h" +#ifdef WLAN_HEADERS + +#include "QCA9984/extra/hw/wifi_top_reg_map.h" +#include "QCA9984/hw/rtc_soc_reg.h" + +#endif +#include "QCA9984/hw/si_reg.h" +#include "QCA9984/extra/hw/pcie_local_reg.h" +#include "QCA9984/hw/ce_wrapper_reg_csr.h" + +#include "QCA9984/extra/hw/soc_core_reg.h" +#include "QCA9984/hw/soc_pcie_reg.h" +#include "QCA9984/extra/hw/ce_reg_csr.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Base address is defined in pcie_local_reg.h. Macros which access the + * registers include the base address in their definition. + */ +#define PCIE_LOCAL_BASE_ADDRESS 0 + +#define FW_EVENT_PENDING_ADDRESS (WIFICMN_SCRATCH_3_ADDRESS) +#define DRAM_BASE_ADDRESS TARG_DRAM_START + +/* Backwards compatibility -- TBDXXX */ + +#define MISSING 0 + +#define WLAN_SYSTEM_SLEEP_DISABLE_LSB WIFI_SYSTEM_SLEEP_DISABLE_LSB +#define WLAN_SYSTEM_SLEEP_DISABLE_MASK WIFI_SYSTEM_SLEEP_DISABLE_MASK +#define WLAN_RESET_CONTROL_COLD_RST_MASK WIFI_RESET_CONTROL_MAC_COLD_RST_MASK +#define WLAN_RESET_CONTROL_WARM_RST_MASK WIFI_RESET_CONTROL_MAC_WARM_RST_MASK +#define SOC_CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_ADDRESS +#define SOC_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_ADDRESS +#define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_ADDRESS +#define SOC_LPO_CAL_OFFSET SOC_LPO_CAL_ADDRESS +#define SOC_RESET_CONTROL_CE_RST_MASK WIFI_RESET_CONTROL_CE_RESET_MASK +#define WLAN_SYSTEM_SLEEP_OFFSET WIFI_SYSTEM_SLEEP_ADDRESS +#define WLAN_RESET_CONTROL_OFFSET WIFI_RESET_CONTROL_ADDRESS +#define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET +#define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK +#define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK +#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS +#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS +#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS +#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK +#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK +#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS +#define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS +#define LOCAL_SCRATCH_OFFSET 0x18 +#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS +#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS +#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS +#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS +#define SI_CONFIG_OFFSET SI_CONFIG_ADDRESS +#define SI_TX_DATA0_OFFSET SI_TX_DATA0_ADDRESS +#define SI_TX_DATA1_OFFSET SI_TX_DATA1_ADDRESS +#define SI_RX_DATA0_OFFSET SI_RX_DATA0_ADDRESS +#define SI_RX_DATA1_OFFSET SI_RX_DATA1_ADDRESS +#define SI_CS_OFFSET SI_CS_ADDRESS +#define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB +#define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK +#define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB +#define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK +#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS +#define MBOX_BASE_ADDRESS MISSING +#define INT_STATUS_ENABLE_ERROR_LSB MISSING +#define INT_STATUS_ENABLE_ERROR_MASK MISSING +#define INT_STATUS_ENABLE_CPU_LSB MISSING +#define INT_STATUS_ENABLE_CPU_MASK MISSING +#define INT_STATUS_ENABLE_COUNTER_LSB MISSING +#define INT_STATUS_ENABLE_COUNTER_MASK MISSING +#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING +#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING +#define INT_STATUS_ENABLE_ADDRESS MISSING +#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING +#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING +#define HOST_INT_STATUS_ADDRESS MISSING +#define CPU_INT_STATUS_ADDRESS MISSING +#define ERROR_INT_STATUS_ADDRESS MISSING +#define ERROR_INT_STATUS_WAKEUP_MASK MISSING +#define ERROR_INT_STATUS_WAKEUP_LSB MISSING +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING +#define COUNT_DEC_ADDRESS MISSING +#define HOST_INT_STATUS_CPU_MASK MISSING +#define HOST_INT_STATUS_CPU_LSB MISSING +#define HOST_INT_STATUS_ERROR_MASK MISSING +#define HOST_INT_STATUS_ERROR_LSB MISSING +#define HOST_INT_STATUS_COUNTER_MASK MISSING +#define HOST_INT_STATUS_COUNTER_LSB MISSING +#define RX_LOOKAHEAD_VALID_ADDRESS MISSING +#define WINDOW_DATA_ADDRESS MISSING +#define WINDOW_READ_ADDR_ADDRESS MISSING +#define WINDOW_WRITE_ADDR_ADDRESS MISSING +/* MAC Descriptor */ +#define RX_PPDU_END_ANTENNA_OFFSET_DWORD (RX_PPDU_END_25_RX_ANTENNA_OFFSET >> 2) +/* GPIO Register */ +#define GPIO_ENABLE_W1TS_LOW_ADDRESS WLAN_GPIO_ENABLE_W1TS_LOW_ADDRESS +#define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB +#define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB +#define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK +/* CE descriptor */ +#define CE_SRC_DESC_SIZE_DWORD 2 +#define CE_DEST_DESC_SIZE_DWORD 2 +#define CE_SRC_DESC_SRC_PTR_OFFSET_DWORD 0 +#define CE_SRC_DESC_INFO_OFFSET_DWORD 1 +#define CE_DEST_DESC_DEST_PTR_OFFSET_DWORD 0 +#define CE_DEST_DESC_INFO_OFFSET_DWORD 1 +#if _BYTE_ORDER == _BIG_ENDIAN +#define CE_SRC_DESC_INFO_NBYTES_MASK 0xFFFF0000 +#define CE_SRC_DESC_INFO_NBYTES_SHIFT 16 +#define CE_SRC_DESC_INFO_GATHER_MASK 0x00008000 +#define CE_SRC_DESC_INFO_GATHER_SHIFT 15 +#define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00004000 +#define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 14 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK 0x00002000 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT 13 +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00001000 +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12 +#define CE_SRC_DESC_INFO_META_DATA_MASK 0x00000FFF +#define CE_SRC_DESC_INFO_META_DATA_SHIFT 0 +#else +#define CE_SRC_DESC_INFO_NBYTES_MASK 0x0000FFFF +#define CE_SRC_DESC_INFO_NBYTES_SHIFT 0 +#define CE_SRC_DESC_INFO_GATHER_MASK 0x00010000 +#define CE_SRC_DESC_INFO_GATHER_SHIFT 16 +#define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00020000 +#define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 17 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK 0x00040000 +#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT 18 +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00080000 +#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19 +#define CE_SRC_DESC_INFO_META_DATA_MASK 0xFFF00000 +#define CE_SRC_DESC_INFO_META_DATA_SHIFT 20 +#endif +#if _BYTE_ORDER == _BIG_ENDIAN +#define CE_DEST_DESC_INFO_NBYTES_MASK 0xFFFF0000 +#define CE_DEST_DESC_INFO_NBYTES_SHIFT 16 +#define CE_DEST_DESC_INFO_GATHER_MASK 0x00008000 +#define CE_DEST_DESC_INFO_GATHER_SHIFT 15 +#define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00004000 +#define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 14 +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK 0x00002000 +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT 13 +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00001000 +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12 +#define CE_DEST_DESC_INFO_META_DATA_MASK 0x00000FFF +#define CE_DEST_DESC_INFO_META_DATA_SHIFT 0 +#else +#define CE_DEST_DESC_INFO_NBYTES_MASK 0x0000FFFF +#define CE_DEST_DESC_INFO_NBYTES_SHIFT 0 +#define CE_DEST_DESC_INFO_GATHER_MASK 0x00010000 +#define CE_DEST_DESC_INFO_GATHER_SHIFT 16 +#define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00020000 +#define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 17 +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK 0x00040000 +#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT 18 +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00080000 +#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19 +#define CE_DEST_DESC_INFO_META_DATA_MASK 0xFFF00000 +#define CE_DEST_DESC_INFO_META_DATA_SHIFT 20 +#endif + +#define MY_TARGET_DEF QCA9984_TARGETdef +#define MY_HOST_DEF QCA9984_HOSTdef +#define MY_CEREG_DEF QCA9984_CE_TARGETdef +#define MY_TARGET_BOARD_DATA_SZ QCA9984_BOARD_DATA_SZ +#define MY_TARGET_BOARD_EXT_DATA_SZ QCA9984_BOARD_EXT_DATA_SZ +#include "targetdef.h" +#include "hostdef.h" +#else +#include "common_drv.h" +#include "targetdef.h" +#include "hostdef.h" +struct targetdef_s *QCA9984_TARGETdef; +struct hostdef_s *QCA9984_HOSTdef; +#endif /* QCA9984_HEADERS_DEF */ diff --git a/hif/src/regtable.c b/hif/src/regtable.c index f1e340fe01..6f2af50e89 100644 --- a/hif/src/regtable.c +++ b/hif/src/regtable.c @@ -28,19 +28,17 @@ #include "targaddrs.h" #include "cepci.h" #include "regtable.h" -#include "ar9888def.h" #include "ar6320def.h" #include "ar6320v2def.h" #include "hif_main.h" #include "adrastea_reg_def.h" +#include "targetdef.h" +#include "hostdef.h" + void target_register_tbl_attach(struct hif_softc *scn, u32 target_type) { switch (target_type) { - case TARGET_TYPE_AR9888: - scn->targetdef = &ar9888_targetdef; - scn->target_ce_def = &ar9888_ce_targetdef; - break; case TARGET_TYPE_AR6320: scn->targetdef = &ar6320_targetdef; scn->target_ce_def = &ar6320_ce_targetdef; @@ -53,6 +51,60 @@ void target_register_tbl_attach(struct hif_softc *scn, u32 target_type) scn->targetdef = &adrastea_targetdef; scn->target_ce_def = &adrastea_ce_targetdef; break; +#if defined(AR6002_HEADERS_DEF) + case TARGET_TYPE_AR6002: + scn->targetdef = AR6002_TARGETdef; + break; +#endif +#if defined(AR6003_HEADERS_DEF) + case TARGET_TYPE_AR6003: + scn->targetdef = AR6003_TARGETdef; + break; +#endif +#if defined(AR6004_HEADERS_DEF) + case TARGET_TYPE_AR6004: + scn->targetdef = AR6004_TARGETdef; + break; +#endif +#if defined(AR9888_HEADERS_DEF) + case TARGET_TYPE_AR9888: + scn->targetdef = AR9888_TARGETdef; + scn->target_ce_def = AR9888_CE_TARGETdef; + break; +#endif +#if defined(AR9888V2_HEADERS_DEF) + case TARGET_TYPE_AR9888V2: + scn->targetdef = AR9888V2_TARGETdef; + scn->target_ce_def = AR9888_CE_TARGETdef; + break; +#endif +#if defined(AR900B_HEADERS_DEF) + case TARGET_TYPE_AR900B: + scn->targetdef = AR900B_TARGETdef; + scn->target_ce_def = AR900B_CE_TARGETdef; + break; +#endif +#if defined(QCA9984_HEADERS_DEF) + case TARGET_TYPE_QCA9984: + scn->targetdef = QCA9984_TARGETdef; + scn->target_ce_def = QCA9984_CE_TARGETdef; + break; +#endif +#if defined(QCA9888_HEADERS_DEF) + case TARGET_TYPE_QCA9888: + scn->targetdef = QCA9888_TARGETdef; + scn->target_ce_def = QCA9888_CE_TARGETdef; + break; +#endif +#ifdef ATH_AHB +#if defined(IPQ4019_HEADERS_DEF) + case TARGET_TYPE_IPQ4019: + scn->targetdef = IPQ4019_TARGETdef; + scn->target_ce_def = IPQ4019_CE_TARGETdef; + break; +#endif +#endif + default: break; } @@ -61,12 +113,6 @@ void target_register_tbl_attach(struct hif_softc *scn, u32 target_type) void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type) { switch (hif_type) { - case HIF_TYPE_AR9888: - scn->hostdef = &ar9888_hostdef; - break; - case HIF_TYPE_AR6320: - scn->hostdef = &ar6320_hostdef; - break; case HIF_TYPE_AR6320V2: scn->hostdef = &ar6320v2_hostdef; break; @@ -74,6 +120,55 @@ void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type) scn->hostdef = &adrastea_hostdef; scn->host_shadow_regs = &adrastea_host_shadow_regs; break; +#if defined(AR6002_HEADERS_DEF) + case HIF_TYPE_AR6002: + scn->hostdef = AR6002_HOSTdef; + break; +#endif +#if defined(AR6003_HEADERS_DEF) + case HIF_TYPE_AR6003: + scn->hostdef = AR6003_HOSTdef; + break; +#endif +#if defined(AR6004_HEADERS_DEF) + case HIF_TYPE_AR6004: + scn->hostdef = AR6004_HOSTdef; + break; +#endif +#if defined(AR9888_HEADERS_DEF) + case HIF_TYPE_AR9888: + scn->hostdef = AR9888_HOSTdef; + break; +#endif +#if defined(AR9888V2_HEADERS_DEF) + case HIF_TYPE_AR9888V2: + scn->hostdef = AR9888V2_HOSTdef; + break; +#endif +#if defined(AR900B_HEADERS_DEF) + case HIF_TYPE_AR900B: + scn->hostdef = AR900B_HOSTdef; + break; +#endif +#if defined(QCA9984_HEADERS_DEF) + case HIF_TYPE_QCA9984: + scn->hostdef = QCA9984_HOSTdef; + break; +#endif +#if defined(QCA9888_HEADERS_DEF) + case HIF_TYPE_QCA9888: + scn->hostdef = QCA9888_HOSTdef; + break; +#endif + +#ifdef ATH_AHB +#if defined(IPQ4019_HEADERS_DEF) + case HIF_TYPE_IPQ4019: + scn->hostdef = IPQ4019_HOSTdef; + break; +#endif +#endif + default: break; }