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qcacld-3.0: Remove sub-ctl codes.

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Firmware does not require the sub-ctl codes from the host. Therefore,
remove the calculation of sub-ctl codes from the host APIs. Also
remove the associated data structures.

Change-Id: Ib5d5f074b45f2dae2bb9a7c172ee7f8750ad5355
CRs-Fixed: 961806
This commit is contained in:
Amar Singhal
2016-01-19 15:23:03 -08:00
committed by Vishwajith Upendra
parent 76b4132090
commit c1f9c1af05
5 changed files with 69 additions and 1434 deletions
Download Patch File Download Diff File Expand all files Collapse all files

91
core/cds/inc/cds_regdomain.h
View File

@@ -92,6 +92,7 @@ enum {
#define SUPER_DOMAIN_MASK 0x0fff #define SUPER_DOMAIN_MASK 0x0fff
#define COUNTRY_CODE_MASK 0x3fff #define COUNTRY_CODE_MASK 0x3fff
#define CF_INTERFERENCE (CHANNEL_CW_INT | CHANNEL_RADAR_INT) #define CF_INTERFERENCE (CHANNEL_CW_INT | CHANNEL_RADAR_INT)
#define NO_CTL 0xff
/* /*
* The following describe the bit masks for different passive scan * The following describe the bit masks for different passive scan
@@ -118,84 +119,6 @@ enum {
#define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL #define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL
#define IS_ECM_CHAN 0x8000000000000000ULL #define IS_ECM_CHAN 0x8000000000000000ULL
/* define in ah_eeprom.h */
#define SD_NO_CTL 0xf0
#define NO_CTL 0xff
#define CTL_MODE_M 0x0f
#define CTL_11A 0
#define CTL_11B 1
#define CTL_11G 2
#define CTL_TURBO 3
#define CTL_108G 4
#define CTL_2GHT20 5
#define CTL_5GHT20 6
#define CTL_2GHT40 7
#define CTL_5GHT40 8
#define CTL_5GVHT80 9
#ifndef ATH_NO_5G_SUPPORT
#define REGDMN_MODE_11A_TURBO REGDMN_MODE_108A
#define CHAN_11A_BMZERO BMZERO,
#define CHAN_11A_BM(_a, _b, _c, _d, _e, _f, _g, _h, _i, _j, _k, _l) \
BM(_a, _b, _c, _d, _e, _f, _g, _h, _i, _j, _k, _l),
#else
/* remove 11a channel info if 11a is not supported */
#define CHAN_11A_BMZERO
#define CHAN_11A_BM(_a, _b, _c, _d, _e, _f, _g, _h, _i, _j, _k, _l)
#endif
#ifndef ATH_REMOVE_2G_TURBO_RD_TABLE
#define REGDMN_MODE_11G_TURBO REGDMN_MODE_108G
#define CHAN_TURBO_G_BMZERO BMZERO,
#define CHAN_TURBO_G_BM(_a, _b, _c, _d, _e, _f, _g, _h, _i, _j, _k, _l) \
BM(_a, _b, _c, _d, _e, _f, _g, _h, _i, _j, _k, _l),
#else
/* remove turbo-g channel info if turbo-g is not supported */
#define CHAN_TURBO_G(a, b)
#define CHAN_TURBO_G_BMZERO
#define CHAN_TURBO_G_BM(_a, _b, _c, _d, _e, _f, _g, _h, _i, _j, _k, _l)
#endif
#define BMLEN 2 /* Use 2 64 bit uint for channel bitmask
NB: Must agree with macro below (BM) */
#define BMZERO {(uint64_t) 0, (uint64_t) 0} /* BMLEN zeros */
#ifndef SUPPRESS_SHIFT_WARNING
#define SUPPRESS_SHIFT_WARNING
#endif
/* Suppress MS warning "C4293: 'operator' : shift count negative or too big,
* undefined behavior"
* This is safe below because the the operand is properly range-checked, but
* the compiler can't reason that out before it spits the warning.
* Using suppress, so the warning can still be enabled globally to catch other
* incorrect uses.
*/
#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi, _fj, _fk, _fl) \
SUPPRESS_SHIFT_WARNING \
{((((_fa >= 0) && (_fa < 64)) ? (((uint64_t) 1) << _fa) : (uint64_t) 0) | \
(((_fb >= 0) && (_fb < 64)) ? (((uint64_t) 1) << _fb) : (uint64_t) 0) | \
(((_fc >= 0) && (_fc < 64)) ? (((uint64_t) 1) << _fc) : (uint64_t) 0) | \
(((_fd >= 0) && (_fd < 64)) ? (((uint64_t) 1) << _fd) : (uint64_t) 0) | \
(((_fe >= 0) && (_fe < 64)) ? (((uint64_t) 1) << _fe) : (uint64_t) 0) | \
(((_ff >= 0) && (_ff < 64)) ? (((uint64_t) 1) << _ff) : (uint64_t) 0) | \
(((_fg >= 0) && (_fg < 64)) ? (((uint64_t) 1) << _fg) : (uint64_t) 0) | \
(((_fh >= 0) && (_fh < 64)) ? (((uint64_t) 1) << _fh) : (uint64_t) 0) | \
(((_fi >= 0) && (_fi < 64)) ? (((uint64_t) 1) << _fi) : (uint64_t) 0) | \
(((_fj >= 0) && (_fj < 64)) ? (((uint64_t) 1) << _fj) : (uint64_t) 0) | \
(((_fk >= 0) && (_fk < 64)) ? (((uint64_t) 1) << _fk) : (uint64_t) 0) | \
(((_fl >= 0) && (_fl < 64)) ? (((uint64_t) 1) << _fl) : (uint64_t) 0) ) \
,(((((_fa > 63) && (_fa < 128)) ? (((uint64_t) 1) << (_fa - 64)) : (uint64_t) 0) | \
(((_fb > 63) && (_fb < 128)) ? (((uint64_t) 1) << (_fb - 64)) : (uint64_t) 0) | \
(((_fc > 63) && (_fc < 128)) ? (((uint64_t) 1) << (_fc - 64)) : (uint64_t) 0) | \
(((_fd > 63) && (_fd < 128)) ? (((uint64_t) 1) << (_fd - 64)) : (uint64_t) 0) | \
(((_fe > 63) && (_fe < 128)) ? (((uint64_t) 1) << (_fe - 64)) : (uint64_t) 0) | \
(((_ff > 63) && (_ff < 128)) ? (((uint64_t) 1) << (_ff - 64)) : (uint64_t) 0) | \
(((_fg > 63) && (_fg < 128)) ? (((uint64_t) 1) << (_fg - 64)) : (uint64_t) 0) | \
(((_fh > 63) && (_fh < 128)) ? (((uint64_t) 1) << (_fh - 64)) : (uint64_t) 0) | \
(((_fi > 63) && (_fi < 128)) ? (((uint64_t) 1) << (_fi - 64)) : (uint64_t) 0) | \
(((_fj > 63) && (_fj < 128)) ? (((uint64_t) 1) << (_fj - 64)) : (uint64_t) 0) | \
(((_fk > 63) && (_fk < 128)) ? (((uint64_t) 1) << (_fk - 64)) : (uint64_t) 0) | \
(((_fl > 63) && (_fl < 128)) ? (((uint64_t) 1) << (_fl - 64)) : (uint64_t) 0)))}
/* /*
* THE following table is the mapping of regdomain pairs specified by * THE following table is the mapping of regdomain pairs specified by
@@ -255,15 +178,6 @@ typedef struct reg_domain {
uint8_t conformance_test_limit; uint8_t conformance_test_limit;
uint64_t dfsMask; /* DFS bitmask for 5Ghz tables */ uint64_t dfsMask; /* DFS bitmask for 5Ghz tables */
uint64_t pscan; /* Bitmask for passive scan */ uint64_t pscan; /* Bitmask for passive scan */
uint32_t flags; /* Requirement flags (AdHoc disallow, noise
floor cal needed, etc) */
uint64_t chan11a[BMLEN]; /* 128 bit bitmask for channel/band selection */
uint64_t chan11a_turbo[BMLEN]; /* 128 bit bitmask for channel/band select */
uint64_t chan11a_dyn_turbo[BMLEN]; /* 128 bit mask for chan/band select */
uint64_t chan11b[BMLEN]; /* 128 bit bitmask for channel/band selection */
uint64_t chan11g[BMLEN]; /* 128 bit bitmask for channel/band selection */
uint64_t chan11g_turbo[BMLEN];
} REG_DOMAIN; } REG_DOMAIN;
struct cmode { struct cmode {
@@ -566,8 +480,7 @@ struct ch_params_s {
int32_t cds_fill_some_regulatory_info(struct regulatory *reg); int32_t cds_fill_some_regulatory_info(struct regulatory *reg);
void cds_fill_and_send_ctl_to_fw(struct regulatory *reg); void cds_fill_and_send_ctl_to_fw(struct regulatory *reg);
int32_t cds_get_country_from_alpha2(uint8_t *alpha2); int32_t cds_get_country_from_alpha2(uint8_t *alpha2);
void cds_fill_send_ctl_info_to_fw(struct regulatory *reg, uint32_t modesAvail, void cds_fill_send_ctl_info_to_fw(struct regulatory *reg);
uint32_t modeSelect);
void cds_set_wma_dfs_region(uint8_t dfs_region); void cds_set_wma_dfs_region(uint8_t dfs_region);
void cds_set_ch_params(uint8_t ch, uint32_t phy_mode, void cds_set_ch_params(uint8_t ch, uint32_t phy_mode,
struct ch_params_s *ch_params); struct ch_params_s *ch_params);

1215
core/cds/inc/cds_regdomain_common.h
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File diff suppressed because it is too large Load Diff

156
core/cds/src/cds_regdomain.c
View File

@@ -372,93 +372,11 @@ int32_t regdmn_get_regdmn_for_country(uint8_t *alpha2)
return -1; return -1;
} }
/* void cds_fill_send_ctl_info_to_fw(struct regulatory *reg)
* Test to see if the bitmask array is all zeros
*/
static bool is_chan_bit_mask_zero(const uint64_t *bitmask)
{
int i;
for (i = 0; i < BMLEN; i++) {
if (bitmask[i] != 0)
return false;
}
return true;
}
/*
* Return the mask of available modes based on the hardware
* capabilities and the specified country code and reg domain.
*/
static uint32_t regdmn_getwmodesnreg(uint32_t modesAvail,
const COUNTRY_CODE_TO_ENUM_RD *country,
const REG_DOMAIN *rd5GHz)
{
/* Check country regulations for allowed modes */
if ((modesAvail & (REGDMN_MODE_11A_TURBO | REGDMN_MODE_TURBO)) &&
(!country->allow11aTurbo))
modesAvail &= ~(REGDMN_MODE_11A_TURBO | REGDMN_MODE_TURBO);
if ((modesAvail & REGDMN_MODE_11G_TURBO) && (!country->allow11gTurbo))
modesAvail &= ~REGDMN_MODE_11G_TURBO;
if ((modesAvail & REGDMN_MODE_11G) && (!country->allow11g))
modesAvail &= ~REGDMN_MODE_11G;
if ((modesAvail & REGDMN_MODE_11A) &&
(is_chan_bit_mask_zero(rd5GHz->chan11a)))
modesAvail &= ~REGDMN_MODE_11A;
if ((modesAvail & REGDMN_MODE_11NG_HT20) && (!country->allow11ng20))
modesAvail &= ~REGDMN_MODE_11NG_HT20;
if ((modesAvail & REGDMN_MODE_11NA_HT20) && (!country->allow11na20))
modesAvail &= ~REGDMN_MODE_11NA_HT20;
if ((modesAvail & REGDMN_MODE_11NG_HT40PLUS) && (!country->allow11ng40))
modesAvail &= ~REGDMN_MODE_11NG_HT40PLUS;
if ((modesAvail & REGDMN_MODE_11NG_HT40MINUS) &&
(!country->allow11ng40))
modesAvail &= ~REGDMN_MODE_11NG_HT40MINUS;
if ((modesAvail & REGDMN_MODE_11NA_HT40PLUS) && (!country->allow11na40))
modesAvail &= ~REGDMN_MODE_11NA_HT40PLUS;
if ((modesAvail & REGDMN_MODE_11NA_HT40MINUS) &&
(!country->allow11na40))
modesAvail &= ~REGDMN_MODE_11NA_HT40MINUS;
if ((modesAvail & REGDMN_MODE_11AC_VHT20) && (!country->allow11na20))
modesAvail &= ~REGDMN_MODE_11AC_VHT20;
if ((modesAvail & REGDMN_MODE_11AC_VHT40PLUS) &&
(!country->allow11na40))
modesAvail &= ~REGDMN_MODE_11AC_VHT40PLUS;
if ((modesAvail & REGDMN_MODE_11AC_VHT40MINUS) &&
(!country->allow11na40))
modesAvail &= ~REGDMN_MODE_11AC_VHT40MINUS;
if ((modesAvail & REGDMN_MODE_11AC_VHT80) && (!country->allow11na80))
modesAvail &= ~REGDMN_MODE_11AC_VHT80;
if ((modesAvail & REGDMN_MODE_11AC_VHT20_2G) && (!country->allow11ng20))
modesAvail &= ~REGDMN_MODE_11AC_VHT20_2G;
return modesAvail;
}
void cds_fill_send_ctl_info_to_fw(struct regulatory *reg, uint32_t modesAvail,
uint32_t modeSelect)
{ {
const REG_DOMAIN *regdomain2G = NULL; const REG_DOMAIN *regdomain2G = NULL;
const REG_DOMAIN *regdomain5G = NULL; const REG_DOMAIN *regdomain5G = NULL;
int8_t ctl_2g, ctl_5g, ctl; int8_t ctl_2g, ctl_5g;
const REG_DOMAIN *rd = NULL;
const struct cmode *cm;
const COUNTRY_CODE_TO_ENUM_RD *country;
const REG_DMN_PAIR_MAPPING *regpair; const REG_DMN_PAIR_MAPPING *regpair;
regpair = reg->regpair; regpair = reg->regpair;
@@ -478,70 +396,6 @@ void cds_fill_send_ctl_info_to_fw(struct regulatory *reg, uint32_t modesAvail,
ctl_2g = regdomain2G->conformance_test_limit; ctl_2g = regdomain2G->conformance_test_limit;
ctl_5g = regdomain5G->conformance_test_limit; ctl_5g = regdomain5G->conformance_test_limit;
/* find second nible of CTL */
country = find_country(reg->country_code);
if (country != NULL)
modesAvail =
regdmn_getwmodesnreg(modesAvail, country, regdomain5G);
for (cm = modes; cm < &modes[QDF_ARRAY_SIZE(modes)]; cm++) {
if ((cm->mode & modeSelect) == 0)
continue;
if ((cm->mode & modesAvail) == 0)
continue;
switch (cm->mode) {
case REGDMN_MODE_TURBO:
rd = regdomain5G;
ctl = rd->conformance_test_limit | CTL_TURBO;
break;
case REGDMN_MODE_11A:
case REGDMN_MODE_11NA_HT20:
case REGDMN_MODE_11NA_HT40PLUS:
case REGDMN_MODE_11NA_HT40MINUS:
case REGDMN_MODE_11AC_VHT20:
case REGDMN_MODE_11AC_VHT40PLUS:
case REGDMN_MODE_11AC_VHT40MINUS:
case REGDMN_MODE_11AC_VHT80:
rd = regdomain5G;
ctl = rd->conformance_test_limit;
break;
case REGDMN_MODE_11B:
rd = regdomain2G;
ctl = rd->conformance_test_limit | CTL_11B;
break;
case REGDMN_MODE_11G:
case REGDMN_MODE_11NG_HT20:
case REGDMN_MODE_11NG_HT40PLUS:
case REGDMN_MODE_11NG_HT40MINUS:
case REGDMN_MODE_11AC_VHT20_2G:
case REGDMN_MODE_11AC_VHT40_2G:
case REGDMN_MODE_11AC_VHT80_2G:
rd = regdomain2G;
ctl = rd->conformance_test_limit | CTL_11G;
break;
case REGDMN_MODE_11G_TURBO:
rd = regdomain2G;
ctl = rd->conformance_test_limit | CTL_108G;
break;
case REGDMN_MODE_11A_TURBO:
rd = regdomain5G;
ctl = rd->conformance_test_limit | CTL_108G;
break;
default:
qdf_print(KERN_ERR "%s: Unkonwn HAL mode 0x%x\n",
__func__, cm->mode);
continue;
}
if (rd == regdomain2G)
ctl_2g = ctl;
if (rd == regdomain5G)
ctl_5g = ctl;
}
/* save the ctl information for future reference */ /* save the ctl information for future reference */
reg->ctl_5g = ctl_5g; reg->ctl_5g = ctl_5g;
@@ -573,17 +427,13 @@ void cds_set_wma_dfs_region(uint8_t dfs_region)
void cds_fill_and_send_ctl_to_fw(struct regulatory *reg) void cds_fill_and_send_ctl_to_fw(struct regulatory *reg)
{ {
tp_wma_handle wma = cds_get_context(QDF_MODULE_ID_WMA); tp_wma_handle wma = cds_get_context(QDF_MODULE_ID_WMA);
uint32_t modeSelect = 0xFFFFFFFF;
if (!wma) { if (!wma) {
WMA_LOGE("%s: Unable to get WMA handle", __func__); WMA_LOGE("%s: Unable to get WMA handle", __func__);
return; return;
} }
wma_get_modeselect(wma, &modeSelect); cds_fill_send_ctl_info_to_fw(reg);
cds_fill_send_ctl_info_to_fw(reg, wma->reg_cap.wireless_modes,
modeSelect);
return; return;
} }

2
core/wma/inc/wma.h
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@@ -1417,8 +1417,6 @@ extern void cds_wma_complete_cback(void *p_cds_context);
extern void wma_send_regdomain_info_to_fw(uint32_t reg_dmn, uint16_t regdmn2G, extern void wma_send_regdomain_info_to_fw(uint32_t reg_dmn, uint16_t regdmn2G,
uint16_t regdmn5G, int8_t ctl2G, uint16_t regdmn5G, int8_t ctl2G,
int8_t ctl5G); int8_t ctl5G);
void wma_get_modeselect(tp_wma_handle wma, uint32_t *modeSelect);
/** /**
* enum frame_index - Frame index * enum frame_index - Frame index
* @GENERIC_NODOWNLD_NOACK_COMP_INDEX: Frame index for no download comp no ack * @GENERIC_NODOWNLD_NOACK_COMP_INDEX: Frame index for no download comp no ack

39
core/wma/src/wma_features.c
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@@ -5602,45 +5602,6 @@ QDF_STATUS wma_resume_target(WMA_HANDLE handle)
return ret; return ret;
} }
/**
* wma_get_modeselect() - get modeSelect flag based on phy_capability
* @wma: wma handle
* @modeSelect: mode Select
*
* Return: none
*/
void wma_get_modeselect(tp_wma_handle wma, uint32_t *modeSelect)
{
switch (wma->phy_capability) {
case WMI_11G_CAPABILITY:
case WMI_11NG_CAPABILITY:
*modeSelect &= ~(REGDMN_MODE_11A | REGDMN_MODE_TURBO |
REGDMN_MODE_108A | REGDMN_MODE_11A_HALF_RATE |
REGDMN_MODE_11A_QUARTER_RATE |
REGDMN_MODE_11NA_HT20 |
REGDMN_MODE_11NA_HT40PLUS |
REGDMN_MODE_11NA_HT40MINUS |
REGDMN_MODE_11AC_VHT20 |
REGDMN_MODE_11AC_VHT40PLUS |
REGDMN_MODE_11AC_VHT40MINUS |
REGDMN_MODE_11AC_VHT80);
break;
case WMI_11A_CAPABILITY:
case WMI_11NA_CAPABILITY:
case WMI_11AC_CAPABILITY:
*modeSelect &= ~(REGDMN_MODE_11B | REGDMN_MODE_11G |
REGDMN_MODE_108G | REGDMN_MODE_11NG_HT20 |
REGDMN_MODE_11NG_HT40PLUS |
REGDMN_MODE_11NG_HT40MINUS |
REGDMN_MODE_11AC_VHT20_2G |
REGDMN_MODE_11AC_VHT40_2G |
REGDMN_MODE_11AC_VHT80_2G);
break;
}
}
#ifdef FEATURE_WLAN_TDLS #ifdef FEATURE_WLAN_TDLS
/** /**
* wma_tdls_event_handler() - handle TDLS event * wma_tdls_event_handler() - handle TDLS event