From c1f9c1af050d5699019f5c5b06544bb97ef4b4be Mon Sep 17 00:00:00 2001 From: Amar Singhal Date: Tue, 19 Jan 2016 15:23:03 -0800 Subject: [PATCH] qcacld-3.0: Remove sub-ctl codes. Firmware does not require the sub-ctl codes from the host. Therefore, remove the calculation of sub-ctl codes from the host APIs. Also remove the associated data structures. Change-Id: Ib5d5f074b45f2dae2bb9a7c172ee7f8750ad5355 CRs-Fixed: 961806 --- core/cds/inc/cds_regdomain.h | 91 +- core/cds/inc/cds_regdomain_common.h | 1215 ++------------------------- core/cds/src/cds_regdomain.c | 156 +--- core/wma/inc/wma.h | 2 - core/wma/src/wma_features.c | 39 - 5 files changed, 69 insertions(+), 1434 deletions(-) diff --git a/core/cds/inc/cds_regdomain.h b/core/cds/inc/cds_regdomain.h index 868b8e8934..4a54aaf9ed 100644 --- a/core/cds/inc/cds_regdomain.h +++ b/core/cds/inc/cds_regdomain.h @@ -92,6 +92,7 @@ enum { #define SUPER_DOMAIN_MASK 0x0fff #define COUNTRY_CODE_MASK 0x3fff #define CF_INTERFERENCE (CHANNEL_CW_INT | CHANNEL_RADAR_INT) +#define NO_CTL 0xff /* * The following describe the bit masks for different passive scan @@ -118,84 +119,6 @@ enum { #define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL #define IS_ECM_CHAN 0x8000000000000000ULL -/* define in ah_eeprom.h */ -#define SD_NO_CTL 0xf0 -#define NO_CTL 0xff -#define CTL_MODE_M 0x0f -#define CTL_11A 0 -#define CTL_11B 1 -#define CTL_11G 2 -#define CTL_TURBO 3 -#define CTL_108G 4 -#define CTL_2GHT20 5 -#define CTL_5GHT20 6 -#define CTL_2GHT40 7 -#define CTL_5GHT40 8 -#define CTL_5GVHT80 9 - -#ifndef ATH_NO_5G_SUPPORT -#define REGDMN_MODE_11A_TURBO REGDMN_MODE_108A -#define CHAN_11A_BMZERO BMZERO, -#define CHAN_11A_BM(_a, _b, _c, _d, _e, _f, _g, _h, _i, _j, _k, _l) \ - BM(_a, _b, _c, _d, _e, _f, _g, _h, _i, _j, _k, _l), -#else -/* remove 11a channel info if 11a is not supported */ -#define CHAN_11A_BMZERO -#define CHAN_11A_BM(_a, _b, _c, _d, _e, _f, _g, _h, _i, _j, _k, _l) -#endif -#ifndef ATH_REMOVE_2G_TURBO_RD_TABLE -#define REGDMN_MODE_11G_TURBO REGDMN_MODE_108G -#define CHAN_TURBO_G_BMZERO BMZERO, -#define CHAN_TURBO_G_BM(_a, _b, _c, _d, _e, _f, _g, _h, _i, _j, _k, _l) \ - BM(_a, _b, _c, _d, _e, _f, _g, _h, _i, _j, _k, _l), -#else -/* remove turbo-g channel info if turbo-g is not supported */ -#define CHAN_TURBO_G(a, b) -#define CHAN_TURBO_G_BMZERO -#define CHAN_TURBO_G_BM(_a, _b, _c, _d, _e, _f, _g, _h, _i, _j, _k, _l) -#endif - -#define BMLEN 2 /* Use 2 64 bit uint for channel bitmask - NB: Must agree with macro below (BM) */ -#define BMZERO {(uint64_t) 0, (uint64_t) 0} /* BMLEN zeros */ - -#ifndef SUPPRESS_SHIFT_WARNING -#define SUPPRESS_SHIFT_WARNING -#endif - -/* Suppress MS warning "C4293: 'operator' : shift count negative or too big, - * undefined behavior" - * This is safe below because the the operand is properly range-checked, but - * the compiler can't reason that out before it spits the warning. - * Using suppress, so the warning can still be enabled globally to catch other - * incorrect uses. - */ -#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi, _fj, _fk, _fl) \ - SUPPRESS_SHIFT_WARNING \ - {((((_fa >= 0) && (_fa < 64)) ? (((uint64_t) 1) << _fa) : (uint64_t) 0) | \ - (((_fb >= 0) && (_fb < 64)) ? (((uint64_t) 1) << _fb) : (uint64_t) 0) | \ - (((_fc >= 0) && (_fc < 64)) ? (((uint64_t) 1) << _fc) : (uint64_t) 0) | \ - (((_fd >= 0) && (_fd < 64)) ? (((uint64_t) 1) << _fd) : (uint64_t) 0) | \ - (((_fe >= 0) && (_fe < 64)) ? (((uint64_t) 1) << _fe) : (uint64_t) 0) | \ - (((_ff >= 0) && (_ff < 64)) ? (((uint64_t) 1) << _ff) : (uint64_t) 0) | \ - (((_fg >= 0) && (_fg < 64)) ? (((uint64_t) 1) << _fg) : (uint64_t) 0) | \ - (((_fh >= 0) && (_fh < 64)) ? (((uint64_t) 1) << _fh) : (uint64_t) 0) | \ - (((_fi >= 0) && (_fi < 64)) ? (((uint64_t) 1) << _fi) : (uint64_t) 0) | \ - (((_fj >= 0) && (_fj < 64)) ? (((uint64_t) 1) << _fj) : (uint64_t) 0) | \ - (((_fk >= 0) && (_fk < 64)) ? (((uint64_t) 1) << _fk) : (uint64_t) 0) | \ - (((_fl >= 0) && (_fl < 64)) ? (((uint64_t) 1) << _fl) : (uint64_t) 0) ) \ - ,(((((_fa > 63) && (_fa < 128)) ? (((uint64_t) 1) << (_fa - 64)) : (uint64_t) 0) | \ - (((_fb > 63) && (_fb < 128)) ? (((uint64_t) 1) << (_fb - 64)) : (uint64_t) 0) | \ - (((_fc > 63) && (_fc < 128)) ? (((uint64_t) 1) << (_fc - 64)) : (uint64_t) 0) | \ - (((_fd > 63) && (_fd < 128)) ? (((uint64_t) 1) << (_fd - 64)) : (uint64_t) 0) | \ - (((_fe > 63) && (_fe < 128)) ? (((uint64_t) 1) << (_fe - 64)) : (uint64_t) 0) | \ - (((_ff > 63) && (_ff < 128)) ? (((uint64_t) 1) << (_ff - 64)) : (uint64_t) 0) | \ - (((_fg > 63) && (_fg < 128)) ? (((uint64_t) 1) << (_fg - 64)) : (uint64_t) 0) | \ - (((_fh > 63) && (_fh < 128)) ? (((uint64_t) 1) << (_fh - 64)) : (uint64_t) 0) | \ - (((_fi > 63) && (_fi < 128)) ? (((uint64_t) 1) << (_fi - 64)) : (uint64_t) 0) | \ - (((_fj > 63) && (_fj < 128)) ? (((uint64_t) 1) << (_fj - 64)) : (uint64_t) 0) | \ - (((_fk > 63) && (_fk < 128)) ? (((uint64_t) 1) << (_fk - 64)) : (uint64_t) 0) | \ - (((_fl > 63) && (_fl < 128)) ? (((uint64_t) 1) << (_fl - 64)) : (uint64_t) 0)))} /* * THE following table is the mapping of regdomain pairs specified by @@ -255,15 +178,6 @@ typedef struct reg_domain { uint8_t conformance_test_limit; uint64_t dfsMask; /* DFS bitmask for 5Ghz tables */ uint64_t pscan; /* Bitmask for passive scan */ - uint32_t flags; /* Requirement flags (AdHoc disallow, noise - floor cal needed, etc) */ - uint64_t chan11a[BMLEN]; /* 128 bit bitmask for channel/band selection */ - uint64_t chan11a_turbo[BMLEN]; /* 128 bit bitmask for channel/band select */ - uint64_t chan11a_dyn_turbo[BMLEN]; /* 128 bit mask for chan/band select */ - - uint64_t chan11b[BMLEN]; /* 128 bit bitmask for channel/band selection */ - uint64_t chan11g[BMLEN]; /* 128 bit bitmask for channel/band selection */ - uint64_t chan11g_turbo[BMLEN]; } REG_DOMAIN; struct cmode { @@ -566,8 +480,7 @@ struct ch_params_s { int32_t cds_fill_some_regulatory_info(struct regulatory *reg); void cds_fill_and_send_ctl_to_fw(struct regulatory *reg); int32_t cds_get_country_from_alpha2(uint8_t *alpha2); -void cds_fill_send_ctl_info_to_fw(struct regulatory *reg, uint32_t modesAvail, - uint32_t modeSelect); +void cds_fill_send_ctl_info_to_fw(struct regulatory *reg); void cds_set_wma_dfs_region(uint8_t dfs_region); void cds_set_ch_params(uint8_t ch, uint32_t phy_mode, struct ch_params_s *ch_params); diff --git a/core/cds/inc/cds_regdomain_common.h b/core/cds/inc/cds_regdomain_common.h index d52cdf60f9..ed762a0296 100644 --- a/core/cds/inc/cds_regdomain_common.h +++ b/core/cds/inc/cds_regdomain_common.h @@ -862,377 +862,12 @@ enum { * comments */ -/* - * 5GHz 11A channel tags - */ -enum { - F1_4912_4947, - F1_4915_4925, - F2_4915_4925, - F1_4935_4945, - F2_4935_4945, - F1_4920_4980, - F2_4920_4980, - F1_4942_4987, - F1_4945_4985, - F1_4950_4980, - F1_5032_5057, - F1_5035_5040, - F2_5035_5040, - F1_5035_5045, - F1_5040_5040, - F1_5040_5080, - F2_5040_5080, - F1_5055_5055, - F2_5055_5055, - - F1_5120_5240, - - F1_5170_5230, - F2_5170_5230, - - F1_5180_5240, - F2_5180_5240, - F3_5180_5240, - F4_5180_5240, - F5_5180_5240, - F6_5180_5240, - F7_5180_5240, - F8_5180_5240, - F9_5180_5240, - F10_5180_5240, - - F1_5240_5280, - - F1_5260_5280, - - F1_5260_5320, - F2_5260_5320, - F3_5260_5320, - F4_5260_5320, - F5_5260_5320, - F6_5260_5320, - F7_5260_5320, - - F1_5260_5700, - - F1_5280_5320, - F2_5280_5320, - F1_5500_5560, - - F1_5500_5580, - F2_5500_5580, - - F1_5500_5620, - - F1_5500_5660, - - F1_5500_5720, - F2_5500_5700, - F3_5500_5700, - F4_5500_5700, - F5_5500_5700, - F6_5500_5700, - - F1_5660_5700, - F2_5660_5720, - F3_5660_5720, - - F1_5745_5765, - - F1_5745_5805, - F2_5745_5805, - F3_5745_5805, - F4_5745_5805, - - F1_5745_5825, - F2_5745_5825, - F3_5745_5825, - F4_5745_5825, - F5_5745_5825, - F6_5745_5825, - F7_5745_5825, - F8_5745_5825, - F9_5745_5825, - - F1_5845_5865, - - W1_4920_4980, - W1_5040_5080, - W1_5170_5230, - W1_5180_5240, - W1_5260_5320, - W1_5745_5825, - W1_5500_5700, - A_DEMO_ALL_CHANNELS -}; - -static const REG_DMN_FREQ_BAND reg_dmn5_ghz_freq[] = { - {4915, 4925, 20, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16}, /* F1_4915_4925 */ - {4915, 4925, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16}, /* F2_4915_4925 */ - {4935, 4945, 20, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16}, /* F1_4935_4945 */ - {4935, 4945, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16}, /* F2_4935_4945 */ - {4920, 4980, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 7}, /* F1_4920_4980 */ - {4920, 4980, 20, 0, 20, 20, NO_DFS, PSCAN_MKK2, 7}, /* F2_4920_4980 */ - {4942, 4987, 27, 6, 5, 5, NO_DFS, PSCAN_FCC, 0}, /* F1_4942_4987 */ - {4945, 4985, 30, 6, 10, 5, NO_DFS, PSCAN_FCC, 0}, /* F1_4945_4985 */ - {4950, 4980, 33, 6, 20, 5, NO_DFS, PSCAN_FCC, 0}, /* F1_4950_4980 */ - {5035, 5040, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12}, /* F1_5035_5040 */ - {5035, 5040, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12}, /* F2_5035_5040 */ - {5040, 5040, 20, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12}, /* F1_5040_5040 */ - {5040, 5080, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 2}, /* F1_5040_5080 */ - {5040, 5080, 20, 0, 20, 20, NO_DFS, NO_PSCAN, 6}, /* F2_5040_5080 */ - {5055, 5055, 20, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12}, /* F1_5055_5055 */ - {5055, 5055, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12}, /* F2_5055_5055 */ - - {5120, 5240, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0}, /* F1_5120_5240 */ - - {5170, 5230, 23, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1}, /* F1_5170_5230 */ - {5170, 5230, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1}, /* F2_5170_5230 */ - - {5180, 5240, 15, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 1}, /* F1_5180_5240 */ - {5180, 5240, 17, 6, 20, 20, NO_DFS, NO_PSCAN, 1}, /* F2_5180_5240 */ - {5180, 5240, 18, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 1}, /* F3_5180_5240 */ - {5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 1}, /* F4_5180_5240 */ - {5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 1}, /* F5_5180_5240 */ - {5180, 5240, 23, 6, 20, 20, NO_DFS, PSCAN_FCC, 1}, /* F6_5180_5240 */ - {5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK3, 0}, /* F7_5180_5240 */ - {5180, 5240, 23, 6, 20, 20, NO_DFS, NO_PSCAN, 1}, /* F8_5180_5240 */ - {5180, 5240, 20, 6, 20, 20, NO_DFS, PSCAN_ETSI, 0}, /* F9_5180_5240 */ - {5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 1}, /* F10_5180_5240 */ - - {5240, 5280, 23, 0, 20, 20, DFS_FCC3, PSCAN_FCC | PSCAN_ETSI, 0}, /* F1_5240_5280 */ - - {5260, 5280, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 2}, /* F1_5260_5280 */ - - {5260, 5320, 18, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 2}, /* F1_5260_5320 */ - - {5260, 5320, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, - PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3, 0}, - /* F2_5260_5320 */ - - {5260, 5320, 24, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 2}, /* F3_5260_5320 */ - {5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2}, /* F4_5260_5320 */ - {5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2}, /* F5_5260_5320 */ - {5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 2}, /* F6_5260_5320 */ - {5260, 5320, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, - PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3, 0}, - /* F7_5260_5320 */ - - {5260, 5700, 5, 6, 20, 20, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0}, /* F1_5260_5700 */ - - {5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2}, /* F1_5280_5320 */ - - {5500, 5580, 23, 6, 20, 20, DFS_FCC3, PSCAN_FCC, 4}, /* F1_5500_5580 */ - {5500, 5580, 30, 6, 20, 20, DFS_FCC3, PSCAN_FCC, 4}, /* F2_5500_5580 */ - - {5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 3}, /* F1_5500_5620 */ - - {5500, 5660, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0}, /* F1_5500_5660 */ - - {5500, 5720, 24, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 4}, /* F1_5500_5720 */ - {5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 3}, /* F2_5500_5700 */ - {5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 3}, /* F3_5500_5700 */ - {5500, 5700, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC, 0}, /* F4_5500_5700 */ - {5500, 5700, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0}, /* F5_5500_5700 */ - {5500, 5700, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC, 0}, /* F6_5500_5700 */ - - {5660, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 4}, /* F1_5660_5700 */ - {5660, 5700, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 4}, /* F2_5660_5700 */ - {5660, 5700, 30, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 4}, /* F3_5660_5700 */ - - {5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN, 3}, /* F1_5745_5805 */ - {5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 3}, /* F2_5745_5805 */ - {5745, 5805, 30, 6, 20, 20, NO_DFS, PSCAN_ETSI, 0}, /* F3_5745_5805 */ - {5745, 5805, 20, 0, 20, 20, NO_DFS, NO_PSCAN, 0}, /* F4_5745_5805 */ - - {5745, 5825, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 5}, /* F1_5745_5825 */ - {5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN, 5}, /* F2_5745_5825 */ - {5745, 5825, 20, 0, 20, 20, NO_DFS, NO_PSCAN, 0}, /* F3_5745_5825 */ - {5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0}, /* F4_5745_5825 */ - {5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 5}, /* F5_5745_5825 */ - {5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 5}, /* F6_5745_5825 */ - {5745, 5825, 30, 6, 20, 20, NO_DFS, PSCAN_ETSI, 0}, /* F7_5745_5825 */ - {5745, 5825, 20, 6, 20, 20, NO_DFS, PSCAN_ETSI, 0}, /* F8_5745_5825 */ - - /* - * Below are the world roaming channels - * All WWR domains have no power limit, instead use the card's CTL - * or max power settings. - */ - {4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0}, /* W1_4920_4980 */ - {5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0}, /* W1_5040_5080 */ - {5170, 5230, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0}, /* W1_5170_5230 */ - {5180, 5240, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0}, /* W1_5180_5240 */ - {5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0}, /* W1_5260_5320 */ - {5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0}, /* W1_5745_5825 */ - {5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0}, /* W1_5500_5700 */ - {4920, 6100, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0}, /* A_DEMO_ALL_CHANNELS */ -}; - -/* - * 2GHz 11b channel tags - */ -enum { - F1_2312_2372, - F2_2312_2372, - - F1_2412_2472, - F2_2412_2472, - F3_2412_2472, - F4_2412_2472, - - F1_2412_2462, - F2_2412_2462, - - F1_2432_2442, - - F1_2457_2472, - - F1_2467_2472, - - F1_2484_2484, - F2_2484_2484, - - F1_2512_2732, - - W1_2312_2372, - W1_2412_2412, - W1_2417_2432, - W1_2437_2442, - W1_2447_2457, - W1_2462_2462, - W1_2467_2467, - W2_2467_2467, - W1_2472_2472, - W2_2472_2472, - W1_2484_2484, - W2_2484_2484, -}; - -static const REG_DMN_FREQ_BAND reg_dmn2_ghz_freq[] = { - {2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, /* F1_2312_2372 */ - {2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, /* F2_2312_2372 */ - - {2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, /* F1_2412_2472 */ - {2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 30}, /* F2_2412_2472 */ - {2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 4}, /* F3_2412_2472 */ - {2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0}, /* F4_2412_2472 */ - - {2412, 2462, 30, 6, 20, 5, NO_DFS, NO_PSCAN, 12}, /* F1_2412_2462 */ - {2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 30}, /* F2_2412_2462 */ - - {2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 4}, /* F1_2432_2442 */ - - {2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, /* F1_2457_2472 */ - - {2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 30}, /* F1_2467_2472 */ - - {2484, 2484, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, /* F1_2484_2484 */ - {2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA | PSCAN_MKKA1 | PSCAN_MKKA2, 31}, /* F2_2484_2484 */ - - {2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, /* F1_2512_2732 */ - - /* - * WWR have powers opened up to 20dBm. Limits should often come from CTL/Max powers - */ - - {2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, /* W1_2312_2372 */ - {2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, /* W1_2412_2412 */ - {2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, /* W1_2417_2432 */ - {2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, /* W1_2437_2442 */ - {2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, /* W1_2447_2457 */ - {2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, /* W1_2462_2462 */ - {2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0}, /* W1_2467_2467 */ - {2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0}, /* W2_2467_2467 */ - {2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0}, /* W1_2472_2472 */ - {2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0}, /* W2_2472_2472 */ - {2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0}, /* W1_2484_2484 */ - {2484, 2484, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0}, /* W2_2484_2484 */ -}; - -/* - * 2GHz 11g channel tags - */ - -enum { - G1_2312_2372, - G2_2312_2372, - - G1_2412_2472, - G2_2412_2472, - G3_2412_2472, - G4_2412_2472, - - G1_2412_2462, - G2_2412_2462, - - G1_2432_2442, - - G1_2457_2472, - - G1_2512_2732, - - G1_2467_2472, - G2_2467_2472, - - G1_2484_2484, - - WG1_2312_2372, - WG1_2412_2462, - WG1_2412_2472, - WG2_2412_2472, - G_DEMO_ALMOST_ALL_CHANNELS, - G_DEMO_ALL_CHANNELS, -}; - -static const REG_DMN_FREQ_BAND reg_dmn2_ghz11g_freq[] = { - {2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, /* G1_2312_2372 */ - {2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, /* G2_2312_2372 */ - - {2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, /* G1_2412_2472 */ - {2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G | PSCAN_MKKA2 | PSCAN_MKKA | PSCAN_EXT_CHAN, 30}, /* G2_2412_2472 */ - {2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 4}, /* G3_2412_2472 */ - {2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G | PSCAN_MKKA2 | PSCAN_MKKA | PSCAN_EXT_CHAN, 0}, /* G4_2412_2472 */ - - {2412, 2462, 30, 6, 20, 5, NO_DFS, NO_PSCAN, 12}, /* G1_2412_2462 */ - {2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 30}, /* G2_2412_2462 */ - - {2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 4}, /* G1_2432_2442 */ - - {2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, /* G1_2457_2472 */ - - {2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, /* G1_2512_2732 */ - - {2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 30}, /* G1_2467_2472 */ - {2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G | PSCAN_MKKA2, 0}, /* G2_2467_2472 */ - - {2484, 2484, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, /* G1_2484_2484 */ - /* - * WWR open up the power to 20dBm - */ - - {2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, /* WG1_2312_2372 */ - {2412, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, /* WG1_2412_2462 */ - {2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN | PSCAN_EXT_CHAN, 0}, /* WG1_2412_2472 */ - {2412, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0}, /* WG2_2412_2472 */ - {2312, 2532, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, /* G_DEMO_ALMOST_ALL_CHANNELS */ - {2312, 2732, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, /* G_DEMO_ALL_CHANNELS */ -}; - /* regulatory capabilities */ #define REGDMN_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 #define REGDMN_EEPROM_EEREGCAP_EN_KK_U2 0x0100 #define REGDMN_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 #define REGDMN_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 -static const JAPAN_BANDCHECK j_bandcheck[] = { - {F1_5170_5230, REGDMN_EEPROM_EEREGCAP_EN_KK_U1_ODD}, - {F4_5180_5240, REGDMN_EEPROM_EEREGCAP_EN_KK_U1_EVEN}, - {F2_5260_5320, REGDMN_EEPROM_EEREGCAP_EN_KK_U2}, - {F4_5500_5700, REGDMN_EEPROM_EEREGCAP_EN_KK_MIDBAND} -}; - static const COMMON_MODE_POWER common_mode_pwrtbl[] = { {4900, 5000, 17}, {5000, 5100, 17}, @@ -1243,794 +878,72 @@ static const COMMON_MODE_POWER common_mode_pwrtbl[] = { {5825, 5850, 23} /* Korea */ }; -/* - * 5GHz Turbo (dynamic & static) tags - */ - -enum { - T1_5130_5650, - T1_5150_5670, - - T1_5200_5200, - T2_5200_5200, - T3_5200_5200, - T4_5200_5200, - T5_5200_5200, - T6_5200_5200, - T7_5200_5200, - T8_5200_5200, - - T1_5200_5280, - T2_5200_5280, - T3_5200_5280, - T4_5200_5280, - T5_5200_5280, - T6_5200_5280, - - T1_5200_5240, - T1_5210_5210, - T2_5210_5210, - T3_5210_5210, - T4_5210_5210, - T5_5210_5210, - T6_5210_5210, - T7_5210_5210, - T8_5210_5210, - T9_5210_5210, - T10_5210_5210, - T1_5240_5240, - - T1_5210_5250, - T1_5210_5290, - T2_5210_5290, - T3_5210_5290, - - T1_5280_5280, - T2_5280_5280, - T1_5290_5290, - T2_5290_5290, - T3_5290_5290, - T1_5250_5290, - T2_5250_5290, - T3_5250_5290, - T4_5250_5290, - - T1_5540_5660, - T2_5540_5660, - T3_5540_5660, - T1_5760_5800, - T2_5760_5800, - T3_5760_5800, - T4_5760_5800, - T5_5760_5800, - T6_5760_5800, - T7_5760_5800, - - T1_5765_5805, - T2_5765_5805, - T3_5765_5805, - T4_5765_5805, - T5_5765_5805, - T6_5765_5805, - T7_5765_5805, - T8_5765_5805, - T9_5765_5805, - - WT1_5210_5250, - WT1_5290_5290, - WT1_5540_5660, - WT1_5760_5800, -}; - -/* - * 2GHz Dynamic turbo tags - */ -#ifndef ATH_REMOVE_2G_TURBO_RD_TABLE -enum { - T1_2312_2372, - T1_2437_2437, - T2_2437_2437, - T3_2437_2437, - T1_2512_2732 -}; - -static const REG_DMN_FREQ_BAND reg_dmn2_ghz11g_turbo_freq[] = { - {2312, 2372, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, /* T1_2312_2372 */ - {2437, 2437, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, /* T1_2437_2437 */ - {2437, 2437, 20, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, /* T2_2437_2437 */ - {2437, 2437, 18, 6, 40, 40, NO_DFS, PSCAN_WWR, 0}, /* T3_2437_2437 */ - {2512, 2732, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, /* T1_2512_2732 */ -}; -#endif /* ATH_REMOVE_2G_TURBO_RD_TABLE */ - static const REG_DOMAIN ah_cmn_reg_domains[] = { - {DEBUG_REG_DMN, FCC, DFS_FCC3, NO_PSCAN, NO_REQ, - CHAN_11A_BM(A_DEMO_ALL_CHANNELS, F6_5745_5825, - -1, -1, -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BM(T1_5130_5650, T1_5150_5670, F6_5745_5825, - -1, -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BM(T1_5200_5240, T1_5280_5280, T1_5540_5660, T1_5765_5805, - -1, -1, -1, -1, -1, -1, -1, -1) - BM(F1_2312_2372, F1_2412_2472, F1_2484_2484, F1_2512_2732, - -1, -1, -1, -1, -1, -1, -1, -1), - BM(G_DEMO_ALMOST_ALL_CHANNELS, - G1_2484_2484, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T1_2312_2372, T1_2437_2437, T1_2512_2732, - -1, -1, -1, -1, -1, -1, -1, -1, -1)}, - - {APL1, FCC, NO_DFS, NO_PSCAN, NO_REQ, - BM(F4_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {APL2, FCC, NO_DFS, NO_PSCAN, NO_REQ, - BM(F1_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T2_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {APL3, FCC, DFS_FCC3, PSCAN_FCC, NO_REQ, - BM(F1_5280_5320, F6_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5290_5290, T1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {APL4, FCC, NO_DFS, NO_PSCAN, NO_REQ, - BM(F5_5180_5240, F9_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5210_5210, T3_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5200_5200, T3_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {APL5, FCC, NO_DFS, NO_PSCAN, NO_REQ, - BM(F2_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T4_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T4_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {APL6, ETSI, DFS_ETSI, PSCAN_FCC_T | PSCAN_FCC, NO_REQ, - BM(F9_5180_5240, F2_5260_5320, F3_5745_5825, -1, -1, -1, -1, -1, -1, - -1, -1, -1), - BM(T2_5210_5210, T1_5250_5290, T1_5760_5800, -1, -1, -1, -1, -1, -1, - -1, -1, -1), - BM(T1_5200_5280, T5_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {APL7, FCC, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, NO_REQ, - BM(F2_5280_5320, F2_5500_5580, F3_5660_5720, F7_5745_5825, -1, -1, -1, - -1, -1, -1, -1, -1), - BM(T3_5290_5290, T5_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5540_5660, T6_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {APL8, ETSI, NO_DFS, NO_PSCAN, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - BM(F6_5260_5320, F4_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T2_5290_5290, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5280_5280, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {APL9, ETSI, DFS_ETSI, PSCAN_ETSI, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - BM(F9_5180_5240, F2_5260_5320, F1_5500_5620, F3_5745_5805, -1, -1, -1, - -1, -1, -1, -1, -1), - BM(T3_5290_5290, T5_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5540_5660, T6_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {APL10, ETSI, DFS_ETSI, PSCAN_ETSI, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - BM(F9_5180_5240, F2_5260_5320, F5_5500_5700, F3_5745_5805, -1, -1, -1, - -1, -1, -1, -1, -1), - BM(T3_5290_5290, T5_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5540_5660, T6_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {APL11, ETSI, DFS_ETSI, PSCAN_ETSI, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - BM(F9_5180_5240, F2_5260_5320, F5_5500_5700, F7_5745_5825, - F1_5845_5865, -1, -1, -1, -1, -1, -1, -1), - BM(T3_5290_5290, T5_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5540_5660, T6_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {APL12, ETSI, DFS_ETSI, PSCAN_ETSI, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - BM(F5_5180_5240, F1_5500_5560, F1_5745_5765, -1, -1, -1, -1, -1, -1, - -1, -1, -1), - BM(T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {ETSI1, ETSI, DFS_ETSI, PSCAN_ETSI, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - BM(F2_5180_5240, F2_5260_5320, F2_5500_5700, -1, -1, -1, -1, -1, -1, - -1, -1, -1), - BM(T1_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T2_5200_5280, T2_5540_5660, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {ETSI2, ETSI, DFS_ETSI, PSCAN_ETSI, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - BM(F3_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T3_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T2_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {ETSI3, ETSI, DFS_ETSI, PSCAN_ETSI, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - BM(F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T2_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {ETSI4, ETSI, DFS_ETSI, PSCAN_ETSI, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - BM(F3_5180_5240, F1_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T2_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T3_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {ETSI5, ETSI, DFS_ETSI, PSCAN_ETSI, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - BM(F1_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T4_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T3_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {ETSI6, ETSI, DFS_ETSI, PSCAN_ETSI, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - BM(F5_5180_5240, F1_5260_5280, F3_5500_5700, -1, -1, -1, -1, -1, -1, - -1, -1, -1), - BM(T1_5210_5250, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T4_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {ETSI8, ETSI, DFS_ETSI, PSCAN_ETSI, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - BM(F4_5180_5240, F2_5260_5320, F1_5660_5700, F4_5745_5825, -1, -1, -1, - -1, -1, -1, -1, -1), - BM(T1_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T2_5200_5280, T2_5540_5660, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - BMZERO}, - - {ETSI9, ETSI, DFS_ETSI, PSCAN_ETSI, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - BM(F4_5180_5240, F2_5260_5320, F1_5500_5660, F8_5745_5825, -1, -1, -1, - -1, -1, -1, -1, -1), - BM(T1_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T2_5200_5280, T2_5540_5660, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - BMZERO}, - - {FCC1, FCC, NO_DFS, NO_PSCAN, NO_REQ, - BM(F2_5180_5240, F4_5260_5320, F5_5745_5825, -1, -1, -1, -1, -1, -1, - -1, -1, -1), - BM(T6_5210_5210, T2_5250_5290, T6_5760_5800, -1, -1, -1, -1, -1, -1, - -1, -1, -1), - BM(T1_5200_5240, T2_5280_5280, T7_5765_5805, -1, -1, -1, -1, -1, -1, - -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {FCC2, FCC, NO_DFS, NO_PSCAN, NO_REQ, - BM(F6_5180_5240, F5_5260_5320, F6_5745_5825, -1, -1, -1, -1, -1, -1, - -1, -1, -1), - BM(T7_5210_5210, T3_5250_5290, T2_5760_5800, -1, -1, -1, -1, -1, -1, - -1, -1, -1), - BM(T7_5200_5200, T1_5240_5240, T2_5280_5280, T1_5765_5805, -1, -1, -1, - -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {FCC3, FCC, DFS_FCC3, PSCAN_FCC | PSCAN_FCC_T, NO_REQ, - BM(F2_5180_5240, F3_5260_5320, F1_5500_5720, F5_5745_5825, -1, -1, -1, - -1, -1, -1, -1, -1), - BM(T6_5210_5210, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T4_5200_5200, T8_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - /* - - Bug Fix: EV 98583 Public Safety channel - Exclude the following channel in FCC Public safety domain - Uni-1: 5180, 5200, 5220, 5240 - Uni-2: 5260, 5280, 5300, 5320 - Uni-3: 5745, 5765, 5785, 5805, 5825 - */ - {FCC4, FCC, DFS_FCC3, PSCAN_FCC | PSCAN_FCC_T, NO_REQ, - BM(F1_4942_4987, F1_4945_4985, F1_4950_4980, -1, -1, -1, -1, -1, -1, - -1, -1, -1), - BM(T8_5210_5210, T4_5250_5290, T7_5760_5800, -1, -1, -1, -1, -1, -1, - -1, -1, -1), - BM(T1_5200_5240, T1_5280_5280, T9_5765_5805, -1, -1, -1, -1, -1, -1, - -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {FCC5, FCC, NO_DFS, NO_PSCAN, NO_REQ, - BM(F2_5180_5240, F6_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T6_5210_5210, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T8_5200_5200, T7_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {FCC6, FCC, DFS_FCC3, PSCAN_FCC, NO_REQ, - BM(F8_5180_5240, F5_5260_5320, F1_5500_5580, F2_5660_5720, - F6_5745_5825, -1, -1, -1, -1, -1, -1, -1), - BM(T7_5210_5210, T3_5250_5290, T2_5760_5800, -1, -1, -1, -1, -1, -1, - -1, -1, -1), - BM(T7_5200_5200, T1_5240_5240, T2_5280_5280, T1_5765_5805, -1, -1, -1, - -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {MKK1, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, - BM(F1_5170_5230, F10_5180_5240, F7_5260_5320, F4_5500_5700, -1, -1, -1, - -1, -1, -1, -1, -1), - BM(T7_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T5_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - {MKK2, MKK, DFS_MKK4, PSCAN_MKK2 | PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, - BM(F2_4915_4925, F2_4935_4945, F1_4920_4980, F1_5035_5040, - F2_5055_5055, F1_5040_5080, F1_5170_5230, F10_5180_5240, -1, -1, -1, - -1), - BM(T7_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T5_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - /* UNI-1 even */ - {MKK3, MKK, NO_DFS, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, - BM(F4_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T9_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - /* UNI-1 even + UNI-2 */ - {MKK4, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, - BM(F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T10_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T6_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - /* UNI-1 even + UNI-2 + mid-band */ - {MKK5, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, - BM(F4_5180_5240, F2_5260_5320, F6_5500_5700, -1, -1, -1, -1, -1, -1, - -1, -1, -1), - BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T5_5200_5280, T3_5540_5660, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - /* UNI-1 odd + even */ - {MKK6, MKK, NO_DFS, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB, - BM(F2_5170_5230, F4_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T3_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T6_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - /* UNI-1 odd + UNI-1 even + UNI-2 */ - {MKK7, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, - BM(F2_5170_5230, F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, - -1, -1, -1), - BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T5_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - /* UNI-1 odd + UNI-1 even + UNI-2 + mid-band */ - {MKK8, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, - BM(F2_5170_5230, F4_5180_5240, F2_5260_5320, F6_5500_5700, -1, -1, -1, - -1, -1, -1, -1, -1), - BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T5_5200_5280, T3_5540_5660, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - /* UNI-1 even + 4.9 GHZ */ - {MKK9, MKK, NO_DFS, PSCAN_MKK2 | PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, - BM(F1_4912_4947, F1_5032_5057, F1_4915_4925, F1_4935_4945, - F2_4920_4980, F1_5035_5045, F1_5055_5055, F2_5040_5080, - F4_5180_5240, -1, -1, -1), - BM(T9_5210_5210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5200_5200, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - /* UNI-1 even + UNI-2 + 4.9 GHZ */ - {MKK10, MKK, DFS_MKK4, PSCAN_MKK2 | PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, - BM(F1_4912_4947, F1_5032_5057, F1_4915_4925, F1_4935_4945, - F2_4920_4980, F1_5035_5045, F1_5055_5055, F2_5040_5080, - F4_5180_5240, F2_5260_5320, -1, -1), - BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - /* Japan UNI-1 even + UNI-2 + mid-band + 4.9GHz */ - {MKK11, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, - BM(F1_4912_4947, F1_5032_5057, F1_4915_4925, F1_4935_4945, - F2_4920_4980, F1_5035_5045, F1_5055_5055, F2_5040_5080, - F4_5180_5240, F2_5260_5320, F6_5500_5700, -1), - BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + 4.9GHz */ - {MKK12, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, - BM(F1_4915_4925, F1_4935_4945, F2_4920_4980, F1_5040_5040, - F1_5055_5055, F2_5040_5080, F2_5170_5230, F4_5180_5240, - F2_5260_5320, F6_5500_5700, -1, -1), - BM(T3_5210_5290, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(T1_5200_5280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - /* UNI-1 odd + UNI-1 even + UNI-2 + mid-band */ - {MKK13, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - BM(F2_5170_5230, F7_5180_5240, F2_5260_5320, F6_5500_5700, -1, -1, -1, - -1, -1, -1, -1, -1), - BMZERO, - BMZERO, - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - /* UNI-1 odd + UNI-1 even + 4.9GHz */ - {MKK14, MKK, DFS_MKK4, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB, - BM(F1_4915_4925, F1_4935_4945, F2_4920_4980, F1_5040_5040, - F2_5040_5080, F1_5055_5055, F2_5170_5230, F4_5180_5240, -1, -1, -1, - -1), - BMZERO, - BMZERO, - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - /* UNI-1 odd + UNI-1 even + UNI-2 + 4.9GHz */ - {MKK15, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, - BM(F1_4915_4925, F1_4935_4945, F2_4920_4980, F1_5040_5040, - F2_5040_5080, F1_5055_5055, F2_5170_5230, F4_5180_5240, - F2_5260_5320, -1, -1, -1), - BMZERO, - BMZERO, - BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, - - /*=== 2 GHz ===*/ - - /* Defined here to use when 2G channels are authorised for country K2 */ - {APLD, NO_CTL, NO_DFS, NO_PSCAN, NO_REQ, - CHAN_11A_BMZERO - CHAN_11A_BMZERO - CHAN_11A_BMZERO - BM(F2_2312_2372, F4_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(G2_2312_2372, G4_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BMZERO}, - - {ETSIA, NO_CTL, NO_DFS, PSCAN_ETSIA, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - CHAN_11A_BMZERO CHAN_11A_BMZERO CHAN_11A_BMZERO BM(F1_2457_2472, -1, - -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1), - BM(G1_2457_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {ETSIB, ETSI, NO_DFS, PSCAN_ETSIB, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - CHAN_11A_BMZERO CHAN_11A_BMZERO CHAN_11A_BMZERO BM(F1_2432_2442, -1, - -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1), - BM(G1_2432_2442, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {ETSIC, ETSI, NO_DFS, PSCAN_ETSIC, - DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, - CHAN_11A_BMZERO CHAN_11A_BMZERO CHAN_11A_BMZERO BM(F3_2412_2472, -1, - -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1), - BM(G3_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {FCCA, FCC, NO_DFS, NO_PSCAN, NO_REQ, - CHAN_11A_BMZERO - CHAN_11A_BMZERO - CHAN_11A_BMZERO - BM(F1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(G1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {MKKA, MKK, NO_DFS, - PSCAN_MKKA | PSCAN_MKKA_G | PSCAN_MKKA1 | PSCAN_MKKA1_G | PSCAN_MKKA2 | - PSCAN_MKKA2_G, DISALLOW_ADHOC_11A_TURB, - CHAN_11A_BMZERO CHAN_11A_BMZERO CHAN_11A_BMZERO BM(F2_2412_2462, - F1_2467_2472, - F2_2484_2484, - -1, -1, -1, -1, -1, - -1, -1, -1, -1), - BM(G2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {MKKC, MKK, NO_DFS, NO_PSCAN, NO_REQ, - CHAN_11A_BMZERO - CHAN_11A_BMZERO - CHAN_11A_BMZERO - BM(F2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(G2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {WORLD, ETSI, NO_DFS, NO_PSCAN, NO_REQ, - CHAN_11A_BMZERO - CHAN_11A_BMZERO - CHAN_11A_BMZERO - BM(F4_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - BM(G4_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {WOR0_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, - CHAN_11A_BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, - -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, - -1, -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BMZERO - BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, - W1_2417_2432, - W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, -1, -1), - BM(WG1_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {WOR01_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, - CHAN_11A_BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, - W1_5500_5700, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, - -1, -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BMZERO - BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432, - W1_2447_2457, - -1, -1, -1, -1, -1, -1, -1), - BM(WG1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {WOR02_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, - CHAN_11A_BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, - W1_5500_5700, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, - -1, -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BMZERO - BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, - W1_2417_2432, - W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), - BM(WG1_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {EU1_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, - CHAN_11A_BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, - W1_5500_5700, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, - -1, -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BMZERO - BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W2_2472_2472, - W1_2417_2432, - W1_2447_2457, W2_2467_2467, -1, -1, -1, -1, -1), - BM(WG2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {WOR1_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, - CHAN_11A_BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, - W1_5500_5700, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BMZERO - CHAN_11A_BMZERO - BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, - W1_2417_2432, - W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, -1, -1), - BM(WG1_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {WOR2_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, - CHAN_11A_BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, - W1_5500_5700, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, - -1, -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BMZERO - BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, - W1_2417_2432, - W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, -1, -1), - BM(WG1_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {WOR3_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, - CHAN_11A_BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, - -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, - -1, -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BMZERO - BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, - W1_2417_2432, - W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), - BM(WG1_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {WOR4_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, - CHAN_11A_BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, - -1, -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, - -1, -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BMZERO - BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432, - W1_2447_2457, - -1, -1, -1, -1, -1, -1, -1), - BM(WG1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {WOR5_ETSIC, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, - CHAN_11A_BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, - -1, -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BMZERO - CHAN_11A_BMZERO - BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, - W1_2417_2432, - W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), - BM(WG1_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {WOR9_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, - CHAN_11A_BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, - -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, - -1, -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BMZERO - BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432, - W1_2447_2457, - -1, -1, -1, -1, -1, -1, -1), - BM(WG1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {WORA_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, - CHAN_11A_BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, - -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BMZERO - CHAN_11A_BMZERO - BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, - W1_2417_2432, - W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), - BM(WG1_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {WORB_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, - CHAN_11A_BM(W1_5260_5320, W1_5180_5240, W1_5500_5700, - -1, -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BMZERO - CHAN_11A_BMZERO - BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, - W1_2417_2432, - W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), - BM(WG1_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {WORC_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, - CHAN_11A_BM(W1_5260_5320, W1_5180_5240, W1_5500_5700, W1_5745_5825, - -1, -1, -1, -1, -1, -1, -1, -1) - CHAN_11A_BMZERO - CHAN_11A_BMZERO - BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, - W1_2417_2432, - W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), - BM(WG1_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), - CHAN_TURBO_G_BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1)}, - - {NULL1, NO_CTL, NO_DFS, NO_PSCAN, NO_REQ, - CHAN_11A_BMZERO CHAN_11A_BMZERO CHAN_11A_BMZERO BMZERO, - BMZERO, - CHAN_TURBO_G_BMZERO}, -}; - -static const struct cmode modes[] = { - {REGDMN_MODE_TURBO, IEEE80211_CHAN_ST}, /* TURBO means 11a Static Turbo */ - {REGDMN_MODE_11A, IEEE80211_CHAN_A}, - {REGDMN_MODE_11B, IEEE80211_CHAN_B}, - {REGDMN_MODE_11G, IEEE80211_CHAN_PUREG}, - {REGDMN_MODE_11G_TURBO, IEEE80211_CHAN_108G}, - {REGDMN_MODE_11A_TURBO, IEEE80211_CHAN_108A}, - {REGDMN_MODE_11NG_HT20, IEEE80211_CHAN_11NG_HT20}, - {REGDMN_MODE_11NG_HT40PLUS, IEEE80211_CHAN_11NG_HT40PLUS}, - {REGDMN_MODE_11NG_HT40MINUS, IEEE80211_CHAN_11NG_HT40MINUS}, - {REGDMN_MODE_11NA_HT20, IEEE80211_CHAN_11NA_HT20}, - {REGDMN_MODE_11NA_HT40PLUS, IEEE80211_CHAN_11NA_HT40PLUS}, - {REGDMN_MODE_11NA_HT40MINUS, IEEE80211_CHAN_11NA_HT40MINUS}, - {REGDMN_MODE_11AC_VHT20, IEEE80211_CHAN_11AC_VHT20}, - {REGDMN_MODE_11AC_VHT40PLUS, IEEE80211_CHAN_11AC_VHT40PLUS}, - {REGDMN_MODE_11AC_VHT40MINUS, IEEE80211_CHAN_11AC_VHT40MINUS}, - {REGDMN_MODE_11AC_VHT80, IEEE80211_CHAN_11AC_VHT80}, - {REGDMN_MODE_11AC_VHT20_2G, IEEE80211_CHAN_11AC_VHT20_2G}, - {REGDMN_MODE_11AC_VHT40_2G, IEEE80211_CHAN_11AC_VHT40_2G}, - {REGDMN_MODE_11AC_VHT80_2G, IEEE80211_CHAN_11AC_VHT80_2G}, + {DEBUG_REG_DMN, FCC, DFS_FCC3}, + {APL1, FCC, NO_DFS}, + {APL2, FCC, NO_DFS}, + {APL3, FCC, DFS_FCC3}, + {APL4, FCC, NO_DFS}, + {APL5, FCC, NO_DFS}, + {APL6, ETSI, DFS_ETSI}, + {APL7, FCC, DFS_FCC3}, + {APL8, ETSI, NO_DFS}, + {APL9, ETSI, DFS_ETSI}, + {APL10, ETSI, DFS_ETSI}, + {APL11, ETSI, DFS_ETSI}, + {APL12, ETSI, DFS_ETSI}, + {ETSI1, ETSI, DFS_ETSI}, + {ETSI2, ETSI, DFS_ETSI}, + {ETSI3, ETSI, DFS_ETSI}, + {ETSI4, ETSI, DFS_ETSI}, + {ETSI5, ETSI, DFS_ETSI}, + {ETSI6, ETSI, DFS_ETSI}, + {ETSI8, ETSI, DFS_ETSI}, + {ETSI9, ETSI, DFS_ETSI}, + {FCC1, FCC, NO_DFS}, + {FCC2, FCC, NO_DFS}, + {FCC3, FCC, DFS_FCC3}, + {FCC4, FCC, DFS_FCC3}, + {FCC5, FCC, NO_DFS}, + {FCC6, FCC, DFS_FCC3}, + {MKK1, MKK, DFS_MKK4}, + {MKK2, MKK, DFS_MKK4}, + {MKK3, MKK, NO_DFS}, + {MKK4, MKK, DFS_MKK4}, + {MKK5, MKK, DFS_MKK4}, + {MKK6, MKK, NO_DFS}, + {MKK7, MKK, DFS_MKK4}, + {MKK8, MKK, DFS_MKK4}, + {MKK9, MKK, NO_DFS}, + {MKK10, MKK, DFS_MKK4}, + {MKK11, MKK, DFS_MKK4}, + {MKK12, MKK, DFS_MKK4}, + {MKK13, MKK, DFS_MKK4}, + {MKK14, MKK, DFS_MKK4}, + {MKK15, MKK, DFS_MKK4}, + {APLD, NO_CTL, NO_DFS}, + {ETSIA, NO_CTL, NO_DFS}, + {ETSIB, ETSI, NO_DFS}, + {ETSIC, ETSI, NO_DFS}, + {FCCA, FCC, NO_DFS}, + {MKKA, MKK, NO_DFS}, + {MKKC, MKK, NO_DFS}, + {WORLD, ETSI, NO_DFS}, + {WOR0_WORLD, NO_CTL, DFS_FCC3}, + {WOR01_WORLD, NO_CTL, DFS_FCC3}, + {WOR02_WORLD, NO_CTL, DFS_FCC3}, + {EU1_WORLD, NO_CTL, DFS_FCC3}, + {WOR1_WORLD, NO_CTL, DFS_FCC3}, + {WOR2_WORLD, NO_CTL, DFS_FCC3}, + {WOR3_WORLD, NO_CTL, DFS_FCC3}, + {WOR4_WORLD, NO_CTL, DFS_FCC3}, + {WOR5_ETSIC, NO_CTL, DFS_FCC3}, + {WOR9_WORLD, NO_CTL, DFS_FCC3}, + {WORA_WORLD, NO_CTL, DFS_FCC3}, + {WORB_WORLD, NO_CTL, DFS_FCC3}, + {WORC_WORLD, NO_CTL, DFS_FCC3}, + {NULL1, NO_CTL, NO_DFS}, }; typedef enum offset { diff --git a/core/cds/src/cds_regdomain.c b/core/cds/src/cds_regdomain.c index 0507496b95..67765ba910 100644 --- a/core/cds/src/cds_regdomain.c +++ b/core/cds/src/cds_regdomain.c @@ -372,93 +372,11 @@ int32_t regdmn_get_regdmn_for_country(uint8_t *alpha2) return -1; } -/* - * Test to see if the bitmask array is all zeros - */ -static bool is_chan_bit_mask_zero(const uint64_t *bitmask) -{ - int i; - - for (i = 0; i < BMLEN; i++) { - if (bitmask[i] != 0) - return false; - } - return true; -} - -/* - * Return the mask of available modes based on the hardware - * capabilities and the specified country code and reg domain. - */ -static uint32_t regdmn_getwmodesnreg(uint32_t modesAvail, - const COUNTRY_CODE_TO_ENUM_RD *country, - const REG_DOMAIN *rd5GHz) -{ - - /* Check country regulations for allowed modes */ - if ((modesAvail & (REGDMN_MODE_11A_TURBO | REGDMN_MODE_TURBO)) && - (!country->allow11aTurbo)) - modesAvail &= ~(REGDMN_MODE_11A_TURBO | REGDMN_MODE_TURBO); - - if ((modesAvail & REGDMN_MODE_11G_TURBO) && (!country->allow11gTurbo)) - modesAvail &= ~REGDMN_MODE_11G_TURBO; - - if ((modesAvail & REGDMN_MODE_11G) && (!country->allow11g)) - modesAvail &= ~REGDMN_MODE_11G; - - if ((modesAvail & REGDMN_MODE_11A) && - (is_chan_bit_mask_zero(rd5GHz->chan11a))) - modesAvail &= ~REGDMN_MODE_11A; - - if ((modesAvail & REGDMN_MODE_11NG_HT20) && (!country->allow11ng20)) - modesAvail &= ~REGDMN_MODE_11NG_HT20; - - if ((modesAvail & REGDMN_MODE_11NA_HT20) && (!country->allow11na20)) - modesAvail &= ~REGDMN_MODE_11NA_HT20; - - if ((modesAvail & REGDMN_MODE_11NG_HT40PLUS) && (!country->allow11ng40)) - modesAvail &= ~REGDMN_MODE_11NG_HT40PLUS; - - if ((modesAvail & REGDMN_MODE_11NG_HT40MINUS) && - (!country->allow11ng40)) - modesAvail &= ~REGDMN_MODE_11NG_HT40MINUS; - - if ((modesAvail & REGDMN_MODE_11NA_HT40PLUS) && (!country->allow11na40)) - modesAvail &= ~REGDMN_MODE_11NA_HT40PLUS; - - if ((modesAvail & REGDMN_MODE_11NA_HT40MINUS) && - (!country->allow11na40)) - modesAvail &= ~REGDMN_MODE_11NA_HT40MINUS; - - if ((modesAvail & REGDMN_MODE_11AC_VHT20) && (!country->allow11na20)) - modesAvail &= ~REGDMN_MODE_11AC_VHT20; - - if ((modesAvail & REGDMN_MODE_11AC_VHT40PLUS) && - (!country->allow11na40)) - modesAvail &= ~REGDMN_MODE_11AC_VHT40PLUS; - - if ((modesAvail & REGDMN_MODE_11AC_VHT40MINUS) && - (!country->allow11na40)) - modesAvail &= ~REGDMN_MODE_11AC_VHT40MINUS; - - if ((modesAvail & REGDMN_MODE_11AC_VHT80) && (!country->allow11na80)) - modesAvail &= ~REGDMN_MODE_11AC_VHT80; - - if ((modesAvail & REGDMN_MODE_11AC_VHT20_2G) && (!country->allow11ng20)) - modesAvail &= ~REGDMN_MODE_11AC_VHT20_2G; - - return modesAvail; -} - -void cds_fill_send_ctl_info_to_fw(struct regulatory *reg, uint32_t modesAvail, - uint32_t modeSelect) +void cds_fill_send_ctl_info_to_fw(struct regulatory *reg) { const REG_DOMAIN *regdomain2G = NULL; const REG_DOMAIN *regdomain5G = NULL; - int8_t ctl_2g, ctl_5g, ctl; - const REG_DOMAIN *rd = NULL; - const struct cmode *cm; - const COUNTRY_CODE_TO_ENUM_RD *country; + int8_t ctl_2g, ctl_5g; const REG_DMN_PAIR_MAPPING *regpair; regpair = reg->regpair; @@ -478,70 +396,6 @@ void cds_fill_send_ctl_info_to_fw(struct regulatory *reg, uint32_t modesAvail, ctl_2g = regdomain2G->conformance_test_limit; ctl_5g = regdomain5G->conformance_test_limit; - /* find second nible of CTL */ - country = find_country(reg->country_code); - if (country != NULL) - modesAvail = - regdmn_getwmodesnreg(modesAvail, country, regdomain5G); - - for (cm = modes; cm < &modes[QDF_ARRAY_SIZE(modes)]; cm++) { - - if ((cm->mode & modeSelect) == 0) - continue; - - if ((cm->mode & modesAvail) == 0) - continue; - - switch (cm->mode) { - case REGDMN_MODE_TURBO: - rd = regdomain5G; - ctl = rd->conformance_test_limit | CTL_TURBO; - break; - case REGDMN_MODE_11A: - case REGDMN_MODE_11NA_HT20: - case REGDMN_MODE_11NA_HT40PLUS: - case REGDMN_MODE_11NA_HT40MINUS: - case REGDMN_MODE_11AC_VHT20: - case REGDMN_MODE_11AC_VHT40PLUS: - case REGDMN_MODE_11AC_VHT40MINUS: - case REGDMN_MODE_11AC_VHT80: - rd = regdomain5G; - ctl = rd->conformance_test_limit; - break; - case REGDMN_MODE_11B: - rd = regdomain2G; - ctl = rd->conformance_test_limit | CTL_11B; - break; - case REGDMN_MODE_11G: - case REGDMN_MODE_11NG_HT20: - case REGDMN_MODE_11NG_HT40PLUS: - case REGDMN_MODE_11NG_HT40MINUS: - case REGDMN_MODE_11AC_VHT20_2G: - case REGDMN_MODE_11AC_VHT40_2G: - case REGDMN_MODE_11AC_VHT80_2G: - rd = regdomain2G; - ctl = rd->conformance_test_limit | CTL_11G; - break; - case REGDMN_MODE_11G_TURBO: - rd = regdomain2G; - ctl = rd->conformance_test_limit | CTL_108G; - break; - case REGDMN_MODE_11A_TURBO: - rd = regdomain5G; - ctl = rd->conformance_test_limit | CTL_108G; - break; - default: - qdf_print(KERN_ERR "%s: Unkonwn HAL mode 0x%x\n", - __func__, cm->mode); - continue; - } - - if (rd == regdomain2G) - ctl_2g = ctl; - - if (rd == regdomain5G) - ctl_5g = ctl; - } /* save the ctl information for future reference */ reg->ctl_5g = ctl_5g; @@ -573,17 +427,13 @@ void cds_set_wma_dfs_region(uint8_t dfs_region) void cds_fill_and_send_ctl_to_fw(struct regulatory *reg) { tp_wma_handle wma = cds_get_context(QDF_MODULE_ID_WMA); - uint32_t modeSelect = 0xFFFFFFFF; if (!wma) { WMA_LOGE("%s: Unable to get WMA handle", __func__); return; } - wma_get_modeselect(wma, &modeSelect); - - cds_fill_send_ctl_info_to_fw(reg, wma->reg_cap.wireless_modes, - modeSelect); + cds_fill_send_ctl_info_to_fw(reg); return; } diff --git a/core/wma/inc/wma.h b/core/wma/inc/wma.h index 5b9ba1f34b..07486eec7d 100644 --- a/core/wma/inc/wma.h +++ b/core/wma/inc/wma.h @@ -1417,8 +1417,6 @@ extern void cds_wma_complete_cback(void *p_cds_context); extern void wma_send_regdomain_info_to_fw(uint32_t reg_dmn, uint16_t regdmn2G, uint16_t regdmn5G, int8_t ctl2G, int8_t ctl5G); -void wma_get_modeselect(tp_wma_handle wma, uint32_t *modeSelect); - /** * enum frame_index - Frame index * @GENERIC_NODOWNLD_NOACK_COMP_INDEX: Frame index for no download comp no ack diff --git a/core/wma/src/wma_features.c b/core/wma/src/wma_features.c index 1130abda7d..2e1f65d372 100644 --- a/core/wma/src/wma_features.c +++ b/core/wma/src/wma_features.c @@ -5602,45 +5602,6 @@ QDF_STATUS wma_resume_target(WMA_HANDLE handle) return ret; } -/** - * wma_get_modeselect() - get modeSelect flag based on phy_capability - * @wma: wma handle - * @modeSelect: mode Select - * - * Return: none - */ -void wma_get_modeselect(tp_wma_handle wma, uint32_t *modeSelect) -{ - - switch (wma->phy_capability) { - case WMI_11G_CAPABILITY: - case WMI_11NG_CAPABILITY: - *modeSelect &= ~(REGDMN_MODE_11A | REGDMN_MODE_TURBO | - REGDMN_MODE_108A | REGDMN_MODE_11A_HALF_RATE | - REGDMN_MODE_11A_QUARTER_RATE | - REGDMN_MODE_11NA_HT20 | - REGDMN_MODE_11NA_HT40PLUS | - REGDMN_MODE_11NA_HT40MINUS | - REGDMN_MODE_11AC_VHT20 | - REGDMN_MODE_11AC_VHT40PLUS | - REGDMN_MODE_11AC_VHT40MINUS | - REGDMN_MODE_11AC_VHT80); - break; - case WMI_11A_CAPABILITY: - case WMI_11NA_CAPABILITY: - case WMI_11AC_CAPABILITY: - *modeSelect &= ~(REGDMN_MODE_11B | REGDMN_MODE_11G | - REGDMN_MODE_108G | REGDMN_MODE_11NG_HT20 | - REGDMN_MODE_11NG_HT40PLUS | - REGDMN_MODE_11NG_HT40MINUS | - REGDMN_MODE_11AC_VHT20_2G | - REGDMN_MODE_11AC_VHT40_2G | - REGDMN_MODE_11AC_VHT80_2G); - break; - } -} - - #ifdef FEATURE_WLAN_TDLS /** * wma_tdls_event_handler() - handle TDLS event