fw-api: New HW header files for version R102 for QCA6290
New hardware header files needed for DV release version R102. This is required to support emulation version E3 for all platforms. Change-Id: Id40755ffba391fcbe246de07f4a0880ca18fc565 CRs-Fixed: 1105853
This commit is contained in:
Dhanashri Atre
committed by
Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
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커밋
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559
hw/qca6290/v1/reo_descriptor_threshold_reached_status.h
Executable file
559
hw/qca6290/v1/reo_descriptor_threshold_reached_status.h
Executable file
@@ -0,0 +1,559 @@
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/*
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* Copyright (c) 2017 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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//
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// DO NOT EDIT! This file is automatically generated
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// These definitions are tied to a particular hardware layout
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#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
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#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#include "uniform_reo_status_header.h"
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// ################ START SUMMARY #################
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//
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// Dword Fields
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// 0-1 struct uniform_reo_status_header status_header;
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// 2 threshold_index[1:0], reserved_2[31:2]
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// 3 link_descriptor_counter0[23:0], reserved_3[31:24]
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// 4 link_descriptor_counter1[23:0], reserved_4[31:24]
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// 5 link_descriptor_counter2[23:0], reserved_5[31:24]
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// 6 link_descriptor_counter_sum[25:0], reserved_6[31:26]
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// 7 reserved_7[31:0]
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// 8 reserved_8[31:0]
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// 9 reserved_9a[31:0]
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// 10 reserved_10a[31:0]
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// 11 reserved_11a[31:0]
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// 12 reserved_12a[31:0]
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// 13 reserved_13a[31:0]
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// 14 reserved_14a[31:0]
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// 15 reserved_15a[31:0]
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// 16 reserved_16a[31:0]
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// 17 reserved_17a[31:0]
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// 18 reserved_18a[31:0]
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// 19 reserved_19a[31:0]
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// 20 reserved_20a[31:0]
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// 21 reserved_21a[31:0]
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// 22 reserved_22a[31:0]
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// 23 reserved_23a[31:0]
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// 24 reserved_24a[27:0], looping_count[31:28]
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//
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// ################ END SUMMARY #################
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#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 25
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struct reo_descriptor_threshold_reached_status {
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struct uniform_reo_status_header status_header;
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uint32_t threshold_index : 2, //[1:0]
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reserved_2 : 30; //[31:2]
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uint32_t link_descriptor_counter0 : 24, //[23:0]
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reserved_3 : 8; //[31:24]
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uint32_t link_descriptor_counter1 : 24, //[23:0]
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reserved_4 : 8; //[31:24]
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uint32_t link_descriptor_counter2 : 24, //[23:0]
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reserved_5 : 8; //[31:24]
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uint32_t link_descriptor_counter_sum : 26, //[25:0]
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reserved_6 : 6; //[31:26]
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uint32_t reserved_7 : 32; //[31:0]
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uint32_t reserved_8 : 32; //[31:0]
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uint32_t reserved_9a : 32; //[31:0]
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uint32_t reserved_10a : 32; //[31:0]
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uint32_t reserved_11a : 32; //[31:0]
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uint32_t reserved_12a : 32; //[31:0]
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uint32_t reserved_13a : 32; //[31:0]
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uint32_t reserved_14a : 32; //[31:0]
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uint32_t reserved_15a : 32; //[31:0]
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uint32_t reserved_16a : 32; //[31:0]
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uint32_t reserved_17a : 32; //[31:0]
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uint32_t reserved_18a : 32; //[31:0]
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uint32_t reserved_19a : 32; //[31:0]
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uint32_t reserved_20a : 32; //[31:0]
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uint32_t reserved_21a : 32; //[31:0]
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uint32_t reserved_22a : 32; //[31:0]
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uint32_t reserved_23a : 32; //[31:0]
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uint32_t reserved_24a : 28, //[27:0]
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looping_count : 4; //[31:28]
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};
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/*
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struct uniform_reo_status_header status_header
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Consumer: SW
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Producer: REO
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Details that can link this status with the original
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command. It also contains info on how long REO took to
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execute this command.
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threshold_index
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The index of the threshold register whose value got
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reached
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<enum 0 reo_desc_counter0_threshold>
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<enum 1 reo_desc_counter1_threshold>
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<enum 2 reo_desc_counter2_threshold>
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<enum 3 reo_desc_counter_sum_threshold>
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<legal all>
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reserved_2
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<legal 0>
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link_descriptor_counter0
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Value of this counter at generation of this message
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<legal all>
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reserved_3
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<legal 0>
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link_descriptor_counter1
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Value of this counter at generation of this message
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<legal all>
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reserved_4
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<legal 0>
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link_descriptor_counter2
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Value of this counter at generation of this message
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<legal all>
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reserved_5
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<legal 0>
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link_descriptor_counter_sum
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Value of this counter at generation of this message
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<legal all>
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reserved_6
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<legal 0>
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reserved_7
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<legal 0>
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reserved_8
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<legal 0>
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reserved_9a
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<legal 0>
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reserved_10a
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<legal 0>
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reserved_11a
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<legal 0>
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reserved_12a
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<legal 0>
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reserved_13a
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<legal 0>
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reserved_14a
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<legal 0>
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reserved_15a
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<legal 0>
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reserved_16a
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<legal 0>
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reserved_17a
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<legal 0>
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reserved_18a
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<legal 0>
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reserved_19a
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<legal 0>
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reserved_20a
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<legal 0>
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reserved_21a
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<legal 0>
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reserved_22a
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<legal 0>
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reserved_23a
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<legal 0>
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reserved_24a
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<legal 0>
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looping_count
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A count value that indicates the number of times the
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producer of entries into this Ring has looped around the
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ring.
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At initialization time, this value is set to 0. On the
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first loop, this value is set to 1. After the max value is
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reached allowed by the number of bits for this field, the
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count value continues with 0 again.
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In case SW is the consumer of the ring entries, it can
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use this field to figure out up to where the producer of
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entries has created new entries. This eliminates the need to
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check where the head pointer' of the ring is located once
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the SW starts processing an interrupt indicating that new
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entries have been put into this ring...
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Also note that SW if it wants only needs to look at the
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LSB bit of this count value.
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<legal all>
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*/
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
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/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX
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The index of the threshold register whose value got
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reached
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<enum 0 reo_desc_counter0_threshold>
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<enum 1 reo_desc_counter1_threshold>
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<enum 2 reo_desc_counter2_threshold>
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<enum 3 reo_desc_counter_sum_threshold>
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<legal all>
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*/
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_OFFSET 0x00000008
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_LSB 0
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_MASK 0x00000003
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/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2
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<legal 0>
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*/
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_OFFSET 0x00000008
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_LSB 2
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_MASK 0xfffffffc
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/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0
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Value of this counter at generation of this message
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<legal all>
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*/
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000c
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_LSB 0
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff
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/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3
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<legal 0>
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*/
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_OFFSET 0x0000000c
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_LSB 24
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_MASK 0xff000000
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/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1
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Value of this counter at generation of this message
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<legal all>
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*/
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000010
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_LSB 0
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff
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/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4
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<legal 0>
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*/
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_OFFSET 0x00000010
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_LSB 24
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_MASK 0xff000000
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/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2
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Value of this counter at generation of this message
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<legal all>
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*/
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000014
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_LSB 0
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff
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/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5
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<legal 0>
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*/
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_OFFSET 0x00000014
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_LSB 24
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_MASK 0xff000000
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/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM
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Value of this counter at generation of this message
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<legal all>
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*/
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x00000018
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff
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/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6
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<legal 0>
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*/
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_OFFSET 0x00000018
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_LSB 26
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_MASK 0xfc000000
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/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7
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<legal 0>
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*/
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_OFFSET 0x0000001c
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_LSB 0
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_MASK 0xffffffff
|
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/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8
|
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<legal 0>
|
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*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_OFFSET 0x00000020
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#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_MASK 0xffffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_OFFSET 0x00000024
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_OFFSET 0x00000028
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_OFFSET 0x00000030
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_OFFSET 0x00000034
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_OFFSET 0x00000038
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_OFFSET 0x00000040
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_OFFSET 0x00000044
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_OFFSET 0x00000048
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_OFFSET 0x00000050
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_OFFSET 0x00000054
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_OFFSET 0x00000058
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_OFFSET 0x00000060
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_MASK 0x0fffffff
|
||||
|
||||
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT
|
||||
|
||||
A count value that indicates the number of times the
|
||||
producer of entries into this Ring has looped around the
|
||||
ring.
|
||||
|
||||
At initialization time, this value is set to 0. On the
|
||||
first loop, this value is set to 1. After the max value is
|
||||
reached allowed by the number of bits for this field, the
|
||||
count value continues with 0 again.
|
||||
|
||||
|
||||
|
||||
In case SW is the consumer of the ring entries, it can
|
||||
use this field to figure out up to where the producer of
|
||||
entries has created new entries. This eliminates the need to
|
||||
check where the head pointer' of the ring is located once
|
||||
the SW starts processing an interrupt indicating that new
|
||||
entries have been put into this ring...
|
||||
|
||||
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_LSB 28
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
|
||||
|
||||
|
||||
#endif // _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
|
||||
489
hw/qca6290/v1/reo_flush_cache.h
Executable file
489
hw/qca6290/v1/reo_flush_cache.h
Executable file
@@ -0,0 +1,489 @@
|
||||
/*
|
||||
* Copyright (c) 2017 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
//
|
||||
// DO NOT EDIT! This file is automatically generated
|
||||
// These definitions are tied to a particular hardware layout
|
||||
|
||||
|
||||
#ifndef _REO_FLUSH_CACHE_H_
|
||||
#define _REO_FLUSH_CACHE_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_reo_cmd_header.h"
|
||||
|
||||
// ################ START SUMMARY #################
|
||||
//
|
||||
// Dword Fields
|
||||
// 0 struct uniform_reo_cmd_header cmd_header;
|
||||
// 1 flush_addr_31_0[31:0]
|
||||
// 2 flush_addr_39_32[7:0], forward_all_mpdus_in_queue[8], release_cache_block_index[9], cache_block_resource_index[11:10], flush_without_invalidate[12], block_cache_usage_after_flush[13], flush_entire_cache[14], reserved_2b[31:15]
|
||||
// 3 reserved_3a[31:0]
|
||||
// 4 reserved_4a[31:0]
|
||||
// 5 reserved_5a[31:0]
|
||||
// 6 reserved_6a[31:0]
|
||||
// 7 reserved_7a[31:0]
|
||||
// 8 reserved_8a[31:0]
|
||||
//
|
||||
// ################ END SUMMARY #################
|
||||
|
||||
#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9
|
||||
|
||||
struct reo_flush_cache {
|
||||
struct uniform_reo_cmd_header cmd_header;
|
||||
uint32_t flush_addr_31_0 : 32; //[31:0]
|
||||
uint32_t flush_addr_39_32 : 8, //[7:0]
|
||||
forward_all_mpdus_in_queue : 1, //[8]
|
||||
release_cache_block_index : 1, //[9]
|
||||
cache_block_resource_index : 2, //[11:10]
|
||||
flush_without_invalidate : 1, //[12]
|
||||
block_cache_usage_after_flush : 1, //[13]
|
||||
flush_entire_cache : 1, //[14]
|
||||
reserved_2b : 17; //[31:15]
|
||||
uint32_t reserved_3a : 32; //[31:0]
|
||||
uint32_t reserved_4a : 32; //[31:0]
|
||||
uint32_t reserved_5a : 32; //[31:0]
|
||||
uint32_t reserved_6a : 32; //[31:0]
|
||||
uint32_t reserved_7a : 32; //[31:0]
|
||||
uint32_t reserved_8a : 32; //[31:0]
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
struct uniform_reo_cmd_header cmd_header
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
Details for command execution tracking purposes.
|
||||
|
||||
flush_addr_31_0
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
Address (lower 32 bits) of the descriptor to flush
|
||||
|
||||
<legal all>
|
||||
|
||||
flush_addr_39_32
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
Address (upper 8 bits) of the descriptor to flush
|
||||
|
||||
<legal all>
|
||||
|
||||
forward_all_mpdus_in_queue
|
||||
|
||||
Is only allowed to be set when the flush address
|
||||
corresponds with a REO descriptor.
|
||||
|
||||
|
||||
|
||||
When set, REO shall first forward all the MPDUs held in
|
||||
the indicated re-order queue, before flushing the descriptor
|
||||
from the cache.
|
||||
|
||||
<legal all>
|
||||
|
||||
release_cache_block_index
|
||||
|
||||
Field not valid when Flush_entire_cache is set.
|
||||
|
||||
|
||||
|
||||
If SW has previously used a blocking resource that it
|
||||
now wants to re-use for this command, this bit shall be set.
|
||||
It prevents SW from having to send a separate
|
||||
REO_UNBLOCK_CACHE command.
|
||||
|
||||
|
||||
|
||||
When set, HW will first release the blocking resource
|
||||
(indicated in field 'Cache_block_resouce_index') before this
|
||||
command gets executed.
|
||||
|
||||
If that resource was already unblocked, this will be
|
||||
considered an error. This command will not be executed, and
|
||||
an error shall be returned.
|
||||
|
||||
<legal all>
|
||||
|
||||
cache_block_resource_index
|
||||
|
||||
Field not valid when Flush_entire_cache is set.
|
||||
|
||||
|
||||
|
||||
Indicates which of the four blocking resources in REO
|
||||
will be assigned for managing the blocking of this
|
||||
(descriptor) address
|
||||
|
||||
<legal all>
|
||||
|
||||
flush_without_invalidate
|
||||
|
||||
Field not valid when Flush_entire_cache is set.
|
||||
|
||||
|
||||
|
||||
When set, REO shall flush the cache line contents from
|
||||
the cache, but there is NO need to invalidate the cache line
|
||||
entry... The contents in the cache can be maintained. This
|
||||
feature can be used by SW (and DV) to get a current snapshot
|
||||
of the contents in the cache
|
||||
|
||||
|
||||
|
||||
<legal all>
|
||||
|
||||
block_cache_usage_after_flush
|
||||
|
||||
Field not valid when Flush_entire_cache is set.
|
||||
|
||||
|
||||
|
||||
When set, REO shall block any cache accesses to this
|
||||
address till explicitly unblocked.
|
||||
|
||||
|
||||
|
||||
Whenever SW sets this bit, SW shall also set bit
|
||||
'Forward_all_mpdus_in_queue' to ensure all packets are
|
||||
flushed out in order to make sure this queue desc is not in
|
||||
one of the aging link lists. In case SW does not want to
|
||||
flush the MPDUs in the queue, see the recipe description
|
||||
below this TLV definition.
|
||||
|
||||
|
||||
|
||||
The 'blocking' index to be used for this is indicated in
|
||||
field 'cache_block_resource_index'. If SW had previously
|
||||
used this blocking resource and was not freed up yet, SW
|
||||
shall first unblock that index (by setting bit
|
||||
Release_cache_block_index) or use an unblock command.
|
||||
|
||||
|
||||
|
||||
If the resource indicated here was already blocked (and
|
||||
did not get unblocked in this command), it is considered an
|
||||
error scenario...
|
||||
|
||||
No flush shall happen. The status for this command shall
|
||||
indicate error.
|
||||
|
||||
|
||||
|
||||
<legal all>
|
||||
|
||||
flush_entire_cache
|
||||
|
||||
When set, the entire cache shall be flushed. The entire
|
||||
cache will also remain blocked, till the
|
||||
'REO_UNBLOCK_COMMAND' is received with bit unblock type set
|
||||
to unblock_cache. All other fields in this command are to be
|
||||
ignored.
|
||||
|
||||
|
||||
|
||||
Note that flushing the entire cache has no changes to
|
||||
the current settings of the blocking resource settings
|
||||
|
||||
|
||||
|
||||
<legal all>
|
||||
|
||||
reserved_2b
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_3a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_4a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_5a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_6a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_7a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_8a
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
|
||||
#define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0
|
||||
#define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
Address (lower 32 bits) of the descriptor to flush
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET 0x00000004
|
||||
#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB 0
|
||||
#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
Address (upper 8 bits) of the descriptor to flush
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB 0
|
||||
#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK 0x000000ff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE
|
||||
|
||||
Is only allowed to be set when the flush address
|
||||
corresponds with a REO descriptor.
|
||||
|
||||
|
||||
|
||||
When set, REO shall first forward all the MPDUs held in
|
||||
the indicated re-order queue, before flushing the descriptor
|
||||
from the cache.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8
|
||||
#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100
|
||||
|
||||
/* Description REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX
|
||||
|
||||
Field not valid when Flush_entire_cache is set.
|
||||
|
||||
|
||||
|
||||
If SW has previously used a blocking resource that it
|
||||
now wants to re-use for this command, this bit shall be set.
|
||||
It prevents SW from having to send a separate
|
||||
REO_UNBLOCK_CACHE command.
|
||||
|
||||
|
||||
|
||||
When set, HW will first release the blocking resource
|
||||
(indicated in field 'Cache_block_resouce_index') before this
|
||||
command gets executed.
|
||||
|
||||
If that resource was already unblocked, this will be
|
||||
considered an error. This command will not be executed, and
|
||||
an error shall be returned.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB 9
|
||||
#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200
|
||||
|
||||
/* Description REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX
|
||||
|
||||
Field not valid when Flush_entire_cache is set.
|
||||
|
||||
|
||||
|
||||
Indicates which of the four blocking resources in REO
|
||||
will be assigned for managing the blocking of this
|
||||
(descriptor) address
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB 10
|
||||
#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00
|
||||
|
||||
/* Description REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE
|
||||
|
||||
Field not valid when Flush_entire_cache is set.
|
||||
|
||||
|
||||
|
||||
When set, REO shall flush the cache line contents from
|
||||
the cache, but there is NO need to invalidate the cache line
|
||||
entry... The contents in the cache can be maintained. This
|
||||
feature can be used by SW (and DV) to get a current snapshot
|
||||
of the contents in the cache
|
||||
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB 12
|
||||
#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000
|
||||
|
||||
/* Description REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH
|
||||
|
||||
Field not valid when Flush_entire_cache is set.
|
||||
|
||||
|
||||
|
||||
When set, REO shall block any cache accesses to this
|
||||
address till explicitly unblocked.
|
||||
|
||||
|
||||
|
||||
Whenever SW sets this bit, SW shall also set bit
|
||||
'Forward_all_mpdus_in_queue' to ensure all packets are
|
||||
flushed out in order to make sure this queue desc is not in
|
||||
one of the aging link lists. In case SW does not want to
|
||||
flush the MPDUs in the queue, see the recipe description
|
||||
below this TLV definition.
|
||||
|
||||
|
||||
|
||||
The 'blocking' index to be used for this is indicated in
|
||||
field 'cache_block_resource_index'. If SW had previously
|
||||
used this blocking resource and was not freed up yet, SW
|
||||
shall first unblock that index (by setting bit
|
||||
Release_cache_block_index) or use an unblock command.
|
||||
|
||||
|
||||
|
||||
If the resource indicated here was already blocked (and
|
||||
did not get unblocked in this command), it is considered an
|
||||
error scenario...
|
||||
|
||||
No flush shall happen. The status for this command shall
|
||||
indicate error.
|
||||
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13
|
||||
#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000
|
||||
|
||||
/* Description REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE
|
||||
|
||||
When set, the entire cache shall be flushed. The entire
|
||||
cache will also remain blocked, till the
|
||||
'REO_UNBLOCK_COMMAND' is received with bit unblock type set
|
||||
to unblock_cache. All other fields in this command are to be
|
||||
ignored.
|
||||
|
||||
|
||||
|
||||
Note that flushing the entire cache has no changes to
|
||||
the current settings of the blocking resource settings
|
||||
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB 14
|
||||
#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK 0x00004000
|
||||
|
||||
/* Description REO_FLUSH_CACHE_2_RESERVED_2B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_2_RESERVED_2B_LSB 15
|
||||
#define REO_FLUSH_CACHE_2_RESERVED_2B_MASK 0xffff8000
|
||||
|
||||
/* Description REO_FLUSH_CACHE_3_RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define REO_FLUSH_CACHE_3_RESERVED_3A_LSB 0
|
||||
#define REO_FLUSH_CACHE_3_RESERVED_3A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_4_RESERVED_4A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET 0x00000010
|
||||
#define REO_FLUSH_CACHE_4_RESERVED_4A_LSB 0
|
||||
#define REO_FLUSH_CACHE_4_RESERVED_4A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_5_RESERVED_5A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET 0x00000014
|
||||
#define REO_FLUSH_CACHE_5_RESERVED_5A_LSB 0
|
||||
#define REO_FLUSH_CACHE_5_RESERVED_5A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_6_RESERVED_6A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET 0x00000018
|
||||
#define REO_FLUSH_CACHE_6_RESERVED_6A_LSB 0
|
||||
#define REO_FLUSH_CACHE_6_RESERVED_6A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_7_RESERVED_7A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET 0x0000001c
|
||||
#define REO_FLUSH_CACHE_7_RESERVED_7A_LSB 0
|
||||
#define REO_FLUSH_CACHE_7_RESERVED_7A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_8_RESERVED_8A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET 0x00000020
|
||||
#define REO_FLUSH_CACHE_8_RESERVED_8A_LSB 0
|
||||
#define REO_FLUSH_CACHE_8_RESERVED_8A_MASK 0xffffffff
|
||||
|
||||
|
||||
#endif // _REO_FLUSH_CACHE_H_
|
||||
698
hw/qca6290/v1/reo_flush_cache_status.h
Executable file
698
hw/qca6290/v1/reo_flush_cache_status.h
Executable file
@@ -0,0 +1,698 @@
|
||||
/*
|
||||
* Copyright (c) 2017 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
//
|
||||
// DO NOT EDIT! This file is automatically generated
|
||||
// These definitions are tied to a particular hardware layout
|
||||
|
||||
|
||||
#ifndef _REO_FLUSH_CACHE_STATUS_H_
|
||||
#define _REO_FLUSH_CACHE_STATUS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_reo_status_header.h"
|
||||
|
||||
// ################ START SUMMARY #################
|
||||
//
|
||||
// Dword Fields
|
||||
// 0-1 struct uniform_reo_status_header status_header;
|
||||
// 2 error_detected[0], block_error_details[2:1], reserved_2a[7:3], cache_controller_flush_status_hit[8], cache_controller_flush_status_desc_type[11:9], cache_controller_flush_status_client_id[15:12], cache_controller_flush_status_error[17:16], cache_controller_flush_count[25:18], reserved_2b[31:26]
|
||||
// 3 reserved_3a[31:0]
|
||||
// 4 reserved_4a[31:0]
|
||||
// 5 reserved_5a[31:0]
|
||||
// 6 reserved_6a[31:0]
|
||||
// 7 reserved_7a[31:0]
|
||||
// 8 reserved_8a[31:0]
|
||||
// 9 reserved_9a[31:0]
|
||||
// 10 reserved_10a[31:0]
|
||||
// 11 reserved_11a[31:0]
|
||||
// 12 reserved_12a[31:0]
|
||||
// 13 reserved_13a[31:0]
|
||||
// 14 reserved_14a[31:0]
|
||||
// 15 reserved_15a[31:0]
|
||||
// 16 reserved_16a[31:0]
|
||||
// 17 reserved_17a[31:0]
|
||||
// 18 reserved_18a[31:0]
|
||||
// 19 reserved_19a[31:0]
|
||||
// 20 reserved_20a[31:0]
|
||||
// 21 reserved_21a[31:0]
|
||||
// 22 reserved_22a[31:0]
|
||||
// 23 reserved_23a[31:0]
|
||||
// 24 reserved_24a[27:0], looping_count[31:28]
|
||||
//
|
||||
// ################ END SUMMARY #################
|
||||
|
||||
#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 25
|
||||
|
||||
struct reo_flush_cache_status {
|
||||
struct uniform_reo_status_header status_header;
|
||||
uint32_t error_detected : 1, //[0]
|
||||
block_error_details : 2, //[2:1]
|
||||
reserved_2a : 5, //[7:3]
|
||||
cache_controller_flush_status_hit: 1, //[8]
|
||||
cache_controller_flush_status_desc_type: 3, //[11:9]
|
||||
cache_controller_flush_status_client_id: 4, //[15:12]
|
||||
cache_controller_flush_status_error: 2, //[17:16]
|
||||
cache_controller_flush_count : 8, //[25:18]
|
||||
reserved_2b : 6; //[31:26]
|
||||
uint32_t reserved_3a : 32; //[31:0]
|
||||
uint32_t reserved_4a : 32; //[31:0]
|
||||
uint32_t reserved_5a : 32; //[31:0]
|
||||
uint32_t reserved_6a : 32; //[31:0]
|
||||
uint32_t reserved_7a : 32; //[31:0]
|
||||
uint32_t reserved_8a : 32; //[31:0]
|
||||
uint32_t reserved_9a : 32; //[31:0]
|
||||
uint32_t reserved_10a : 32; //[31:0]
|
||||
uint32_t reserved_11a : 32; //[31:0]
|
||||
uint32_t reserved_12a : 32; //[31:0]
|
||||
uint32_t reserved_13a : 32; //[31:0]
|
||||
uint32_t reserved_14a : 32; //[31:0]
|
||||
uint32_t reserved_15a : 32; //[31:0]
|
||||
uint32_t reserved_16a : 32; //[31:0]
|
||||
uint32_t reserved_17a : 32; //[31:0]
|
||||
uint32_t reserved_18a : 32; //[31:0]
|
||||
uint32_t reserved_19a : 32; //[31:0]
|
||||
uint32_t reserved_20a : 32; //[31:0]
|
||||
uint32_t reserved_21a : 32; //[31:0]
|
||||
uint32_t reserved_22a : 32; //[31:0]
|
||||
uint32_t reserved_23a : 32; //[31:0]
|
||||
uint32_t reserved_24a : 28, //[27:0]
|
||||
looping_count : 4; //[31:28]
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
struct uniform_reo_status_header status_header
|
||||
|
||||
Consumer: SW
|
||||
|
||||
Producer: REO
|
||||
|
||||
|
||||
|
||||
Details that can link this status with the original
|
||||
command. It also contains info on how long REO took to
|
||||
execute this command.
|
||||
|
||||
error_detected
|
||||
|
||||
Status for blocking resource handling
|
||||
|
||||
|
||||
|
||||
0: No error has been detected while executing this
|
||||
command
|
||||
|
||||
1: an error in the blocking resource management was
|
||||
detected
|
||||
|
||||
See field 'Block_error_details'
|
||||
|
||||
block_error_details
|
||||
|
||||
Field only valid when 'Error_detected' is set.
|
||||
|
||||
0: no blocking related error found
|
||||
|
||||
1: blocking resource was already in use
|
||||
|
||||
2: resource that was asked to be unblocked, was not
|
||||
blocked
|
||||
|
||||
<legal 0-2>
|
||||
|
||||
reserved_2a
|
||||
|
||||
<legal 0>
|
||||
|
||||
cache_controller_flush_status_hit
|
||||
|
||||
The status that the cache controller returned for
|
||||
executing the flush command
|
||||
|
||||
|
||||
|
||||
descriptor hit
|
||||
|
||||
1 = hit
|
||||
|
||||
0 = miss
|
||||
|
||||
<legal all>
|
||||
|
||||
cache_controller_flush_status_desc_type
|
||||
|
||||
The status that the cache controller returned for
|
||||
executing the flush command
|
||||
|
||||
Descriptor type
|
||||
|
||||
FLOW_QUEUE_DESCRIPTOR
|
||||
3'd0
|
||||
|
||||
|
||||
<legal all>
|
||||
|
||||
cache_controller_flush_status_client_id
|
||||
|
||||
The status that the cache controller returned for
|
||||
executing the flush command
|
||||
|
||||
|
||||
|
||||
client ID
|
||||
|
||||
Module who made flush the request
|
||||
|
||||
|
||||
|
||||
In REO, this is always set to 0
|
||||
|
||||
<legal 0>
|
||||
|
||||
cache_controller_flush_status_error
|
||||
|
||||
The status that the cache controller returned for
|
||||
executing the flush command
|
||||
|
||||
|
||||
|
||||
Error condition
|
||||
|
||||
2'b00: No error found
|
||||
|
||||
2'b01: HW IF still busy
|
||||
|
||||
2'b10: Line is currently locked. Used for the one line
|
||||
flush command.
|
||||
|
||||
2'b11: At least one line is currently still locked. Used
|
||||
for the cache flush command.
|
||||
|
||||
|
||||
|
||||
<legal all>
|
||||
|
||||
cache_controller_flush_count
|
||||
|
||||
The number of lines that were actually flushed out.
|
||||
|
||||
<legal all>
|
||||
|
||||
reserved_2b
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_3a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_4a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_5a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_6a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_7a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_8a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_9a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_10a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_11a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_12a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_13a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_14a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_15a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_16a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_17a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_18a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_19a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_20a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_21a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_22a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_23a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_24a
|
||||
|
||||
<legal 0>
|
||||
|
||||
looping_count
|
||||
|
||||
A count value that indicates the number of times the
|
||||
producer of entries into this Ring has looped around the
|
||||
ring.
|
||||
|
||||
At initialization time, this value is set to 0. On the
|
||||
first loop, this value is set to 1. After the max value is
|
||||
reached allowed by the number of bits for this field, the
|
||||
count value continues with 0 again.
|
||||
|
||||
|
||||
|
||||
In case SW is the consumer of the ring entries, it can
|
||||
use this field to figure out up to where the producer of
|
||||
entries has created new entries. This eliminates the need to
|
||||
check where the head pointer' of the ring is located once
|
||||
the SW starts processing an interrupt indicating that new
|
||||
entries have been put into this ring...
|
||||
|
||||
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
|
||||
#define REO_FLUSH_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
|
||||
#define REO_FLUSH_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
|
||||
#define REO_FLUSH_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
|
||||
#define REO_FLUSH_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
|
||||
#define REO_FLUSH_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED
|
||||
|
||||
Status for blocking resource handling
|
||||
|
||||
|
||||
|
||||
0: No error has been detected while executing this
|
||||
command
|
||||
|
||||
1: an error in the blocking resource management was
|
||||
detected
|
||||
|
||||
See field 'Block_error_details'
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS
|
||||
|
||||
Field only valid when 'Error_detected' is set.
|
||||
|
||||
0: no blocking related error found
|
||||
|
||||
1: blocking resource was already in use
|
||||
|
||||
2: resource that was asked to be unblocked, was not
|
||||
blocked
|
||||
|
||||
<legal 0-2>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_LSB 1
|
||||
#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_MASK 0x00000006
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_2_RESERVED_2A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_LSB 3
|
||||
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_MASK 0x000000f8
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT
|
||||
|
||||
The status that the cache controller returned for
|
||||
executing the flush command
|
||||
|
||||
|
||||
|
||||
descriptor hit
|
||||
|
||||
1 = hit
|
||||
|
||||
0 = miss
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8
|
||||
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE
|
||||
|
||||
The status that the cache controller returned for
|
||||
executing the flush command
|
||||
|
||||
Descriptor type
|
||||
|
||||
FLOW_QUEUE_DESCRIPTOR
|
||||
3'd0
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9
|
||||
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID
|
||||
|
||||
The status that the cache controller returned for
|
||||
executing the flush command
|
||||
|
||||
|
||||
|
||||
client ID
|
||||
|
||||
Module who made flush the request
|
||||
|
||||
|
||||
|
||||
In REO, this is always set to 0
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12
|
||||
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR
|
||||
|
||||
The status that the cache controller returned for
|
||||
executing the flush command
|
||||
|
||||
|
||||
|
||||
Error condition
|
||||
|
||||
2'b00: No error found
|
||||
|
||||
2'b01: HW IF still busy
|
||||
|
||||
2'b10: Line is currently locked. Used for the one line
|
||||
flush command.
|
||||
|
||||
2'b11: At least one line is currently still locked. Used
|
||||
for the cache flush command.
|
||||
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16
|
||||
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT
|
||||
|
||||
The number of lines that were actually flushed out.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18
|
||||
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x03fc0000
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_2_RESERVED_2B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_OFFSET 0x00000008
|
||||
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_LSB 26
|
||||
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_MASK 0xfc000000
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_3_RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_4_RESERVED_4A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
|
||||
#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_5_RESERVED_5A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
|
||||
#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_6_RESERVED_6A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
|
||||
#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_7_RESERVED_7A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
|
||||
#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_8_RESERVED_8A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
|
||||
#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_9_RESERVED_9A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
|
||||
#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_10_RESERVED_10A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
|
||||
#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_11_RESERVED_11A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
|
||||
#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_12_RESERVED_12A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
|
||||
#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_13_RESERVED_13A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
|
||||
#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_14_RESERVED_14A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
|
||||
#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_15_RESERVED_15A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
|
||||
#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_16_RESERVED_16A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
|
||||
#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_17_RESERVED_17A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
|
||||
#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_18_RESERVED_18A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
|
||||
#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_19_RESERVED_19A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
|
||||
#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_20_RESERVED_20A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
|
||||
#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_21_RESERVED_21A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
|
||||
#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_22_RESERVED_22A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
|
||||
#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_23_RESERVED_23A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
|
||||
#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_24_RESERVED_24A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
|
||||
#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
|
||||
|
||||
/* Description REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT
|
||||
|
||||
A count value that indicates the number of times the
|
||||
producer of entries into this Ring has looped around the
|
||||
ring.
|
||||
|
||||
At initialization time, this value is set to 0. On the
|
||||
first loop, this value is set to 1. After the max value is
|
||||
reached allowed by the number of bits for this field, the
|
||||
count value continues with 0 again.
|
||||
|
||||
|
||||
|
||||
In case SW is the consumer of the ring entries, it can
|
||||
use this field to figure out up to where the producer of
|
||||
entries has created new entries. This eliminates the need to
|
||||
check where the head pointer' of the ring is located once
|
||||
the SW starts processing an interrupt indicating that new
|
||||
entries have been put into this ring...
|
||||
|
||||
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
|
||||
#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_LSB 28
|
||||
#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
|
||||
|
||||
|
||||
#endif // _REO_FLUSH_CACHE_STATUS_H_
|
||||
281
hw/qca6290/v1/reo_flush_queue.h
Executable file
281
hw/qca6290/v1/reo_flush_queue.h
Executable file
@@ -0,0 +1,281 @@
|
||||
/*
|
||||
* Copyright (c) 2017 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
//
|
||||
// DO NOT EDIT! This file is automatically generated
|
||||
// These definitions are tied to a particular hardware layout
|
||||
|
||||
|
||||
#ifndef _REO_FLUSH_QUEUE_H_
|
||||
#define _REO_FLUSH_QUEUE_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_reo_cmd_header.h"
|
||||
|
||||
// ################ START SUMMARY #################
|
||||
//
|
||||
// Dword Fields
|
||||
// 0 struct uniform_reo_cmd_header cmd_header;
|
||||
// 1 flush_desc_addr_31_0[31:0]
|
||||
// 2 flush_desc_addr_39_32[7:0], block_desc_addr_usage_after_flush[8], block_resource_index[10:9], reserved_2a[31:11]
|
||||
// 3 reserved_3a[31:0]
|
||||
// 4 reserved_4a[31:0]
|
||||
// 5 reserved_5a[31:0]
|
||||
// 6 reserved_6a[31:0]
|
||||
// 7 reserved_7a[31:0]
|
||||
// 8 reserved_8a[31:0]
|
||||
//
|
||||
// ################ END SUMMARY #################
|
||||
|
||||
#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9
|
||||
|
||||
struct reo_flush_queue {
|
||||
struct uniform_reo_cmd_header cmd_header;
|
||||
uint32_t flush_desc_addr_31_0 : 32; //[31:0]
|
||||
uint32_t flush_desc_addr_39_32 : 8, //[7:0]
|
||||
block_desc_addr_usage_after_flush: 1, //[8]
|
||||
block_resource_index : 2, //[10:9]
|
||||
reserved_2a : 21; //[31:11]
|
||||
uint32_t reserved_3a : 32; //[31:0]
|
||||
uint32_t reserved_4a : 32; //[31:0]
|
||||
uint32_t reserved_5a : 32; //[31:0]
|
||||
uint32_t reserved_6a : 32; //[31:0]
|
||||
uint32_t reserved_7a : 32; //[31:0]
|
||||
uint32_t reserved_8a : 32; //[31:0]
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
struct uniform_reo_cmd_header cmd_header
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
Details for command execution tracking purposes.
|
||||
|
||||
flush_desc_addr_31_0
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
Address (lower 32 bits) of the descriptor to flush
|
||||
|
||||
<legal all>
|
||||
|
||||
flush_desc_addr_39_32
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
Address (upper 8 bits) of the descriptor to flush
|
||||
|
||||
<legal all>
|
||||
|
||||
block_desc_addr_usage_after_flush
|
||||
|
||||
When set, REO shall not re-fetch this address till SW
|
||||
explicitly unblocked this address
|
||||
|
||||
|
||||
|
||||
If the blocking resource was already used, this command
|
||||
shall fail and an error is reported
|
||||
|
||||
|
||||
|
||||
<legal all>
|
||||
|
||||
block_resource_index
|
||||
|
||||
Field only valid when 'Block_desc_addr_usage_after_flush
|
||||
' is set.
|
||||
|
||||
|
||||
|
||||
Indicates which of the four blocking resources in REO
|
||||
will be assigned for managing the blocking of this address.
|
||||
|
||||
<legal all>
|
||||
|
||||
reserved_2a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_3a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_4a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_5a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_6a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_7a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_8a
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
|
||||
#define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0
|
||||
#define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
Address (lower 32 bits) of the descriptor to flush
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004
|
||||
#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB 0
|
||||
#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
Address (upper 8 bits) of the descriptor to flush
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008
|
||||
#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB 0
|
||||
#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH
|
||||
|
||||
When set, REO shall not re-fetch this address till SW
|
||||
explicitly unblocked this address
|
||||
|
||||
|
||||
|
||||
If the blocking resource was already used, this command
|
||||
shall fail and an error is reported
|
||||
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008
|
||||
#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8
|
||||
#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX
|
||||
|
||||
Field only valid when 'Block_desc_addr_usage_after_flush
|
||||
' is set.
|
||||
|
||||
|
||||
|
||||
Indicates which of the four blocking resources in REO
|
||||
will be assigned for managing the blocking of this address.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008
|
||||
#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB 9
|
||||
#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK 0x00000600
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_2_RESERVED_2A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET 0x00000008
|
||||
#define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB 11
|
||||
#define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK 0xfffff800
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_3_RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_4_RESERVED_4A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET 0x00000010
|
||||
#define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_5_RESERVED_5A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET 0x00000014
|
||||
#define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_6_RESERVED_6A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET 0x00000018
|
||||
#define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_7_RESERVED_7A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET 0x0000001c
|
||||
#define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_8_RESERVED_8A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET 0x00000020
|
||||
#define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK 0xffffffff
|
||||
|
||||
|
||||
#endif // _REO_FLUSH_QUEUE_H_
|
||||
473
hw/qca6290/v1/reo_flush_queue_status.h
Executable file
473
hw/qca6290/v1/reo_flush_queue_status.h
Executable file
@@ -0,0 +1,473 @@
|
||||
/*
|
||||
* Copyright (c) 2017 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
//
|
||||
// DO NOT EDIT! This file is automatically generated
|
||||
// These definitions are tied to a particular hardware layout
|
||||
|
||||
|
||||
#ifndef _REO_FLUSH_QUEUE_STATUS_H_
|
||||
#define _REO_FLUSH_QUEUE_STATUS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_reo_status_header.h"
|
||||
|
||||
// ################ START SUMMARY #################
|
||||
//
|
||||
// Dword Fields
|
||||
// 0-1 struct uniform_reo_status_header status_header;
|
||||
// 2 error_detected[0], reserved_2a[31:1]
|
||||
// 3 reserved_3a[31:0]
|
||||
// 4 reserved_4a[31:0]
|
||||
// 5 reserved_5a[31:0]
|
||||
// 6 reserved_6a[31:0]
|
||||
// 7 reserved_7a[31:0]
|
||||
// 8 reserved_8a[31:0]
|
||||
// 9 reserved_9a[31:0]
|
||||
// 10 reserved_10a[31:0]
|
||||
// 11 reserved_11a[31:0]
|
||||
// 12 reserved_12a[31:0]
|
||||
// 13 reserved_13a[31:0]
|
||||
// 14 reserved_14a[31:0]
|
||||
// 15 reserved_15a[31:0]
|
||||
// 16 reserved_16a[31:0]
|
||||
// 17 reserved_17a[31:0]
|
||||
// 18 reserved_18a[31:0]
|
||||
// 19 reserved_19a[31:0]
|
||||
// 20 reserved_20a[31:0]
|
||||
// 21 reserved_21a[31:0]
|
||||
// 22 reserved_22a[31:0]
|
||||
// 23 reserved_23a[31:0]
|
||||
// 24 reserved_24a[27:0], looping_count[31:28]
|
||||
//
|
||||
// ################ END SUMMARY #################
|
||||
|
||||
#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 25
|
||||
|
||||
struct reo_flush_queue_status {
|
||||
struct uniform_reo_status_header status_header;
|
||||
uint32_t error_detected : 1, //[0]
|
||||
reserved_2a : 31; //[31:1]
|
||||
uint32_t reserved_3a : 32; //[31:0]
|
||||
uint32_t reserved_4a : 32; //[31:0]
|
||||
uint32_t reserved_5a : 32; //[31:0]
|
||||
uint32_t reserved_6a : 32; //[31:0]
|
||||
uint32_t reserved_7a : 32; //[31:0]
|
||||
uint32_t reserved_8a : 32; //[31:0]
|
||||
uint32_t reserved_9a : 32; //[31:0]
|
||||
uint32_t reserved_10a : 32; //[31:0]
|
||||
uint32_t reserved_11a : 32; //[31:0]
|
||||
uint32_t reserved_12a : 32; //[31:0]
|
||||
uint32_t reserved_13a : 32; //[31:0]
|
||||
uint32_t reserved_14a : 32; //[31:0]
|
||||
uint32_t reserved_15a : 32; //[31:0]
|
||||
uint32_t reserved_16a : 32; //[31:0]
|
||||
uint32_t reserved_17a : 32; //[31:0]
|
||||
uint32_t reserved_18a : 32; //[31:0]
|
||||
uint32_t reserved_19a : 32; //[31:0]
|
||||
uint32_t reserved_20a : 32; //[31:0]
|
||||
uint32_t reserved_21a : 32; //[31:0]
|
||||
uint32_t reserved_22a : 32; //[31:0]
|
||||
uint32_t reserved_23a : 32; //[31:0]
|
||||
uint32_t reserved_24a : 28, //[27:0]
|
||||
looping_count : 4; //[31:28]
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
struct uniform_reo_status_header status_header
|
||||
|
||||
Consumer: SW
|
||||
|
||||
Producer: REO
|
||||
|
||||
|
||||
|
||||
Details that can link this status with the original
|
||||
command. It also contains info on how long REO took to
|
||||
execute this command.
|
||||
|
||||
error_detected
|
||||
|
||||
Status of the blocking resource
|
||||
|
||||
0: No error has been detected while executing this
|
||||
command
|
||||
|
||||
1: Error detected: The resource to be used for blocking
|
||||
was already in use.
|
||||
|
||||
reserved_2a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_3a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_4a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_5a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_6a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_7a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_8a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_9a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_10a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_11a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_12a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_13a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_14a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_15a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_16a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_17a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_18a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_19a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_20a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_21a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_22a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_23a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_24a
|
||||
|
||||
<legal 0>
|
||||
|
||||
looping_count
|
||||
|
||||
A count value that indicates the number of times the
|
||||
producer of entries into this Ring has looped around the
|
||||
ring.
|
||||
|
||||
At initialization time, this value is set to 0. On the
|
||||
first loop, this value is set to 1. After the max value is
|
||||
reached allowed by the number of bits for this field, the
|
||||
count value continues with 0 again.
|
||||
|
||||
|
||||
|
||||
In case SW is the consumer of the ring entries, it can
|
||||
use this field to figure out up to where the producer of
|
||||
entries has created new entries. This eliminates the need to
|
||||
check where the head pointer' of the ring is located once
|
||||
the SW starts processing an interrupt indicating that new
|
||||
entries have been put into this ring...
|
||||
|
||||
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
|
||||
#define REO_FLUSH_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
|
||||
#define REO_FLUSH_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
|
||||
#define REO_FLUSH_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
|
||||
#define REO_FLUSH_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
|
||||
#define REO_FLUSH_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED
|
||||
|
||||
Status of the blocking resource
|
||||
|
||||
0: No error has been detected while executing this
|
||||
command
|
||||
|
||||
1: Error detected: The resource to be used for blocking
|
||||
was already in use.
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
|
||||
#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_MASK 0x00000001
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
|
||||
#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_LSB 1
|
||||
#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_MASK 0xfffffffe
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
|
||||
#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
|
||||
#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
|
||||
#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
|
||||
#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
|
||||
#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
|
||||
#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
|
||||
#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
|
||||
#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
|
||||
#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
|
||||
#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
|
||||
#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
|
||||
#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
|
||||
#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
|
||||
#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
|
||||
#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
|
||||
#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
|
||||
#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
|
||||
#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
|
||||
#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
|
||||
#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
|
||||
#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
|
||||
|
||||
/* Description REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT
|
||||
|
||||
A count value that indicates the number of times the
|
||||
producer of entries into this Ring has looped around the
|
||||
ring.
|
||||
|
||||
At initialization time, this value is set to 0. On the
|
||||
first loop, this value is set to 1. After the max value is
|
||||
reached allowed by the number of bits for this field, the
|
||||
count value continues with 0 again.
|
||||
|
||||
|
||||
|
||||
In case SW is the consumer of the ring entries, it can
|
||||
use this field to figure out up to where the producer of
|
||||
entries has created new entries. This eliminates the need to
|
||||
check where the head pointer' of the ring is located once
|
||||
the SW starts processing an interrupt indicating that new
|
||||
entries have been put into this ring...
|
||||
|
||||
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
|
||||
#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28
|
||||
#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
|
||||
|
||||
|
||||
#endif // _REO_FLUSH_QUEUE_STATUS_H_
|
||||
320
hw/qca6290/v1/reo_flush_timeout_list.h
Executable file
320
hw/qca6290/v1/reo_flush_timeout_list.h
Executable file
@@ -0,0 +1,320 @@
|
||||
/*
|
||||
* Copyright (c) 2017 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
//
|
||||
// DO NOT EDIT! This file is automatically generated
|
||||
// These definitions are tied to a particular hardware layout
|
||||
|
||||
|
||||
#ifndef _REO_FLUSH_TIMEOUT_LIST_H_
|
||||
#define _REO_FLUSH_TIMEOUT_LIST_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_reo_cmd_header.h"
|
||||
|
||||
// ################ START SUMMARY #################
|
||||
//
|
||||
// Dword Fields
|
||||
// 0 struct uniform_reo_cmd_header cmd_header;
|
||||
// 1 ac_timout_list[1:0], reserved_1[31:2]
|
||||
// 2 minimum_release_desc_count[15:0], minimum_forward_buf_count[31:16]
|
||||
// 3 reserved_3a[31:0]
|
||||
// 4 reserved_4a[31:0]
|
||||
// 5 reserved_5a[31:0]
|
||||
// 6 reserved_6a[31:0]
|
||||
// 7 reserved_7a[31:0]
|
||||
// 8 reserved_8a[31:0]
|
||||
//
|
||||
// ################ END SUMMARY #################
|
||||
|
||||
#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9
|
||||
|
||||
struct reo_flush_timeout_list {
|
||||
struct uniform_reo_cmd_header cmd_header;
|
||||
uint32_t ac_timout_list : 2, //[1:0]
|
||||
reserved_1 : 30; //[31:2]
|
||||
uint32_t minimum_release_desc_count : 16, //[15:0]
|
||||
minimum_forward_buf_count : 16; //[31:16]
|
||||
uint32_t reserved_3a : 32; //[31:0]
|
||||
uint32_t reserved_4a : 32; //[31:0]
|
||||
uint32_t reserved_5a : 32; //[31:0]
|
||||
uint32_t reserved_6a : 32; //[31:0]
|
||||
uint32_t reserved_7a : 32; //[31:0]
|
||||
uint32_t reserved_8a : 32; //[31:0]
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
struct uniform_reo_cmd_header cmd_header
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
Details for command execution tracking purposes.
|
||||
|
||||
ac_timout_list
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
The AC_timeout list to be used for this command
|
||||
|
||||
<legal all>
|
||||
|
||||
reserved_1
|
||||
|
||||
<legal 0>
|
||||
|
||||
minimum_release_desc_count
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
The minimum number of link descriptors requested to be
|
||||
released. If set to 0, only buffer release counts seems to
|
||||
be important... When set to very high value, likely the
|
||||
entire timeout list will be exhausted before this count is
|
||||
reached or maybe this count will not get reached. REO
|
||||
however will stop here as it can not do anything else.
|
||||
|
||||
|
||||
|
||||
When both this field and field Minimum_forward_buf_count
|
||||
are > 0, REO needs to meet both requirements. When both
|
||||
entries are 0 (which should be a programming error), REO
|
||||
does not need to do anything.
|
||||
|
||||
|
||||
|
||||
Note that this includes counts of MPDU link Desc as well
|
||||
as MSDU link Desc. Where the count of MSDU link Desc is not
|
||||
known to REO it's approximated by deriving from MSDU count
|
||||
|
||||
<legal all>
|
||||
|
||||
minimum_forward_buf_count
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
The minimum number of buffer descriptors requested to be
|
||||
passed on to the REO destination rings.
|
||||
|
||||
|
||||
|
||||
If set to 0, only descriptor release counts seems to be
|
||||
important...
|
||||
|
||||
|
||||
|
||||
When set to very high value, likely the entire timeout
|
||||
list will be exhausted before this count is reached or maybe
|
||||
this count will not get reached. REO however will stop here
|
||||
as it can not do anything else.
|
||||
|
||||
|
||||
|
||||
Note that REO does not know the exact buffer count. This
|
||||
can be approximated by using the MSDU_COUNT
|
||||
|
||||
<legal all>
|
||||
|
||||
reserved_3a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_4a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_5a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_6a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_7a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_8a
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_TIMEOUT_LIST_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
|
||||
#define REO_FLUSH_TIMEOUT_LIST_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
The AC_timeout list to be used for this command
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_OFFSET 0x00000004
|
||||
#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_MASK 0x00000003
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_OFFSET 0x00000004
|
||||
#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_LSB 2
|
||||
#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_MASK 0xfffffffc
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
The minimum number of link descriptors requested to be
|
||||
released. If set to 0, only buffer release counts seems to
|
||||
be important... When set to very high value, likely the
|
||||
entire timeout list will be exhausted before this count is
|
||||
reached or maybe this count will not get reached. REO
|
||||
however will stop here as it can not do anything else.
|
||||
|
||||
|
||||
|
||||
When both this field and field Minimum_forward_buf_count
|
||||
are > 0, REO needs to meet both requirements. When both
|
||||
entries are 0 (which should be a programming error), REO
|
||||
does not need to do anything.
|
||||
|
||||
|
||||
|
||||
Note that this includes counts of MPDU link Desc as well
|
||||
as MSDU link Desc. Where the count of MSDU link Desc is not
|
||||
known to REO it's approximated by deriving from MSDU count
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x00000008
|
||||
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_MASK 0x0000ffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
The minimum number of buffer descriptors requested to be
|
||||
passed on to the REO destination rings.
|
||||
|
||||
|
||||
|
||||
If set to 0, only descriptor release counts seems to be
|
||||
important...
|
||||
|
||||
|
||||
|
||||
When set to very high value, likely the entire timeout
|
||||
list will be exhausted before this count is reached or maybe
|
||||
this count will not get reached. REO however will stop here
|
||||
as it can not do anything else.
|
||||
|
||||
|
||||
|
||||
Note that REO does not know the exact buffer count. This
|
||||
can be approximated by using the MSDU_COUNT
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x00000008
|
||||
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_LSB 16
|
||||
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_MASK 0xffff0000
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_OFFSET 0x00000010
|
||||
#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_OFFSET 0x00000014
|
||||
#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_OFFSET 0x00000018
|
||||
#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_OFFSET 0x0000001c
|
||||
#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_OFFSET 0x00000020
|
||||
#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_MASK 0xffffffff
|
||||
|
||||
|
||||
#endif // _REO_FLUSH_TIMEOUT_LIST_H_
|
||||
545
hw/qca6290/v1/reo_flush_timeout_list_status.h
Executable file
545
hw/qca6290/v1/reo_flush_timeout_list_status.h
Executable file
@@ -0,0 +1,545 @@
|
||||
/*
|
||||
* Copyright (c) 2017 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
//
|
||||
// DO NOT EDIT! This file is automatically generated
|
||||
// These definitions are tied to a particular hardware layout
|
||||
|
||||
|
||||
#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
|
||||
#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_reo_status_header.h"
|
||||
|
||||
// ################ START SUMMARY #################
|
||||
//
|
||||
// Dword Fields
|
||||
// 0-1 struct uniform_reo_status_header status_header;
|
||||
// 2 error_detected[0], timout_list_empty[1], reserved_2a[31:2]
|
||||
// 3 release_desc_count[15:0], forward_buf_count[31:16]
|
||||
// 4 reserved_4a[31:0]
|
||||
// 5 reserved_5a[31:0]
|
||||
// 6 reserved_6a[31:0]
|
||||
// 7 reserved_7a[31:0]
|
||||
// 8 reserved_8a[31:0]
|
||||
// 9 reserved_9a[31:0]
|
||||
// 10 reserved_10a[31:0]
|
||||
// 11 reserved_11a[31:0]
|
||||
// 12 reserved_12a[31:0]
|
||||
// 13 reserved_13a[31:0]
|
||||
// 14 reserved_14a[31:0]
|
||||
// 15 reserved_15a[31:0]
|
||||
// 16 reserved_16a[31:0]
|
||||
// 17 reserved_17a[31:0]
|
||||
// 18 reserved_18a[31:0]
|
||||
// 19 reserved_19a[31:0]
|
||||
// 20 reserved_20a[31:0]
|
||||
// 21 reserved_21a[31:0]
|
||||
// 22 reserved_22a[31:0]
|
||||
// 23 reserved_23a[31:0]
|
||||
// 24 reserved_24a[27:0], looping_count[31:28]
|
||||
//
|
||||
// ################ END SUMMARY #################
|
||||
|
||||
#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 25
|
||||
|
||||
struct reo_flush_timeout_list_status {
|
||||
struct uniform_reo_status_header status_header;
|
||||
uint32_t error_detected : 1, //[0]
|
||||
timout_list_empty : 1, //[1]
|
||||
reserved_2a : 30; //[31:2]
|
||||
uint32_t release_desc_count : 16, //[15:0]
|
||||
forward_buf_count : 16; //[31:16]
|
||||
uint32_t reserved_4a : 32; //[31:0]
|
||||
uint32_t reserved_5a : 32; //[31:0]
|
||||
uint32_t reserved_6a : 32; //[31:0]
|
||||
uint32_t reserved_7a : 32; //[31:0]
|
||||
uint32_t reserved_8a : 32; //[31:0]
|
||||
uint32_t reserved_9a : 32; //[31:0]
|
||||
uint32_t reserved_10a : 32; //[31:0]
|
||||
uint32_t reserved_11a : 32; //[31:0]
|
||||
uint32_t reserved_12a : 32; //[31:0]
|
||||
uint32_t reserved_13a : 32; //[31:0]
|
||||
uint32_t reserved_14a : 32; //[31:0]
|
||||
uint32_t reserved_15a : 32; //[31:0]
|
||||
uint32_t reserved_16a : 32; //[31:0]
|
||||
uint32_t reserved_17a : 32; //[31:0]
|
||||
uint32_t reserved_18a : 32; //[31:0]
|
||||
uint32_t reserved_19a : 32; //[31:0]
|
||||
uint32_t reserved_20a : 32; //[31:0]
|
||||
uint32_t reserved_21a : 32; //[31:0]
|
||||
uint32_t reserved_22a : 32; //[31:0]
|
||||
uint32_t reserved_23a : 32; //[31:0]
|
||||
uint32_t reserved_24a : 28, //[27:0]
|
||||
looping_count : 4; //[31:28]
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
struct uniform_reo_status_header status_header
|
||||
|
||||
Consumer: SW
|
||||
|
||||
Producer: REO
|
||||
|
||||
|
||||
|
||||
Details that can link this status with the original
|
||||
command. It also contains info on how long REO took to
|
||||
execute this command.
|
||||
|
||||
error_detected
|
||||
|
||||
0: No error has been detected while executing this
|
||||
command
|
||||
|
||||
1: command not properly executed and returned with an
|
||||
error
|
||||
|
||||
|
||||
|
||||
NOTE: Current no error is defined, but field is put in
|
||||
place to avoid data structure changes in future...
|
||||
|
||||
timout_list_empty
|
||||
|
||||
When set, REO has depleted the timeout list and all
|
||||
entries are gone.
|
||||
|
||||
<legal all>
|
||||
|
||||
reserved_2a
|
||||
|
||||
<legal 0>
|
||||
|
||||
release_desc_count
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
The number of link descriptors released
|
||||
|
||||
<legal all>
|
||||
|
||||
forward_buf_count
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
The number of buffers forwarded to the REO destination
|
||||
rings
|
||||
|
||||
<legal all>
|
||||
|
||||
reserved_4a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_5a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_6a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_7a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_8a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_9a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_10a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_11a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_12a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_13a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_14a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_15a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_16a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_17a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_18a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_19a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_20a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_21a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_22a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_23a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_24a
|
||||
|
||||
<legal 0>
|
||||
|
||||
looping_count
|
||||
|
||||
A count value that indicates the number of times the
|
||||
producer of entries into this Ring has looped around the
|
||||
ring.
|
||||
|
||||
At initialization time, this value is set to 0. On the
|
||||
first loop, this value is set to 1. After the max value is
|
||||
reached allowed by the number of bits for this field, the
|
||||
count value continues with 0 again.
|
||||
|
||||
|
||||
|
||||
In case SW is the consumer of the ring entries, it can
|
||||
use this field to figure out up to where the producer of
|
||||
entries has created new entries. This eliminates the need to
|
||||
check where the head pointer' of the ring is located once
|
||||
the SW starts processing an interrupt indicating that new
|
||||
entries have been put into this ring...
|
||||
|
||||
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED
|
||||
|
||||
0: No error has been detected while executing this
|
||||
command
|
||||
|
||||
1: command not properly executed and returned with an
|
||||
error
|
||||
|
||||
|
||||
|
||||
NOTE: Current no error is defined, but field is put in
|
||||
place to avoid data structure changes in future...
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_MASK 0x00000001
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY
|
||||
|
||||
When set, REO has depleted the timeout list and all
|
||||
entries are gone.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_OFFSET 0x00000008
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_LSB 1
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_MASK 0x00000002
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_OFFSET 0x00000008
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_LSB 2
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_MASK 0xfffffffc
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
The number of link descriptors released
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_OFFSET 0x0000000c
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_MASK 0x0000ffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
The number of buffers forwarded to the REO destination
|
||||
rings
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_OFFSET 0x0000000c
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_LSB 16
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_MASK 0xffff0000
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_OFFSET 0x00000010
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_OFFSET 0x00000014
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_OFFSET 0x00000018
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_OFFSET 0x00000020
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_OFFSET 0x00000024
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_OFFSET 0x00000028
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_OFFSET 0x00000030
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_OFFSET 0x00000034
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_OFFSET 0x00000038
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_OFFSET 0x00000040
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_OFFSET 0x00000044
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_OFFSET 0x00000048
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_OFFSET 0x00000050
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_OFFSET 0x00000054
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_OFFSET 0x00000058
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_OFFSET 0x00000060
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_MASK 0x0fffffff
|
||||
|
||||
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT
|
||||
|
||||
A count value that indicates the number of times the
|
||||
producer of entries into this Ring has looped around the
|
||||
ring.
|
||||
|
||||
At initialization time, this value is set to 0. On the
|
||||
first loop, this value is set to 1. After the max value is
|
||||
reached allowed by the number of bits for this field, the
|
||||
count value continues with 0 again.
|
||||
|
||||
|
||||
|
||||
In case SW is the consumer of the ring entries, it can
|
||||
use this field to figure out up to where the producer of
|
||||
entries has created new entries. This eliminates the need to
|
||||
check where the head pointer' of the ring is located once
|
||||
the SW starts processing an interrupt indicating that new
|
||||
entries have been put into this ring...
|
||||
|
||||
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_LSB 28
|
||||
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
|
||||
|
||||
|
||||
#endif // _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
|
||||
268
hw/qca6290/v1/reo_unblock_cache.h
Executable file
268
hw/qca6290/v1/reo_unblock_cache.h
Executable file
@@ -0,0 +1,268 @@
|
||||
/*
|
||||
* Copyright (c) 2017 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
//
|
||||
// DO NOT EDIT! This file is automatically generated
|
||||
// These definitions are tied to a particular hardware layout
|
||||
|
||||
|
||||
#ifndef _REO_UNBLOCK_CACHE_H_
|
||||
#define _REO_UNBLOCK_CACHE_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_reo_cmd_header.h"
|
||||
|
||||
// ################ START SUMMARY #################
|
||||
//
|
||||
// Dword Fields
|
||||
// 0 struct uniform_reo_cmd_header cmd_header;
|
||||
// 1 unblock_type[0], cache_block_resource_index[2:1], reserved_1a[31:3]
|
||||
// 2 reserved_2a[31:0]
|
||||
// 3 reserved_3a[31:0]
|
||||
// 4 reserved_4a[31:0]
|
||||
// 5 reserved_5a[31:0]
|
||||
// 6 reserved_6a[31:0]
|
||||
// 7 reserved_7a[31:0]
|
||||
// 8 reserved_8a[31:0]
|
||||
//
|
||||
// ################ END SUMMARY #################
|
||||
|
||||
#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9
|
||||
|
||||
struct reo_unblock_cache {
|
||||
struct uniform_reo_cmd_header cmd_header;
|
||||
uint32_t unblock_type : 1, //[0]
|
||||
cache_block_resource_index : 2, //[2:1]
|
||||
reserved_1a : 29; //[31:3]
|
||||
uint32_t reserved_2a : 32; //[31:0]
|
||||
uint32_t reserved_3a : 32; //[31:0]
|
||||
uint32_t reserved_4a : 32; //[31:0]
|
||||
uint32_t reserved_5a : 32; //[31:0]
|
||||
uint32_t reserved_6a : 32; //[31:0]
|
||||
uint32_t reserved_7a : 32; //[31:0]
|
||||
uint32_t reserved_8a : 32; //[31:0]
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
struct uniform_reo_cmd_header cmd_header
|
||||
|
||||
Consumer: REO
|
||||
|
||||
Producer: SW
|
||||
|
||||
|
||||
|
||||
Details for command execution tracking purposes.
|
||||
|
||||
unblock_type
|
||||
|
||||
Unblock type
|
||||
|
||||
|
||||
|
||||
<enum 0 unblock_resource_index> Unblock a block
|
||||
resource, whose index is given in field
|
||||
'cache_block_resource_index'.
|
||||
|
||||
If the indicated blocking resource is not in use (=> not
|
||||
blocking an address at the moment), the command status will
|
||||
indicate an error.
|
||||
|
||||
|
||||
|
||||
<enum 1 unblock_cache> The entire cache usage is
|
||||
unblocked.
|
||||
|
||||
If the entire cache is not in a blocked mode at the
|
||||
moment this command is received, the command status will
|
||||
indicate an error.
|
||||
|
||||
Note that unlocking the entire cache has no changes to
|
||||
the current settings of the blocking resource settings
|
||||
|
||||
|
||||
|
||||
<legal all>
|
||||
|
||||
cache_block_resource_index
|
||||
|
||||
Field not valid when field Unblock_type is set to
|
||||
unblock_cache.
|
||||
|
||||
|
||||
|
||||
Indicates which of the four blocking resources in REO
|
||||
should be released from blocking a (descriptor) address.
|
||||
|
||||
<legal all>
|
||||
|
||||
reserved_1a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_2a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_3a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_4a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_5a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_6a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_7a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_8a
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_UNBLOCK_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
|
||||
#define REO_UNBLOCK_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE
|
||||
|
||||
Unblock type
|
||||
|
||||
|
||||
|
||||
<enum 0 unblock_resource_index> Unblock a block
|
||||
resource, whose index is given in field
|
||||
'cache_block_resource_index'.
|
||||
|
||||
If the indicated blocking resource is not in use (=> not
|
||||
blocking an address at the moment), the command status will
|
||||
indicate an error.
|
||||
|
||||
|
||||
|
||||
<enum 1 unblock_cache> The entire cache usage is
|
||||
unblocked.
|
||||
|
||||
If the entire cache is not in a blocked mode at the
|
||||
moment this command is received, the command status will
|
||||
indicate an error.
|
||||
|
||||
Note that unlocking the entire cache has no changes to
|
||||
the current settings of the blocking resource settings
|
||||
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_OFFSET 0x00000004
|
||||
#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_MASK 0x00000001
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX
|
||||
|
||||
Field not valid when field Unblock_type is set to
|
||||
unblock_cache.
|
||||
|
||||
|
||||
|
||||
Indicates which of the four blocking resources in REO
|
||||
should be released from blocking a (descriptor) address.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000004
|
||||
#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_LSB 1
|
||||
#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000006
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_1_RESERVED_1A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_1_RESERVED_1A_OFFSET 0x00000004
|
||||
#define REO_UNBLOCK_CACHE_1_RESERVED_1A_LSB 3
|
||||
#define REO_UNBLOCK_CACHE_1_RESERVED_1A_MASK 0xfffffff8
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_2_RESERVED_2A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_2_RESERVED_2A_OFFSET 0x00000008
|
||||
#define REO_UNBLOCK_CACHE_2_RESERVED_2A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_2_RESERVED_2A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_3_RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_3_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define REO_UNBLOCK_CACHE_3_RESERVED_3A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_3_RESERVED_3A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_4_RESERVED_4A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_4_RESERVED_4A_OFFSET 0x00000010
|
||||
#define REO_UNBLOCK_CACHE_4_RESERVED_4A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_4_RESERVED_4A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_5_RESERVED_5A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_5_RESERVED_5A_OFFSET 0x00000014
|
||||
#define REO_UNBLOCK_CACHE_5_RESERVED_5A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_5_RESERVED_5A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_6_RESERVED_6A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_6_RESERVED_6A_OFFSET 0x00000018
|
||||
#define REO_UNBLOCK_CACHE_6_RESERVED_6A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_6_RESERVED_6A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_7_RESERVED_7A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_7_RESERVED_7A_OFFSET 0x0000001c
|
||||
#define REO_UNBLOCK_CACHE_7_RESERVED_7A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_7_RESERVED_7A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_8_RESERVED_8A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_8_RESERVED_8A_OFFSET 0x00000020
|
||||
#define REO_UNBLOCK_CACHE_8_RESERVED_8A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_8_RESERVED_8A_MASK 0xffffffff
|
||||
|
||||
|
||||
#endif // _REO_UNBLOCK_CACHE_H_
|
||||
518
hw/qca6290/v1/reo_unblock_cache_status.h
Executable file
518
hw/qca6290/v1/reo_unblock_cache_status.h
Executable file
@@ -0,0 +1,518 @@
|
||||
/*
|
||||
* Copyright (c) 2017 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
//
|
||||
// DO NOT EDIT! This file is automatically generated
|
||||
// These definitions are tied to a particular hardware layout
|
||||
|
||||
|
||||
#ifndef _REO_UNBLOCK_CACHE_STATUS_H_
|
||||
#define _REO_UNBLOCK_CACHE_STATUS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_reo_status_header.h"
|
||||
|
||||
// ################ START SUMMARY #################
|
||||
//
|
||||
// Dword Fields
|
||||
// 0-1 struct uniform_reo_status_header status_header;
|
||||
// 2 error_detected[0], unblock_type[1], reserved_2a[31:2]
|
||||
// 3 reserved_3a[31:0]
|
||||
// 4 reserved_4a[31:0]
|
||||
// 5 reserved_5a[31:0]
|
||||
// 6 reserved_6a[31:0]
|
||||
// 7 reserved_7a[31:0]
|
||||
// 8 reserved_8a[31:0]
|
||||
// 9 reserved_9a[31:0]
|
||||
// 10 reserved_10a[31:0]
|
||||
// 11 reserved_11a[31:0]
|
||||
// 12 reserved_12a[31:0]
|
||||
// 13 reserved_13a[31:0]
|
||||
// 14 reserved_14a[31:0]
|
||||
// 15 reserved_15a[31:0]
|
||||
// 16 reserved_16a[31:0]
|
||||
// 17 reserved_17a[31:0]
|
||||
// 18 reserved_18a[31:0]
|
||||
// 19 reserved_19a[31:0]
|
||||
// 20 reserved_20a[31:0]
|
||||
// 21 reserved_21a[31:0]
|
||||
// 22 reserved_22a[31:0]
|
||||
// 23 reserved_23a[31:0]
|
||||
// 24 reserved_24a[27:0], looping_count[31:28]
|
||||
//
|
||||
// ################ END SUMMARY #################
|
||||
|
||||
#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 25
|
||||
|
||||
struct reo_unblock_cache_status {
|
||||
struct uniform_reo_status_header status_header;
|
||||
uint32_t error_detected : 1, //[0]
|
||||
unblock_type : 1, //[1]
|
||||
reserved_2a : 30; //[31:2]
|
||||
uint32_t reserved_3a : 32; //[31:0]
|
||||
uint32_t reserved_4a : 32; //[31:0]
|
||||
uint32_t reserved_5a : 32; //[31:0]
|
||||
uint32_t reserved_6a : 32; //[31:0]
|
||||
uint32_t reserved_7a : 32; //[31:0]
|
||||
uint32_t reserved_8a : 32; //[31:0]
|
||||
uint32_t reserved_9a : 32; //[31:0]
|
||||
uint32_t reserved_10a : 32; //[31:0]
|
||||
uint32_t reserved_11a : 32; //[31:0]
|
||||
uint32_t reserved_12a : 32; //[31:0]
|
||||
uint32_t reserved_13a : 32; //[31:0]
|
||||
uint32_t reserved_14a : 32; //[31:0]
|
||||
uint32_t reserved_15a : 32; //[31:0]
|
||||
uint32_t reserved_16a : 32; //[31:0]
|
||||
uint32_t reserved_17a : 32; //[31:0]
|
||||
uint32_t reserved_18a : 32; //[31:0]
|
||||
uint32_t reserved_19a : 32; //[31:0]
|
||||
uint32_t reserved_20a : 32; //[31:0]
|
||||
uint32_t reserved_21a : 32; //[31:0]
|
||||
uint32_t reserved_22a : 32; //[31:0]
|
||||
uint32_t reserved_23a : 32; //[31:0]
|
||||
uint32_t reserved_24a : 28, //[27:0]
|
||||
looping_count : 4; //[31:28]
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
struct uniform_reo_status_header status_header
|
||||
|
||||
Consumer: SW
|
||||
|
||||
Producer: REO
|
||||
|
||||
|
||||
|
||||
Details that can link this status with the original
|
||||
command. It also contains info on how long REO took to
|
||||
execute this command.
|
||||
|
||||
error_detected
|
||||
|
||||
Status for blocking resource handling
|
||||
|
||||
|
||||
|
||||
0: No error has been detected while executing this
|
||||
command
|
||||
|
||||
1: The blocking resource was not in use, and therefor it
|
||||
could not be 'unblocked'
|
||||
|
||||
unblock_type
|
||||
|
||||
Reference to the type of Unblock command type...
|
||||
|
||||
|
||||
|
||||
<enum 0 unblock_resource_index> Unblock a blocking
|
||||
resource
|
||||
|
||||
|
||||
|
||||
<enum 1 unblock_cache> The entire cache usage is
|
||||
unblock.
|
||||
|
||||
|
||||
|
||||
<legal all>
|
||||
|
||||
reserved_2a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_3a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_4a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_5a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_6a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_7a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_8a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_9a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_10a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_11a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_12a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_13a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_14a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_15a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_16a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_17a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_18a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_19a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_20a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_21a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_22a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_23a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_24a
|
||||
|
||||
<legal 0>
|
||||
|
||||
looping_count
|
||||
|
||||
A count value that indicates the number of times the
|
||||
producer of entries into this Ring has looped around the
|
||||
ring.
|
||||
|
||||
At initialization time, this value is set to 0. On the
|
||||
first loop, this value is set to 1. After the max value is
|
||||
reached allowed by the number of bits for this field, the
|
||||
count value continues with 0 again.
|
||||
|
||||
|
||||
|
||||
In case SW is the consumer of the ring entries, it can
|
||||
use this field to figure out up to where the producer of
|
||||
entries has created new entries. This eliminates the need to
|
||||
check where the head pointer' of the ring is located once
|
||||
the SW starts processing an interrupt indicating that new
|
||||
entries have been put into this ring...
|
||||
|
||||
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_UNBLOCK_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
|
||||
#define REO_UNBLOCK_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
|
||||
#define REO_UNBLOCK_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
|
||||
#define REO_UNBLOCK_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
|
||||
#define REO_UNBLOCK_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
|
||||
#define REO_UNBLOCK_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED
|
||||
|
||||
Status for blocking resource handling
|
||||
|
||||
|
||||
|
||||
0: No error has been detected while executing this
|
||||
command
|
||||
|
||||
1: The blocking resource was not in use, and therefor it
|
||||
could not be 'unblocked'
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
|
||||
#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE
|
||||
|
||||
Reference to the type of Unblock command type...
|
||||
|
||||
|
||||
|
||||
<enum 0 unblock_resource_index> Unblock a blocking
|
||||
resource
|
||||
|
||||
|
||||
|
||||
<enum 1 unblock_cache> The entire cache usage is
|
||||
unblock.
|
||||
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_OFFSET 0x00000008
|
||||
#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_LSB 1
|
||||
#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_MASK 0x00000002
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
|
||||
#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_LSB 2
|
||||
#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_MASK 0xfffffffc
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
|
||||
#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
|
||||
#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
|
||||
#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
|
||||
#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
|
||||
#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
|
||||
#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
|
||||
#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
|
||||
#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
|
||||
#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
|
||||
#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
|
||||
#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
|
||||
#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
|
||||
#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
|
||||
#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
|
||||
#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
|
||||
#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
|
||||
#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
|
||||
#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
|
||||
#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
|
||||
#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
|
||||
#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_LSB 0
|
||||
#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
|
||||
|
||||
/* Description REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT
|
||||
|
||||
A count value that indicates the number of times the
|
||||
producer of entries into this Ring has looped around the
|
||||
ring.
|
||||
|
||||
At initialization time, this value is set to 0. On the
|
||||
first loop, this value is set to 1. After the max value is
|
||||
reached allowed by the number of bits for this field, the
|
||||
count value continues with 0 again.
|
||||
|
||||
|
||||
|
||||
In case SW is the consumer of the ring entries, it can
|
||||
use this field to figure out up to where the producer of
|
||||
entries has created new entries. This eliminates the need to
|
||||
check where the head pointer' of the ring is located once
|
||||
the SW starts processing an interrupt indicating that new
|
||||
entries have been put into this ring...
|
||||
|
||||
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
|
||||
#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_LSB 28
|
||||
#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
|
||||
|
||||
|
||||
#endif // _REO_UNBLOCK_CACHE_STATUS_H_
|
||||
1503
hw/qca6290/v1/reo_update_rx_reo_queue.h
Executable file
1503
hw/qca6290/v1/reo_update_rx_reo_queue.h
Executable file
파일 크기가 너무 크기때문에 변경 상태를 표시하지 않습니다.
Load Diff
448
hw/qca6290/v1/reo_update_rx_reo_queue_status.h
Executable file
448
hw/qca6290/v1/reo_update_rx_reo_queue_status.h
Executable file
@@ -0,0 +1,448 @@
|
||||
/*
|
||||
* Copyright (c) 2017 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
//
|
||||
// DO NOT EDIT! This file is automatically generated
|
||||
// These definitions are tied to a particular hardware layout
|
||||
|
||||
|
||||
#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
|
||||
#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_reo_status_header.h"
|
||||
|
||||
// ################ START SUMMARY #################
|
||||
//
|
||||
// Dword Fields
|
||||
// 0-1 struct uniform_reo_status_header status_header;
|
||||
// 2 reserved_2a[31:0]
|
||||
// 3 reserved_3a[31:0]
|
||||
// 4 reserved_4a[31:0]
|
||||
// 5 reserved_5a[31:0]
|
||||
// 6 reserved_6a[31:0]
|
||||
// 7 reserved_7a[31:0]
|
||||
// 8 reserved_8a[31:0]
|
||||
// 9 reserved_9a[31:0]
|
||||
// 10 reserved_10a[31:0]
|
||||
// 11 reserved_11a[31:0]
|
||||
// 12 reserved_12a[31:0]
|
||||
// 13 reserved_13a[31:0]
|
||||
// 14 reserved_14a[31:0]
|
||||
// 15 reserved_15a[31:0]
|
||||
// 16 reserved_16a[31:0]
|
||||
// 17 reserved_17a[31:0]
|
||||
// 18 reserved_18a[31:0]
|
||||
// 19 reserved_19a[31:0]
|
||||
// 20 reserved_20a[31:0]
|
||||
// 21 reserved_21a[31:0]
|
||||
// 22 reserved_22a[31:0]
|
||||
// 23 reserved_23a[31:0]
|
||||
// 24 reserved_24a[27:0], looping_count[31:28]
|
||||
//
|
||||
// ################ END SUMMARY #################
|
||||
|
||||
#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 25
|
||||
|
||||
struct reo_update_rx_reo_queue_status {
|
||||
struct uniform_reo_status_header status_header;
|
||||
uint32_t reserved_2a : 32; //[31:0]
|
||||
uint32_t reserved_3a : 32; //[31:0]
|
||||
uint32_t reserved_4a : 32; //[31:0]
|
||||
uint32_t reserved_5a : 32; //[31:0]
|
||||
uint32_t reserved_6a : 32; //[31:0]
|
||||
uint32_t reserved_7a : 32; //[31:0]
|
||||
uint32_t reserved_8a : 32; //[31:0]
|
||||
uint32_t reserved_9a : 32; //[31:0]
|
||||
uint32_t reserved_10a : 32; //[31:0]
|
||||
uint32_t reserved_11a : 32; //[31:0]
|
||||
uint32_t reserved_12a : 32; //[31:0]
|
||||
uint32_t reserved_13a : 32; //[31:0]
|
||||
uint32_t reserved_14a : 32; //[31:0]
|
||||
uint32_t reserved_15a : 32; //[31:0]
|
||||
uint32_t reserved_16a : 32; //[31:0]
|
||||
uint32_t reserved_17a : 32; //[31:0]
|
||||
uint32_t reserved_18a : 32; //[31:0]
|
||||
uint32_t reserved_19a : 32; //[31:0]
|
||||
uint32_t reserved_20a : 32; //[31:0]
|
||||
uint32_t reserved_21a : 32; //[31:0]
|
||||
uint32_t reserved_22a : 32; //[31:0]
|
||||
uint32_t reserved_23a : 32; //[31:0]
|
||||
uint32_t reserved_24a : 28, //[27:0]
|
||||
looping_count : 4; //[31:28]
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
struct uniform_reo_status_header status_header
|
||||
|
||||
Consumer: SW
|
||||
|
||||
Producer: REO
|
||||
|
||||
|
||||
|
||||
Details that can link this status with the original
|
||||
command. It also contains info on how long REO took to
|
||||
execute this command.
|
||||
|
||||
reserved_2a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_3a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_4a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_5a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_6a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_7a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_8a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_9a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_10a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_11a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_12a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_13a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_14a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_15a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_16a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_17a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_18a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_19a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_20a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_21a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_22a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_23a
|
||||
|
||||
<legal 0>
|
||||
|
||||
reserved_24a
|
||||
|
||||
<legal 0>
|
||||
|
||||
looping_count
|
||||
|
||||
A count value that indicates the number of times the
|
||||
producer of entries into this Ring has looped around the
|
||||
ring.
|
||||
|
||||
At initialization time, this value is set to 0. On the
|
||||
first loop, this value is set to 1. After the max value is
|
||||
reached allowed by the number of bits for this field, the
|
||||
count value continues with 0 again.
|
||||
|
||||
|
||||
|
||||
In case SW is the consumer of the ring entries, it can
|
||||
use this field to figure out up to where the producer of
|
||||
entries has created new entries. This eliminates the need to
|
||||
check where the head pointer' of the ring is located once
|
||||
the SW starts processing an interrupt indicating that new
|
||||
entries have been put into this ring...
|
||||
|
||||
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_LSB 0
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
|
||||
|
||||
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT
|
||||
|
||||
A count value that indicates the number of times the
|
||||
producer of entries into this Ring has looped around the
|
||||
ring.
|
||||
|
||||
At initialization time, this value is set to 0. On the
|
||||
first loop, this value is set to 1. After the max value is
|
||||
reached allowed by the number of bits for this field, the
|
||||
count value continues with 0 again.
|
||||
|
||||
|
||||
|
||||
In case SW is the consumer of the ring entries, it can
|
||||
use this field to figure out up to where the producer of
|
||||
entries has created new entries. This eliminates the need to
|
||||
check where the head pointer' of the ring is located once
|
||||
the SW starts processing an interrupt indicating that new
|
||||
entries have been put into this ring...
|
||||
|
||||
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28
|
||||
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
|
||||
|
||||
|
||||
#endif // _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
|
||||
19
hw/qca6290/v1/wcss_version.h
Executable file
19
hw/qca6290/v1/wcss_version.h
Executable file
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (c) 2017 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#define WCSS_VERSION 72
|
||||
Reference in New Issue
Block a user