fw-api: New HW header files for version R102 for QCA6290

New hardware header files needed for DV release version R102.
This is required to support emulation version E3 for all platforms.

Change-Id: Id40755ffba391fcbe246de07f4a0880ca18fc565
CRs-Fixed: 1105853

hw/qca6290/v1/reo_descriptor_threshold_reached_status.h

@@ -0,0 +1,559 @@
+/*
+ * Copyright (c) 2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
+#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct uniform_reo_status_header status_header;
+//	2	threshold_index[1:0], reserved_2[31:2]
+//	3	link_descriptor_counter0[23:0], reserved_3[31:24]
+//	4	link_descriptor_counter1[23:0], reserved_4[31:24]
+//	5	link_descriptor_counter2[23:0], reserved_5[31:24]
+//	6	link_descriptor_counter_sum[25:0], reserved_6[31:26]
+//	7	reserved_7[31:0]
+//	8	reserved_8[31:0]
+//	9	reserved_9a[31:0]
+//	10	reserved_10a[31:0]
+//	11	reserved_11a[31:0]
+//	12	reserved_12a[31:0]
+//	13	reserved_13a[31:0]
+//	14	reserved_14a[31:0]
+//	15	reserved_15a[31:0]
+//	16	reserved_16a[31:0]
+//	17	reserved_17a[31:0]
+//	18	reserved_18a[31:0]
+//	19	reserved_19a[31:0]
+//	20	reserved_20a[31:0]
+//	21	reserved_21a[31:0]
+//	22	reserved_22a[31:0]
+//	23	reserved_23a[31:0]
+//	24	reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 25
+
+struct reo_descriptor_threshold_reached_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t threshold_index                 :  2, //[1:0]
+                      reserved_2                      : 30; //[31:2]
+             uint32_t link_descriptor_counter0        : 24, //[23:0]
+                      reserved_3                      :  8; //[31:24]
+             uint32_t link_descriptor_counter1        : 24, //[23:0]
+                      reserved_4                      :  8; //[31:24]
+             uint32_t link_descriptor_counter2        : 24, //[23:0]
+                      reserved_5                      :  8; //[31:24]
+             uint32_t link_descriptor_counter_sum     : 26, //[25:0]
+                      reserved_6                      :  6; //[31:26]
+             uint32_t reserved_7                      : 32; //[31:0]
+             uint32_t reserved_8                      : 32; //[31:0]
+             uint32_t reserved_9a                     : 32; //[31:0]
+             uint32_t reserved_10a                    : 32; //[31:0]
+             uint32_t reserved_11a                    : 32; //[31:0]
+             uint32_t reserved_12a                    : 32; //[31:0]
+             uint32_t reserved_13a                    : 32; //[31:0]
+             uint32_t reserved_14a                    : 32; //[31:0]
+             uint32_t reserved_15a                    : 32; //[31:0]
+             uint32_t reserved_16a                    : 32; //[31:0]
+             uint32_t reserved_17a                    : 32; //[31:0]
+             uint32_t reserved_18a                    : 32; //[31:0]
+             uint32_t reserved_19a                    : 32; //[31:0]
+             uint32_t reserved_20a                    : 32; //[31:0]
+             uint32_t reserved_21a                    : 32; //[31:0]
+             uint32_t reserved_22a                    : 32; //[31:0]
+             uint32_t reserved_23a                    : 32; //[31:0]
+             uint32_t reserved_24a                    : 28, //[27:0]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+			
+			Consumer: SW
+			
+			Producer: REO
+			
+			
+			
+			Details that can link this status with the original
+			command. It also contains info on how long REO took to
+			execute this command.
+
+threshold_index
+			
+			The index of the threshold register whose value got
+			reached
+			
+			
+			
+			<enum 0     reo_desc_counter0_threshold>
+			
+			<enum 1     reo_desc_counter1_threshold>
+			
+			<enum 2     reo_desc_counter2_threshold>
+			
+			<enum 3     reo_desc_counter_sum_threshold>
+			
+			
+			
+			<legal all>
+
+reserved_2
+			
+			<legal 0>
+
+link_descriptor_counter0
+			
+			Value of this counter at generation of this message
+			
+			<legal all>
+
+reserved_3
+			
+			<legal 0>
+
+link_descriptor_counter1
+			
+			Value of this counter at generation of this message
+			
+			<legal all>
+
+reserved_4
+			
+			<legal 0>
+
+link_descriptor_counter2
+			
+			Value of this counter at generation of this message
+			
+			<legal all>
+
+reserved_5
+			
+			<legal 0>
+
+link_descriptor_counter_sum
+			
+			Value of this counter at generation of this message
+			
+			<legal all>
+
+reserved_6
+			
+			<legal 0>
+
+reserved_7
+			
+			<legal 0>
+
+reserved_8
+			
+			<legal 0>
+
+reserved_9a
+			
+			<legal 0>
+
+reserved_10a
+			
+			<legal 0>
+
+reserved_11a
+			
+			<legal 0>
+
+reserved_12a
+			
+			<legal 0>
+
+reserved_13a
+			
+			<legal 0>
+
+reserved_14a
+			
+			<legal 0>
+
+reserved_15a
+			
+			<legal 0>
+
+reserved_16a
+			
+			<legal 0>
+
+reserved_17a
+			
+			<legal 0>
+
+reserved_18a
+			
+			<legal 0>
+
+reserved_19a
+			
+			<legal 0>
+
+reserved_20a
+			
+			<legal 0>
+
+reserved_21a
+			
+			<legal 0>
+
+reserved_22a
+			
+			<legal 0>
+
+reserved_23a
+			
+			<legal 0>
+
+reserved_24a
+			
+			<legal 0>
+
+looping_count
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX
+			
+			The index of the threshold register whose value got
+			reached
+			
+			
+			
+			<enum 0     reo_desc_counter0_threshold>
+			
+			<enum 1     reo_desc_counter1_threshold>
+			
+			<enum 2     reo_desc_counter2_threshold>
+			
+			<enum 3     reo_desc_counter_sum_threshold>
+			
+			
+			
+			<legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_OFFSET 0x00000008
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_MASK 0x00000003
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_OFFSET  0x00000008
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_LSB     2
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_MASK    0xfffffffc
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0
+			
+			Value of this counter at generation of this message
+			
+			<legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_OFFSET  0x0000000c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_LSB     24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_MASK    0xff000000
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1
+			
+			Value of this counter at generation of this message
+			
+			<legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_OFFSET  0x00000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_LSB     24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_MASK    0xff000000
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2
+			
+			Value of this counter at generation of this message
+			
+			<legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000014
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_OFFSET  0x00000014
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_LSB     24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_MASK    0xff000000
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM
+			
+			Value of this counter at generation of this message
+			
+			<legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x00000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_OFFSET  0x00000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_LSB     26
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_MASK    0xfc000000
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_OFFSET  0x0000001c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_LSB     0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_MASK    0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_OFFSET  0x00000020
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_LSB     0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_MASK    0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_OFFSET 0x00000024
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_LSB    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_MASK   0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_OFFSET 0x00000040
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_OFFSET 0x00000044
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_OFFSET 0x00000048
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_OFFSET 0x00000050
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_OFFSET 0x00000054
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_OFFSET 0x00000058
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A
+			
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_

hw/qca6290/v1/reo_flush_cache.h

@@ -0,0 +1,489 @@
+/*
+ * Copyright (c) 2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_FLUSH_CACHE_H_
+#define _REO_FLUSH_CACHE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	struct uniform_reo_cmd_header cmd_header;
+//	1	flush_addr_31_0[31:0]
+//	2	flush_addr_39_32[7:0], forward_all_mpdus_in_queue[8], release_cache_block_index[9], cache_block_resource_index[11:10], flush_without_invalidate[12], block_cache_usage_after_flush[13], flush_entire_cache[14], reserved_2b[31:15]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9
+
+struct reo_flush_cache {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t flush_addr_31_0                 : 32; //[31:0]
+             uint32_t flush_addr_39_32                :  8, //[7:0]
+                      forward_all_mpdus_in_queue      :  1, //[8]
+                      release_cache_block_index       :  1, //[9]
+                      cache_block_resource_index      :  2, //[11:10]
+                      flush_without_invalidate        :  1, //[12]
+                      block_cache_usage_after_flush   :  1, //[13]
+                      flush_entire_cache              :  1, //[14]
+                      reserved_2b                     : 17; //[31:15]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Details for command execution tracking purposes.
+
+flush_addr_31_0
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Address (lower 32 bits) of the descriptor to flush
+			
+			<legal all>
+
+flush_addr_39_32
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Address (upper 8 bits) of the descriptor to flush
+			
+			<legal all>
+
+forward_all_mpdus_in_queue
+			
+			Is only allowed to be set when the flush address
+			corresponds with a REO descriptor.
+			
+			
+			
+			When set, REO shall first forward all the MPDUs held in
+			the indicated re-order queue, before flushing the descriptor
+			from the cache.
+			
+			<legal all>
+
+release_cache_block_index
+			
+			Field not valid when Flush_entire_cache is set.
+			
+			
+			
+			If SW has previously used a blocking resource that it
+			now wants to re-use for this command, this bit shall be set.
+			It prevents SW from having to send a separate
+			REO_UNBLOCK_CACHE command.
+			
+			
+			
+			When set, HW will first release the blocking resource
+			(indicated in field 'Cache_block_resouce_index') before this
+			command gets executed.
+			
+			If that resource was already unblocked, this will be
+			considered an error. This command will not be executed, and
+			an error shall be returned.
+			
+			<legal all>
+
+cache_block_resource_index
+			
+			Field not valid when Flush_entire_cache is set.
+			
+			
+			
+			Indicates which of the four blocking resources in REO
+			will be assigned for managing the blocking of this
+			(descriptor) address 
+			
+			<legal all>
+
+flush_without_invalidate
+			
+			Field not valid when Flush_entire_cache is set.
+			
+			
+			
+			When set, REO shall flush the cache line contents from
+			the cache, but there is NO need to invalidate the cache line
+			entry... The contents in the cache can be maintained. This
+			feature can be used by SW (and DV) to get a current snapshot
+			of the contents in the cache
+			
+			
+			
+			<legal all>
+
+block_cache_usage_after_flush
+			
+			Field not valid when Flush_entire_cache is set.
+			
+			
+			
+			When set, REO shall block any cache accesses to this
+			address till explicitly unblocked. 
+			
+			
+			
+			Whenever SW sets this bit, SW shall also set bit
+			'Forward_all_mpdus_in_queue' to ensure all packets are
+			flushed out in order to make sure this queue desc is not in
+			one of the aging link lists. In case SW does not want to
+			flush the MPDUs in the queue, see the recipe description
+			below this TLV definition.
+			
+			
+			
+			The 'blocking' index to be used for this is indicated in
+			field 'cache_block_resource_index'. If SW had previously
+			used this blocking resource and was not freed up yet, SW
+			shall first unblock that index (by setting bit
+			Release_cache_block_index) or use an unblock command.
+			
+			
+			
+			If the resource indicated here was already blocked (and
+			did not get unblocked in this command), it is considered an
+			error scenario...
+			
+			No flush shall happen. The status for this command shall
+			indicate error.
+			
+			
+			
+			<legal all>
+
+flush_entire_cache
+			
+			When set, the entire cache shall be flushed. The entire
+			cache will also remain blocked, till the
+			'REO_UNBLOCK_COMMAND' is received with bit unblock type set
+			to unblock_cache. All other fields in this command are to be
+			ignored.
+			
+			
+			
+			Note that flushing the entire cache has no changes to
+			the current settings of the blocking resource settings
+			
+			
+			
+			<legal all>
+
+reserved_2b
+			
+			<legal 0>
+
+reserved_3a
+			
+			<legal 0>
+
+reserved_4a
+			
+			<legal 0>
+
+reserved_5a
+			
+			<legal 0>
+
+reserved_6a
+			
+			<legal 0>
+
+reserved_7a
+			
+			<legal 0>
+
+reserved_8a
+			
+			<legal 0>
+*/
+
+#define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET   0x00000000
+#define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB      0
+#define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK     0xffffffff
+
+/* Description		REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Address (lower 32 bits) of the descriptor to flush
+			
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET                     0x00000004
+#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB                        0
+#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK                       0xffffffff
+
+/* Description		REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Address (upper 8 bits) of the descriptor to flush
+			
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET                    0x00000008
+#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB                       0
+#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK                      0x000000ff
+
+/* Description		REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE
+			
+			Is only allowed to be set when the flush address
+			corresponds with a REO descriptor.
+			
+			
+			
+			When set, REO shall first forward all the MPDUs held in
+			the indicated re-order queue, before flushing the descriptor
+			from the cache.
+			
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET          0x00000008
+#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB             8
+#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK            0x00000100
+
+/* Description		REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX
+			
+			Field not valid when Flush_entire_cache is set.
+			
+			
+			
+			If SW has previously used a blocking resource that it
+			now wants to re-use for this command, this bit shall be set.
+			It prevents SW from having to send a separate
+			REO_UNBLOCK_CACHE command.
+			
+			
+			
+			When set, HW will first release the blocking resource
+			(indicated in field 'Cache_block_resouce_index') before this
+			command gets executed.
+			
+			If that resource was already unblocked, this will be
+			considered an error. This command will not be executed, and
+			an error shall be returned.
+			
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET           0x00000008
+#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB              9
+#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK             0x00000200
+
+/* Description		REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX
+			
+			Field not valid when Flush_entire_cache is set.
+			
+			
+			
+			Indicates which of the four blocking resources in REO
+			will be assigned for managing the blocking of this
+			(descriptor) address 
+			
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET          0x00000008
+#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB             10
+#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK            0x00000c00
+
+/* Description		REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE
+			
+			Field not valid when Flush_entire_cache is set.
+			
+			
+			
+			When set, REO shall flush the cache line contents from
+			the cache, but there is NO need to invalidate the cache line
+			entry... The contents in the cache can be maintained. This
+			feature can be used by SW (and DV) to get a current snapshot
+			of the contents in the cache
+			
+			
+			
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET            0x00000008
+#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB               12
+#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK              0x00001000
+
+/* Description		REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH
+			
+			Field not valid when Flush_entire_cache is set.
+			
+			
+			
+			When set, REO shall block any cache accesses to this
+			address till explicitly unblocked. 
+			
+			
+			
+			Whenever SW sets this bit, SW shall also set bit
+			'Forward_all_mpdus_in_queue' to ensure all packets are
+			flushed out in order to make sure this queue desc is not in
+			one of the aging link lists. In case SW does not want to
+			flush the MPDUs in the queue, see the recipe description
+			below this TLV definition.
+			
+			
+			
+			The 'blocking' index to be used for this is indicated in
+			field 'cache_block_resource_index'. If SW had previously
+			used this blocking resource and was not freed up yet, SW
+			shall first unblock that index (by setting bit
+			Release_cache_block_index) or use an unblock command.
+			
+			
+			
+			If the resource indicated here was already blocked (and
+			did not get unblocked in this command), it is considered an
+			error scenario...
+			
+			No flush shall happen. The status for this command shall
+			indicate error.
+			
+			
+			
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET       0x00000008
+#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB          13
+#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK         0x00002000
+
+/* Description		REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE
+			
+			When set, the entire cache shall be flushed. The entire
+			cache will also remain blocked, till the
+			'REO_UNBLOCK_COMMAND' is received with bit unblock type set
+			to unblock_cache. All other fields in this command are to be
+			ignored.
+			
+			
+			
+			Note that flushing the entire cache has no changes to
+			the current settings of the blocking resource settings
+			
+			
+			
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET                  0x00000008
+#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB                     14
+#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK                    0x00004000
+
+/* Description		REO_FLUSH_CACHE_2_RESERVED_2B
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET                         0x00000008
+#define REO_FLUSH_CACHE_2_RESERVED_2B_LSB                            15
+#define REO_FLUSH_CACHE_2_RESERVED_2B_MASK                           0xffff8000
+
+/* Description		REO_FLUSH_CACHE_3_RESERVED_3A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET                         0x0000000c
+#define REO_FLUSH_CACHE_3_RESERVED_3A_LSB                            0
+#define REO_FLUSH_CACHE_3_RESERVED_3A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_CACHE_4_RESERVED_4A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET                         0x00000010
+#define REO_FLUSH_CACHE_4_RESERVED_4A_LSB                            0
+#define REO_FLUSH_CACHE_4_RESERVED_4A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_CACHE_5_RESERVED_5A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET                         0x00000014
+#define REO_FLUSH_CACHE_5_RESERVED_5A_LSB                            0
+#define REO_FLUSH_CACHE_5_RESERVED_5A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_CACHE_6_RESERVED_6A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET                         0x00000018
+#define REO_FLUSH_CACHE_6_RESERVED_6A_LSB                            0
+#define REO_FLUSH_CACHE_6_RESERVED_6A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_CACHE_7_RESERVED_7A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET                         0x0000001c
+#define REO_FLUSH_CACHE_7_RESERVED_7A_LSB                            0
+#define REO_FLUSH_CACHE_7_RESERVED_7A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_CACHE_8_RESERVED_8A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET                         0x00000020
+#define REO_FLUSH_CACHE_8_RESERVED_8A_LSB                            0
+#define REO_FLUSH_CACHE_8_RESERVED_8A_MASK                           0xffffffff
+
+
+#endif // _REO_FLUSH_CACHE_H_

hw/qca6290/v1/reo_flush_cache_status.h

@@ -0,0 +1,698 @@
+/*
+ * Copyright (c) 2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_FLUSH_CACHE_STATUS_H_
+#define _REO_FLUSH_CACHE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct uniform_reo_status_header status_header;
+//	2	error_detected[0], block_error_details[2:1], reserved_2a[7:3], cache_controller_flush_status_hit[8], cache_controller_flush_status_desc_type[11:9], cache_controller_flush_status_client_id[15:12], cache_controller_flush_status_error[17:16], cache_controller_flush_count[25:18], reserved_2b[31:26]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//	9	reserved_9a[31:0]
+//	10	reserved_10a[31:0]
+//	11	reserved_11a[31:0]
+//	12	reserved_12a[31:0]
+//	13	reserved_13a[31:0]
+//	14	reserved_14a[31:0]
+//	15	reserved_15a[31:0]
+//	16	reserved_16a[31:0]
+//	17	reserved_17a[31:0]
+//	18	reserved_18a[31:0]
+//	19	reserved_19a[31:0]
+//	20	reserved_20a[31:0]
+//	21	reserved_21a[31:0]
+//	22	reserved_22a[31:0]
+//	23	reserved_23a[31:0]
+//	24	reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 25
+
+struct reo_flush_cache_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t error_detected                  :  1, //[0]
+                      block_error_details             :  2, //[2:1]
+                      reserved_2a                     :  5, //[7:3]
+                      cache_controller_flush_status_hit:  1, //[8]
+                      cache_controller_flush_status_desc_type:  3, //[11:9]
+                      cache_controller_flush_status_client_id:  4, //[15:12]
+                      cache_controller_flush_status_error:  2, //[17:16]
+                      cache_controller_flush_count    :  8, //[25:18]
+                      reserved_2b                     :  6; //[31:26]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+             uint32_t reserved_9a                     : 32; //[31:0]
+             uint32_t reserved_10a                    : 32; //[31:0]
+             uint32_t reserved_11a                    : 32; //[31:0]
+             uint32_t reserved_12a                    : 32; //[31:0]
+             uint32_t reserved_13a                    : 32; //[31:0]
+             uint32_t reserved_14a                    : 32; //[31:0]
+             uint32_t reserved_15a                    : 32; //[31:0]
+             uint32_t reserved_16a                    : 32; //[31:0]
+             uint32_t reserved_17a                    : 32; //[31:0]
+             uint32_t reserved_18a                    : 32; //[31:0]
+             uint32_t reserved_19a                    : 32; //[31:0]
+             uint32_t reserved_20a                    : 32; //[31:0]
+             uint32_t reserved_21a                    : 32; //[31:0]
+             uint32_t reserved_22a                    : 32; //[31:0]
+             uint32_t reserved_23a                    : 32; //[31:0]
+             uint32_t reserved_24a                    : 28, //[27:0]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+			
+			Consumer: SW
+			
+			Producer: REO
+			
+			
+			
+			Details that can link this status with the original
+			command. It also contains info on how long REO took to
+			execute this command.
+
+error_detected
+			
+			Status for blocking resource handling
+			
+			
+			
+			0: No error has been detected while executing this
+			command
+			
+			1: an error in the blocking resource management was
+			detected
+			
+			See field 'Block_error_details'
+
+block_error_details
+			
+			Field only valid when 'Error_detected' is set.
+			
+			0: no blocking related error found
+			
+			1: blocking resource was already in use
+			
+			2: resource that was asked to be unblocked, was not
+			blocked
+			
+			<legal 0-2>
+
+reserved_2a
+			
+			<legal 0>
+
+cache_controller_flush_status_hit
+			
+			The status that the cache controller returned for
+			executing the flush command
+			
+			
+			
+			descriptor hit
+			
+			1 = hit
+			
+			0 = miss
+			
+			<legal all>
+
+cache_controller_flush_status_desc_type
+			
+			The status that the cache controller returned for
+			executing the flush command
+			
+			Descriptor type
+			
+			FLOW_QUEUE_DESCRIPTOR                
+			3'd0
+			
+			
+			 <legal all>
+
+cache_controller_flush_status_client_id
+			
+			The status that the cache controller returned for
+			executing the flush command
+			
+			
+			
+			client ID
+			
+			Module who made flush the request
+			
+			
+			
+			In REO, this is always set to 0
+			
+			<legal 0>
+
+cache_controller_flush_status_error
+			
+			The status that the cache controller returned for
+			executing the flush command
+			
+			
+			
+			Error condition
+			
+			2'b00: No error found
+			
+			2'b01: HW IF still busy
+			
+			2'b10: Line is currently locked. Used for the one line
+			flush command.
+			
+			2'b11: At least one line is currently still locked. Used
+			for the cache flush command.
+			
+			
+			
+			<legal all>
+
+cache_controller_flush_count
+			
+			The number of lines that were actually flushed out.
+			
+			<legal all>
+
+reserved_2b
+			
+			<legal 0>
+
+reserved_3a
+			
+			<legal 0>
+
+reserved_4a
+			
+			<legal 0>
+
+reserved_5a
+			
+			<legal 0>
+
+reserved_6a
+			
+			<legal 0>
+
+reserved_7a
+			
+			<legal 0>
+
+reserved_8a
+			
+			<legal 0>
+
+reserved_9a
+			
+			<legal 0>
+
+reserved_10a
+			
+			<legal 0>
+
+reserved_11a
+			
+			<legal 0>
+
+reserved_12a
+			
+			<legal 0>
+
+reserved_13a
+			
+			<legal 0>
+
+reserved_14a
+			
+			<legal 0>
+
+reserved_15a
+			
+			<legal 0>
+
+reserved_16a
+			
+			<legal 0>
+
+reserved_17a
+			
+			<legal 0>
+
+reserved_18a
+			
+			<legal 0>
+
+reserved_19a
+			
+			<legal 0>
+
+reserved_20a
+			
+			<legal 0>
+
+reserved_21a
+			
+			<legal 0>
+
+reserved_22a
+			
+			<legal 0>
+
+reserved_23a
+			
+			<legal 0>
+
+reserved_24a
+			
+			<legal 0>
+
+looping_count
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+#define REO_FLUSH_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_FLUSH_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+#define REO_FLUSH_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
+#define REO_FLUSH_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_FLUSH_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED
+			
+			Status for blocking resource handling
+			
+			
+			
+			0: No error has been detected while executing this
+			command
+			
+			1: an error in the blocking resource management was
+			detected
+			
+			See field 'Block_error_details'
+*/
+#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_OFFSET               0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_LSB                  0
+#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_MASK                 0x00000001
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS
+			
+			Field only valid when 'Error_detected' is set.
+			
+			0: no blocking related error found
+			
+			1: blocking resource was already in use
+			
+			2: resource that was asked to be unblocked, was not
+			blocked
+			
+			<legal 0-2>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_OFFSET          0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_LSB             1
+#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_MASK            0x00000006
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_RESERVED_2A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_OFFSET                  0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_LSB                     3
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_MASK                    0x000000f8
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT
+			
+			The status that the cache controller returned for
+			executing the flush command
+			
+			
+			
+			descriptor hit
+			
+			1 = hit
+			
+			0 = miss
+			
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE
+			
+			The status that the cache controller returned for
+			executing the flush command
+			
+			Descriptor type
+			
+			FLOW_QUEUE_DESCRIPTOR                
+			3'd0
+			
+			
+			 <legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID
+			
+			The status that the cache controller returned for
+			executing the flush command
+			
+			
+			
+			client ID
+			
+			Module who made flush the request
+			
+			
+			
+			In REO, this is always set to 0
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR
+			
+			The status that the cache controller returned for
+			executing the flush command
+			
+			
+			
+			Error condition
+			
+			2'b00: No error found
+			
+			2'b01: HW IF still busy
+			
+			2'b10: Line is currently locked. Used for the one line
+			flush command.
+			
+			2'b11: At least one line is currently still locked. Used
+			for the cache flush command.
+			
+			
+			
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT
+			
+			The number of lines that were actually flushed out.
+			
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_LSB    18
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_MASK   0x03fc0000
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_RESERVED_2B
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_OFFSET                  0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_LSB                     26
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_MASK                    0xfc000000
+
+/* Description		REO_FLUSH_CACHE_STATUS_3_RESERVED_3A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_OFFSET                  0x0000000c
+#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_4_RESERVED_4A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_OFFSET                  0x00000010
+#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_5_RESERVED_5A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_OFFSET                  0x00000014
+#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_6_RESERVED_6A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_OFFSET                  0x00000018
+#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_7_RESERVED_7A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_OFFSET                  0x0000001c
+#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_8_RESERVED_8A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_OFFSET                  0x00000020
+#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_9_RESERVED_9A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_OFFSET                  0x00000024
+#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_10_RESERVED_10A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_OFFSET                0x00000028
+#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_11_RESERVED_11A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_OFFSET                0x0000002c
+#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_12_RESERVED_12A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_OFFSET                0x00000030
+#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_13_RESERVED_13A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_OFFSET                0x00000034
+#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_14_RESERVED_14A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_OFFSET                0x00000038
+#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_15_RESERVED_15A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_OFFSET                0x0000003c
+#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_16_RESERVED_16A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_OFFSET                0x00000040
+#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_17_RESERVED_17A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_OFFSET                0x00000044
+#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_18_RESERVED_18A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_OFFSET                0x00000048
+#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_19_RESERVED_19A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_OFFSET                0x0000004c
+#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_20_RESERVED_20A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_OFFSET                0x00000050
+#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_21_RESERVED_21A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_OFFSET                0x00000054
+#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_22_RESERVED_22A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_OFFSET                0x00000058
+#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_23_RESERVED_23A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_OFFSET                0x0000005c
+#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_24_RESERVED_24A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_OFFSET                0x00000060
+#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_MASK                  0x0fffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_OFFSET               0x00000060
+#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_LSB                  28
+#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_MASK                 0xf0000000
+
+
+#endif // _REO_FLUSH_CACHE_STATUS_H_

hw/qca6290/v1/reo_flush_queue.h

@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_FLUSH_QUEUE_H_
+#define _REO_FLUSH_QUEUE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	struct uniform_reo_cmd_header cmd_header;
+//	1	flush_desc_addr_31_0[31:0]
+//	2	flush_desc_addr_39_32[7:0], block_desc_addr_usage_after_flush[8], block_resource_index[10:9], reserved_2a[31:11]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9
+
+struct reo_flush_queue {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t flush_desc_addr_31_0            : 32; //[31:0]
+             uint32_t flush_desc_addr_39_32           :  8, //[7:0]
+                      block_desc_addr_usage_after_flush:  1, //[8]
+                      block_resource_index            :  2, //[10:9]
+                      reserved_2a                     : 21; //[31:11]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Details for command execution tracking purposes.
+
+flush_desc_addr_31_0
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Address (lower 32 bits) of the descriptor to flush
+			
+			<legal all>
+
+flush_desc_addr_39_32
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Address (upper 8 bits) of the descriptor to flush
+			
+			<legal all>
+
+block_desc_addr_usage_after_flush
+			
+			When set, REO shall not re-fetch this address till SW
+			explicitly unblocked this address
+			
+			
+			
+			If the blocking resource was already used, this command
+			shall fail and an error is reported
+			
+			
+			
+			<legal all>
+
+block_resource_index
+			
+			Field only valid when 'Block_desc_addr_usage_after_flush
+			' is set.
+			
+			
+			
+			Indicates which of the four blocking resources in REO
+			will be assigned for managing the blocking of this address.
+			
+			<legal all>
+
+reserved_2a
+			
+			<legal 0>
+
+reserved_3a
+			
+			<legal 0>
+
+reserved_4a
+			
+			<legal 0>
+
+reserved_5a
+			
+			<legal 0>
+
+reserved_6a
+			
+			<legal 0>
+
+reserved_7a
+			
+			<legal 0>
+
+reserved_8a
+			
+			<legal 0>
+*/
+
+#define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET   0x00000000
+#define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB      0
+#define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK     0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Address (lower 32 bits) of the descriptor to flush
+			
+			<legal all>
+*/
+#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET                0x00000004
+#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB                   0
+#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Address (upper 8 bits) of the descriptor to flush
+			
+			<legal all>
+*/
+#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET               0x00000008
+#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB                  0
+#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK                 0x000000ff
+
+/* Description		REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH
+			
+			When set, REO shall not re-fetch this address till SW
+			explicitly unblocked this address
+			
+			
+			
+			If the blocking resource was already used, this command
+			shall fail and an error is reported
+			
+			
+			
+			<legal all>
+*/
+#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET   0x00000008
+#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB      8
+#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK     0x00000100
+
+/* Description		REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX
+			
+			Field only valid when 'Block_desc_addr_usage_after_flush
+			' is set.
+			
+			
+			
+			Indicates which of the four blocking resources in REO
+			will be assigned for managing the blocking of this address.
+			
+			<legal all>
+*/
+#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET                0x00000008
+#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB                   9
+#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK                  0x00000600
+
+/* Description		REO_FLUSH_QUEUE_2_RESERVED_2A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET                         0x00000008
+#define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB                            11
+#define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK                           0xfffff800
+
+/* Description		REO_FLUSH_QUEUE_3_RESERVED_3A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET                         0x0000000c
+#define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB                            0
+#define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_4_RESERVED_4A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET                         0x00000010
+#define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB                            0
+#define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_5_RESERVED_5A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET                         0x00000014
+#define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB                            0
+#define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_6_RESERVED_6A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET                         0x00000018
+#define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB                            0
+#define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_7_RESERVED_7A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET                         0x0000001c
+#define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB                            0
+#define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_8_RESERVED_8A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET                         0x00000020
+#define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB                            0
+#define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK                           0xffffffff
+
+
+#endif // _REO_FLUSH_QUEUE_H_

hw/qca6290/v1/reo_flush_queue_status.h

@@ -0,0 +1,473 @@
+/*
+ * Copyright (c) 2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_FLUSH_QUEUE_STATUS_H_
+#define _REO_FLUSH_QUEUE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct uniform_reo_status_header status_header;
+//	2	error_detected[0], reserved_2a[31:1]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//	9	reserved_9a[31:0]
+//	10	reserved_10a[31:0]
+//	11	reserved_11a[31:0]
+//	12	reserved_12a[31:0]
+//	13	reserved_13a[31:0]
+//	14	reserved_14a[31:0]
+//	15	reserved_15a[31:0]
+//	16	reserved_16a[31:0]
+//	17	reserved_17a[31:0]
+//	18	reserved_18a[31:0]
+//	19	reserved_19a[31:0]
+//	20	reserved_20a[31:0]
+//	21	reserved_21a[31:0]
+//	22	reserved_22a[31:0]
+//	23	reserved_23a[31:0]
+//	24	reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 25
+
+struct reo_flush_queue_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t error_detected                  :  1, //[0]
+                      reserved_2a                     : 31; //[31:1]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+             uint32_t reserved_9a                     : 32; //[31:0]
+             uint32_t reserved_10a                    : 32; //[31:0]
+             uint32_t reserved_11a                    : 32; //[31:0]
+             uint32_t reserved_12a                    : 32; //[31:0]
+             uint32_t reserved_13a                    : 32; //[31:0]
+             uint32_t reserved_14a                    : 32; //[31:0]
+             uint32_t reserved_15a                    : 32; //[31:0]
+             uint32_t reserved_16a                    : 32; //[31:0]
+             uint32_t reserved_17a                    : 32; //[31:0]
+             uint32_t reserved_18a                    : 32; //[31:0]
+             uint32_t reserved_19a                    : 32; //[31:0]
+             uint32_t reserved_20a                    : 32; //[31:0]
+             uint32_t reserved_21a                    : 32; //[31:0]
+             uint32_t reserved_22a                    : 32; //[31:0]
+             uint32_t reserved_23a                    : 32; //[31:0]
+             uint32_t reserved_24a                    : 28, //[27:0]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+			
+			Consumer: SW
+			
+			Producer: REO
+			
+			
+			
+			Details that can link this status with the original
+			command. It also contains info on how long REO took to
+			execute this command.
+
+error_detected
+			
+			Status of the blocking resource
+			
+			0: No error has been detected while executing this
+			command
+			
+			1: Error detected: The resource to be used for blocking
+			was already in use.
+
+reserved_2a
+			
+			<legal 0>
+
+reserved_3a
+			
+			<legal 0>
+
+reserved_4a
+			
+			<legal 0>
+
+reserved_5a
+			
+			<legal 0>
+
+reserved_6a
+			
+			<legal 0>
+
+reserved_7a
+			
+			<legal 0>
+
+reserved_8a
+			
+			<legal 0>
+
+reserved_9a
+			
+			<legal 0>
+
+reserved_10a
+			
+			<legal 0>
+
+reserved_11a
+			
+			<legal 0>
+
+reserved_12a
+			
+			<legal 0>
+
+reserved_13a
+			
+			<legal 0>
+
+reserved_14a
+			
+			<legal 0>
+
+reserved_15a
+			
+			<legal 0>
+
+reserved_16a
+			
+			<legal 0>
+
+reserved_17a
+			
+			<legal 0>
+
+reserved_18a
+			
+			<legal 0>
+
+reserved_19a
+			
+			<legal 0>
+
+reserved_20a
+			
+			<legal 0>
+
+reserved_21a
+			
+			<legal 0>
+
+reserved_22a
+			
+			<legal 0>
+
+reserved_23a
+			
+			<legal 0>
+
+reserved_24a
+			
+			<legal 0>
+
+looping_count
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+#define REO_FLUSH_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_FLUSH_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+#define REO_FLUSH_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
+#define REO_FLUSH_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_FLUSH_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED
+			
+			Status of the blocking resource
+			
+			0: No error has been detected while executing this
+			command
+			
+			1: Error detected: The resource to be used for blocking
+			was already in use.
+*/
+#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_OFFSET               0x00000008
+#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_LSB                  0
+#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_MASK                 0x00000001
+
+/* Description		REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_OFFSET                  0x00000008
+#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_LSB                     1
+#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_MASK                    0xfffffffe
+
+/* Description		REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_OFFSET                  0x0000000c
+#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_OFFSET                  0x00000010
+#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_OFFSET                  0x00000014
+#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_OFFSET                  0x00000018
+#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_OFFSET                  0x0000001c
+#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_OFFSET                  0x00000020
+#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_OFFSET                  0x00000024
+#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_OFFSET                0x00000028
+#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_OFFSET                0x0000002c
+#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_OFFSET                0x00000030
+#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_OFFSET                0x00000034
+#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_OFFSET                0x00000038
+#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_OFFSET                0x0000003c
+#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_OFFSET                0x00000040
+#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_OFFSET                0x00000044
+#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_OFFSET                0x00000048
+#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_OFFSET                0x0000004c
+#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_OFFSET                0x00000050
+#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_OFFSET                0x00000054
+#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_OFFSET                0x00000058
+#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_OFFSET                0x0000005c
+#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_OFFSET                0x00000060
+#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_MASK                  0x0fffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET               0x00000060
+#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_LSB                  28
+#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_MASK                 0xf0000000
+
+
+#endif // _REO_FLUSH_QUEUE_STATUS_H_

hw/qca6290/v1/reo_flush_timeout_list.h

@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) 2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_FLUSH_TIMEOUT_LIST_H_
+#define _REO_FLUSH_TIMEOUT_LIST_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	struct uniform_reo_cmd_header cmd_header;
+//	1	ac_timout_list[1:0], reserved_1[31:2]
+//	2	minimum_release_desc_count[15:0], minimum_forward_buf_count[31:16]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9
+
+struct reo_flush_timeout_list {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t ac_timout_list                  :  2, //[1:0]
+                      reserved_1                      : 30; //[31:2]
+             uint32_t minimum_release_desc_count      : 16, //[15:0]
+                      minimum_forward_buf_count       : 16; //[31:16]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Details for command execution tracking purposes.
+
+ac_timout_list
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			The AC_timeout list to be used for this command
+			
+			<legal all>
+
+reserved_1
+			
+			<legal 0>
+
+minimum_release_desc_count
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			The minimum number of link descriptors requested to be
+			released. If set to 0, only buffer release counts seems to
+			be important... When set to very high value, likely the
+			entire timeout list will be exhausted before this count is
+			reached or maybe this count will not get reached. REO
+			however will stop here as it can not do anything else.
+			
+			
+			
+			When both this field and field Minimum_forward_buf_count
+			are > 0, REO needs to meet both requirements. When both
+			entries are 0 (which should be a programming error), REO
+			does not need to do anything.
+			
+			
+			
+			Note that this includes counts of MPDU link Desc as well
+			as MSDU link Desc. Where the count of MSDU link Desc is not
+			known to REO it's approximated by deriving from MSDU count
+			
+			<legal all>
+
+minimum_forward_buf_count
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			The minimum number of buffer descriptors requested to be
+			passed on to the REO destination rings. 
+			
+			
+			
+			If set to 0, only descriptor release counts seems to be
+			important... 
+			
+			
+			
+			When set to very high value, likely the entire timeout
+			list will be exhausted before this count is reached or maybe
+			this count will not get reached. REO however will stop here
+			as it can not do anything else.
+			
+			
+			
+			Note that REO does not know the exact buffer count. This
+			can be approximated by using the MSDU_COUNT
+			
+			<legal all>
+
+reserved_3a
+			
+			<legal 0>
+
+reserved_4a
+			
+			<legal 0>
+
+reserved_5a
+			
+			<legal 0>
+
+reserved_6a
+			
+			<legal 0>
+
+reserved_7a
+			
+			<legal 0>
+
+reserved_8a
+			
+			<legal 0>
+*/
+
+#define REO_FLUSH_TIMEOUT_LIST_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			The AC_timeout list to be used for this command
+			
+			<legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_OFFSET               0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_LSB                  0
+#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_MASK                 0x00000003
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_OFFSET                   0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_LSB                      2
+#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_MASK                     0xfffffffc
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			The minimum number of link descriptors requested to be
+			released. If set to 0, only buffer release counts seems to
+			be important... When set to very high value, likely the
+			entire timeout list will be exhausted before this count is
+			reached or maybe this count will not get reached. REO
+			however will stop here as it can not do anything else.
+			
+			
+			
+			When both this field and field Minimum_forward_buf_count
+			are > 0, REO needs to meet both requirements. When both
+			entries are 0 (which should be a programming error), REO
+			does not need to do anything.
+			
+			
+			
+			Note that this includes counts of MPDU link Desc as well
+			as MSDU link Desc. Where the count of MSDU link Desc is not
+			known to REO it's approximated by deriving from MSDU count
+			
+			<legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_OFFSET   0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_LSB      0
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_MASK     0x0000ffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			The minimum number of buffer descriptors requested to be
+			passed on to the REO destination rings. 
+			
+			
+			
+			If set to 0, only descriptor release counts seems to be
+			important... 
+			
+			
+			
+			When set to very high value, likely the entire timeout
+			list will be exhausted before this count is reached or maybe
+			this count will not get reached. REO however will stop here
+			as it can not do anything else.
+			
+			
+			
+			Note that REO does not know the exact buffer count. This
+			can be approximated by using the MSDU_COUNT
+			
+			<legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_OFFSET    0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_LSB       16
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_MASK      0xffff0000
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_OFFSET                  0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_OFFSET                  0x00000010
+#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_OFFSET                  0x00000014
+#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_OFFSET                  0x00000018
+#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_OFFSET                  0x0000001c
+#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_OFFSET                  0x00000020
+#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_MASK                    0xffffffff
+
+
+#endif // _REO_FLUSH_TIMEOUT_LIST_H_

hw/qca6290/v1/reo_flush_timeout_list_status.h

@@ -0,0 +1,545 @@
+/*
+ * Copyright (c) 2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
+#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct uniform_reo_status_header status_header;
+//	2	error_detected[0], timout_list_empty[1], reserved_2a[31:2]
+//	3	release_desc_count[15:0], forward_buf_count[31:16]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//	9	reserved_9a[31:0]
+//	10	reserved_10a[31:0]
+//	11	reserved_11a[31:0]
+//	12	reserved_12a[31:0]
+//	13	reserved_13a[31:0]
+//	14	reserved_14a[31:0]
+//	15	reserved_15a[31:0]
+//	16	reserved_16a[31:0]
+//	17	reserved_17a[31:0]
+//	18	reserved_18a[31:0]
+//	19	reserved_19a[31:0]
+//	20	reserved_20a[31:0]
+//	21	reserved_21a[31:0]
+//	22	reserved_22a[31:0]
+//	23	reserved_23a[31:0]
+//	24	reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 25
+
+struct reo_flush_timeout_list_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t error_detected                  :  1, //[0]
+                      timout_list_empty               :  1, //[1]
+                      reserved_2a                     : 30; //[31:2]
+             uint32_t release_desc_count              : 16, //[15:0]
+                      forward_buf_count               : 16; //[31:16]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+             uint32_t reserved_9a                     : 32; //[31:0]
+             uint32_t reserved_10a                    : 32; //[31:0]
+             uint32_t reserved_11a                    : 32; //[31:0]
+             uint32_t reserved_12a                    : 32; //[31:0]
+             uint32_t reserved_13a                    : 32; //[31:0]
+             uint32_t reserved_14a                    : 32; //[31:0]
+             uint32_t reserved_15a                    : 32; //[31:0]
+             uint32_t reserved_16a                    : 32; //[31:0]
+             uint32_t reserved_17a                    : 32; //[31:0]
+             uint32_t reserved_18a                    : 32; //[31:0]
+             uint32_t reserved_19a                    : 32; //[31:0]
+             uint32_t reserved_20a                    : 32; //[31:0]
+             uint32_t reserved_21a                    : 32; //[31:0]
+             uint32_t reserved_22a                    : 32; //[31:0]
+             uint32_t reserved_23a                    : 32; //[31:0]
+             uint32_t reserved_24a                    : 28, //[27:0]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+			
+			Consumer: SW
+			
+			Producer: REO
+			
+			
+			
+			Details that can link this status with the original
+			command. It also contains info on how long REO took to
+			execute this command.
+
+error_detected
+			
+			0: No error has been detected while executing this
+			command
+			
+			1: command not properly executed and returned with an
+			error
+			
+			
+			
+			NOTE: Current no error is defined, but field is put in
+			place to avoid data structure changes in future...
+
+timout_list_empty
+			
+			When set, REO has depleted the timeout list and all
+			entries are gone.
+			
+			<legal all>
+
+reserved_2a
+			
+			<legal 0>
+
+release_desc_count
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			The number of link descriptors released
+			
+			<legal all>
+
+forward_buf_count
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			The number of buffers forwarded to the REO destination
+			rings
+			
+			<legal all>
+
+reserved_4a
+			
+			<legal 0>
+
+reserved_5a
+			
+			<legal 0>
+
+reserved_6a
+			
+			<legal 0>
+
+reserved_7a
+			
+			<legal 0>
+
+reserved_8a
+			
+			<legal 0>
+
+reserved_9a
+			
+			<legal 0>
+
+reserved_10a
+			
+			<legal 0>
+
+reserved_11a
+			
+			<legal 0>
+
+reserved_12a
+			
+			<legal 0>
+
+reserved_13a
+			
+			<legal 0>
+
+reserved_14a
+			
+			<legal 0>
+
+reserved_15a
+			
+			<legal 0>
+
+reserved_16a
+			
+			<legal 0>
+
+reserved_17a
+			
+			<legal 0>
+
+reserved_18a
+			
+			<legal 0>
+
+reserved_19a
+			
+			<legal 0>
+
+reserved_20a
+			
+			<legal 0>
+
+reserved_21a
+			
+			<legal 0>
+
+reserved_22a
+			
+			<legal 0>
+
+reserved_23a
+			
+			<legal 0>
+
+reserved_24a
+			
+			<legal 0>
+
+looping_count
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED
+			
+			0: No error has been detected while executing this
+			command
+			
+			1: command not properly executed and returned with an
+			error
+			
+			
+			
+			NOTE: Current no error is defined, but field is put in
+			place to avoid data structure changes in future...
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_OFFSET        0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_LSB           0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_MASK          0x00000001
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY
+			
+			When set, REO has depleted the timeout list and all
+			entries are gone.
+			
+			<legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_OFFSET     0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_LSB        1
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_MASK       0x00000002
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_OFFSET           0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_LSB              2
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_MASK             0xfffffffc
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			The number of link descriptors released
+			
+			<legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_OFFSET    0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_LSB       0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_MASK      0x0000ffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			The number of buffers forwarded to the REO destination
+			rings
+			
+			<legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_OFFSET     0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_LSB        16
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_MASK       0xffff0000
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_OFFSET           0x00000010
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_MASK             0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_OFFSET           0x00000014
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_MASK             0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_OFFSET           0x00000018
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_MASK             0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_OFFSET           0x0000001c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_MASK             0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_OFFSET           0x00000020
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_MASK             0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_OFFSET           0x00000024
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_MASK             0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_OFFSET         0x00000028
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_OFFSET         0x0000002c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_OFFSET         0x00000030
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_OFFSET         0x00000034
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_OFFSET         0x00000038
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_OFFSET         0x0000003c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_OFFSET         0x00000040
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_OFFSET         0x00000044
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_OFFSET         0x00000048
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_OFFSET         0x0000004c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_OFFSET         0x00000050
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_OFFSET         0x00000054
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_OFFSET         0x00000058
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_OFFSET         0x0000005c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A
+			
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_OFFSET         0x00000060
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_MASK           0x0fffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_OFFSET        0x00000060
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_LSB           28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_MASK          0xf0000000
+
+
+#endif // _REO_FLUSH_TIMEOUT_LIST_STATUS_H_

hw/qca6290/v1/reo_unblock_cache.h

@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) 2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_UNBLOCK_CACHE_H_
+#define _REO_UNBLOCK_CACHE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	struct uniform_reo_cmd_header cmd_header;
+//	1	unblock_type[0], cache_block_resource_index[2:1], reserved_1a[31:3]
+//	2	reserved_2a[31:0]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9
+
+struct reo_unblock_cache {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t unblock_type                    :  1, //[0]
+                      cache_block_resource_index      :  2, //[2:1]
+                      reserved_1a                     : 29; //[31:3]
+             uint32_t reserved_2a                     : 32; //[31:0]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Details for command execution tracking purposes.
+
+unblock_type
+			
+			Unblock type
+			
+			
+			
+			<enum 0 unblock_resource_index> Unblock a block
+			resource, whose index is given in field
+			'cache_block_resource_index'.
+			
+			If the indicated blocking resource is not in use (=> not
+			blocking an address at the moment), the command status will
+			indicate an error.
+			
+			
+			
+			<enum 1 unblock_cache> The entire cache usage is
+			unblocked. 
+			
+			If the entire cache is not in a blocked mode at the
+			moment this command is received, the command status will
+			indicate an error.
+			
+			Note that unlocking the entire cache has no changes to
+			the current settings of the blocking resource settings
+			
+			
+			
+			<legal all>
+
+cache_block_resource_index
+			
+			Field not valid when field Unblock_type is set to
+			unblock_cache.
+			
+			
+			
+			Indicates which of the four blocking resources in REO
+			should be released from blocking a (descriptor) address.
+			
+			<legal all>
+
+reserved_1a
+			
+			<legal 0>
+
+reserved_2a
+			
+			<legal 0>
+
+reserved_3a
+			
+			<legal 0>
+
+reserved_4a
+			
+			<legal 0>
+
+reserved_5a
+			
+			<legal 0>
+
+reserved_6a
+			
+			<legal 0>
+
+reserved_7a
+			
+			<legal 0>
+
+reserved_8a
+			
+			<legal 0>
+*/
+
+#define REO_UNBLOCK_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB    0
+#define REO_UNBLOCK_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK   0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE
+			
+			Unblock type
+			
+			
+			
+			<enum 0 unblock_resource_index> Unblock a block
+			resource, whose index is given in field
+			'cache_block_resource_index'.
+			
+			If the indicated blocking resource is not in use (=> not
+			blocking an address at the moment), the command status will
+			indicate an error.
+			
+			
+			
+			<enum 1 unblock_cache> The entire cache usage is
+			unblocked. 
+			
+			If the entire cache is not in a blocked mode at the
+			moment this command is received, the command status will
+			indicate an error.
+			
+			Note that unlocking the entire cache has no changes to
+			the current settings of the blocking resource settings
+			
+			
+			
+			<legal all>
+*/
+#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_OFFSET                      0x00000004
+#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_LSB                         0
+#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_MASK                        0x00000001
+
+/* Description		REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX
+			
+			Field not valid when field Unblock_type is set to
+			unblock_cache.
+			
+			
+			
+			Indicates which of the four blocking resources in REO
+			should be released from blocking a (descriptor) address.
+			
+			<legal all>
+*/
+#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_OFFSET        0x00000004
+#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_LSB           1
+#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_MASK          0x00000006
+
+/* Description		REO_UNBLOCK_CACHE_1_RESERVED_1A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_1_RESERVED_1A_OFFSET                       0x00000004
+#define REO_UNBLOCK_CACHE_1_RESERVED_1A_LSB                          3
+#define REO_UNBLOCK_CACHE_1_RESERVED_1A_MASK                         0xfffffff8
+
+/* Description		REO_UNBLOCK_CACHE_2_RESERVED_2A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_2_RESERVED_2A_OFFSET                       0x00000008
+#define REO_UNBLOCK_CACHE_2_RESERVED_2A_LSB                          0
+#define REO_UNBLOCK_CACHE_2_RESERVED_2A_MASK                         0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_3_RESERVED_3A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_3_RESERVED_3A_OFFSET                       0x0000000c
+#define REO_UNBLOCK_CACHE_3_RESERVED_3A_LSB                          0
+#define REO_UNBLOCK_CACHE_3_RESERVED_3A_MASK                         0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_4_RESERVED_4A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_4_RESERVED_4A_OFFSET                       0x00000010
+#define REO_UNBLOCK_CACHE_4_RESERVED_4A_LSB                          0
+#define REO_UNBLOCK_CACHE_4_RESERVED_4A_MASK                         0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_5_RESERVED_5A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_5_RESERVED_5A_OFFSET                       0x00000014
+#define REO_UNBLOCK_CACHE_5_RESERVED_5A_LSB                          0
+#define REO_UNBLOCK_CACHE_5_RESERVED_5A_MASK                         0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_6_RESERVED_6A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_6_RESERVED_6A_OFFSET                       0x00000018
+#define REO_UNBLOCK_CACHE_6_RESERVED_6A_LSB                          0
+#define REO_UNBLOCK_CACHE_6_RESERVED_6A_MASK                         0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_7_RESERVED_7A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_7_RESERVED_7A_OFFSET                       0x0000001c
+#define REO_UNBLOCK_CACHE_7_RESERVED_7A_LSB                          0
+#define REO_UNBLOCK_CACHE_7_RESERVED_7A_MASK                         0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_8_RESERVED_8A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_8_RESERVED_8A_OFFSET                       0x00000020
+#define REO_UNBLOCK_CACHE_8_RESERVED_8A_LSB                          0
+#define REO_UNBLOCK_CACHE_8_RESERVED_8A_MASK                         0xffffffff
+
+
+#endif // _REO_UNBLOCK_CACHE_H_

hw/qca6290/v1/reo_unblock_cache_status.h

@@ -0,0 +1,518 @@
+/*
+ * Copyright (c) 2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_UNBLOCK_CACHE_STATUS_H_
+#define _REO_UNBLOCK_CACHE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct uniform_reo_status_header status_header;
+//	2	error_detected[0], unblock_type[1], reserved_2a[31:2]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//	9	reserved_9a[31:0]
+//	10	reserved_10a[31:0]
+//	11	reserved_11a[31:0]
+//	12	reserved_12a[31:0]
+//	13	reserved_13a[31:0]
+//	14	reserved_14a[31:0]
+//	15	reserved_15a[31:0]
+//	16	reserved_16a[31:0]
+//	17	reserved_17a[31:0]
+//	18	reserved_18a[31:0]
+//	19	reserved_19a[31:0]
+//	20	reserved_20a[31:0]
+//	21	reserved_21a[31:0]
+//	22	reserved_22a[31:0]
+//	23	reserved_23a[31:0]
+//	24	reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 25
+
+struct reo_unblock_cache_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t error_detected                  :  1, //[0]
+                      unblock_type                    :  1, //[1]
+                      reserved_2a                     : 30; //[31:2]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+             uint32_t reserved_9a                     : 32; //[31:0]
+             uint32_t reserved_10a                    : 32; //[31:0]
+             uint32_t reserved_11a                    : 32; //[31:0]
+             uint32_t reserved_12a                    : 32; //[31:0]
+             uint32_t reserved_13a                    : 32; //[31:0]
+             uint32_t reserved_14a                    : 32; //[31:0]
+             uint32_t reserved_15a                    : 32; //[31:0]
+             uint32_t reserved_16a                    : 32; //[31:0]
+             uint32_t reserved_17a                    : 32; //[31:0]
+             uint32_t reserved_18a                    : 32; //[31:0]
+             uint32_t reserved_19a                    : 32; //[31:0]
+             uint32_t reserved_20a                    : 32; //[31:0]
+             uint32_t reserved_21a                    : 32; //[31:0]
+             uint32_t reserved_22a                    : 32; //[31:0]
+             uint32_t reserved_23a                    : 32; //[31:0]
+             uint32_t reserved_24a                    : 28, //[27:0]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+			
+			Consumer: SW
+			
+			Producer: REO
+			
+			
+			
+			Details that can link this status with the original
+			command. It also contains info on how long REO took to
+			execute this command.
+
+error_detected
+			
+			Status for blocking resource handling
+			
+			
+			
+			0: No error has been detected while executing this
+			command
+			
+			1: The blocking resource was not in use, and therefor it
+			could not be 'unblocked'
+
+unblock_type
+			
+			Reference to the type of Unblock command type...
+			
+			
+			
+			<enum 0 unblock_resource_index> Unblock a blocking
+			resource
+			
+			
+			
+			<enum 1 unblock_cache> The entire cache usage is
+			unblock. 
+			
+			
+			
+			<legal all>
+
+reserved_2a
+			
+			<legal 0>
+
+reserved_3a
+			
+			<legal 0>
+
+reserved_4a
+			
+			<legal 0>
+
+reserved_5a
+			
+			<legal 0>
+
+reserved_6a
+			
+			<legal 0>
+
+reserved_7a
+			
+			<legal 0>
+
+reserved_8a
+			
+			<legal 0>
+
+reserved_9a
+			
+			<legal 0>
+
+reserved_10a
+			
+			<legal 0>
+
+reserved_11a
+			
+			<legal 0>
+
+reserved_12a
+			
+			<legal 0>
+
+reserved_13a
+			
+			<legal 0>
+
+reserved_14a
+			
+			<legal 0>
+
+reserved_15a
+			
+			<legal 0>
+
+reserved_16a
+			
+			<legal 0>
+
+reserved_17a
+			
+			<legal 0>
+
+reserved_18a
+			
+			<legal 0>
+
+reserved_19a
+			
+			<legal 0>
+
+reserved_20a
+			
+			<legal 0>
+
+reserved_21a
+			
+			<legal 0>
+
+reserved_22a
+			
+			<legal 0>
+
+reserved_23a
+			
+			<legal 0>
+
+reserved_24a
+			
+			<legal 0>
+
+looping_count
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+#define REO_UNBLOCK_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_UNBLOCK_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+#define REO_UNBLOCK_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_UNBLOCK_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED
+			
+			Status for blocking resource handling
+			
+			
+			
+			0: No error has been detected while executing this
+			command
+			
+			1: The blocking resource was not in use, and therefor it
+			could not be 'unblocked'
+*/
+#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_OFFSET             0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_LSB                0
+#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_MASK               0x00000001
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE
+			
+			Reference to the type of Unblock command type...
+			
+			
+			
+			<enum 0 unblock_resource_index> Unblock a blocking
+			resource
+			
+			
+			
+			<enum 1 unblock_cache> The entire cache usage is
+			unblock. 
+			
+			
+			
+			<legal all>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_OFFSET               0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_LSB                  1
+#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_MASK                 0x00000002
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_OFFSET                0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_LSB                   2
+#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_MASK                  0xfffffffc
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_OFFSET                0x0000000c
+#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_MASK                  0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_OFFSET                0x00000010
+#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_MASK                  0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_OFFSET                0x00000014
+#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_MASK                  0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_OFFSET                0x00000018
+#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_MASK                  0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_OFFSET                0x0000001c
+#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_MASK                  0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_OFFSET                0x00000020
+#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_MASK                  0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_OFFSET                0x00000024
+#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_MASK                  0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_OFFSET              0x00000028
+#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_OFFSET              0x0000002c
+#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_OFFSET              0x00000030
+#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_OFFSET              0x00000034
+#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_OFFSET              0x00000038
+#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_OFFSET              0x0000003c
+#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_OFFSET              0x00000040
+#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_OFFSET              0x00000044
+#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_OFFSET              0x00000048
+#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_OFFSET              0x0000004c
+#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_OFFSET              0x00000050
+#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_OFFSET              0x00000054
+#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_OFFSET              0x00000058
+#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_OFFSET              0x0000005c
+#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A
+			
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_OFFSET              0x00000060
+#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_MASK                0x0fffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_OFFSET             0x00000060
+#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_LSB                28
+#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_MASK               0xf0000000
+
+
+#endif // _REO_UNBLOCK_CACHE_STATUS_H_

hw/qca6290/v1/reo_update_rx_reo_queue.h

@@ -0,0 +1,1503 @@
+/*
+ * Copyright (c) 2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_UPDATE_RX_REO_QUEUE_H_
+#define _REO_UPDATE_RX_REO_QUEUE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	struct uniform_reo_cmd_header cmd_header;
+//	1	rx_reo_queue_desc_addr_31_0[31:0]
+//	2	rx_reo_queue_desc_addr_39_32[7:0], update_receive_queue_number[8], update_vld[9], update_associated_link_descriptor_counter[10], update_disable_duplicate_detection[11], update_soft_reorder_enable[12], update_ac[13], update_bar[14], update_rty[15], update_chk_2k_mode[16], update_oor_mode[17], update_ba_window_size[18], update_pn_check_needed[19], update_pn_shall_be_even[20], update_pn_shall_be_uneven[21], update_pn_handling_enable[22], update_pn_size[23], update_ignore_ampdu_flag[24], update_svld[25], update_ssn[26], update_seq_2k_error_detected_flag[27], update_pn_error_detected_flag[28], update_pn_valid[29], update_pn[30], reserved_2a[31]
+//	3	receive_queue_number[15:0], vld[16], associated_link_descriptor_counter[18:17], disable_duplicate_detection[19], soft_reorder_enable[20], ac[22:21], bar[23], rty[24], chk_2k_mode[25], oor_mode[26], pn_check_needed[27], pn_shall_be_even[28], pn_shall_be_uneven[29], pn_handling_enable[30], ignore_ampdu_flag[31]
+//	4	ba_window_size[7:0], pn_size[9:8], svld[10], ssn[22:11], seq_2k_error_detected_flag[23], pn_error_detected_flag[24], pn_valid[25], reserved_4a[31:26]
+//	5	pn_31_0[31:0]
+//	6	pn_63_32[31:0]
+//	7	pn_95_64[31:0]
+//	8	pn_127_96[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 9
+
+struct reo_update_rx_reo_queue {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t rx_reo_queue_desc_addr_31_0     : 32; //[31:0]
+             uint32_t rx_reo_queue_desc_addr_39_32    :  8, //[7:0]
+                      update_receive_queue_number     :  1, //[8]
+                      update_vld                      :  1, //[9]
+                      update_associated_link_descriptor_counter:  1, //[10]
+                      update_disable_duplicate_detection:  1, //[11]
+                      update_soft_reorder_enable      :  1, //[12]
+                      update_ac                       :  1, //[13]
+                      update_bar                      :  1, //[14]
+                      update_rty                      :  1, //[15]
+                      update_chk_2k_mode              :  1, //[16]
+                      update_oor_mode                 :  1, //[17]
+                      update_ba_window_size           :  1, //[18]
+                      update_pn_check_needed          :  1, //[19]
+                      update_pn_shall_be_even         :  1, //[20]
+                      update_pn_shall_be_uneven       :  1, //[21]
+                      update_pn_handling_enable       :  1, //[22]
+                      update_pn_size                  :  1, //[23]
+                      update_ignore_ampdu_flag        :  1, //[24]
+                      update_svld                     :  1, //[25]
+                      update_ssn                      :  1, //[26]
+                      update_seq_2k_error_detected_flag:  1, //[27]
+                      update_pn_error_detected_flag   :  1, //[28]
+                      update_pn_valid                 :  1, //[29]
+                      update_pn                       :  1, //[30]
+                      reserved_2a                     :  1; //[31]
+             uint32_t receive_queue_number            : 16, //[15:0]
+                      vld                             :  1, //[16]
+                      associated_link_descriptor_counter:  2, //[18:17]
+                      disable_duplicate_detection     :  1, //[19]
+                      soft_reorder_enable             :  1, //[20]
+                      ac                              :  2, //[22:21]
+                      bar                             :  1, //[23]
+                      rty                             :  1, //[24]
+                      chk_2k_mode                     :  1, //[25]
+                      oor_mode                        :  1, //[26]
+                      pn_check_needed                 :  1, //[27]
+                      pn_shall_be_even                :  1, //[28]
+                      pn_shall_be_uneven              :  1, //[29]
+                      pn_handling_enable              :  1, //[30]
+                      ignore_ampdu_flag               :  1; //[31]
+             uint32_t ba_window_size                  :  8, //[7:0]
+                      pn_size                         :  2, //[9:8]
+                      svld                            :  1, //[10]
+                      ssn                             : 12, //[22:11]
+                      seq_2k_error_detected_flag      :  1, //[23]
+                      pn_error_detected_flag          :  1, //[24]
+                      pn_valid                        :  1, //[25]
+                      reserved_4a                     :  6; //[31:26]
+             uint32_t pn_31_0                         : 32; //[31:0]
+             uint32_t pn_63_32                        : 32; //[31:0]
+             uint32_t pn_95_64                        : 32; //[31:0]
+             uint32_t pn_127_96                       : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Details for command execution tracking purposes.
+
+rx_reo_queue_desc_addr_31_0
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Address (lower 32 bits) of the REO queue descriptor
+			
+			<legal all>
+
+rx_reo_queue_desc_addr_39_32
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Address (upper 8 bits) of the REO queue descriptor
+			
+			<legal all>
+
+update_receive_queue_number
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, receive_queue_number from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+
+update_vld
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, VLD from this command will be updated in the
+			descriptor.
+			
+			<legal all>
+
+update_associated_link_descriptor_counter
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Associated_link_descriptor_counter from this
+			command will be updated in the descriptor.
+			
+			<legal all>
+
+update_disable_duplicate_detection
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Disable_duplicate_detection from this command
+			will be updated in the descriptor.
+			
+			<legal all>
+
+update_soft_reorder_enable
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Soft_reorder_enable from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+
+update_ac
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, AC from this command will be updated in the
+			descriptor.
+			
+			<legal all>
+
+update_bar
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, BAR from this command will be updated in the
+			descriptor.
+			
+			<legal all>
+
+update_rty
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, RTY from this command will be updated in the
+			descriptor.
+			
+			<legal all>
+
+update_chk_2k_mode
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Chk_2k_mode from this command will be updated
+			in the descriptor.
+			
+			<legal all>
+
+update_oor_mode
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, OOR_Mode from this command will be updated in
+			the descriptor.
+			
+			<legal all>
+
+update_ba_window_size
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, BA_window_size from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+
+update_pn_check_needed
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Pn_check_needed from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+
+update_pn_shall_be_even
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Pn_shall_be_even from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+
+update_pn_shall_be_uneven
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Pn_shall_be_uneven from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+
+update_pn_handling_enable
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Pn_handling_enable from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+
+update_pn_size
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Pn_size from this command will be updated in
+			the descriptor.
+			
+			<legal all>
+
+update_ignore_ampdu_flag
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Ignore_ampdu_flag from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+
+update_svld
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Svld from this command will be updated in the
+			descriptor.
+			
+			<legal all>
+
+update_ssn
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, SSN from this command will be updated in the
+			descriptor.
+			
+			<legal all>
+
+update_seq_2k_error_detected_flag
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Seq_2k_error_detected_flag from this command
+			will be updated in the descriptor.
+			
+			<legal all>
+
+update_pn_error_detected_flag
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, pn_error_detected_flag from this command will
+			be updated in the descriptor.
+			
+			<legal all>
+
+update_pn_valid
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, pn_valid from this command will be updated in
+			the descriptor.
+			
+			<legal all>
+
+update_pn
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, all pn_... fields from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+
+reserved_2a
+			
+			<legal 0>
+
+receive_queue_number
+			
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+vld
+			
+			Field only valid when Update_VLD is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+associated_link_descriptor_counter
+			
+			Field only valid when
+			Update_Associated_link_descriptor_counter is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+disable_duplicate_detection
+			
+			Field only valid when Update_Disable_duplicate_detection
+			is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+soft_reorder_enable
+			
+			Field only valid when Update_Soft_reorder_enable is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+ac
+			
+			Field only valid when Update_AC is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+bar
+			
+			Field only valid when Update_BAR is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+rty
+			
+			Field only valid when Update_RTY is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+chk_2k_mode
+			
+			Field only valid when Update_Chk_2k_Mode is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+oor_mode
+			
+			Field only valid when Update_OOR_Mode is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+pn_check_needed
+			
+			Field only valid when Update_Pn_check_needed is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+pn_shall_be_even
+			
+			Field only valid when Update_Pn_shall_be_even is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+pn_shall_be_uneven
+			
+			Field only valid when Update_Pn_shall_be_uneven is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+pn_handling_enable
+			
+			Field only valid when Update_Pn_handling_enable is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+ignore_ampdu_flag
+			
+			Field only valid when Update_Ignore_ampdu_flag is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+ba_window_size
+			
+			Field only valid when Update_BA_window_size is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+pn_size
+			
+			Field only valid when Update_Pn_size is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			
+			
+			<enum 0     pn_size_24>
+			
+			<enum 1     pn_size_48>
+			
+			<enum 2     pn_size_128>
+			
+			
+			
+			<legal 0-2>
+
+svld
+			
+			Field only valid when Update_Svld is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+ssn
+			
+			Field only valid when Update_SSN is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+seq_2k_error_detected_flag
+			
+			Field only valid when Update_Seq_2k_error_detected_flag
+			is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+pn_error_detected_flag
+			
+			Field only valid when Update_pn_error_detected_flag is
+			set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+pn_valid
+			
+			Field only valid when Update_pn_valid is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+reserved_4a
+			
+			<legal 0>
+
+pn_31_0
+			
+			Field only valid when Update_Pn is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+pn_63_32
+			
+			Field only valid when Update_pn is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+pn_95_64
+			
+			Field only valid when Update_pn is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+
+pn_127_96
+			
+			Field only valid when Update_pn is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+
+#define REO_UPDATE_RX_REO_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Address (lower 32 bits) of the REO queue descriptor
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB    0
+#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK   0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Address (upper 8 bits) of the REO queue descriptor
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB   0
+#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK  0x000000ff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, receive_queue_number from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_LSB    8
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_MASK   0x00000100
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, VLD from this command will be updated in the
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_OFFSET                  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_LSB                     9
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_MASK                    0x00000200
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Associated_link_descriptor_counter from this
+			command will be updated in the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000400
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Disable_duplicate_detection from this command
+			will be updated in the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000800
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Soft_reorder_enable from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_OFFSET  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_LSB     12
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_MASK    0x00001000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, AC from this command will be updated in the
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_OFFSET                   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_LSB                      13
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_MASK                     0x00002000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, BAR from this command will be updated in the
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_OFFSET                  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_LSB                     14
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_MASK                    0x00004000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, RTY from this command will be updated in the
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_OFFSET                  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_LSB                     15
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_MASK                    0x00008000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Chk_2k_mode from this command will be updated
+			in the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_OFFSET          0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_LSB             16
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_MASK            0x00010000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, OOR_Mode from this command will be updated in
+			the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_OFFSET             0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_LSB                17
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_MASK               0x00020000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, BA_window_size from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_OFFSET       0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_LSB          18
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_MASK         0x00040000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Pn_check_needed from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_OFFSET      0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_LSB         19
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_MASK        0x00080000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Pn_shall_be_even from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_OFFSET     0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_LSB        20
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_MASK       0x00100000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Pn_shall_be_uneven from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_LSB      21
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_MASK     0x00200000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Pn_handling_enable from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_OFFSET   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_LSB      22
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_MASK     0x00400000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Pn_size from this command will be updated in
+			the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_OFFSET              0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_LSB                 23
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_MASK                0x00800000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Ignore_ampdu_flag from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_OFFSET    0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_LSB       24
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_MASK      0x01000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Svld from this command will be updated in the
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_OFFSET                 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_LSB                    25
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_MASK                   0x02000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, SSN from this command will be updated in the
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_OFFSET                  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_LSB                     26
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_MASK                    0x04000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, Seq_2k_error_detected_flag from this command
+			will be updated in the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x08000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, pn_error_detected_flag from this command will
+			be updated in the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_LSB  28
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x10000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, pn_valid from this command will be updated in
+			the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_OFFSET             0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_LSB                29
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_MASK               0x20000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			When set, all pn_... fields from this command will be
+			updated in the descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_OFFSET                   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_LSB                      30
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_MASK                     0x40000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_RESERVED_2A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_RESERVED_2A_OFFSET                 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_RESERVED_2A_LSB                    31
+#define REO_UPDATE_RX_REO_QUEUE_2_RESERVED_2A_MASK                   0x80000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER
+			
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_OFFSET        0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_MASK          0x0000ffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_VLD
+			
+			Field only valid when Update_VLD is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_VLD_OFFSET                         0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_VLD_LSB                            16
+#define REO_UPDATE_RX_REO_QUEUE_3_VLD_MASK                           0x00010000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER
+			
+			Field only valid when
+			Update_Associated_link_descriptor_counter is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 17
+#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00060000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION
+			
+			Field only valid when Update_Disable_duplicate_detection
+			is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_LSB    19
+#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_MASK   0x00080000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE
+			
+			Field only valid when Update_Soft_reorder_enable is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_OFFSET         0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_LSB            20
+#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_MASK           0x00100000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_AC
+			
+			Field only valid when Update_AC is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_AC_OFFSET                          0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_AC_LSB                             21
+#define REO_UPDATE_RX_REO_QUEUE_3_AC_MASK                            0x00600000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_BAR
+			
+			Field only valid when Update_BAR is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_BAR_OFFSET                         0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_BAR_LSB                            23
+#define REO_UPDATE_RX_REO_QUEUE_3_BAR_MASK                           0x00800000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_RTY
+			
+			Field only valid when Update_RTY is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_RTY_OFFSET                         0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_RTY_LSB                            24
+#define REO_UPDATE_RX_REO_QUEUE_3_RTY_MASK                           0x01000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE
+			
+			Field only valid when Update_Chk_2k_Mode is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_OFFSET                 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_LSB                    25
+#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_MASK                   0x02000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE
+			
+			Field only valid when Update_OOR_Mode is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_OFFSET                    0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_LSB                       26
+#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_MASK                      0x04000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED
+			
+			Field only valid when Update_Pn_check_needed is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_OFFSET             0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_LSB                27
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_MASK               0x08000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN
+			
+			Field only valid when Update_Pn_shall_be_even is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_OFFSET            0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_LSB               28
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_MASK              0x10000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN
+			
+			Field only valid when Update_Pn_shall_be_uneven is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_OFFSET          0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_LSB             29
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_MASK            0x20000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE
+			
+			Field only valid when Update_Pn_handling_enable is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_OFFSET          0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_LSB             30
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_MASK            0x40000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG
+			
+			Field only valid when Update_Ignore_ampdu_flag is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_OFFSET           0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_LSB              31
+#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_MASK             0x80000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE
+			
+			Field only valid when Update_BA_window_size is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_OFFSET              0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_LSB                 0
+#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_MASK                0x000000ff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE
+			
+			Field only valid when Update_Pn_size is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			
+			
+			<enum 0     pn_size_24>
+			
+			<enum 1     pn_size_48>
+			
+			<enum 2     pn_size_128>
+			
+			
+			
+			<legal 0-2>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_OFFSET                     0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_LSB                        8
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_MASK                       0x00000300
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_4_SVLD
+			
+			Field only valid when Update_Svld is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_OFFSET                        0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_LSB                           10
+#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_MASK                          0x00000400
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_4_SSN
+			
+			Field only valid when Update_SSN is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_SSN_OFFSET                         0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_SSN_LSB                            11
+#define REO_UPDATE_RX_REO_QUEUE_4_SSN_MASK                           0x007ff800
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG
+			
+			Field only valid when Update_Seq_2k_error_detected_flag
+			is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET  0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_LSB     23
+#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_MASK    0x00800000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG
+			
+			Field only valid when Update_pn_error_detected_flag is
+			set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_OFFSET      0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_LSB         24
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_MASK        0x01000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_4_PN_VALID
+			
+			Field only valid when Update_pn_valid is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_OFFSET                    0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_LSB                       25
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_MASK                      0x02000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_OFFSET                 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_LSB                    26
+#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_MASK                   0xfc000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_5_PN_31_0
+			
+			Field only valid when Update_Pn is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_OFFSET                     0x00000014
+#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_LSB                        0
+#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_MASK                       0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_6_PN_63_32
+			
+			Field only valid when Update_pn is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_OFFSET                    0x00000018
+#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_LSB                       0
+#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_MASK                      0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_7_PN_95_64
+			
+			Field only valid when Update_pn is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_OFFSET                    0x0000001c
+#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_LSB                       0
+#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_MASK                      0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_8_PN_127_96
+			
+			Field only valid when Update_pn is set
+			
+			
+			
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_OFFSET                   0x00000020
+#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_LSB                      0
+#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_MASK                     0xffffffff
+
+
+#endif // _REO_UPDATE_RX_REO_QUEUE_H_

hw/qca6290/v1/reo_update_rx_reo_queue_status.h

@@ -0,0 +1,448 @@
+/*
+ * Copyright (c) 2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
+#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct uniform_reo_status_header status_header;
+//	2	reserved_2a[31:0]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//	9	reserved_9a[31:0]
+//	10	reserved_10a[31:0]
+//	11	reserved_11a[31:0]
+//	12	reserved_12a[31:0]
+//	13	reserved_13a[31:0]
+//	14	reserved_14a[31:0]
+//	15	reserved_15a[31:0]
+//	16	reserved_16a[31:0]
+//	17	reserved_17a[31:0]
+//	18	reserved_18a[31:0]
+//	19	reserved_19a[31:0]
+//	20	reserved_20a[31:0]
+//	21	reserved_21a[31:0]
+//	22	reserved_22a[31:0]
+//	23	reserved_23a[31:0]
+//	24	reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 25
+
+struct reo_update_rx_reo_queue_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t reserved_2a                     : 32; //[31:0]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+             uint32_t reserved_9a                     : 32; //[31:0]
+             uint32_t reserved_10a                    : 32; //[31:0]
+             uint32_t reserved_11a                    : 32; //[31:0]
+             uint32_t reserved_12a                    : 32; //[31:0]
+             uint32_t reserved_13a                    : 32; //[31:0]
+             uint32_t reserved_14a                    : 32; //[31:0]
+             uint32_t reserved_15a                    : 32; //[31:0]
+             uint32_t reserved_16a                    : 32; //[31:0]
+             uint32_t reserved_17a                    : 32; //[31:0]
+             uint32_t reserved_18a                    : 32; //[31:0]
+             uint32_t reserved_19a                    : 32; //[31:0]
+             uint32_t reserved_20a                    : 32; //[31:0]
+             uint32_t reserved_21a                    : 32; //[31:0]
+             uint32_t reserved_22a                    : 32; //[31:0]
+             uint32_t reserved_23a                    : 32; //[31:0]
+             uint32_t reserved_24a                    : 28, //[27:0]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+			
+			Consumer: SW
+			
+			Producer: REO
+			
+			
+			
+			Details that can link this status with the original
+			command. It also contains info on how long REO took to
+			execute this command.
+
+reserved_2a
+			
+			<legal 0>
+
+reserved_3a
+			
+			<legal 0>
+
+reserved_4a
+			
+			<legal 0>
+
+reserved_5a
+			
+			<legal 0>
+
+reserved_6a
+			
+			<legal 0>
+
+reserved_7a
+			
+			<legal 0>
+
+reserved_8a
+			
+			<legal 0>
+
+reserved_9a
+			
+			<legal 0>
+
+reserved_10a
+			
+			<legal 0>
+
+reserved_11a
+			
+			<legal 0>
+
+reserved_12a
+			
+			<legal 0>
+
+reserved_13a
+			
+			<legal 0>
+
+reserved_14a
+			
+			<legal 0>
+
+reserved_15a
+			
+			<legal 0>
+
+reserved_16a
+			
+			<legal 0>
+
+reserved_17a
+			
+			<legal 0>
+
+reserved_18a
+			
+			<legal 0>
+
+reserved_19a
+			
+			<legal 0>
+
+reserved_20a
+			
+			<legal 0>
+
+reserved_21a
+			
+			<legal 0>
+
+reserved_22a
+			
+			<legal 0>
+
+reserved_23a
+			
+			<legal 0>
+
+reserved_24a
+			
+			<legal 0>
+
+looping_count
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_OFFSET          0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_MASK            0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_OFFSET          0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_MASK            0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_OFFSET          0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_MASK            0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_OFFSET          0x00000014
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_MASK            0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_OFFSET          0x00000018
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_MASK            0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_OFFSET          0x0000001c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_MASK            0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_OFFSET          0x00000020
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_MASK            0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_OFFSET          0x00000024
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_MASK            0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_OFFSET        0x00000028
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_OFFSET        0x0000002c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_OFFSET        0x00000030
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_OFFSET        0x00000034
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_OFFSET        0x00000038
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_OFFSET        0x0000003c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_OFFSET        0x00000040
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_OFFSET        0x00000044
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_OFFSET        0x00000048
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_OFFSET        0x0000004c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_OFFSET        0x00000050
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_OFFSET        0x00000054
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_OFFSET        0x00000058
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_OFFSET        0x0000005c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A
+			
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_OFFSET        0x00000060
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_MASK          0x0fffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET       0x00000060
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_LSB          28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_MASK         0xf0000000
+
+
+#endif // _REO_UPDATE_RX_REO_QUEUE_STATUS_H_

hw/qca6290/v1/wcss_version.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#define WCSS_VERSION 72