Merge "msm: camera: csiphy: Add support for enable/disable CSIRX for PRBS9" into camera-kernel.lnx.5.0

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

@@ -429,6 +429,7 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 	uint32_t                lane_enable = 0;
 	uint16_t                lane_assign = 0;
 	uint8_t                 lane_cnt = 0;
+	uint16_t                preamble_en = 0;
 
 	if (!cfg_dev || !csiphy_dev) {
 		CAM_ERR(CAM_CSIPHY, "Invalid Args");
@@ -502,6 +503,27 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 		return rc;
 	}
 
+
+	preamble_en = (cam_cmd_csiphy_info->mipi_flags &
+		PREAMBLE_PATTEN_CAL_MASK);
+
+	/* Cannot support CPHY combo mode with One sensor setting
+	 * preamble enable and second/third sensor is without
+	 * preamble enable.
+	 */
+	if (csiphy_dev->preamble_enable && !preamble_en &&
+		csiphy_dev->csiphy_info[index].csiphy_3phase) {
+		CAM_ERR(CAM_CSIPHY,
+			"Cannot support CPHY combo mode with differnt preamble settings");
+		return -EINVAL;
+	} else if (preamble_en &&
+		!csiphy_dev->csiphy_info[index].csiphy_3phase) {
+		CAM_ERR(CAM_CSIPHY,
+			"Preamble pattern enablement is not supported for DPHY sensors");
+		return -EINVAL;
+	}
+
+	csiphy_dev->preamble_enable = preamble_en;
 	csiphy_dev->csiphy_info[index].lane_cnt = cam_cmd_csiphy_info->lane_cnt;
 	csiphy_dev->csiphy_info[index].lane_assign =
 		cam_cmd_csiphy_info->lane_assign;
@@ -513,7 +535,7 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 	csiphy_dev->csiphy_info[index].secure_mode =
 		cam_cmd_csiphy_info->secure_mode;
 	csiphy_dev->csiphy_info[index].mipi_flags =
-		cam_cmd_csiphy_info->mipi_flags;
+		(cam_cmd_csiphy_info->mipi_flags & SKEW_CAL_MASK);
 
 	lane_assign = csiphy_dev->csiphy_info[index].lane_assign;
 	lane_cnt = csiphy_dev->csiphy_info[index].lane_cnt;
@@ -543,9 +565,10 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 			index);
 
 	CAM_DBG(CAM_CSIPHY,
-		"phy version:%d, phy_idx: %d",
+		"phy version:%d, phy_idx: %d, preamble_en: %u",
 		csiphy_dev->hw_version,
-		csiphy_dev->soc_info.index);
+		csiphy_dev->soc_info.index,
+		csiphy_dev->preamble_enable);
 	CAM_DBG(CAM_CSIPHY,
 		"3phase:%d, combo mode:%d, secure mode:%d",
 		csiphy_dev->csiphy_info[index].csiphy_3phase,
@@ -705,8 +728,7 @@ static int cam_csiphy_cphy_data_rate_config(
 	intermediate_var = csiphy_device->csiphy_info[idx].settle_time;
 	do_div(intermediate_var, 200000000);
 	settle_cnt = intermediate_var;
-	skew_cal_enable =
-		csiphy_device->csiphy_info[idx].mipi_flags & SKEW_CAL_MASK;
+	skew_cal_enable = csiphy_device->csiphy_info[idx].mipi_flags;
 
 	CAM_DBG(CAM_CSIPHY, "required data rate : %llu", phy_data_rate);
 	for (data_rate_idx = 0; data_rate_idx < num_table_entries;
@@ -789,6 +811,38 @@ static int cam_csiphy_cphy_data_rate_config(
 	return 0;
 }
 
+static int __cam_csiphy_prgm_bist_reg(struct csiphy_device *csiphy_dev, bool is_3phase)
+{
+	int i = 0;
+	int bist_arr_size = csiphy_dev->ctrl_reg->csiphy_bist_reg->num_data_settings;
+	struct csiphy_reg_t *csiphy_common_reg = NULL;
+	void __iomem *csiphybase = NULL;
+
+	csiphybase = csiphy_dev->soc_info.reg_map[0].mem_base;
+
+	for (i = 0; i < bist_arr_size; i++) {
+		csiphy_common_reg = &csiphy_dev->ctrl_reg->csiphy_bist_reg->bist_arry[i];
+		switch (csiphy_common_reg->csiphy_param_type) {
+		case CSIPHY_3PH_REGS:
+			if (is_3phase)
+				cam_io_w_mb(csiphy_common_reg->reg_data,
+					csiphybase + csiphy_common_reg->reg_addr);
+		break;
+		case CSIPHY_2PH_REGS:
+			if (!is_3phase)
+				cam_io_w_mb(csiphy_common_reg->reg_data,
+						csiphybase + csiphy_common_reg->reg_addr);
+		break;
+		default:
+			cam_io_w_mb(csiphy_common_reg->reg_data,
+				csiphybase + csiphy_common_reg->reg_addr);
+		break;
+		}
+	}
+
+	return 0;
+}
+
 int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev,
 	int32_t dev_handle)
 {
@@ -939,8 +993,7 @@ int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev,
 	intermediate_var = csiphy_dev->csiphy_info[index].settle_time;
 	do_div(intermediate_var, 200000000);
 	settle_cnt = intermediate_var;
-	skew_cal_enable =
-		csiphy_dev->csiphy_info[index].mipi_flags & SKEW_CAL_MASK;
+	skew_cal_enable = csiphy_dev->csiphy_info[index].mipi_flags;
 
 	for (lane_pos = 0; lane_pos < max_lanes; lane_pos++) {
 		CAM_DBG(CAM_CSIPHY, "lane_pos: %d is configuring", lane_pos);
@@ -983,6 +1036,8 @@ int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev,
 		}
 	}
 
+	if (csiphy_dev->preamble_enable)
+		__cam_csiphy_prgm_bist_reg(csiphy_dev, is_3phase);
 	if (csiphy_dev->csiphy_info[index].csiphy_3phase) {
 		rc = cam_csiphy_cphy_data_rate_config(csiphy_dev, index);
 		if (rc) {

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h

@@ -204,6 +204,11 @@ struct data_rate_settings_t {
 	struct data_rate_reg_info_t data_rate_settings[MAX_DATA_RATES];
 };
 
+struct bist_reg_settings_t {
+	ssize_t num_data_settings;
+	struct csiphy_reg_t *bist_arry;
+};
+
 /**
  * struct csiphy_ctrl_t
  * @csiphy_reg                : Register address
@@ -228,6 +233,7 @@ struct csiphy_ctrl_t {
 	struct csiphy_reg_t (*csiphy_3ph_reg)[MAX_SETTINGS_PER_LANE];
 	struct csiphy_reg_t (*csiphy_3ph_combo_reg)[MAX_SETTINGS_PER_LANE];
 	struct csiphy_reg_t (*csiphy_2ph_3ph_mode_reg)[MAX_SETTINGS_PER_LANE];
+	struct bist_reg_settings_t *csiphy_bist_reg;
 	enum   cam_vote_level (*getclockvoting)(struct csiphy_device *phy_dev,
 		int32_t index);
 	struct data_rate_settings_t *data_rates_settings_table;
@@ -288,7 +294,7 @@ struct cam_csiphy_param {
  * @crm_cb                     : Callback API pointers
  * @enable_irq_dump            : Debugfs flag to enable hw IRQ register dump
  * @en_status_reg_dump         : Debugfs flag to enable cphy/dphy specific
- *                               status register dump
+ * @preamble_enable            : To enable preamble pattern
  */
 struct csiphy_device {
 	char                           device_name[CAM_CTX_DEV_NAME_MAX_LENGTH];
@@ -320,6 +326,7 @@ struct csiphy_device {
 	struct cam_req_mgr_crm_cb     *crm_cb;
 	bool                           enable_irq_dump;
 	bool                           en_status_reg_dump;
+	uint16_t                       preamble_enable;
 };
 
 /**

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c

@@ -477,6 +477,7 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
 		csiphy_dev->is_divisor_32_comp = true;
 		csiphy_dev->clk_lane = 0;
 		csiphy_dev->ctrl_reg->data_rates_settings_table = NULL;
+		csiphy_dev->ctrl_reg->csiphy_bist_reg = &bist_setting_2_1_0;
 	} else {
 		CAM_ERR(CAM_CSIPHY, "invalid hw version : 0x%x",
 			csiphy_dev->hw_version);

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_0_hwreg.h

@@ -476,4 +476,28 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 	},
 };
 
+struct csiphy_reg_t bist_arr_2_1_0[] = {
+	/* 3Phase BIST CONFIGURATION REG SET */
+	{0x02D4, 0x64, 0x00, CSIPHY_3PH_REGS},
+	{0x02D8, 0x3E, 0x00, CSIPHY_3PH_REGS},
+	{0x0250, 0x00, 0x00, CSIPHY_3PH_REGS},
+	{0x0244, 0xB1, 0x00, CSIPHY_3PH_REGS},
+	{0x0240, 0x85, 0x00, CSIPHY_3PH_REGS},
+	{0x06D4, 0x64, 0x00, CSIPHY_3PH_REGS},
+	{0x06D8, 0x3E, 0x00, CSIPHY_3PH_REGS},
+	{0x0650, 0x00, 0x00, CSIPHY_3PH_REGS},
+	{0x0644, 0xB1, 0x00, CSIPHY_3PH_REGS},
+	{0x0640, 0x85, 0x00, CSIPHY_3PH_REGS},
+	{0x0AD4, 0x64, 0x00, CSIPHY_3PH_REGS},
+	{0x0AD8, 0x3E, 0x00, CSIPHY_3PH_REGS},
+	{0x0A50, 0x00, 0x00, CSIPHY_3PH_REGS},
+	{0x0A44, 0xB1, 0x00, CSIPHY_3PH_REGS},
+	{0x0A40, 0x85, 0x00, CSIPHY_3PH_REGS},
+};
+
+struct bist_reg_settings_t bist_setting_2_1_0 = {
+	.num_data_settings = ARRAY_SIZE(bist_arr_2_1_0),
+	.bist_arry = bist_arr_2_1_0,
+};
+
 #endif /* _CAM_CSIPHY_2_1_0_HWREG_H_ */