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asoc: bolero: check if clock is enabled before accessing register

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Reset GFMUX reg for va-macro and wsa-macro when adsp is up
after SSR. And check if clock is enabled before accessing
register to avoid kernel panic.

Change-Id: Idce9695be552cab0e8e389cf72eeb7a67a754bf9
Signed-off-by: Meng Wang <mengw@codeaurora.org>
This commit is contained in:
Meng Wang
2019-06-25 09:39:48 +08:00
parent 5a2bcfb472
commit bd93024823
3 changed files with 35 additions and 5 deletions
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13
asoc/codecs/bolero/wsa-macro.c
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@@ -905,6 +905,7 @@ static int wsa_macro_event_handler(struct snd_soc_component *component,
{
struct device *wsa_dev = NULL;
struct wsa_macro_priv *wsa_priv = NULL;
int ret = 0;
if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__))
return -EINVAL;
@@ -923,6 +924,18 @@ static int wsa_macro_event_handler(struct snd_soc_component *component,
case BOLERO_MACRO_EVT_SSR_UP:
/* reset swr after ssr/pdr */
wsa_priv->reset_swr = true;
/* enable&disable WSA_CORE_CLK to reset GFMUX reg */
ret = bolero_clk_rsc_request_clock(wsa_priv->dev,
wsa_priv->default_clk_id,
WSA_CORE_CLK, true);
if (ret < 0)
dev_err_ratelimited(wsa_priv->dev,
"%s, failed to enable clk, ret:%d\n",
__func__, ret);
else
bolero_clk_rsc_request_clock(wsa_priv->dev,
wsa_priv->default_clk_id,
WSA_CORE_CLK, false);
if (wsa_priv->swr_ctrl_data)
swrm_wcd_notify(
wsa_priv->swr_ctrl_data[0].wsa_swr_pdev,