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soc: swr-mstr: switch to bank 0 before ssr/pdr

Do bank switch to default bank during ssr/pdr as master
is reset to default state. This avoids wrong state of
swr master during pdr.

Change-Id: I86a7bd53d471e9d864d25dcb84ad8fe12151cc0d
Signed-off-by: Ramprasad Katkam <[email protected]>
Ramprasad Katkam 6 年之前
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b4c7c680ef
共有 1 个文件被更改,包括 3 次插入1 次删除
  1. 3 1
      soc/swr-mstr-ctrl.c

+ 3 - 1
soc/swr-mstr-ctrl.c

@@ -493,9 +493,9 @@ static int swrm_cmd_fifo_wr_cmd(struct swr_mstr_ctrl *swrm, u8 cmd_data,
 	dev_dbg(swrm->dev, "%s: reg: 0x%x, cmd_id: 0x%x,wcmd_id: 0x%x, \
 			dev_num: 0x%x, cmd_data: 0x%x\n", __func__,
 			reg_addr, cmd_id, swrm->wcmd_id,dev_addr, cmd_data);
+	swr_master_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
 	/* wait for FIFO WR command to complete to avoid overflow */
 	usleep_range(250, 255);
-	swr_master_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
 	if (cmd_id == 0xF) {
 		/*
 		 * sleep for 10ms for MSM soundwire variant to allow broadcast
@@ -2042,6 +2042,7 @@ static int swrm_runtime_resume(struct device *dev)
 		if (swrm_clk_request(swrm, true))
 			goto exit;
 		if (!swrm->clk_stop_mode0_supp || swrm->state == SWR_MSTR_SSR) {
+			enable_bank_switch(swrm, 0, SWR_ROW_50, SWR_MIN_COL);
 			list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
 				ret = swr_device_up(swr_dev);
 				if (ret) {
@@ -2096,6 +2097,7 @@ static int swrm_runtime_suspend(struct device *dev)
 			goto exit;
 		}
 		if (!swrm->clk_stop_mode0_supp || swrm->state == SWR_MSTR_SSR) {
+			enable_bank_switch(swrm, 0, SWR_ROW_50, SWR_MIN_COL);
 			swrm_clk_pause(swrm);
 			swr_master_write(swrm, SWRM_COMP_CFG_ADDR, 0x00);
 			list_for_each_entry(swr_dev, &mstr->devices, dev_list) {