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qcacmn: Add delayed register write support in HAL

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In case the bus is in low power mode, the register writes (followed by a
memory barrier) may take a long time (~4ms). This can cause the caller
to block till the PCIe write is completed. Thus, even though PCI
writes are posted, it can still block the caller.

Hence, in case the bus is in low power mode (not in M0), or not in high
throughput scenarios, queue the register write in a workqueue. The
register write will happen in the delayed work context. In other cases,
i.e ,when the bus is not in low power mode or in high thoughput
scenarios, do the register writes in caller context.

Change-Id: Idf218e4581545bc6ac67b91d0f70d495387ca90e
CRs-Fixed: 2602029
This commit is contained in:
Mohit Khanna
2020-02-07 11:40:13 -08:00
committed by nshrivas
parent d5a7a4ca89
commit b4429e8278
6 changed files with 525 additions and 7 deletions
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11
hal/wifi3.0/hal_hw_headers.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -228,9 +228,16 @@
#define SRNG_SRC_ADDR(_srng, _reg) \
SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, SRC)
#ifdef FEATURE_HAL_DELAYED_WRITE
#define SRNG_REG_WRITE(_srng, _reg, _value, _dir) \
hal_write_address_32_mb(_srng->hal_soc, \
hal_delayed_reg_write(_srng->hal_soc, _srng,\
SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value))
#else
#define SRNG_REG_WRITE(_srng, _reg, _value, _dir) \
hal_write_address_32_mb(_srng->hal_soc,\
SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value))
#endif
#define SRNG_REG_READ(_srng, _reg, _dir) \
hal_read_address_32_mb(_srng->hal_soc, \